ISL23418UFRUZ-TK_技术文档

Single, 128-Tap, Low Voltage Digitally Controlled

Potentiometer (XDCP™)

ISL23418

The ISL23418 is a volatile, low voltage, low noise, low power,

SPI™ bus, 128 taps, single digitally controlled potentiometer

(DCP), which integrates DCP core, wiper switches, and control

logic on a monolithic CMOS integrated circuit.

Features

• 128 Resistor Taps

• SPI Serial Interface

- No Additional Level Translator for Low Bus Supply

- Daisy Chaining of Multiple DCP

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wiper is controlled by the user through the SPI

bus interface. The potentiometer has an associated volatile

Wiper Register (WR) that can be directly written to and read by

the user. The contents of the WR controls the position of the

wiper. When powered on, the ISL23418 wiper always

commences at mid-scale (64-tap position).

• Wiper Resistance: 70Ω Typical @ V = 3.3V

CC

• Shutdown Mode: Forces DCP into End-to-end Open Circuit;

RW Shorted to RL Internally

• Power-on Preset to Mid-scale (64-tap Position)

• Shutdown and Standby Current <2.8µA Max

• Power Supply

- V = 1.7V to 5.5V Analog Power Supply

CC

The low voltage, low power consumption, and small package

size of the ISL23418 make it an ideal choice for use in battery

- V

LOGIC

= 1.2V to 5.5V SPI Bus/Logic Power Supply

operated equipment. The ISL23418 has a V

down to 1.2V bus operation, independent from the V value.

pin allowing

LOGIC

• DCP Terminal Voltage from 0V to V

CC

• 10kΩ, 50kΩ or 100kΩ Total Resistance

• Extended Industrial Temperature Range: -40°C to +125°C

• 10 Ld MSOP or 10 Ld µTQFN Packages

• Pb-free (RoHS compliant)

This allows for low logic levels to be connected directly to the

ISL23418 without passing through a voltage level shifter.

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal

processing.

Applications

• Power Supply Margining

Related Literature

• See ISL23415, “Single, Low Voltage Digitally Controlled

Potentiometer (XDCP™)”

• RF Power Amplifier Bias Compensation

• LCD Bias Compensation

• Gain Adjustment in Battery Powered Instruments

• Portable Medical Equipment Calibration

10000

8000

6000

4000

2000

0

V_REF

RH1

-

V_{REF_M}

RW1

ISL23418

+

ISL28114

RL1

0

25

50

75

100

125

TAP POSITION (DECIMAL)

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

POSITION, 10k

FIGURE 2. V

ADJUSTMENT

REF

August 3, 2011

FN7901.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation

or one of its subsidiaries .All other trademarks mentioned are the property of their respective owners.

1

ISL23418

Block Diagram

V

CC

LOGIC

RH

SCK

SDI

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

I/O BLOCK

LEVEL

SHIFTER

WR

SDO

CS

VOLATILE

REGISTER

AND

WIPER

CONTROL

CIRCUITRY

RL

RW

GND

Pin Configurations

Pin Description

ISL23418

(10 LD MSOP)

TOP VIEW

MSOP

µTQFN

SYMBOL

DESCRIPTION

1

10

V

SPI bus/logic supply; range 1.2V to

5.5V

LOGIC

O

10

GND

V

1

2

3

4

5

LOGIC

SCK

2

3

1

2

SCK

SDO

Logic pin: serial bus clock input

V

9

CC

Logic pin: serial bus data output

(configurable)

RH

SDO

SDI

CS

8

7

RW

RL

4

5

6

7

8

9

3

4

5

6

7

8

SDI

CS

Logic pin: serial bus data input

Logic pin: active low Chip Select

DCP “low” terminal

6

RL

ISL23418

(10 LD µTQFN)

TOP VIEW

RW

RH

DCP wiper terminal

DCP “high” terminal

V

Analog power supply; range 1.7V to

5.5V

CC

O

SCK

1

9

8

7

6

GND

10

9

GND

Ground pin

SDO

SDI

CS

2

3

4

V

CC

RH

RW

FN7901.0

August 3, 2011

2

ISL23418

Ordering Information

RESISTANCE

PART NUMBER

(Note 5)

PART

MARKING

OPTION

(kΩ)

TEMP. RANGE

PACKAGE

(Pb-free)

PKG.

DWG. #

(°C)

ISL23418TFUZ (Notes 1, 3)

ISL23418UFUZ (Notes 1, 3)

ISL23418WFUZ (Notes 1, 3)

ISL23418TFRUZ-T7A (Notes 2, 4)

ISL23418TFRUZ-TK (Notes 2, 4)

ISL23418UFRUZ-T7A (Notes 2, 4)

ISL23418UFRUZ-TK (Notes 2, 4)

ISL23418WFRUZ-T7A (Notes 2, 4)

ISL23418WFRUZ-TK (Notes 2, 4)

NOTES:

3418T

3418U

100

50

-40 to +125

10 Ld MSOP

M10.118

10 Ld MSOP

M10.118

3418W

HL

10

10 Ld MSOP

M10.118

100

50

10 Ld 2.1x1.6 µTQFN

L10.2.1x1.6A

HL

HK

50

HJ

10

HJ

10

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate -

e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23418. For more information on MSL please see Tech Brief TB363.

FN7901.0

August 3, 2011

3

ISL23418

Absolute Maximum Ratings

Thermal Information

Supply Voltage Range

Thermal Resistance (Typical)

10 Ld MSOP Package (Notes 6, 7). . . . . . .

10 Ld µTQFN Package (Notes 6, 7) . . . . . .

θ

_JA(°C/W)

170

θ

_JC(°C/W)

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

70

90

CC

LOGIC

145

Voltage on any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Wiper Current I (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

ESD Rating

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV

CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 200V

Latch Up

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V

CC

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V

LOGIC

DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V

CC

Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

7. For θ , the “case temp” location is taken at the package top center.

JC

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

to R Resistance

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

R

W option

U option

T option

10

50

kΩ

TOTAL

H

L

kΩ

100

±2

R

to R Resistance Tolerance

-20

+20

%

H

L

End-to-End Temperature Coefficient

W option

U option

T option

175

85

ppm/°C

V

70

V

, V

RH RL

DCP Terminal Voltage

Wiper Resistance

V

or V to GND

RL

0

V

CC

RH

R

RH - floating, V = 0V, force I current

RL

70

200

Ω

W

to the wiper, I = (V - V )/R

W

CC RL

TOTAL,

V

= 2.7V to 5.5V

CC

V

= 1.7V

580

32/32/32

<0.1

16

Ω

CC

C /C /C

W

Terminal Capacitance

Leakage on DCP Pins

Resistor Noise Density

See “DCP Macro Model” on page 8.

Voltage at pin from GND to V

pF

µA

H

L

I

-0.4

0.4

LkgDCP

Noise

CC

Wiper at middle point, W option

Wiper at middle point, U option

Wiper at middle point, T option

nV/ Hz

√

49

nV/ Hz

√

61

nV/ Hz

√

Feed Thru Digital Feedthrough from Bus to Wiper Wiper at middle point

-65

dB

PSRR

Power Supply Reject Ratio

Wiper output change if V change

CC

-75

±10%; wiper at middle point

VOLTAGE DIVIDER MODE (0V @ RL; V @ RH; measured at RW, unloaded)

CC

INL

Integral Non-linearity, Guaranteed

W, U, T option

-0.5

±0.15

+0.5

LSB

(Note 13) Monotonic

(Note 9)

FN7901.0

August 3, 2011

4

ISL23418

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

DNL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

Differential Non-linearity, Guaranteed W, U, T option

-0.5

-2.5

-1.0

0

±0.15

-1.5

-0.7

+0.5

LSB

(Note 9)

(Note 12) Monotonic

FSerror

(Note 11)

Full-scale Error

W option

U, T option

W option

U, T option

0

LSB

(Note 9)

0

LSB

(Note 9)

ZSerror

(Note 10)

Zero-scale Error

-1.5

-0.7

2.5

1.0

LSB

(Note 9)

0

LSB

(Note 9)

TC

(Note 14)

Ratiometric Temperature Coefficient

W option, Wiper Register set to 40 hex

U option, Wiper Register set to 40 hex

T option, Wiper Register set to 40 hex

From code 0 to 7F hex

8

4

ppm/°C

ns

V

2.3

t

Large Signal Wiper Settling Time

-3dB Cutoff Frequency

300

1200

250

120

LS_Settling

f

Wiper at middle point W option

Wiper at middle point U option

Wiper at middle point T option

kHz

cutoff

kHz

RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)

Integral Non-linearity, Guaranteed W option; V = 2.7V to 5.5V

R

-1.0

-0.5

0

±0.5

±3.0

±0.15

±1.0

±0.15

±0.4

±0.15

±0.4

1.8

+1.0

+0.5

3.0

MI

INL

CC

(Note 18) Monotonic

(Note 15)

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

R

Differential Non-linearity, Guaranteed W option; V = 2.7V to 5.5V

CC

MI

(Note 15)

DNL

(Note 17) Monotonic

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

R

Offset, Wiper at 0 Position

W option; V = 2.7V to 5.5V

CC

MI

(Note 15)

offset

(Note 16)

W option; V = 1.7V

CC

3.0

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

0

0.3

1

MI

(Note 15)

U, T option; V = 1.7V

CC

0.5

MI

(Note 15)

FN7901.0

August 3, 2011

5

ISL23418

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

TCR

(Note 19)

Resistance Temperature Coefficient

W option; Wiper register set between

32 hex and 7F hex

220

100

75

ppm/°C

U option; Wiper register set between

32 hex and 7F hex

ppm/°C

T option; Wiper register set between

32 hex and 7F hex

Operating Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise

CC

LOGIC

stated. Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

mA

I

V

Supply Current (Write/Read)

V

= 5.5V, V = 5.5V,

1.5

LOGIC

CC

f

= 5MHz (for SPI active read and write)

SCK

V

= 1.2V, V = 1.7V,

CC

30

µA

LOGIC

= 1MHz (for SPI active read and write)

f

SCK

I

V

Supply Current (Write/Read)

V

= 5.5V, V = 5.5V

CC

100

10

µA

CC

LOGIC

= 1.2V, V = 1.7V

CC

I

Standby Current

= V = 5.5V,

CC

1.3

LOGIC SB

LOGIC

SPI interface in standby

V

= 1.2V, V = 1.7V,

0.4

1.5

1

µA

µs

LOGIC

CC

SPI interface in standby

I

V

Standby Current

V = V = 5.5V,

LOGIC CC

SPI interface in standby

CC SB

CC

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

V

Shutdown Current

V

= V = 5.5V,

LOGIC CC

1.3

0.4

1.5

1

LOGIC SHDN LOGIC

SPI interface in standby

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

V

Shutdown Current

V = V = 5.5V,

LOGIC CC

SPI interface in standby

CC SHDN

CC

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

Leakage Current, at Pins CS, SDO, SDI,

SCK

Voltage at pin from GND to V

-0.4

<0.1

0.4

1.5

3.5

1.5

0.4

LkgDig

LOGIC

t

Wiper Response Time

W option; CS rising edge to wiper new position,

from 10% to 90% of final value.

DCP

U option; CS rising edge to wiper new position,

from 10% to 90% of final value.

µs

T option; CS rising edge to wiper new position,

from 10% to 90% of final value.

µs

tShdnRec DCP Recall Time from Shutdown Mode CS rising edge to wiper recalled position and

RH connection

µs

V

, V

V

, V

Ramp Rate

Ramp monotonic at any level

0.01

50

V/ms

CC LOGIC CC LOGIC

Ramp

FN7901.0

August 3, 2011

6

ISL23418

Serial Interface Specification For SCK, SDI, SDO, CS, unless otherwise noted.

MIN

TYP

MAX

SYMBOL

PARAMETER

Input LOW Voltage

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

V

-0.3

0.3 x V

V

IL

LOGIC

V

Input HIGH Voltage

0.7 x V

V

LOGIC

+ 0.3

IH

LOGIC

Hysteresis

SDI and SCK Input Buffer Hysteresis

V

> 2V

< 2V

0.05 x V

LOGIC

0.1 x V

0

LOGIC

V

SDO Output Buffer LOW Voltage

SDO Pull-up Resistor Off-chip

I

= 3mA, V

> 2V

0.4

V

OL

LOGIC

= 1.5mA, V

< 2V

0.2 x V

LOGIC

R

Maximum is determined by t and t with

1.5

kΩ

pu

RO

FO

maximum bus load Cb = 30pF, f

= 5MHz

SCK

C

SCK, SDO, SDI, CS Pin Capacitance

SCK Frequency

10

pF

MHz

ns

f

V

= 1.7V to 5.5V

= 1.2V to 1.6V

≥ 1.7V

5

1

SCK

LOGIC

t

SPI Clock Cycle Time

200

CYC

t

SPI Clock High Time

≥ 1.7V

100

250

50

ns

WH

t

SPI Clock Low Time

≥ 1.7V

ns

WL

t

Lead Time

≥ 1.7V

ns

LEAD

t

Lag Time

≥ 1.7V

ns

LAG

t

SDI, SCK and CS Input Setup Time

SDI, SCK and CS Input Hold Time

SDI, SCK and CS Input Rise Time

SDI, SCK and CS Input Fall Time

SDO Output Disable Time

SDO Output Setup Time

SDO Output Valid Time

SDO Output Hold Time

SDO Output Rise Time

SDO Output Fall Time

CS Deselect Time

≥ 1.7V

ns

SU

t

≥ 1.7V

50

ns

H

t

≥ 1.7V

10

ns

RI

t

≥ 1.7V

10

20

ns

FI

t

≥ 1.7V

0

100

ns

DIS

t

≥ 1.7V

50

ns

SO

t

≥ 1.7V

150

0

ns

V

t

≥ 1.7V

ns

HO

RO

t

R

= 1.5k, Cbus = 30pF

60

ns

pu

t

R

ns

FO

CS

2

µs

NOTES:

8. Typical values are for T = +25°C and 3.3V supply voltages.

A

9. LSB = [V(RW)

127

– V(RW) ]/127. V(RW) and V(RW) are V(RW) for the DCP register set to 7F hex and 00 hex, respectively. LSB is the incremental

0

127 0

voltage when changing from one tap to an adjacent tap.

10. ZS error = V(RW) /LSB.

0

11. FS error = [V(RW)

127

– V ]/LSB.

CC

12. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

i

13. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 127

i

0

Max(V(RW) ) – Min(V(RW) )

6

10

14.

i

for i = 16 to 127 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage

and Min( ) is the minimum value of the wiper voltage over the temperature range.

----------------------------------------------------------------------------- ---------------------

TC

=

×

V

V(RWi(+25°C))

+165°C

15. MI = |RW

– RW |/127. MI is a minimum increment. RW and RW are the measured resistances for the DCP register set to 7F hex and 00

127 0

127

hex, respectively.

0

16. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

127

17. RDNL = (RW – RW )/MI -1, for i = 16 to 127.

i-1

i

18. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 127.

i

0

6

[Max(Ri) – Min(Ri)]

10

19.

for i = 16 to 127, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the

minimum value of the resistance over the temperature range.

------------------------------------------------------ ---------------------

TC

=

×

R

Ri(+25°C)

+165°C

20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN7901.0

August 3, 2011

7

ISL23418

DCP Macro Model

R

TOTAL

RH

RL

C

L

C

H

C

W

32pF

RW

Timing Diagrams

Input Timing

t

CS

t

LAG

LEAD

CYC

SCK

SDI

...

t

WH

t

RI

FI

t

WL

SU

H

...

MSB

LSB

SDO

Output Timing

CS

SCK

SDO

SDI

...

t

SO

HO

DIS

MSB

LSB

t

V

ADDR

XDCP™ Timing (for All Load Instructions)

CS

t

DCP

SCK

...

MSB

LSB

SDI

V

W

SDO

*When CS is HIGH

SDO at Z or Hi-Z state

FN7901.0

August 3, 2011

8

ISL23418

Typical Performance Curves

0.4

0.30

0.2

0

0.15

0

-0.2

-0.4

-0.15

-0.30

0

25

50

75

100

125

0

25

50

75

100

125

TAP POSITION (DECIMAL)

FIGURE 3. 10k DNL vs TAP POSITION, V = 5V

CC

FIGURE 4. 50k DNL vs TAP POSITION, V = 5V

CC

0.30

0.15

0

0.4

0.2

0

-0.2

-0.4

-0.15

-0.30

0

25

50

75

100

125

25

50

75

100

TAP POSITION (DECIMAL)

FIGURE 5. 10k INL vs TAP POSITION, V = 5V

CC

FIGURE 6. 50k INL vs TAP POSITION, V = 5V

CC

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.15

-0.30

25

50

75

100

0

25

50

75

100

125

TAP POSITION (DECIMAL)

FIGURE 7. 10k RDNL vs TAP POSITION, V = 5V

CC

FIGURE 8. 50k RDNL vs TAP POSITION, V = 5V

CC

FN7901.0

August 3, 2011

9

ISL23418

Typical Performance Curves (Continued)

0.6

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.6

-0.15

-0.30

0

25

50

75

100

125

0

25

50

75

100

125

TAP POSITION (DECIMAL)

FIGURE 9. 10k RINL vs TAP POSITION, V = 5V

CC

FIGURE 10. 50k RINL vs TAP POSITION, V = 5V

CC

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

+125°C

+25°C

-40°C

0

25

50

75

100

125

0

25

50

75

100

125

TAP POSITION (DECIMAL)

FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

300

250

200

150

100

50

70

60

50

40

30

20

10

0

7.5

32.5

57.5

82.5

107.5

7.5

32.5

57.5

82.5

107.5

TAP POSITION (DECIMAL)

FIGURE 13. 10k TCv vs TAP POSITION

FIGURE 14. 50k TCv vs TAP POSITION

FN7901.0

August 3, 2011

10

ISL23418

Typical Performance Curves (Continued)

600

500

400

300

200

100

0

200

150

100

50

0

7.5

32.5

57.5

82.5

107.5

32.5

57.5

82.5

107.5

TAP POSITION (DECIMAL)

FIGURE 15. 10k TCr vs TAP POSITION

FIGURE 16. 50k TCr vs TAP POSITION

35

30

25

20

15

10

5

120

90

60

30

0

7.5

32.5

57.5

82.5

107.5

7.5

32.5

57.5

82.5

107.5

TAP POSITION (DECIMAL)

FIGURE 17. 100k TCv vs TAP POSITION

FIGURE 18. 100k TCr vs TAP POSITION

SCK CLOCK

RW PIN

CH1: 1V/DIV, 1µs/DIV

CH2: 10mV/DIV, 1µs/DIV

20mV/DIV

5µs/DIV

FIGURE 19. WIPER DIGITAL FEEDTHROUGH

FIGURE 20. WIPER TRANSITION GLITCH

FN7901.0

August 3, 2011

11

ISL23418

Typical Performance Curves (Continued)

1V/DIV

1µs/DIV

0.1s/DIV

VRW

CS RISING EDGE

FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME

FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE

1.2

1.0

0.8

CH1: 0.5V/DIV, 0.2µs/DIV RH PIN

CH2: 0.2V/DIV, 0.2µs/DIV RW PIN

V

= 5.5V, V

= 5.5V

LOGIC

CC

0.6

0.4

0.2

0

V

= 1.7V, V

= 1.2V

LOGIC

CC

R

= 10k

TOTAL

-40

-15

10

35

60

85

110

-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP

TEMPERATURE (°C)

FIGURE 23. 10k -3dB CUT OFF FREQUENCY

FIGURE 24. STANDBY CURRENT vs TEMPERATURE

FN7901.0

August 3, 2011

12

ISL23418

Voltage at any DCP pins, RH, RL, or RW should not exceed V

CC

Functional Pin Descriptions

Potentiometers Pins

RH AND RL

level at any conditions during power-up and normal operation.

The V pin must be connected to the SPI bus supply, which

LOGIC

allows reliable communication with a wide range of

microcontrollers, independently of the V level. This is

CC

extremely important in systems in which the digital supply has

lower levels than the analog supply.

The high (RH) and low (RL) terminals of the ISL23418 are

equivalent to the fixed terminals of a mechanical potentiometer.

The RH and RL are referenced to the relative position of the wiper

and not to the voltage potential on the terminals. With the WR

register set to 127 decimal, the wiper is closest to RH, and with

the WR register set to 0, the wiper is closest to RL.

DCP Description

Each DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of DCP are

equivalent to the fixed terminals of a mechanical potentiometer

(RH and RL pins). The RW pin of the DCP is connected to

intermediate nodes and is equivalent to the wiper terminal of a

mechanical potentiometer. The position of the wiper terminal

within the DCP is controlled by the 8-bit volatile Wiper Register

(WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h),

its wiper terminal (RW) is closest to its “Low” terminal (RL). When

the WR register of a DCP contains all ones (WR[7:0] = 7Fh), its

wiper terminal (RW) is closest to its “High” terminal (RH). As the

value of WR increases from all zeroes (0) to all ones (127

decimal), the wiper moves monotonically from the position

closest to RL to the position closest to RH. At the same time, the

resistance between RW and RL increases monotonically, while

the resistance between RH and RW decreases monotonically.

RW

RW is the wiper terminal, and it is equivalent to the moveable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WR register.

Bus Interface Pins

SERIAL CLOCK (SCK)

The SCK input is the serial clock of the SPI serial interface.

SERIAL DATA INPUT (SDI)

SDI is a serial data input pin for the SPI interface. SDI receives

operation code, wiper address and data from the SPI remote

host device. The data bits are shifted in at the rising edge of the

serial clock, SCK, while CS input is low.

While the ISL23418 is being powered up, the WR is reset to 40h

(64 decimal), which locates RW to the mid value between RL and

RH.

SERIAL DATA OUTPUT (SDO)

WR can be read or written to directly using the SPI serial

interface as described in the following sections.

SDO is a serial data output pin. During a read cycle, the data bits

are shifted out on the falling edge of the serial clock SCK and are

available to the master on the following rising edge of SCK.

Memory Description

The output type is configured through ACR[1] bit for Push-Pull or

Open Drain operation. Default setting for this pin is Push-Pull. An

external pull-up resistor is required for Open Drain output

operation. When CS is HIGH, the SDO pin is in tri-state (Z) or

high-tri-state (Hi-Z), depending on the selected configuration.

The ISL23418 contains two volatile 8-bit registers: the Wiper

Register (WR) and the Access Control Register (ACR). A memory

map of ISL23418 is shown in Table 1. WR, at address 0, contains

the current wiper position of the DCP. ACR, at address 10h,

contains information and control bits as described in Table 2.

CHIP SELECT (CS)

TABLE 1. MEMORY MAP

CS LOW enables the ISL23418, placing it in the active power

mode. A HIGH to LOW transition on CS is required prior to the

start of any operation after power-up. When CS is HIGH, the

ISL23418 is deselected, the SDO pin is at high impedance, and

the device is in standby state.

ADDRESS

(hex)

DEFAULT SETTING

(hex)

VOLATILE

ACR

10

0

40

80

WR

VLOGIC

TABLE 2. ACCESS CONTROL REGISTER (ACR)

VLOGIC is an input pin that supplies an internal level translator

for serial bus operation from 1.2V to 5.5V.

BIT #

7

6

5

0

4

0

3

0

2

0

1

0

NAME

0

SHDN

SDO

Principles of Operation

Shutdown Function

The ISL23418 is an integrated circuit incorporating one DCP with

its associated registers and an SPI serial interface providing

direct communication between a host and the potentiometer.

The resistor array is composed of individual resistors connected

in series. At either end of the array and between each resistor is

an electronic switch that transfers the potential at that point to

the wiper. The electronic switches on the device operate in a

“make before break” mode when the wiper changes tap

positions.

The SHDN bit (ACR[6]) disables or enables shutdown mode for all

DCP channels simultaneously. When this bit is 0, DCP is forced to

end-to-end open circuit, and RW is connected to RL through a

2kΩ serial resistor, as shown in Figure 25. Default value of the

SHDN bit is 1.

FN7901.0

August 3, 2011

13

ISL23418

SPI Serial Interface

RH

The ISL23418 supports an SPI serial protocol, mode 0. The

device is accessed via the SDI input and SDO output, with data

clocked in on the rising edge of SCK and clocked out on the

falling edge of SCK. CS must be LOW during communication with

the ISL23418. The SCK and CS lines are controlled by the host or

master. The ISL23418 operates only as a slave device. All

communication over the SPI interface is conducted by sending

the MSB of each byte of data first.

RW

RL

2kΩ

Protocol Conventions

FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE

The SPI protocol contains an Instruction Byte followed by one or

more Data Bytes. A valid Instruction Byte contains instruction as

the three MSBs, with the following five register address bits

(Table 3). The next byte sent to the ISL23418 is the Data Byte.

In shutdown mode, the RW terminal is shorted to the RL terminal

with around 2kΩ resistance, as shown in Figure 25. When the device

enters shutdown, all current DCP WR settings are maintained. When

the device exits shutdown, the wipers return to the previous WR

settings after a short settling time (Figure 26).

TABLE 3. INSTRUCTION BYTE FORMAT

BIT #

7

6

5

4

3

2

1

0

I2

I1

I0

R4

R3

R2

R1

R0

Table 4 contains a valid instruction set for ISL23418. If the

[R4:R0] bits are zero, then the read or write is to the WR register. If

the [R4:R0] bits are 10000, then the operation is to the ACR.

POWER-UP

MID SCALE = 40H

USER PROGRAMMED

AFTER SHDN

Write Operation

SHDN RELEASED

A write operation to the ISL23418 is a two or more bytes

operation. It first requires CS to transition from HIGH to LOW.

Then the host sends a valid Instruction Byte to the SDI pin,

followed by one or more Data Bytes. The host terminates the

write operation by pulling the CS pin from LOW to HIGH. The

instruction is executed on the rising edge of CS (Figure 27).

SHDN ACTIVATED

WIPER RESTORE TO

ORIGINAL POSITION

SHDN MODE

TIME (s)

0

FIGURE 26. SHUTDOWN MODE WIPER RESPONSE

Read Operation

In shutdown mode, if there is a glitch in the power supply that

causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the

wipers are RESET to their mid position. This is done to avoid an

undefined state at the wiper outputs.

A read operation to the ISL23418 is a four-byte operation. First,

the CS transitions from HIGH to LOW. Then the host sends a valid

Instruction Byte to the SDI pin, followed by a “dummy” Data Byte,

an NOP Instruction Byte, and another “dummy” Data Byte. The

SPI host receives the Instruction Byte (instruction code + register

address) and the requested Data Byte from the SDO pin on the

rising edge of SCK during the third and fourth bytes, respectively.

The host terminates the read by pulling the CS pin from LOW to

HIGH (Figure 28).

TABLE 4. INSTRUCTION SET

INSTRUCTION SET

I2

0

1

I1

0

1

0

1

I0

0

1

0

R4

X

R3

X

R2

X

R1

X

R0

X

OPERATION

NOP

X

ACR READ

X

ACR WRTE

R4

R3

R2

R1

R0

WR or ACR READ

WR or ACR WRTE

where “X” means “do not care.”

FN7901.0

August 3, 2011

14

ISL23418

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCK

DATA BYTE

WR INSTRUCTION

ADDR

SDI

SDO

FIGURE 27. TWO-BYTE WRITE SEQUENCE

1

8

16

24

32

CS

SCK

NOP

RD

ADDR

SDI

RD

ADDR

READ DATA

SDO

FIGURE 28. FOUR-BYTE READ SEQUENCE

FN7901.0

August 3, 2011

15

ISL23418

First there is a HIGH-to-LOW transition on the CS line, followed by

Applications Information

Communicating with ISL23418

Communication with ISL23418 is accomplished by using the SPI

interface through the ACR (address 10000b) and WR (address

00000b) registers.

N two-byte read instructions on the SDI line, with reversed chain

access sequence. The instruction byte + dummy data byte for the

last DCP in the chain goes first, followed by a LOW-to-HIGH

transition on the CS line. The read instructions are executed

during the second part of the read sequence. It also starts by a

HIGH-to-LOW transition on the CS line, followed by N number of

two-byte NOP instructions on the SDI line and a LOW-to-HIGH

transition of CS. The data is read on every even byte during the

second part of the read sequence, while every odd byte contains

code 111b followed by the address from which the data is being

read.

The wiper of the potentiometer is controlled by the WR register.

Writes and reads can be made directly to these registers to

control and monitor the wiper position.

Daisy Chain Configuration

When an application needs more than one ISL23418, it can

communicate with all of them without additional CS lines by

daisy chaining the DCPs, as shown in Figure 29. In daisy chain

configuration, the SDO pin of the previous chip is connected to

the SDI pin of the following chip, and each CS and SCK pin is

connected to the corresponding microcontroller pin in parallel,

like regular SPI interface implementation. The daisy chain

configuration can also be used for simultaneous setting of

multiple DCPs. Note that the number of daisy chained DCPs is

limited only by the driving capabilities of the SCK and CS pins of

the microcontroller. For a larger number of SPI devices, buffering

of the SCK and CS lines is required.

Wiper Transition

When stepping up through each tap in voltage divider mode,

some tap transition points can exhibit noticeable voltage

transients or overshoot/undershoot, which results from the

sudden transition from a very low impedance “make” to a much

higher impedance “break” within a short period of time (<1µs).

Several code transitions, such as 0Fh to 10h, 1Fh to 20h,..., and

EFh to 7Fh, have higher transient glitch. Note that all switching

transients settle well within the settling time as stated in the

datasheet. A small capacitor can be added externally to reduce

the amplitude of these voltage transients, but this also reduces

the useful bandwidth of the circuit, which may not be a good

solution for some applications. Using fast amplifiers in a signal

chain for fast recovery may be a good idea in these cases.

Daisy Chain Write Operation

The write operation starts with a HIGH to LOW transition on the

CS line, followed by N number of two-byte write instructions on

the SDI line, with reversed chain access sequence. The

instruction byte + data byte for the last DCP in the chain go first,

as shown in Figure 30, where N is the number of DCPs in the

chain. Serial data is going through the DCPs from DCP0 to

DCP(N-1) as follows: DCP0 --> DCP1 --> DCP2 --> ... --> DCP(N-1).

The write instruction is executed on the rising edge of CS for all N

DCPs simultaneously.

V

Requirements

LOGIC

Keeping V

powered all the time during normal operation is

LOGIC

recommended. In cases in which turning V

necessary, grounding the V

OFF is

LOGIC

pin is recommended. Grounding

LOGIC

the V

LOGIC

pin or both V

LOGIC

and V does not affect other

CC

devices on the same bus. It is good practice to put a 1µF capacitor

in parallel with a 0.1µF decoupling capacitor close to the V pin.

LOGIC

V

Requirements and Placement

Daisy Chain Read Operation

CC

Putting a 1µF capacitor in parallel with a 0.1µF decoupling capacitor

The read operation consists of two parts. First, the read

instructions (N two-byte operations) are sent with a valid address.

Second, the requested data is read while sending NOP

instructions (N two-byte operations), as shown in

Figures 31 and 32.

close to the V pin is recommended.

CC

N DCP IN A CHAIN

CS

SCK

DCP0

DCP1

DCP2

DCP(N-1)

CS

MOSI

MISO

CS

SCK

SDI

SCK

SDI

SCK

SDI

SCK

SDI

µC

SDO

FIGURE 29. DAISY CHAIN CONFIGURATION

FN7901.0

August 3, 2011

16

ISL23418

CS

SCK

16 CLKS

C P0

16 CLKLS

C P2

16 CLKS

WR

D

WR

D

C P1

C P2

WR

D

SDI

D

C P1

C P2

SDO 0

WR

D

SDO 1

SDO 2

FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCK

SDI

INSTRUCTION

ADDR

DATA IN

SDO

DATA OUT

FIGURE 31. TWO-BYTE READ INSTRUCTION

CS

SCK

SDI

16 CLKS

RD DCP2

16 CLKS

RD DCP1

16 CLKS

RD DCP0

16 CLKS

NOP

16 CLKS

NOP

16 CLKS

NOP

DCP0 OUT

DCP2 OUT

DCP1 OUT

SDO

FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP

FN7901.0

August 3, 2011

17

ISL23418

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest revision.

DATE

REVISION

FN7901.0

CHANGE

8/3/2011

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL23418

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7901.0

August 3, 2011

18

ISL23418

Mini Small Outline Plastic Packages (MSOP)

N

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.020 BSC

0.50 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

10

0.95 REF

10

-

0.10 (0.004)

-A-

C

b

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

θ

-

o

a

SIDE VIEW

5

15

5

15

-

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 0 12/02

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

FN7901.0

August 3, 2011

19

ISL23418

Package Outline Drawing

L10.2.1x1.6A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

8.

PIN 1

INDEX AREA

2.10

A

PIN #1 ID

8.

0.05 MIN.

B

1

4

1

4X 0.20 MIN.

0.10 MIN.

10

5

0.80

10X 0.40

10 X 0.20

0.10

6

9

2X

6X 0.50

4

TOP VIEW

(10 X 0.20)

0.10 M C A B

M C

BOTTOM VIEW

SEE DETAIL "X"

(0.05 MIN)

(0.10 MIN.)

MAX. 0.55

PACKAGE

OUTLINE

1

0.10 C

C

(10X 0.60)

SEATING PLANE

0.08 C

(2.00)

SIDE VIEW

0 . 125 REF

(0.80)

(1.30)

C

(6X 0.50 )

(2.50)

0-0.05

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All Dimensions are in millimeters. Angles are in degrees.

Dimensions in ( ) for Reference Only.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Lead width dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Maximum package warpage is 0.05mm.

6. Maximum allowable burrs is 0.076mm in all directions.

7. Same as JEDEC MO-255UABD except:

No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm

Lead Length dim. = 0.45mm max. not 0.42mm.

8. The configuration of the pin #1 identifier is optional, but must be located within

the zone indicated. The pin #1 identifier may be either a mold or mark feature.

FN7901.0

August 3, 2011

20


型号：	ISL23418UFRUZ-TK
厂家：	Intersil
描述：	Single, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCPâ¢) 单， 128抽头，低电压数字控制电位器（ XDCPâ ?? ¢ ）电位器
文件：	总20页 (文件大小：927K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL23418UFRUZ-TK [INTERSIL]

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