ISL28117FUZ [INTERSIL]
40V Precision Low Power Operational Amplifiers; 40V精密低功耗运算放大器
| 型号： | ISL28117FUZ |
| 厂家： | 
Intersil |
| 描述： | 40V Precision Low Power Operational Amplifiers |
| 文件： | 总25页 (文件大小：1056K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40V Precision Low Power Operational Amplifiers
ISL28117, ISL28217
Features
• Low Input Offset . . . . . . . . . . . . . . ±50µV, Max.
• Superb Offset TC . . . . . . . . . . . . 0.6µV/°C, Max.
• Input Bias Current . . . . . . . . . . . . . . ±1nA, Max.
The ISL28117 and ISL28217 are a family of very high
precision amplifiers featuring low noise vs power
consumption, low offset voltage, low I
current and
BIAS
low temperature drift making them the ideal choice for
applications requiring both high DC accuracy and AC
performance. The combination of precision, low noise,
and small footprint provides the user with outstanding
value and flexibility relative to similar competitive parts.
• Input Bias Current TC . . . . . . . . . .±5pA/°C, Max.
• Low Current Consumption . . . . . . . . . . . . .440µA
• Voltage Noise. . . . . . . . . . . . . . . . . . . . . 8nV/Hz
• Wide Supply Range. . . . . . . . . . . . . . 4.5V to 40V
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls, and industrial controls.
• Operating Temperature Range . . -40°C to +125°C
• Small Package Offerings in Single and Dual
• Pb-Free (RoHS Compliant)
The ISL28117 single and ISL28217 dual are offered in an
8 Ld SOIC package. Both devices are offered in standard
pin configurations and operate over the extended
temperature range to -40°C to +125°C.
Related Literature*(see page 23)
• See AN1508 “ISL281X7SOICEVAL1Z Evaluation
Board User’s Guide”
Applications*(see page 23)
• Precision Instruments
• See AN1509 “ISL282X7SOICEVAL2Z Evaluation
Board User’s Guide”
• Medical Instrumentation
• Spectral Analysis Equipment
• Active Filter Blocks
• Thermocouples and RTD Reference Buffers
• Data Acquisition
• Power Supply Control
Typical Application
V
Temperature Coefficient
OS
(V TC)
OS
18
16
14
12
10
8
C
1
V
= ± 15V
S
8.2nF
V
+
-
OUTPUT
R
R
V
2
1
IN
+
1.84k
4.93k
3.3nF
6
C
2
4
V
-
2
Sallen-Key Low Pass Filter (10kHz)
0
-0.45 -0.30 -0.15
0
0.15
0.30 0.45
V
TC (µV/°C)
OS
April 13, 2010
FN6632.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL28117, ISL28217
Ordering Information
PART NUMBER
(Notes2, 3)
PART
MARKING
V
(MAX)
PACKAGE
(Pb-Free)
PKG.
DWG. #
OS
(µV)
ISL28117FBBZ
28117 FBZ
50 (B Grade)
50 (B Grade)
50 (B Grade)
100 (C Grade)
100 (C Grade)
100 (C Grade)
TBD (B Grade)
TBD (B Grade)
8 Ld SOIC
M8.15E
ISL28117FBBZ-T7 (Note 1)
ISL28117FBBZ-T13 (Note 1)
ISL28117FBZ
28117 FBZ
28117 FBZ
28117 FBZ -C
28117 FBZ -C
28117 FBZ -C
8117Z
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld MSOP
8 Ld MSOP
M8.15E
M8.15E
M8.15E
M8.15E
M8.15E
M8.118
M8.118
ISL28117FBZ-T7 (Note 1)
ISL28117FBZ-T13 (Note 1)
ISL28117FUBZ Coming Soon
ISL28117FUBZ-T13 (Note 1)
8117Z
Coming Soon
ISL28117FUZ
8117Z -C
150 (C Grade)
150 (C Grade)
50 (B Grade)
50 (B Grade)
50 (B Grade)
100 (C Grade)
100 (C Grade)
100 (C Grade)
8 Ld MSOP
8 Ld MSOP
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
8 Ld SOIC
M8.118
M8.118
M8.15E
M8.15E
M8.15E
M8.15E
M8.15E
M8.15E
ISL28117FUZ-T13 (Note 1)
ISL28217FBBZ
8117Z -C
28217 FBZ
ISL28217FBBZ-T7 (Note 1)
ISL28217FBBZ-T13 (Note 1)
ISL28217FBZ
28217 FBZ
28217 FBZ
28217 FBZ -C
28217 FBZ -C
28217 FBZ -C
Evaluation Board
Evaluation Board
ISL28217FBZ-T7 (Note 1)
ISL28217FBZ-T13 (Note 1)
ISL28117SOICEVAL1Z
ISL28217SOICEVAL2Z
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217. For more information on
MSL please see techbrief TB363.
Pin Configurations
ISL28117
(8 LD SOIC, MSOP)
TOP VIEW
ISL28217
(8 LD SOIC)
TOP VIEW
V
_A
1
2
3
4
8
7
6
5
V+
OUT
NC
-IN
+IN
V -
1
2
3
4
8
7
6
5
NC
V+
-IN_A
+IN_A
V -
V
_B
- +
OUT
- +
-IN_B
+IN_B
+ -
V
OUT
NC
April 13, 2010
FN6632.4
2
ISL28117, ISL28217
Pin Descriptions
ISL28117
ISL28217
(8 LD SOIC)
(8 LD SOIC)
PIN NAME
EQUIVALENT CIRCUIT
DESCRIPTION
3
4
+IN
+IN_A
Circuit 1
Amplifier A non-inverting input
3
4
5
6
7
8
V-
Circuit 3
Circuit 1
Circuit 1
Circuit 2
Circuit 3
Circuit 2
Negative power supply
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
+IN_B
-IN_B
V
_B
OUT
V+
7
6
Positive power supply
Amplifier A output
V
OUT
_A
1
2
V
OUT
2
-IN
-IN_A
NC
Circuit 1
-
Amplifier A inverting input
1, 5, 8
No internal connection
V+
V+
V+
500Ω
500Ω
CAPACITIVELY
COUPLED
ESD CLAMP
IN-
IN+
OUT
V-
V-
V-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
April 13, 2010
FN6632.4
3
ISL28117, ISL28217
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . ....42V
Maximum Differential Input Current . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . 42V
Min/Max Input Voltage . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Max/Min Input current for Input Voltage >V+ or <V-. . .±20mA
Output Short-Circuit Duration (1 output at a time). . . Indefinite
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . 4.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical, Notes 4, 5) θJA (°C/W) θJC (°C/W)
8 Ld SOIC ISL28117 . . . . . . . . . .
8 Ld SOIC ISL28217 . . . . . . . . . .
8 Ld MSOP ISL28117 . . . . . . . . . .
120
105
155
60
50
50
Maximum Storage Temperature Range . . . -65°C to +150°C
Maximum Junction Temperature (T ) . . . . . . . . . +150°C
JMAX
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range (T ) . . . . . . . -40°C to +125°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief
TB379 for details.
5. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications V ± 15V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply
S
CM
O
A
over the operating temperature range, -40°C to +125°C. Temperature data
established by characterization.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 6) TYP (Note 6) UNIT
V
Input Offset Voltage, SOIC Package ISL28x17 B Grade
-50
-110
-100
-190
-150
-250
-0.6
-0.9
-1
8
4
4
50
110
100
190
150
250
0.6
0.9
1
µV
µV
OS
ISL28x17 C Grade
µV
µV
Input Offset Voltage, MSOP
Package
ISL28117 C Grade
µV
µV
TCV
Input Offset Voltage Temperature ISL28x17 B Grade
0.14
0.14
0.14
µV/C
µV/C
µV/C
OS
Coefficient; SOIC Package
ISL28x17 C Grade
Input Offset Voltage Temperature ISL28117 C Grade
Coefficient; MSOP Package
I
Input Bias Current
-1
-1.5
-5
0.08
1
1.5
5
nA
nA
B
TCI
Input Bias Current Temperature
Coefficient
1
pA/C
B
I
Input Offset Current
-1.5
-1.85
-3
0.08
1.5
1.85
3
nA
nA
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
pA/C
OS
V
Input Voltage Range
Guaranteed by CMRR test
= -13V to +13V
-13
120
13
V
dB
CM
CMRR
Common-Mode Rejection Ratio
V
145
145
CM
120
120
dB
PSRR
Power Supply Rejection Ratio
Open-Loop Gain
V = ±2.25V to ±20V
dB
S
120
3,000
dB
A
V
= -13V to +13V, R = 10kΩ to
18,000
V/mV
VOL
O
L
ground
April 13, 2010
FN6632.4
4
ISL28117, ISL28217
Electrical Specifications V ± 15V, V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply
over the operating temperature range, -40°C to +125°C. Temperature data
S
CM
O
A
established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
Output Voltage High
CONDITIONS
= 10kΩ to ground
(Note 6)
TYP
(Note 6) UNIT
V
R
R
13.5
13.2
13.3
13.1
13.7
V
V
V
V
OH
L
= 2kΩ to ground
13.55
-13.7
-13.55
0.44
L
V
Output Voltage Low
R = 10kΩ to ground
-13.5
-13.2
-13.3
-13.1
0.53
V
V
OL
L
R = 2kΩ to ground
V
L
V
I
Supply Current/Amplifier
mA
mA
mA
V
S
0.68
I
Short-Circuit
43
SC
V
Supply Voltage Range
Guaranteed by PSRR
± 2.25
± 20
SUPPLY
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
Voltage Noise V
A = 1k, R = 2kΩ
1.5
0.25
10
MHz
V
L
e
0.1Hz to 10Hz
f = 10Hz
µV
P-P
nVp-p
P-P
e
e
e
e
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
Total Harmonic Distortion
nV/√Hz
n
n
n
n
f = 100Hz
f = 1kHz
8.2
8
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
%
f = 10kHz
f = 1kHz
8
in
THD + N
0.1
0.0009
1kHz, G = 1, V = 3.5V
,
,
O
RMS
R = 2kΩ
L
1kHz, G = 1, V = 3.5V
0.0005
%
O
RMS
R = 10kΩ
L
TRANSIENT RESPONSE
SR
Slew Rate, V
20% to 80%
A = 11, R = 2kΩ, V = 4V
0.5
V/µs
ns
OUT
V
L
O
P-P
t , t ,
Rise Time
A
= 1,
V
= 50mV
,
100
r
f
V
OUT
P-P
Small Signal 10% to 90% of V
RL = 10kΩ to V
OUT
OUT
CM
Fall Time
90% to 10% of V
A
to V
= 1,
V
= 50mV , RL = 10k
Ω
120
21
ns
µs
µs
µs
µs
µs
µs
V
OUT
P-P
CM
t
Settling Time to 0.1%
10V Step; 10% to V
A
V
= -1,
V
= 10V , RL = 5kΩ to
P-P
s
V
OUT
OUT
OUT
OUT
OUT
Settling Time to 0.01%
10V Step; 10% to V
CM
A
= -1,
V
V
V
= 10V , RL = 5kΩ to
P-P
24
V
V
OUT
Settling Time to 0.1%
4V Step; 10% to V
CM
A
= -1,
= 4V , RL = 5kΩ to
P-P
13
V
V
OUT
Settling Time to 0.01%
4V Step; 10% to V
CM
A
= -1,
= 4V , RL = 5kΩ to
P-P
18
V
V
OUT
CM
t
Output Positive Overload Recovery
Time
A
V
= -100, V = 0.2
V
RL = 2kΩ to
RL = 2kΩ to
5.6
10.6
OL
V
IN
P-P,
P-P,
CM
A = -100, V = 0.2
V
Output Negative Overload
Recovery Time
V
IN
V
CM
April 13, 2010
FN6632.4
5
ISL28117, ISL28217
Electrical Specifications V ± 5V, V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by
S
CM
O
A
characterization.
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 6)
TYP
(Note 6) UNIT
V
Input Offset Voltage; SOIC Package
ISL28x17 B Grade
-50
-110
-100
-190
-150
-250
-0.6
-0.9
-1
4
50
110
100
190
150
250
0.6
0.9
1
µV
µV
OS
ISL28x17 C Grade
ISL28117 C Grade
8
8
µV
µV
Input Offset Voltage; MSOP Package
µV
µV
TCV
Input Offset Voltage Temperature
Coefficient; SOIC Package
ISL28x17 B Grade
ISL28x17 C Grade
ISL28117 C Grade
0.14
0.14
0.14
µV/C
µV/C
µV/C
OS
Input Offset Voltage Temperature
Coefficient; MSOP Package
I
Input Bias Current
-1
-1.5
-5
0.18
1
1.5
5
nA
nA
B
TCI
Input Bias Current Temperature
Coefficient
1
pA/C
B
I
Input Offset Current
-1.5
-1.85
-3
0.3
1.5
1.85
3
nA
nA
OS
TCI
Input Offset Current Temperature
Coefficient
0.42
pA/C
OS
V
Input Voltage Range
-3
120
3
V
dB
CM
CMRR
Common-Mode Rejection Ratio
V
= -3V to +3V
145
145
CM
120
120
dB
PSRR
Power Supply Rejection Ratio
Open-Loop Gain
V = ±2.25V to ±5V
dB
S
120
3,000
dB
A
V
= -3.0V to +3.0V
O
18,000
V/mV
VOL
R = 10kΩ to ground
L
V
Output Voltage High
R
R
= 10kΩ to ground
= 2kΩ to ground
3.5
3.2
3.3
3.1
3.7
3.55
-3.7
-3.55
0.44
43
V
V
OH
L
L
V
V
V
Output Voltage Low
R = 10kΩ to ground
-3.5
-3.2
-3.3
-3.1
0.53
0.68
V
OL
L
V
R = 2kΩ to ground
V
L
V
I
Supply Current/Amplifier
Short-Circuit
mA
mA
mA
S
I
SC
AC SPECIFICATIONS
GBWP Gain Bandwidth Product
A = 1k, R = 2kΩ
1.5
MHz
V
L
April 13, 2010
FN6632.4
6
ISL28117, ISL28217
Electrical Specifications V ± 5V, V
= 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over
the operating temperature range, -40°C to +125°C. Temperature data established by
S
CM
O
A
characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
Voltage Noise
CONDITIONS
0.1Hz to 10Hz
(Note 6)
TYP
0.25
12
(Note 6) UNIT
e
µV
P-P
np-p
e
e
e
e
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
f = 1kHz
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
n
n
n
n
8.6
8
8
in
0.1
TRANSIENT RESPONSE
SR Slew Rate, V
20% to 80%
A =11, R = 2kΩ, V = 4V
0.5
V/µs
ns
OUT
V
L
O
P-P
t , t , Small
Signal
Rise Time
10% to 90% of V
A
= 1,
V
= 50mV ,
P-P
CM
= 50mV ,
P-P
100
r
f
V
OUT
RL = 10kΩ to V
OUT
OUT
Fall Time
90% to 10% of V
A
= 1,
V
120
12
19
7
ns
µs
µs
µs
µs
V
OUT
RL = 10kΩ to V
CM
t
Settling Time to 0.1%
4V Step; 10% to V
A
= -1,
V
= 4V
,
s
V
OUT
P-P
RL = 5kΩ to V
OUT
Settling Time to 0.01%
4V Step; 10% to V
CM
A
= -1,
V
= 4V
,
V
OUT
P-P
RL = 5kΩ to V
OUT
CM
t
Output Positive Overload Recovery Time A = -100, V = 0.2V
OL
V
IN
CM
P-P
P-P
RL = 2kΩ to V
Output Negative Overload Recovery
Time
A
= -100, V = 0.2V
5.8
V
IN
RL = 2kΩ to V
CM
NOTE:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified.
140
140
120
100
80
V
= ±15V
V
= ±5V
S
S
120
100
80
60
40
20
0
60
40
20
0
-50
-30
-10
10
(µV)
30
50
-50
-30
-10
10
(µV)
30
50
V
V
OS
OS
FIGURE 2. V
DISTRIBUTION FOR GRADE B
FIGURE 1. V
DISTRIBUTION for GRADE B
OS
OS
April 13, 2010
FN6632.4
7
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
300
300
250
200
150
100
50
V
= ± 5V
S
V
= ± 15V
S
250
200
150
100
50
0
0
-100
-60
-20
V
20
(µV)
60
100
-100
-60
-20
V
20
(µV)
60
100
OS
OS
FIGURE 4. V
DISTRIBUTION FOR GRADE C
FIGURE 3. V
DISTRIBUTION FOR GRADE C
OS
OS
100
18
16
14
12
10
8
V
= ± 15V
V
= ± 15V
S
S
50
0
6
-50
-100
4
2
0
-50
0
50
100
150
-0.45 -0.30 -0.15
0
0.15
0.30 0.45
V
TC (µV/°C)
TEMPERATURE (°C)
OS
FIGURE 5. V
RANGE vs TEMPERATURE
FIGURE 6. TCV
vs NUMBER OF AMPLIFIERS
OS
OS
100
50
16
14
12
10
8
V
= ±5V
V
= ± 5V
S
S
0
6
-50
4
2
-100
0
-0.45
-0.30 -0.15
0
0.15
0.30
0.45
-50
0
50
TEMPERATURE (°C)
100
150
V
TC (µV/°C)
OS
FIGURE 8. TCV
vs NUMBER OF AMPLIFIERS
FIGURE 7. V
RANGE vs TEMPERATURE
OS
OS
April 13, 2010
FN6632.4
8
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
500
400
300
200
100
0
70
V
= ± 15V
V
= ±15V
S
S
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5 -2.5 -1.5 -0.5 0.5
1.5
2.5
3.5 MORE
I +TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 9. I + RANGE vs TEMPERATURE
FIGURE 10. TCI + vs NUMBER OF AMPLIFIERS
B
B
500
400
300
200
100
0
70
V
= ± 15V
S
V
= ±15V
S
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5 -2.5 -1.5 -0.5 0.5
1.5
2.5
3.5
I -TC (pA/°C)
TEMPERATURE (°C)
B
FIGURE 11. I - RANGE vs TEMPERATURE
FIGURE 12. TCI - vs NUMBER OF AMPLIFIERS
B
B
500
80
V
= ± 5V
V
= ±5V
S
S
400
300
200
100
0
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5 -2.5 -1.5 -0.5
0.5
1.5
2.5
3.5
TEMPERATURE (°C)
I +TC(pA/°C)
B
FIGURE 14. I TC+ vs NUMBER OF AMPLIFIERS
FIGURE 13. I + RANGE vs TEMPERATURE
B
B
April 13, 2010
FN6632.4
9
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
500
400
300
200
100
0
90
V
= ± 5V
S
V
= ±5V
S
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5 -2.5 -1.5 -0.5 0.5
1.5
2.5
3.5
I -TC(pA/°C)
TEMPERATURE (°C)
B
FIGURE 15. I - RANGE vs TEMPERATURE
FIGURE 16. I TC- vs NUMBER OF AMPLIFIERS
B
B
500
90
V
= ± 15V
S
V
= ±15V
S
400
300
200
100
0
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-50
0
50
100
150
-3.5 -2.5 -1.5 -0.5 0.5
1.5
2.5
3.5
TEMPERATURE (°C)
I
TC (pA/°C)
OS
FIGURE 17. I
RANGE vs TEMPERATURE
FIGURE 18. I TC vs NUMBER OF AMPLIFIERS
OS
OS
500
100
V
= ± 5V
V
= ±5V
S
S
400
300
200
100
0
90
80
70
60
50
40
30
20
10
0
-100
-200
-300
-400
-500
-3.5 -2.5 -1.5 -0.5
0.5
1.5
2.5
3.5
-50
0
50
TEMPERATURE (°C)
100
150
I
TC (pA/°C)
OS
FIGURE 19. I
RANGE vs TEMPERATURE
FIGURE 20. I TC vs NUMBER OF AMPLIFIERS
OS
OS
April 13, 2010
FN6632.4
10
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
0.70
0.60
0.50
0.40
0.30
14.4
V
R
= ±15V
= 10kΩ
S
L
±15V
14.2
14.0
13.8
13.6
13.4
13.2
±2.25V
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. SUPPLY CURRENT PER AMP vs
TEMPERATURE
FIGURE 22. +V
vs TEMPERATURE
OUT
-140
-130
-135
-140
-145
-150
-155
-160
V
= ±13V
CM
V
= ±2.25V TO ±20V
S
-145
-150
-155
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 24. CMRR vs TEMPERATURE
FIGURE 23. PSRR vs TEMPERATURE
60
55
50
45
40
35
30
25
60
55
50
45
40
35
30
25
I - @ ±15V
SC
I
+ @ ±15V
SC
-50
0
50
100
150
-50
0
50
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. SHORT CIRCUIT CURRENT vs
TEMPERATURE
FIGURE 26. SHORT CIRCUIT CURRENT vs
TEMPERATURE
April 13, 2010
FN6632.4
11
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
100
20000
15000
10000
V
= ±13V
O
80
60
40
20
0
V
= ±15V
S
+125°C
+25°C
-40°C
-20
-40
-60
-15
-10
-5
0
5
10
15
-50
0
50
100
150
TEMPERATURE (°C)
VCM (V)
FIGURE 28. INPUT V
vs INPUT COMMON MODE
FIGURE 27. AV
vs TEMPERATURE
OS
VOLTAGE, V = ±15V
OL
S
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
100
80
V
R
= ±15V
= 10kΩ
S
L
V
= +5V
S
60
+125°C
40
20
+25°C
-40°C
0
-20
-40
-60
-5
-3
-1
V
1
3
5
-50
0
50
100
150
(V)
TEMPERATURE (°C)
CM
FIGURE 29. V
vs INPUT COMMON MODE VOLTAGE,
FIGURE 30. V
vs TEMPERATURE
OUT
OS
V = ±5V
S
-13.2
-13.4
-13.6
-13.8
-14.0
-14.2
-14.4
14.4
14.2
14.0
13.8
13.6
13.4
13.2
V
R
= +15V
= 2kΩ
V
S
= +15V
= 2kΩ
S
L
R
L
-50
0
50
100
150
-50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
FIGURE 31. V
vs TEMPERATURE
FIGURE 32. V
vs TEMPERATURE
OUT
OUT
April 13, 2010
FN6632.4
12
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
100
250
200
150
100
50
V
= ±18.2V
S
AV = 1
10
0
-50
-100
-150
-200
-250
V+ = 36.4V
= 10, R = 100k
R
g
f
AV = 10,000
1
1
10
100
1k
10k
100k
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (Hz)
TIME (s)
FIGURE 34. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 33. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
1
200
180
160
140
V
= ±18.2V
S
AV = 1
PHASE
120
100
80
60
40
20
0
GAIN
-20
-40
-60
R
= 10k
L
C
= 10pF
L
SIMULATION
-80
-100
0.1
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 36. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
FIGURE 35. INPUT NOISE CURRENT SPECTRAL DENSITY
R = 10kΩ, C = 10pF
L
L
220
200
180
160
140
120
100
80
200
180
160
140
120
100
80
60
40
20
V
= ±2.5V
S
V
= ±5V
S
PHASE
V
= ±15V
S
GAIN
0
-20
-40
-60
60
R
= 10k
L
R
= INF
L
40
C
= 100pF
L
C
= 10pF
L
SIMULATION
20
-80
SIMULATION
-100
0
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1m 10m 100m
1
10 100
1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
FIGURE 38. CMRR vs FREQUENCY, V = ±2.25, ±5V,
S
R = 10kΩ, C = 100pF
±15V
L
L
April 13, 2010
FN6632.4
13
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
120
110
100
90
80
70
60
50
40
30
20
10
0
70
R
= 100, R = 100k
f
g
AV = 1000
AV = 100
AV = 10
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
PSRR+ AND PSRR- VS = ±2.25V
V
C
= ±20V
= 4pF
S
L
R
= 10k
L
R
= INF
= 4pF
L
V
= 50mV
OUT
P-P
C
L
AV = +1
= 1V
V
R
= 10k, R = 100k
f
CM
P-P
g
AV = 1
PSRR+ AND PSRR- VS = ±15V
100 1k 10k 100k
FREQUENCY (Hz)
R
= OPEN, R = 0
f
g
-10
-10
10
100
1k
10k
100k
1M
10M
10M
10
1M
FREQUENCY (Hz)
FIGURE 40. FREQUENCY RESPONSE vs CLOSED LOOP
GAIN
FIGURE 39. PSRR vs FREQUENCY, V = ±5V, ±15V
S
4
2
R
= 10k
L
2
0
R = R = 100k
1
0
f
g
-2
R = R = 10k
-1
-2
-3
-4
-5
-6
-7
-8
f
g
R
= 4.99k
= 1k
L
-4
R = R = 1k
f
g
-6
R
L
R = R = 100
f
g
-8
V
R
= ±20V
= 10k
S
V
C
= ±20V
= 4pF
R
= 499
S
L
L
-10
C
= 4pF
L
L
-12
-14
-16
AV = +1
= 50mV
AV = +2
= 50mV
R
= 100
100k
L
V
V
OUT
P-P
OUT
P-P
10k
10
100
1k
10k
1M
10M
10
100
1k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 41. FREQUENCY RESPONSE vs FEEDBACK
FIGURE 42. GAIN vs FREQUENCY vs R
L
RESISTANCE R /R
f
g
2
1
12
10
8
V
= ±2.25V
S
V
= ±2.5V
= 10k
S
R
V
= ±5V
L
S
0
AV = +1
= 50mV
V
OUT
P-P
6
-1
-2
-3
-4
-5
-6
-7
-8
V
= ±15V
4
S
2
C = 0.01µF
L
C
= 47pF
V = ±20V
S
L
0
-2
-4
-6
-8
C
L
= 4pF
= 10k
C
= 100pF
L
R
L
C
= 4pF
C
= 270pF
L
L
AV = +1
C
= 470pF
L
V
= 50mV
OUT
P-P
1k
FREQUENCY (Hz)
C
= 1000pF
10k
L
10k
10
100
100k
1M
10M
10
100
1k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 44. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
FIGURE 43. GAIN vs FREQUENCY vs C
L
April 13, 2010
FN6632.4
14
ISL28117, ISL28217
Typical Performance Curves V = ±15V, V = 0V, R = Open, unless otherwise
S
CM
L
specified. (Continued)
180
160
140
120
100
80
2.4
2.0
1.6
1.2
0.8
0.4
0
V
= ±15V, RL = 2k, 10k
V = ±5V, RL = 2k, 10k
S
S
V
= ±15V
S
R -Driver Ch. = Open
L
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
R -Receiving Ch. = 10k
L
60
C
= 4pF
L
CL = 4pF
AV = +1
40
AV = +1
V
= 4V
OUT
P-P
V
= 1V
P-P
20
SOURCE
0
10
100
1k
10k
100k
1M
10M
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
FREQUENCY (Hz)
FIGURE 46. LARGE SIGNAL TRANSIENT RESPONSE vs
R V = ±5V, ±15V
FIGURE 45. CROSSTALK, V = ±15V
S
L
S
14
12
10
8
0.04
0
60
50
40
30
20
10
0
INPUT
-0.04
-0.08
-0.12
-0.16
-0.20
-0.24
-0.28
OUTPUT @ VS = ±15V
V
= ±15V
S
R
= 2k
L
RL = 10k
CL = 4pF
AV = +1
6
C
= 4pF
L
AV = -100
4
R = 100k, R = 1k
f
g
V
= 50mV
OUT
P-P
V
= 200mV
IN
P-P
2
0
OUTPUT @ V = ±5V
S
-2
-10
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
0
5
10
15
20
TIME (µs)
25
30
35
40
FIGURE 48. POSITIVE OUTPUT OVERLOAD RESPONSE
FIGURE 47. SMALL SIGNAL TRANSIENT RESPONSE,
TIME, V = ±5V, ±15V
V = ±5V, ±15V
S
S
80
0.24
0.20
4
V
L
= ±15V
= 10k
S
R
70
60
50
40
30
20
10
0
2
OUTPUT @ V = ±5V
S
AV = 1
= 50mV
V
0.16
0.12
0.08
0.04
0
0
OUT
P-P
R
= 2k
-2
-4
-6
-8
-10
-12
L
C
= 4pF
L
AV = -100
R = 100k, R = 1k
f
g
V
= 200mV
IN
P-P
INPUT
OUTPUT @ V = ±15V
S
-0.04
-0.08
1
10
100
CAPACITANCE (pF)
1k
10k
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
FIGURE 50. % OVERSHOOT vs LOAD CAPACITANCE,
FIGURE 49. NEGATIVE OUTPUT OVERLOAD RESPONSE
V = ±15V
TIME, V = ±5V, ±15V
S
S
April 13, 2010
FN6632.4
15
ISL28117, ISL28217
Applications Information
Functional Description
V+
The ISL28117 and ISL28217 are single and dual, low
noise precision op amps. Both devices are fabricated in a
new precision 40V complementary bipolar DI process. A
super-beta NPN input stage with input bias current
cancellation provides low input bias current (180pA
typical), low input offset voltage (13µV typical), low input
noise voltage (8nV/√Hz), and low 1/f noise corner
frequency (~8Hz). These amplifiers also feature high
open loop gain (18kV/mV) for excellent CMRR (145dB)
500Ω
V
OUT
500Ω
V
R
IN
L
V-
FIGURE 51. INPUT ESD DIODE CURRENT LIMITING-
UNITY GAIN
and THD+N performance (0.0005% @ 3.5V
into 2kΩ). A complimentary bipolar output stage enables
, 1kHz
RMS
The series resistors limit the high feed-through currents
that can occur in pulse applications when the input
dV/dT exceeds the 0.5V/µs slew rate of the amplifier.
Without the series resistors, the input can forward-bias
the anti-parallel diodes causing current to flow to the
output resulting in severe distortion and possible diode
failure. Figure 46 provides an example of distortion free
high capacitive load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V
(±2.25V) to 40V (±20V) range and are fully
characterized at 10V (±5V) and 30V (±15V). The Power
Supply Rejection Ratio typically exceeds 140dB over the
full operating voltage range and 120dB minimum over
the -40°C to +125°C temperature range. The worst case
common mode input voltage range over temperature is
2V to each rail. With ±15V supplies, CMRR performance
is typically >130dB over-temperature. The minimum
CMRR performance over the -40°C to +125°C
large signal response using a 4V
input pulse with an
P-P
input rise time of <1ns. The series resistors enable the
input differential voltage to be equal to the maximum
power supply voltage (40V) without damage.
In applications where one or both amplifier input
terminals are at risk of exposure to high voltages beyond
the power supply rails, current limiting resistors may be
needed at the input terminal to limit the current through
the power supply ESD diodes to 20mA max.
temperature range is >120dB for power supply voltages
from ±5V (10V) to ±15V (30V).
Input Performance
Output Current Limiting
The super-beta NPN input pair provides excellent
frequency response while maintaining high input
precision. High NPN beta (>1000) reduces input bias
current while maintaining good frequency response, low
input bias current and low noise. Input bias cancellation
circuits provide additional bias current reduction to
<1nA, and excellent temperature stabilization. Figures 9
through 16 show the high degree of bias current stability
at ±5V and ±15V supplies that is maintained across the
-40°C to +125°C temperature range. The low bias
current TC also produces very low input offset current
TC, which reduces DC input offset errors in precision,
high impedance amplifiers.
The output current is internally limited to approximately
±45mA at +25°C and can withstand a short circuit to
either rail as long as the power dissipation limits are not
exceeded. This applies to only 1 amplifier at a time for
the dual op amp. Continuous operation under these
conditions may degrade long term reliability. Figures 25
and 26 show the current limit variation with temperature.
Output Phase Reversal
Output phase reversal is a change of polarity in the
amplifier transfer function when the input voltage
exceeds the supply voltage. The ISL28117 and ISL28217
are immune to output phase reversal, even when the
input voltage is 1V beyond the supplies.
The +25°C maximum input offset voltage (V ) for the
OS
“B” grade is 50µV and 100µV for the “C” grade. Input
offset voltage temperature coefficients (V TC) are a
Power Dissipation
OS
maximum of ±0.6µV/°C for the “B” and ±0.9µV/°C for the
“C” grade. Figures 1 through 4 show the typical gaussian-
like distribution over the ±5V to ±15V supply range and
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply
conditions. It is therefore important to calculate the
over the full temperature range. The V
behavior is smooth (Figures 5 through 8) maintaining
temperature
OS
maximum junction temperature (T
) for all
JMAX
applications to determine if power supply voltages, load
conditions, or package type need to be modified to
remain in the safe operating area. These parameters are
related using Equation 1:
constant TC across the entire temperature range.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD
protection diodes to the positive and negative supply
rails, series connected 500Ω current limiting resistors
and an anti-parallel diode pair across the inputs
(Figure 51).
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
April 13, 2010
FN6632.4
16
ISL28117, ISL28217
where:
• P
LICENSE STATEMENT
The information in this SPICE model is protected under
the United States copyright laws. Intersil Corporation
hereby grants users of this macro-model hereto referred
to as “Licensee”, a nonexclusive, nontransferable licence
to use this model as long as the Licensee abides by the
terms of this agreement. Before using this macro-model,
the Licensee should read this license. If the Licensee
does not accept these terms, permission to use the
model is not granted.
is the sum of the maximum power
DMAXTOTAL
dissipation of each amplifier in the package (PD
)
MAX
• PD
for each amplifier can be calculated using
MAX
Equation 2:
V
OUTMAX
R
L
----------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
MAX
S
qMAX
S
(EQ. 2)
where:
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to
anyone outside the Licensee’s company. The Licensee
may modify the macro-model to suit his/her specific
applications, and the Licensee may make copies of this
macro-model for use within their company only.
• T
= Maximum ambient temperature
MAX
• θ = Thermal resistance of the package
JA
• PD
= Maximum power dissipation of 1 amplifier
MAX
• V = Total supply voltage
S
This macro-model is provided “AS IS, WHERE IS, AND
WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED
OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY
IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE.”
• I
= Maximum quiescent supply current of
1 amplifier
qMAX
• V
application
= Maximum output voltage swing of the
OUTMAX
In no event will Intersil be liable for special, collateral,
incidental, or consequential damages in connection with
or arising out of the use of this macro-model. Intersil
reserves the right to make changes to the product and
the macro-model without prior notice.
ISL28117 and ISL28217 SPICE Model
Figure 52 shows the SPICE model schematic and
Figure 53 shows the net list for the ISL28117 and
ISL28217 SPICE model for a Grade “B” part. The model
is a simplified version of the actual device and simulates
important AC and DC parameters. AC parameters
incorporated into the model are: 1/f and flatband noise,
Slew Rate, CMRR, Gain and Phase. The DC parameters
are VOS, IOS, total supply current and output voltage
swing. The model uses typical parameters given in the
“Electrical Specifications” Table beginning on page 4.
The AVOL is adjusted for 155dB with the dominate pole
at 0.02Hz. The CMRR is set (210dB, f
= 10Hz). The
cm
input stage models the actual device to present an
accurate AC representation. The model is configured for
ambient temperature of +25°C.
Figures 54 through 64 show the characterization vs
simulation results for the Noise Voltage, Closed Loop
Gain vs Frequency, Closed Loop Gain vs RL, Large Signal
Step Response, Open Loop Gain Phase and Simulated
CMRR vs Frequency.
April 13, 2010
FN6632.4
17
ISL28117, ISL28217
.
V++
V++
R3
R4
IEE1
4
5
96E-6
4.45k
4.45k
4
5
CASCODE
CASCODE
6
7
Q4
Q5
3
D1
DX
C4
2
2pF
SUPERB
SUPERB
Vin-
V5
V
-
Q1 Q2
IN
C5
2pF
R1
8
5E11
24
25
EOS
C6
1.2pF
1
IOS
Mirror
Vc
D12
DN
0.1V
R17
VCM
+
-
+
-
Vmid
Q3
0.3nA
9
+
-
IEE
R2
200E-6
290
In+
VOS
5E11
En
13E-6
V
+
IN
V--
VCM
Voltage Noise
Input Stage
V++
V++
D2
DX
D4
DX
G1
G3
G5
L1
13
10
4
15.9159E
+
+
+
-
+
-
+
-
R5
1
R7
C2
R9
V1
V3
17
400pF
2.1E3
R11
1
1.86V
1.86V
1.99e10
-
-
5
11
Vc
Vg
Vmid
Vg
Vc
R12
1
R6
1
R8
R10
C3
Vmid
G4
G6
G2
2.1E3
1.99e10
400pF
18
+
-
+
-
-
+
-
+
-
+
V4
V2
L2
1.86V
1.86V
12
14
VCM
15.9159E
D5
DX
D3
DX
V--
V--
VCM
ST
nd
Mid Supply Ref
Common Mode Gain Stage
1
Gain Stage
2
Gain Stage
V++
D8
DX
D9
DX
G7
V+
V+
+
-
+
E2
R15
90
-
-
+
22
23
V5
DX
DX
D6
20
21
ISY
0.44mA
V
OUT
VOUT
1.12V
Vg
V6
D7
1.12V
R16
90
V-
G8
-
+
+
-
+
-
-
+
D10
DY
D11
DY
-
E3
V-
+
V--
G9
G10
Supply Isolation Stage
Output Stage
FIGURE 52. SPICE SCHEMATIC
April 13, 2010
FN6632.4
18
ISL28117, ISL28217
* source ISL28117_SPICEmodel
R_R7
VG V++ 1.99e10
V-- VG 1.99e10
VG V++ 4e-10
V-- VG 4e-10
13 V++ DX
* Revision B, November 20th 2009 LaFontaine
* Model for Grade B Noise, supply currents, 210dB
f=10Hz CMRR, 155dB f=0.02Hz AOL, SR = 0.5V/µsec
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
R_R8
C_C2
C_C3
D_D4
D_D5
V_V3
V_V4
*
V-- 14 DX
13 VG 1.86
VG 14 1.86
*
*
*
*
*
|
|
|
|
|
-input
*Mid supply Ref
|
|
|
|
+Vsupply
R_R9
R_R10
I_ISY
E_E2
E_E3
*
VMID V++ 2.1E3
|
|
|
-Vsupply
V-- VMID 2.1E3
V+ V- DC 0.44E-3
V++ 0 V+ 0 1
|
|
output
|
.subckt ISL28117subckt Vin+ Vin-V+ V- VOUT
V-- 0 V- 0 1
* source ISL28107subckt
*
*Common Mode Gain Stage with Zero
*Voltage Noise
G_G5
G_G6
R_R11
R_R12
L_L1
L_L2
*
V++ VC VCM VMID 3.162277
V-- VC VCM VMID 3.162277
E_En
IN+ VIN+ 25 0 1
25 0 290
R_R17
D_D12
V_V7
VC 17
18 VC
1
1
24 25 DN
24 0 0.1
17 V++ 15.9159E-3
18 V-- 15.9159E-3
*
*Input Stage
I_IOS
C_C6
IN+ VIN- DC 0.08E-9
IN+ VIN- 1.2E-12
VCM VIN- 5e11
IN+ VCM 5e11
2 VIN- 1 SuperB
3 8 1 SuperB
*Output Stage with Correction Current Sources
G_G7
G_G8
G_G9
G_G10
D_D6
D_D7
D_D8
D_D9
D_D10
D_D11
V_V5
V_V6
R_R15
R_R16
*
VOUT V++ V++ VG 1.11e-2
V-- VOUT VG V-- 1.11e-2
22 V-- VOUT VG 1.11e-2
23 V-- VG VOUT 1.11e-2
VG 20 DX
R_R1
R_R2
Q_Q1
Q_Q2
Q_Q3
V-- 1 7 Mirror
4 6 2 Cascode
5 6 3 Cascode
4 V++ 4.45e3
21 VG DX
Q_Q4
V++ 22 DX
Q_Q5
V++ 23 DX
R_R3
V-- 22 DY
R_R4
5 V++ 4.45e3
V-- 23 DY
C_C4 VIN- 0 2e-12
C_C5 8 0 2e-12
20 VOUT 1.12
VOUT 21 1.12
D_D1
I_IEE
I_IEE1
V_VOS
E_EOS
*
6 7 DX
VOUT V++ 9E1
1 V-- DC 200e-6
V++ 6 DC 96e-6
9 IN+ 8e-6
V-- VOUT 9E1
.model SuperB npn
8 9 VC VMID 1
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
*1st Gain Stage
G_G1
G_G2
R_R5
R_R6
D_D2
D_D3
V_V1
V_V2
*
V++ 11 4 5 8.129384e-2
.model Cascode npn
V-- 11 4 5 8.129384e-2
11 V++ 1
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
V-- 11
1
10 V++ DX
V-- 12 DX
10 11 1.86
11 12 1.86
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
*2nd Gain Stage
G_G3
G_G4
V++ VG 11 VMID 2.83e-3
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28117subckt
V-- VG 11 VMID 2.83e-3
FIGURE 53. SPICE NET LIST
April 13, 2010
FN6632.4
19
ISL28117, ISL28217
Characterization vs Simulation Results
100
100
10
1
V
= ±18.2V
S
AV = 1
10
1.0
1.0
10
100
1.0k
10k
100k
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 54. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 55. SIMULATED INPUT NOISE VOLTAGE
70
70
R
= 100, R = 100k
f
R
= 100, R = 100k
f
AV = 1000
AV = 100
AV = 10
g
g
AV = 1000
AV = 100
AV = 10
60
40
20
60
50
40
30
20
10
0
R
= 1k, R = 100k
f
g
R
= 1k, R = 100k
f
g
V
C
= ±20V
= 4pF
V
= ±15V
= 4pF
S
L
S
C
L
R
= 10k
R
= 10k
L
L
V
= 50mV
V
= 50mV
OUT
P-P
OUT
P-P
R
= 10k, R = 100k
f
R
= 10k, R = 100k
f
g
g
AV = 1
AV = 1
0
R
g
= OPEN, R = 0
f
R
= OPEN, R = 0
g
f
-10
10
-10
1k
10k
100k
1M
10M
10
100
100
1.0k
10k
100k
1.0M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 57. SIMULATED CLOSED LOOP GAIN vs
FREQUENCY
FIGURE 56. CHARACTERIZED CLOSED LOOP GAIN vs
FREQUENCY
1
2
R
= 10k
L
R
= 10k
L
1
0
0
-2
-4
-6
-8
R
= 4.99k
L
-1
-2
-3
-4
-5
-6
-7
-8
R
= 1k
L
R
= 4.99k
= 1k
L
R
L
V
= ±15V
= 4pF
S
V
= ±20V
= 4pF
R
= 499
R
= 499
S
L
L
C
L
C
L
AV = +1
AV = +1
R
=100
L
V
= 50mV
R
= 100
100k
OUT
P-P
L
V
= 50mV
OUT
P-P
10
100
1.0k
10k
100k
1.0M
10M
10
100
1k
10k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 59. SIMULATED CLOSED LOOP GAIN vs R
FIGURE 58. CHARACTERIZED CLOSED LOOP GAIN vs
L
R
L
April 13, 2010
FN6632.4
20
ISL28117, ISL28217
Characterization vs Simulation Results (Continued)
3
2.4
2.0
1.6
1.2
0.8
0.4
0
2
INPUT
V
= ±15V, RL =10k
S
OUTPUT
1
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-1
-2
-3
CL = 4pF
AV = +1
C
= 4pF
L
AV = +1
V
V
= 4V
OUT
P-P
= 4V
OUT
P-P
0
20
40
TIME (µs)
60
80
100
0
10 20 30 40 50 60 70 80 90 100
TIME (µs)
FIGURE 61. SIMULATED LARGE SIGNAL 10V STEP
RESPONSE
FIGURE 60. CHARACTERIZED LARGE SIGNAL
TRANSIENT RESPONSE vs R V = ±15V
L
S
200
160
200
180
160
140
120
100
80
PHASE
PHASE
120
60
40
80
20
0
GAIN
40
GAIN
-20
-40
-60
-80
-100
R
= 10k
L
0
C
= 10pF
L
SIMULATION
-40
0.1m 1m 10m 100m
1
10 100 1k 10k 100k 1M 10M 100M
1.0m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 62. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 63. SIMULATED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
250
200
150
100
50
1m 10m 0.1
1
10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 64. SIMULATED CMRR vs FREQUENCY
April 13, 2010
FN6632.4
21
ISL28117, ISL28217
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
3/18/10
FN6632.4
1. Updated “Ordering Information” on page 2 by adding two rows for MSOP packages
ISL28117FUBZ and ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout
accordingly.
2. Added POD for MSOP M8.118 to the end of datasheet
3. In “Ordering Information” on page 2, Separated each part number with it's own specific -
T7 and -T13 suffix and removed “Add “-T7” or “-T13” suffix for Tape and Reel.” from Note 1.
4. Updated ±15 and ±5V Electrical Specification table with the following edits:
A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs
for MSOP Grade C package.
B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS
specs for MSOP Grade C package.
5. Added “Thermal Information” on page 4 for ISL28117 MSOP package.
3/3/10
Added “Related Literature*(see page 23)” on page 1.
Added Evaluation Boards to “Ordering Information” on page 2.
Added Theta JC values to “Thermal Information” on page 4. Added applicable Theta JC Note 5.
Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W.
1/21/10
Part marking in “Ordering Information” on page 2 changed as follows:
ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ"
ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C"
ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ"
ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C"
12/24/09
11/25/09
On page 7: Changed label in Figure 1 from “V = +5V” to “V = ±5V”
S S
On page 7: Changed label in Figure 2 from “V = +15V” to “V = ±15V”
S
S
Changed Typical VOS spec from “13” to “8” (B Grade), “19” to “4” (C Grade), IB from “0.18”
to “0.08, IOS from “0.3” to “0.08”. Edited Spice Schematic - L1 from “95.4957” to “15.9159E”,
R1 from “6k” to 1, R9 from “1” to “2.1E3”, R10 from “1” to “2.1E3, R12 from “6k” to “1”, L2
from “95.4957” to “15.9159E”. Edited Spice Net List - Changed Revision from “A” to “B”, Date
change from “October 29th 2009” to “November 20th 2009”, added after AOL “SR =
0.5V/µsec, Input Stage changed in I_IOS from “0.3E-9” to 0.08E-9”, V_VOS “13e-6” to
“8e-6”, Mid supply Ref R_R9 and R_R10 changed “1” to “2.1E3”, Common Mode Gain Stage
with Zero change in G_G5 and G_G6 “5.27046e-15” to “3.162277”, R_R11 and R_R12 “6.3”
to “1”, L_L1 and L_L2 “95.4957” to “15.9159E-3”
11/12/09
10/16/09
FN6632.3
FN6632.2
Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model
and license statement. Replaced typical application schematic on page 1.
On page 2 “Ordering Information”, changed the following:
a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B".
Corrected part marking for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B"
B) Updated package outline drawing to most recent revision (no changes were made to
package dimensions; land pattern was added and dimensions were moved from table onto
drawing)
c) Added "Add “-T7” or “-T13” suffix for tape and reel." to the tape and reel Note 1.
d) added Note 3 callout to all parts (Note 3 reads: "For Moisture Sensitivity Level (MSL), please
see device information page for ISL28117, ISL28217. For more information on MSL please see
techbrief TB363.")
e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices
April 13, 2010
FN6632.4
22
ISL28117, ISL28217
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev. (Continued)
DATE
REVISION
CHANGE
10/08/09
FN6632.1
1. Removed “very” from “...low noise..” 1st sentence, page 1.
2. Removed “Low” from 6th bullet under features, page 1.
3. Modified typical characteristics curves to show conservative performance. Specific channel
designations removed. On temperature curves, changed formatting to indicate range from
typical value. Changes include:
a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34,
37 & 38 (all Channel A curves)
b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures
9 thru 20 (all “conservative channels”)
c. Added Figures 30, 31, 32
4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same
graphic)
5. Added temp labels to Figures 28 & 29
09/03/09
FN6632.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL28117, ISL28217
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
April 13, 2010
23
FN6632.4
ISL28117, ISL28217
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
April 13, 2010
FN6632.4
24
ISL28117, ISL28217
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.25 - 0.036
0.10 C
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
April 13, 2010
FN6632.4
25
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