ISL28118 [INTERSIL]
40V Precision Single-Supply, Rail-to-Rail Output, Low-Power; 40V精密单电源，轨到轨输出，低功耗
| 型号： | ISL28118 |
| 厂家： | 
Intersil |
| 描述： | 40V Precision Single-Supply, Rail-to-Rail Output, Low-Power |
| 文件： | 总28页 (文件大小：1541K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
40V Precision Single-Supply, Rail-to-Rail Output,
Low-Power Operational Amplifiers
ISL28118, ISL28218
Features
The ISL28118 and ISL28218 are single and dual, low-power
precision amplifiers optimized for single-supply applications.
These devices feature a common mode input voltage range
extending to 0.5V below the V- rail, a rail-rail differential input
voltage range for use as a comparator, and rail-to-rail output
voltage swing, which makes them ideal for single-supply
applications where input operation at ground is important.
• Rail-to-Rail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV
• Below-Ground (V-) Input Capability to -0.5V
• Rail-to-Rail Input Differential Voltage Range for Comparator
Applications
• Single-Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V
• Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 850µA
• Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/√Hz
• Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/√Hz
These op amps feature low power, low offset voltage, and low
temperature drift, making them the ideal choice for
applications requiring both high DC accuracy and AC
performance. These amplifiers are designed to operate over a
single supply range of 3V to 40V or a split supply voltage range
of +1.8V/-1.2V to ±20V. The combination of precision and
small footprint provides the user with outstanding value and
flexibility relative to similar competitive parts.
• Low Input Offset Voltage
- ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µV Max.
- ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230µV Max.
• Superb Offset Voltage Temperature Drift
- ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2µV/°C, Max.
- ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4µV/°C, Max.
Applications for these amplifiers include precision
instrumentation, data acquisition, precision power supply
controls, and industrial controls.
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
• No Phase Reversal
Both parts are offered in 8 Ld TDFN, 8 Ld SOIC and 8 Ld MSOP
packages. All devices are offered in standard pin
configurations and operate over the extended temperature
range of -40°C to +125°C.
Applications
• Precision Instruments
• Medical Instrumentation
• Data Acquisition
Related Literature
• AN1595: ISL28218SOICEVAL1Z Evaluation Board User’s
Guide
• Power Supply Control
• Industrial Process Control
R
F
400
300
100kΩ
LOAD
+3V
to 40V
R
-
IN
IN-
200
-
V
-40°C
OUT
V+
ISL28118
10kΩ
R
SENSE
100
0
+25°C
R
+
V-
IN
+125°C
IN+
+
-100
-200
-300
-400
10kΩ
GAIN = 10
R
+
REF
100kΩ
V
REF
-16
-15
-14
-13 13
14
15
16
INPUT COMMON MODE VOLTAGE (V)
FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE
CURRENT SENSE AMPLIFIER
May 16, 2011
FN7532.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL28118, ISL28218
Pin Configurations
ISL28118
(8 LD TDFN)
TOP VIEW
ISL28118
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
NC
-IN
1
2
3
4
8
7
6
5
NC
NC
NC
1
2
3
4
8
7
6
5
V
-IN
V
+
- +
+
- +
+IN
VOUT
NC
+IN
VOUT
NC
PD
V
V
-
-
ISL28218
(8 LD TDFN)
TOP VIEW
ISL28218
(8 LD SOIC, 8 LD MSOP)
TOP VIEW
VOUT_A
-IN_A
1
2
3
4
8
7
6
5
V
+
VOUT_A
V
+
1
2
3
4
8
7
6
5
VOUT B
_
-
+
-IN_A
+IN_A
VOUT_B
-IN_B
- +
+IN_A
-IN_B
+IN_B
+
-
+
-
PD
V
-
+IN_B
V
-
Pin Descriptions
ISL28118
(8 LD SOIC,
MSOP)
ISL28218
(8 LD SOIC,
MSOP)
ISL28118
(8 LD TDFN)
ISL28218
(8 LD TDFN)
PIN
NAME
EQUIVALENT
CIRCUIT
DESCRIPTION
3
2
6
4
3
2
6
4
3
2
3
2
1
4
5
6
7
8
-
+IN_A
-IN_A
VOUT_A
V-
1
1
2
3
1
1
2
3
-
Amplifier A non-inverting input
Amplifier A inverting input
Amplifier A output
1
4
Negative power supply
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
5
+IN_B
-IN_B
VOUT_B
V+
6
7
7
7
8
Positive power supply
No Connect
1, 5, 8
PAD
1, 5, 8
-
NC
PAD
PAD
Thermal Pad is electrically isolated from active
circuitry. Pad can float, connect to Ground, or connect
to a potential source that is free from signals or noise
sources.
V
+
V
+
V
+
CAPACITIVELY
TRIGGERED ESD
CLAMP
OUT
IN-
IN
+
V
-
V
-
V
-
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
FN7532.2
May 16, 2011
2
ISL28118, ISL28218
Ordering Information
PART NUMBER
(Notes 2, 3)
TEMPERATURE RANGE
PACKAGE
(Pb-Free)
PKG.
DWG. #
PART MARKING
(°C)
ISL28118FBZ (Note 1)
28118 FBZ
-40 to +125
8 Ld SOIC
M8.15E
Coming Soon
ISL28118FRTZ (Note 1)
118Z
-40 to +125
-40 to +125
-40 to +125
8 Ld TDFN
8 Ld MSOP
8 Ld SOIC
L8.3x3A
M8.118
M8.15E
ISL28118FUZ (Note 1)
ISL28218FBZ (Note 1)
8118Z
28218 FBZ
Coming Soon
ISL28218FRTZ
218Z
-40 to +125
-40 to +125
8 Ld TDFN
8 Ld MSOP
L8.3x3A
M8.118
Coming Soon
ISL28218FUZ
8218Z
ISL28218SOICEVAL1Z
NOTES:
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL28118, ISL28218. For more information on MSL, please see
Technical Brief TB363.
FN7532.2
May 16, 2011
3
ISL28118, ISL28218
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V
Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite
ESD Tolerance
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per CDM-22CI0ID). . . . . . . . . . . . . . . 2kV
Thermal Resistance (Typical)
ISL28118
θ
JA (°C/W)
θ
JC (°C/W)
8 Ld TDFN Package (Notes 5, 6). . . . . . . . . .
8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . .
8 Ld MSOP Package (Notes 4, 7) . . . . . . . . .
ISL28218
8 Ld TDFN Package (Notes 5, 6). . . . . . . . . .
8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . .
8 Ld MSOP Package (Notes 4, 7) . . . . . . . . .
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
50
120
165
9
60
57
48
120
150
5.5
55
45
Operating Conditions
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 40V (±20V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the
operating temperature range, -40°C to +125°C. Temperature data established by characterization.
MIN
MAX
PARAMETER
VOS
DESCRIPTION
Input Offset Voltage
CONDITIONS
(Note 8)
TYP
25
(Note 8)
UNIT
µV
ISL28118
ISL28218
-150
-270
-230
-290
-1.2
150
270
230
290
1.2
µV
40
µV
µV
TCVOS
ΔVOS
IB
Input Offset Voltage Temperature ISL28118
Coefficient
0.2
0.3
44
µV/°C
µV/°C
µV
ISL28218
-1.4
1.4
Input Offset Voltage Match
(ISL28218 only)
-280
-365
-575
-800
280
365
µV
Input Bias Current
-230
nA
nA
TCIB
IOS
Input Bias Current
Temperature Coefficient
-0.8
4
nA/°C
Input Offset Current
-50
-75
50
75
nA
nA
FN7532.2
May 16, 2011
4
ISL28118, ISL28218
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the
operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN
MAX
PARAMETER
CMRR
DESCRIPTION
CONDITIONS
(Note 8)
TYP
118
118
(Note 8)
UNIT
dB
dB
dB
dB
dB
dB
dB
V
Common-Mode Rejection Ratio
VCM = V- - 0.5V to V+ - 1.8V
V
CM = V- to V+ -1.8V
102
98
ISL28118 SOIC
V
CM = V- to V+ -1.8V
ISL28118 MSOP
102
97
118
118
V
CM = V- to V+ -1.8V
103
99
ISL28218
VCMIR
PSRR
AVOL
Common Mode Input Voltage
Range
Guaranteed by CMRR test
V- - 0.5
V-
V+ - 1.8
V+ - 1.8
V
Power Supply Rejection Ratio
Open-Loop Gain
V
S = 3V to 40V, VCMIR = Valid Input Voltage
109
105
125
120
125
122
120
116
124
136
136
136
dB
dB
dB
dB
dB
dB
dB
dB
mV
mV
mV
mV
mV
mV
VO = -13V to +13V, RL = 10kΩ to ground,
ISL28118 SOIC
V
O = -13V to +13V, RL = 10kΩ to ground,
ISL28218
V
O = -13V to +13V, RL = 10kΩ to ground,
ISL28118 MSOP
VOL
Output Voltage Low, VOUT to V- ,
See Figure 32
ISL28118
RL = 10kΩ
70
85
ISL28218
RL = 10kΩ
70
73
VOH
Output Voltage High, V+ to VOUT
See Figure 32
ISL28118
ISL28218
RL = 10kΩ
110
120
IS
Supply Current/Amplifier
ISL28118
RL = Open
0.85
0.85
1.2
1.6
1.1
1.4
mA
mA
mA
mA
mA
ISL28218
RL = Open
ISC+
Output Short Circuit Source
Current
RL = 10Ω to V-
16
28
ISC-
Output Short Circuit Sink Current RL = 10Ω to V+
Supply Voltage Range Guaranteed by PSRR
mA
V
VSUPPLY
3
40
AC SPECIFICATIONS
GBWP
enp-p
en
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P; RL = 2k
0.1Hz to 10Hz, VS = ±18V
f = 10Hz, VS = ±18V
4
MHz
Voltage Noise
300
8.5
5.8
5.6
5.6
nVP-P
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
en
f = 100Hz, VS = ±18V
en
f = 1kHz, VS = ±18V
en
f = 10kHz, VS = ±18V
FN7532.2
May 16, 2011
5
ISL28118, ISL28218
Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the
operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
f = 1kHz, VS = ±18V
(Note 8)
TYP
355
(Note 8)
UNIT
fA/√Hz
%
in
THD + N
TRANSIENT RESPONSE
Current Noise Density
Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ
0.0003
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 10VP-P
±1.2
100
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to
VCM
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
100
8.5
ns
µs
RL = 2kΩ to VCM
ts
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = 1, VOUT = 10VP-P, Rf = 0Ω
RL = 2kΩ to VCM
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +125°C. Temperature data established by characterization.
MIN
MAX
PARAMETER
VOS
DESCRIPTION
Input Offset Voltage
CONDITIONS
(Note 8)
TYP
25
(Note 8)
UNIT
µV
ISL28118
ISL28218
-150
-270
-230
-290
-1.2
150
270
230
290
1.2
µV
40
µV
µV
TCVOS
ΔVOS
IB
Input Offset Voltage Temperature
Coefficient
ISL28118
ISL28218
0.2
0.3
44
µV/°C
µV/°C
µV
-1.4
1.4
Input Offset Voltage Match
(ISL28218 only)
-280
-365
-575
-800
280
365
µV
Input Bias Current
-230
nA
nA
TCIB
IOS
Input Bias Current
Temperature Coefficient
-0.8
4
nA/°C
Input Offset Current
-50
-75
50
75
nA
nA
dB
dB
dB
dB
dB
dB
dB
V
CMRR
Common-Mode Rejection Ratio
V
CM = V- - 0.5V to V+ - 1.8V
CM = V- to V+ -1.8V
119
117
V
101
97
ISL28118 SOIC
VCM = V- to V+ -1.8V
101
96
117
117
ISL28118 MSOP
VCM = V- to V+ -1.8V
101
97
ISL28218
VCMIR
Common Mode Input Voltage
Range
Guaranteed by CMRR test
V- - 0.5
V-
V+ - 1.8
V+ - 1.8
V
FN7532.2
May 16, 2011
6
ISL28118, ISL28218
Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)
MIN
MAX
PARAMETER
PSRR
DESCRIPTION
CONDITIONS
(Note 8)
TYP
124
(Note 8)
UNIT
dB
Power Supply Rejection Ratio
VS = 3V to 10V, VCMIR = Valid Input Voltage,
ISL28118 SOIC
109
105
dB
ISL28218 SOIC
ISL28118 MSOP
108
103
122
117
124
132
dB
dB
dB
dB
AVOL
Open-Loop Gain
VO = -3V to +3V, RL = 10kΩ to ground,
ISL28118 SOIC
ISL28218 SOIC
ISL28118 MSOP
RL = 10kΩ
120
115
132
dB
dB
VOL
VOH
IS
Output Voltage Low, VOUT to V- ,
See Figure 32
38
45
65
70
1.1
1.4
mV
mV
mV
mV
mA
µA
Output Voltage High, V+ to VOUT
See Figure 31
RL = 10kΩ
Supply Current/Amplifier
RL = Open
0.85
ISC+
ISC-
AC SPECIFICATIONS
Output Short Circuit Source Current RL = 10Ω to V-
13
20
mA
mA
Output Short Circuit Sink Current
RL = 10Ω to V+
GBWP
enp-p
en
Gain Bandwidth Product
ACL = 101, VOUT = 100mVP-P; RL = 2k
3.2
320
9
MHz
nVP-P
Voltage Noise
0.1Hz to 10Hz
f = 10Hz
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Voltage Noise Density
Current Noise Density
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
%
en
f = 100Hz
f = 1kHz
5.7
en
5.5
en
f = 10kHz
f = 1kHz
5.5
in
380
0.0003
THD + N
Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 1.25VRMS, RL = 10kΩ
TRANSIENT RESPONSE
SR
Slew Rate
AV = 1, RL = 2kΩ, VO = 4VP-P
±1
V/µs
ns
tr, tf, Small
Signal
Rise Time
10% to 90% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to
VCM
100
Fall Time
90% to 10% of VOUT
AV = 1, VOUT = 100mVP-P, Rf = 0Ω,
100
4
ns
µs
RL = 2kΩ to VCM
ts
Settling Time to 0.01%
4V Step; 10% to VOUT
AV = 1, VOUT = 4VP-P, Rf = 0Ω
RL = 2kΩ to VCM
NOTE:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN7532.2
May 16, 2011
7
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
200
150
100
50
200
150
100
50
V
= ±15V
V = ±5V
S
S
0
0
V
(µV)
V
(µV)
OS
OS
FIGURE 3. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 4. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION
250
250
V
= ±15V
V = ±5V
S
S
200
150
100
50
200
150
100
50
0
0
V
(µV)
V
(µV)
OS
OS
FIGURE 5. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 6. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION
18
18
V
= ±15V
V = ±5V
S
S
16
14
12
10
8
16
14
12
10
8
6
6
4
4
2
2
0
0
TCV (µV/C)
TCV (µV/C)
OS
OS
FIGURE 7. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±15V
FIGURE 8. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±5V
FN7532.2
May 16, 2011
8
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
30
25
20
15
10
5
35
30
25
20
15
10
5
V
= ±5V
V
= ±15V
S
S
0
0
TCV (µV/C)
TCV (µV/C)
OS
OS
FIGURE 9. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±15V
FIGURE 10. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±5V
400
300
100
90
80
200
70
-40°C
100
0
+25°C
60
V
= ±15V
S
+125°C
50
40
30
20
10
0
-100
-200
-300
-400
V
= ±5V
20
S
-16
-15
-14
-13 13
14
15
16
-40
-20
0
40
60
80
100
120
TEMPERATURE (°C)
INPUT COMMON MODE VOLTAGE (V)
FIGURE 11. VOS vs TEMPERATURE
FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE
VOLTAGE, VS = ±15V
-150
0
-50
V
= ±20V
S
-200
-250
-300
-350
-400
-100
-150
-200
-250
-300
-350
-400
-450
-500
V
= ± 15V
S
V
= +2V/-1V
S
V
= ±2.25V
40
S
V
= ±5V
80
S
-40
-20
0
20
60
100
120
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
(V)
V
TEMPERATURE (°C)
S
FIGURE 13. IBIAS vs VS
FIGURE 14. IBIAS vs TEMPERATURE vs SUPPLY
FN7532.2
May 16, 2011
9
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
124
122
120
118
116
114
112
110
124
122
120
118
116
114
112
110
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. ISL28118 CMRR vs TEMPERATURE, VS = ±15V
FIGURE 16. ISL28118 CMRR vs TEMPERATURE, VS = ±5V
132
130
128
126
124
132
130
128
126
124
CHANNEL-B
122
122
CHANNEL-A
120
120
118
118
CHANNEL-B
116
CHANNEL-A
116
114
112
110
114
112
110
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 17. ISL28218 CMRR vs TEMPERATURE, VS = ±15V
FIGURE 18. ISL28218 CMRR vs TEMPERATURE, VS = ±5V
140
140
130
120
110
100
90
135
ISL28118
130
125
80
70
ISL28218
120
60
50
40
30
20
10
0
115
110
105
100
V
= ±15V
S
SIMULATION
-40
-20
0
20
40
60
80
100
120
1m 0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
TEMPERATURE (°C)
FIGURE 19. CMRR vs FREQUENCY, VS = ±15V
FIGURE 20. PSRR vs TEMPERATURE, VS = ±15V
FN7532.2
May 16, 2011
10
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
140
130
120
110
100
90
140
130
120
110
100
90
PSRR+
PSRR+
80
80
70
70
60
60
50
50
40
30
20
10
V
= ±15V
= 1
= 4pF
= 10k
40
30
20
10
V
= ±5V
A = 1
V
S
S
A
V
C
R
C
R
V
= 4pF
= 10k
L
L
PSRR-
PSRR-
L
L
0
0
V
= 1V
= 1V
CM
P-P
CM P-P
-10
10
-10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. PSRR vs FREQUENCY, VS = ±15V
FIGURE 22. PSRR vs FREQUENCY, VS = ±5V
200
180
160
140
120
100
80
60
40
20
0
-20
-40
-60
-80
-100
70
60
50
40
30
20
10
0
R
= 10kΩ, R = 10Ω
G
F
A
= 1000
CL
PHASE
R
= 10kΩ, R = 100Ω
F
G
V
= ±5V & ±15V
= 4pF
= 2k
S
A
= 100
= 10
CL
C
R
V
L
L
= 100mV
OUT
P-P
A
CL
GAIN
R
= 10kΩ, R = 1kΩ
F
G
A
= 1
CL
V
R
= ±15V
= 1MΩ
S
L
R
= 0, R = ∞
F
G
-10
100
1m 0.01 0.1
1
10 100 1k 10k 100k 1M 10M100M 1G
FREQUENCY (Hz)
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V
FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
1
0
1
0
-1
-2
-3
-1
-2
-3
-4
-5
-6
-7
-8
-9
-4
-5
-6
-7
-8
-9
R
= OPEN, 100k, 10k
R = OPEN, 100k, 10k
L
L
R
= 1k
R
= 1k
L
L
V
= ±15V
= 4pF
= +1
V
= ±5V
= 4pF
= +1
R
= 499
R
= 499
L
S
S
L
C
C
L
R
= 100
R = 100
L
L
L
A
A
V
V
R
= 49.9
R = 49.9
L
L
V
= 100mV
V
= 100mV
OUT
p-p
OUT
p-p
100 1k
10k
100k
FREQUENCY (Hz)
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 25. GAIN vs FREQUENCY vs RL, VS = ±15V
FIGURE 26. GAIN vs FREQUENCY vs RL, VS = ±5V
FN7532.2
May 16, 2011
11
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
1
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9-
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
V
= ±1.5V
S
V
S
V
= 10mV
V = 50mV
OUT
OUT
P-P
= ±5V
S
= ±15V
V
= ±5V
= 4pF
= +1
P-P
S
C
R
A
= 4pF
= 10k
= +1
L
L
C
V
= 100mV
L
OUT
P-P
P-P
A
V
V
= 500mV
V
OUT
R
= INF
V
= 100mV
L
OUT
P-P
V
= 1V
P-P
OUT
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 27. GAIN vs FREQUENCY vs OUTPUT VOLTAGE
FIGURE 28. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
90
40
V
R
= ±5V
= 10k
V
R
= ±15V
= 10k
S
S
38
36
34
32
30
28
26
24
22
20
L
L
V
V
OH
OH
80
70
60
50
40
V
V
OL
OL
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 29. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
S = ±15V, RL = 10k
FIGURE 30. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE,
VS = ±5V, RL = 10k
V
1
0.1
1
V
= ±5V and ±15V
V = ±5V and ±15V
S
S
+125°C
+25°C
+125°C
+25°C
0.1
0.01
-40°C
-40°C
0.01
0.001
0.001
0.001
0.01
0.1
LOAD CURRENT (mA)
1
10
0.001
0.01
0.1
LOAD CURRENT (mA)
1
10
FIGURE 31. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,
VS = ±5V and ±15V
FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,
VS = ±5V and ±15V
FN7532.2
May 16, 2011
12
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
15
14
13
12
11
5
4
3
2
V
= ±15V
= 2
V
= ±5V
= 2
S
S
A
A
V
V
R
V
= R = 100k
R
= R = 100k
+125°C
F
G
F
G
= ±7.5V-DC
+125°C
V
= ±2.5V-DC
IN
IN
-40°C
-40°C
10
-10
1
-1
+75°C
0°C
+75°C
0°C
-11
-12
-13
-14
-15
-2
-3
-4
-5
+25°C
10
+25°C
10
2
4
6
8
2
4
6
8
12
14
16
12
14
16
0
18
20
0
18
20
I-FORCE (mA)
I-FORCE (mA)
FIGURE 33. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V
FIGURE 34. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V
1400
1200
1400
1200
V
= ±21V
V
= ±21V
S
S
1000
800
600
400
1000
800
600
400
V
= ±15V
V
= ±15V
S
S
V
= ±2.25V
V
= ±2.25V
S
S
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 35. ISL28118 SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
FIGURE 36. ISL28218 SUPPLY CURRENT vs TEMPERATURE vs
SUPPLY VOLTAGE
1100
1000
900
800
700
600
500
400
300
200
100
0
ISL28218
ISL28118
0
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42
(V)
V
SUPPLY
FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN7532.2
May 16, 2011
13
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
100
10
1
100
10
1
100
10
1
100
10
V
= ±18V
S
V
= ±5V
S
INPUT NOISE VOLTAGE
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
INPUT NOISE CURRENT
1
0.1
0.1
0.1
100k
0.1
0.1
0.1
1
10
100
1k
10k
100k
1
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 38. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±18V
FIGURE 39. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs
FREQUENCY, VS = ±5V
500
500
V
= ±5V
= 10k
V
= ±18V
= 10k
S
S
400
300
200
100
0
400
300
200
100
0
A
A
V
V
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
TIME (s)
TIME (s)
FIGURE 40. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V
FIGURE 41. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V
0.1
0.1
V
= ±15V
= 4pF
= 2k
V
= ±15V
= 4pF
= 10k
= 10V
-40°C
+25°C
S
-40°C
+25°C
S
C
R
V
C
R
V
L
L
L
L
A
= 10
V
= 10V
OUT
P-P
OUT
P-P
+125°C
+125°C
0.01
0.001
0.01
0.001
C-WEIGHTED
22Hz TO 500kHz
C-WEIGHTED
22Hz TO 500kHz
A
= 10
V
A
= 1
V
-40°C
= 1
-40°C
+25°C
A
+125°C
V
+125°C
10k
+25°C
1k
0.0001
0.0001
10
100
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
FIGURE 42. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,
RL = 2k
FIGURE 43. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10,
RL = 10k
FN7532.2
May 16, 2011
14
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
1
1
V
C
R
= ±15V
= 4pF
= 2k
C-WEIGHTED
22Hz TO 22kHz
S
V
C
R
= ±15V
= 4pF
= 10k
C-WEIGHTED
22Hz TO 22kHz
S
L
L
L
L
f = 1kHz
f = 1kHz
0.1
0.1
+125°C
-40°C
+125°C
-40°C
+25°C
+25°C
0.01
0.01
A
= 10
V
A
= 10
V
A
= 1
V
A
= 1
0.001
0.0001
V
0.001
0.0001
+125°C
20
-40°C
25 30
+25°C
10
-40°C
30
+125°C
20
+25°C
10
0
5
15
(V
0
5
15
(V
25
V
)
V
)
P-P
OUT
P-P
OUT
FIGURE 44. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 2k
FIGURE 45. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE,
AV = 1, 10, RL = 10k
6
2.4
V
= ±15V
= 1
= 2k
V
= ±5V
= 1
S
S
2.0
1.6
1.2
0.8
A
A
V
V
4
2
R
C
R
C
= 2k
= 4pF
L
L
L
L
= 4pF
0.4
0
0
-0.4
-0.8
-1.2
-1.6
-2.0
-2.4
-2
-4
-6
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
TIME (µs)
TIME (µs)
FIGURE 46. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
FIGURE 47. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V
100
6
V
V
= ±15V
AND
= ±5V
= 1
= 2k
= 4pF
V
V
= ±5V
= ±5.9V
S
S
80
60
5
4
IN
S
INPUT
A
V
3
40
R
C
L
L
2
20
1
OUTPUT
0
0
-1
-2
-3
-4
-5
-6
-20
-40
-60
-80
-100
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TIME (µs)
2
0
1
2
3
4
TIME (ms)
FIGURE 48. SMALL SIGNAL TRANSIENT RESPONSE,
VS = ±5V, ±15V
FIGURE 49. NO PHASE REVERSAL
FN7532.2
May 16, 2011
15
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
0
200
160
120
80
20
16
12
8
0
-40
INPUT
V
A
R
V
= ±15V
= 100
= 10k
S
V
INPUT
L
-4
-8
= 100mV
IN
P-P
OVERDRIVE = 1V
-80
OUTPUT
-12
-16
-20
-120
OUTPUT
V
= ±15V
= 100
= 10k
S
A
V
-160
-200
40
4
R
V
L
= 100mV
IN
P-P
OVERDRIVE = 1V
0
0
40
0
4
8
12
16
20
24
28 32 36 40
0
4
8
12
16
20
24
28
32
36
TIME (µs)
TIME (µs)
FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
S = ±15V
FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
V
6
5
4
3
2
60
50
40
30
20
0
-10
-20
-30
-40
-50
-60
0
V
= ±5V
= 100
= 10k
S
A
V
-1
-2
-3
-4
INPUT
R
V
L
= 50mV
IN
P-P
OVERDRIVE = 1V
OUTPUT
OUTPUT
INPUT
V
A
R
V
= ±5V
= 100
= 10k
S
V
1
0
L
10
0
-5
-6
= 50mV
IN
P-P
OVERDRIVE = 1V
0
4
8
12
16
20
24
28
32
36
40
0
4
8
12
16
20
24
28 32 36
40
TIME (µs)
TIME (µs)
FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
S = ±5V
FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±5V
V
100
100
10
V
= ±5V
V
= ±15V
S
S
A
= 10
A
= 10
V
V
10
1
A
= 100
A
= 100
V
V
1
0.10
0.01
0.10
0.01
A
= 1
V
A
= 1
V
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 54. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V
FIGURE 55. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±5V
FN7532.2
May 16, 2011
16
ISL28118, ISL28218
Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
60
50
40
30
20
10
0
60
50
40
30
20
10
0
V
V
= ±5V
V
V
= ±15V
S
S
= 100mV
= 100mV
OUT
P-P
OUT
P-P
A
= 1
A
= 1
V
V
A
= 10
A
= 10
V
V
A
= -1
V
A
= -1
V
0.001
0.01
0.1
1
10
100
0.001
0.010
0.100
1
10
100
LOAD CAPACITANCE (nF)
LOAD CAPACITANCE (nF)
FIGURE 56. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V
FIGURE 57. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V
30
30
V
R
= ±15V
= 10k
V
= ±15V
R = 10k
L
S
S
28
26
24
22
20
18
16
14
12
10
28
26
24
22
20
18
16
14
12
10
L
I
-SINK
SC
I
-SINK
SC
I
-SOURCE
SC
I
-SOURCE
100
SC
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 58. ISL28118 SHORT CIRCUIT CURRENT vs
TEMPERATURE, VS = ±15V
FIGURE 59. ISL28218 SHORT CIRCUIT CURRENT vs
TEMPERATURE, VS = ±15V
150
30
V
= ±15V
140
130
120
110
100
90
80
70
60
50
S
V
= ±15V
= 1
S
28
26
24
22
20
18
16
14
12
10
8
C
V
= 4pF
= 1V
A
L
V
CM
P-P
R _
= ∞
TRANSMIT
40
L
30
20
10
0
6
4
2
R _
= 10k
L
RECEIVE
R _
L
= 2k
TRANSMIT
R _
L
= 10k
RECEIVE
100
0
1k
10
1k
10k
100k
1M
10M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 60. MAX OUTPUT VOLTAGE vs FREQUENCY
FIGURE 61. CHANNEL SEPARATION vs FREQUENCY, RL = inf,
S = ±15V
V
FN7532.2
May 16, 2011
17
ISL28118, ISL28218
Applications Information
Functional Description
R
F
V+
The ISL28118 and ISL28218 are single and dual, 3.2MHz,
single-supply, rail-to-rail output amplifiers with a common mode
input voltage range extending to a range of 0.5V below the V- rail.
Their input stages are optimized for precision sensing of
ground-referenced signals in single-supply applications. The input
stage is able to handle large input differential voltages without
phase inversion, making these amplifiers suitable for
R
R
-
IN
-
V
-
IN
+
IN
+
V
+
R
IN
L
R
G
V-
high-voltage comparator applications. Their bipolar design
features high open loop gain and excellent DC input and output
temperature stability. These op amps feature very low quiescent
current of 850µV, and low temperature drift. Both devices are
fabricated in a new precision 40V complementary bipolar DI
process and are immune from latch-up.
FIGURE 62. INPUT ESD DIODE CURRENT LIMITING
Output Drive Capability
The bipolar rail-to-rail output stage features low saturation levels
that enable an output voltage swing to less than 15mV when the
total output load (including feedback resistance) is held below
50µA (Figures 31 and 32). With ±15V supplies, this can be
achieved by using feedback resistor values >300kΩ.
Operating Voltage Range
The op amp is designed to operate over a single supply range of 3V
to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The
device is fully characterized at 10V (±5V) and 30V (±15V). Both DC
and AC performance remain virtually unchanged over the
complete operating voltage range. Parameter variation with
operating voltage is shown in the “Typical Performance Curves”
beginning on page 8.
The output stage is internally current limited. Output current limit
over temperature is shown in Figures 33 and 34. The amplifiers
can withstand a short circuit to either rail as long as the power
dissipation limits are not exceeded. This applies to only one
amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long-term reliability.
The input common mode voltage to the V+ rail (V+ -1.8V over the
full temperature range) may limit amplifier operation when
operating from split V+ and V- supplies. Figure 12 shows the
common mode input voltage range variation over temperature.
The amplifiers perform well when driving capacitive loads
(Figures 56 and 57). The unity gain, voltage follower (buffer)
configuration provides the highest bandwidth but is also the
most sensitive to ringing produced by load capacitance found in
BNC cables. Unity gain overshoot is limited to 35% at
capacitance values to 0.33nF. At gains of 10 and higher, the
device is capable of driving more than 10nF without significant
overshoot.
Input Stage Performance
The ISL28118 and ISL28218 PNP input stage has a common
mode input range extending up to 0.5V below ground at +25°C
(Figure 12). Full amplifier performance is guaranteed down for
input voltage down to ground (V-) over the -40°C to +125°C
temperature range. For common mode voltages down to -0.5V
below ground (V-), the amplifiers are fully functional, but
performance degrades slightly over the full temperature range.
This feature provides excellent CMRR, AC performance, and DC
accuracy when amplifying low-level, ground-referenced signals.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28118 and ISL28218 are immune to output
phase reversal out to 0.5V beyond the rail (VABS MAX) limit
(Figure 49).
The input stage has a maximum input differential voltage equal
to a diode drop greater than the supply voltage (max 42V) and
does not contain the back-to-back input protection diodes found
on many similar amplifiers. This feature enables the device to
function as a precision comparator by maintaining very high
input impedance for high-voltage differential input comparator
voltages. The high differential input impedance also enables the
device to operate reliably in large signal pulse applications,
without the need for anti-parallel clamp diodes required on
MOSFET and most bipolar input stage op amps. Thus, input
signal distortion caused by nonlinear clamps under high slew
rate conditions is avoided.
Single Channel Usage
The ISL28218 is a dual op amp. If the application requires only
one channel, the user must configure the unused channel to
prevent it from oscillating. The unused channel oscillates if the
input and output pins are floating. This results in
higher-than-expected supply currents and possible noise
injection into the channel being used. The proper way to prevent
oscillation is to short the output to the inverting input, and
ground the positive input (Figure 63).
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails,
current-limiting resistors may be needed at each input terminal
(see Figure 62, RIN+, RIN-) to limit current through the
power-supply ESD diodes to 20mA.
-
+
FIGURE 63. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
FN7532.2
May 16, 2011
18
ISL28118, ISL28218
Power Dissipation
ISL28118 and ISL28218 SPICE Model
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
Figure 64 shows the SPICE model schematic and Figure 65 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, slew rate, CMRR, and gain and phase.
The DC parameters are IOS, total supply current, and output
voltage swing. The model uses typical parameters given in the
“Electrical Specifications” table beginning on page 4. The AVOL is
adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is
set at 120dB, f = 50kHz. The input stage models the actual device
to present an accurate AC representation. The model is configured
for an ambient temperature of +25°C.
(EQ. 1)
T
= T
+ θ xPD
MAX JA MAXTOTAL
JMAX
where
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX
)
Figures 66 through 80 show the characterization vs simulation
results for the noise voltage, open loop gain phase, closed loop
gain vs frequency, gain vs frequency vs RL, CMRR, large signal
10V step response, small signal 0.1V step, and output voltage
swing ±15V supplies.
• TMAX = Maximum ambient temperature
• ΘJA = Thermal resistance of the package
PDMAX for each amplifier can be calculated using Equation 2:
LICENSE STATEMENT
V
OUTMAX
R
L
(EQ. 2)
------------------------
PD
= V × I
+ (V - V ) ×
OUTMAX
The information in the SPICE model is protected under United
States copyright laws. Intersil Corporation hereby grants users of
this macro-model, hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model, as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
MAX
S
qMAX
S
where
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of one amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications, and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FN7532.2
May 16, 2011
19
I1
80e-6
D3
G1
+
-
R5
I2
54E-6
I3
54E-6
1
13GAIN = 0.65897
V1
Vin-
9
-0.91
-0.96
D1DBREAK
0.1
V7
0.1
V8
Q7
Q6
14
PNP_LATERAL 7
10
PNP_LATERAL
EOS
+
-
+
12
-
1
2
R2
5e11
PNP_input
PNP_input
Q8
Q9
4
D2DBREAK
GAIN = 1
CinDif
1.33E-12
D13 D14
5
0
V2
8
11
0
IOS
4e-9
R1
5e11
3
750
R17
750
R18
Vcm
15G2
R3
1k
R4
1k
R6
En
-
1
Vin+
6
GAIN = 0.3
GAIN = 0.65897
D4
Cin2
4.02e-12
V--
Cin1
4.02e-12
V--
Input Stage
1st Gain Stage
V+
E2
+
+
-
-
V++
GAIN = 1
0
V++
V++
D5
L1
R13
795.7981
L3
3.18319E-09
D10
D11
-
3.18319E-09
+
R15
G9
16
G5
+
+
C1
6.6667E-11
80
Vout
G13
GAIN = 12.5e-3
+
+
-
18
R9
1e-3
21
-
-
-
R7
V5
GAIN = 1.2566e-3
R11
D7
GAIN = 1
GAIN = 1
3.7304227e9
GAIN = 1.69138e-3
DX
24
1e-3
C3
10e-12
V3
V4
-0.4
-0.91
19
VOUT
Vc
Vg
23
26
27
Vmid
ISY
2.5E-3
D8
D X
V6
-0.4
25
+
+
R10
1e-3
-0.96
R12
1e-3
-
-
C4
10e-12
GAIN = 0.5
C2
6.6667E-11
3.7304227e9
G10
-
20
G4
-
17
22
G11
G12
+
G6
-
G8
-
D12
+
+
-
L4
R16
80
+
-
GAIN = 1.2566e-3
+
+
-
D9
L2
+
3.18319E-09
GAIN = 12.5e-3
R14
795.7981
GAIN = 1.69138e-3
3.18319E-09
GAIN = 12.5e-3
GAIN = 1
D6
G14
GAIN = 1
GAIN = 12.5e-3
V--
V--
V--
E3
+ +
V-
-
Common Mode
Gain Stage
with Zero
Output Stage Correction Current Sources
-
2nd Gain Stage Mid Supply ref
V
GAIN = 1
0
FIGURE 64. SPICE SCHEMATIC
ISL28118, ISL28218
*ISL28118_218 Macromodel - covers
following *products
*ISL28118
*ISL28218
*
*Revision History:
* Revision A, LaFontaine February 8th 2011
* Model for Noise, supply currents, CMRR
*120dB f = 40kHz, AVOL 136dB f = 0.5Hz
* SR = 1.2V/us, GBWP 4MHz.
V_V8
R_R17
*R_R18
*
*Input Stage
Q_Q6
Q_Q7
Q_Q8
Q_Q9
I_I1
4 0 0.1
2 0 750
3 0 750
R_R14
C_C3
C_C4
*
V-- 23 795.7981
23 V++ 10e-12
V-- 23 10e-12
*Output Stage with Correction Current
Sources
11 10 9 PNP_input
8 7 9 PNP_input
V-- VIN- 7 PNP_LATERAL
V-- 12 10 PNP_LATERAL
V++ 9 DC 80e-6
V++ 7 DC 54E-6
V++ 10 DC 54E-6
6 VIN- DC 4e-9
7 10 DBREAK
10 7 DBREAK
5 6 5e11
VIN- 5 5e11
V-- 8 1000
V-- 11 1000
V-- VIN- 4.02e-12
V-- 6 4.02e-12
6 VIN- 1.33E-12
G_G11
G_G12
G_G13
G_G14
D_D7
D_D8
D_D9
D_D10
D_D11
D_D12
V_V5
26 V-- VOUT 23 12.5e-3
27 V-- 23 VOUT 12.5e-3
VOUT V++ V++ 23 12.5e-3
V-- VOUT 23 V-- 12.5e-3
23 24 DX
25 23 DX
V-- 26 DY
V++ 26 DX
V++ 27 DX
V-- 27 DY
24 VOUT -0.4
VOUT 25 -0.4
VOUT V++ 80
V-- VOUT 80
*Copyright 2011 by Intersil Corporation
I_I2
I_I3
*Refer to data sheet “LICENSE STATEMENT”
*Use of this model indicates your acceptance
*with the terms and provisions in the License
*Statement.
I_IOS
*D_D1
*D_D2
R_R1
R_R2
R_R3
R_R4
C_Cin1
C_Cin2
C_CinDif
*
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
characteristics *under a wide range of
external circuit *configurations using
compatible simulation *platforms – such as
iSim PE.
V_V6
R_R15
R_R16
.model PNP_LATERAL pnp(is=1e-016
bf=250 va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model PNP_input pnp(is=1e-016 bf=100
va=80
+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0
af=1)
.model DBREAK D(bv=43 rs=1)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28118_218
*
*Device performance features supported by
this *model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances,
*Open loop gain and phase,
*Closed loop bandwidth and frequency
*response,
*Loading effects on closed loop frequency
*response,
*Input noise terms including 1/f effects,
*Slew rate,
*Input and Output Headroom limits to I/O
*voltage swing,
*Supply current at nominal specified supply
*voltages,
*1st Gain Stage
G_G1
G_G2
V_V1
V_V2
D_D3
D_D4
R_R5
R_R6
*
V++ 14 8 11 0.65897
V-- 14 8 11 0.65897
13 14 -0.91
14 15 -0.96
13 V++ DX
V-- 15 DX
14 V++ 1
V-- 14 1
*2nd Gain Stage
G_G3
G_G4
V_V3
V_V4
D_D5
D_D6
R_R7
R_R8
C_C1
C_C2
*
V++ VG 14 VMID 1.69138e-3
V-- VG 14 VMID 1.69138e-3
16 VG -0.91
VG 17 -0.96
16 V++ DX
*
V-- 17 DX
*Device performance features NOT
supported *by this model:
*Harmonic distortion effects,
*Output current limiting (current will limit at
*40mA),
*Disable operation (if any),
VG V++ 3.7304227e9
V-- VG 3.7304227e9
VG V++ 6.6667E-11
V-- VG 6.6667E-11
*Thermal effects and/or over temperature
*parameter variation,
*Limited performance variation vs. supply
*voltage is modeled,
*Part to part performance variation due to
*normal process parameter spread,
*Any performance difference arising from
*different packaging,
*Mid supply Ref
E_E2
E_E3
E_E4
I_ISY
*
V++ 0 V+ 0 1
V-- 0 V- 0 1
VMID V-- V++ V-- 0.5
V+ V- DC 0.85E-3
*Common Mode Gain Stage with Zero
G_G5
G_G6
G_G7
G_G8
E_EOS
L_L1
L_L2
L_L3
L_L4
R_R9
R_R10
R_R11
R_R12
*
V++ 19 5 VMID 1
V-- 19 5 VMID 1
V++ VC 19 VMID 1
V-- VC 19 VMID 1
12 6 VC VMID 1
18 V++ 3.18319E-09
20 V-- 3.18319E-09
21 V++ 3.18319E-09
22 V-- 3.18319E-09
19 18 1e-3
*Load current reflected into the power supply
*current.
* source ISL28118_218 SPICEmodel
*
* Connections:
+input
*
*
*
*
|
|
|
|
-input
|
|
|
+Vsupply
|
|
-Vsupply
output
|
.subckt ISL28118_218 Vin+ Vin-V+ V- VOUT
* source ISL28118_218_presubckt_0
*
20 19 1e-3
VC 21 1e-3
22 VC 1e-3
*Voltage Noise
E_En
VIN+ 6 2 0 0.3
1 2 DN
1 2 DN
*Pole Stage
G_G9
G_G10
D_D13
D_D14
V_V7
V++ 23 VG VMID 1.2566e-3
V-- 23 VG VMID 1.2566e-3
23 V++ 795.7981
1 0 0.1
R_R13
FIGURE 65. SPICE NET LIST
FN7532.2
May 16, 2011
21
ISL28118, ISL28218
Characterization vs Simulation Results
100
10
1
100
10
1
100
10
1
V
= ±18V
S
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
0.1
0.1
0.1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 66. CHARACTERIZED INPUT NOISE VOLTAGE
FIGURE 67. SIMULATED INPUT NOISE VOLTAGE
200
180
160
140
120
100
80
200
180
160
140
120
100
80
PHASE
PHASE
60
60
40
40
20
20
0
-20
-40
-60
-80
GAIN
0
GAIN
-20
-40
-60
-80
-100
V
R
= ±15V
= 1MΩ
V
R
= ±15V
S
S
= 1MΩ
L
L
-100
1m
0.1
1
10 100 1k 10k 100k 1M 10M100M 1G
FREQUENCY (Hz)
1m
0.1
0.01
1
10 100 1k 10k 100k 1M 10M100M 1G
FREQUENCY (Hz)
0.01
FIGURE 68. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 69. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
70
70
R
= 10kΩ, R = 10Ω
G
R
= 10kΩ, R = 10Ω
G
F
F
A
= 1000
A
= 1000
= 100
= 10
CL
CL
60
50
40
30
20
10
0
60
50
40
30
20
10
0
R
= 10kΩ, R = 100Ω
R = 10kΩ, R = 100Ω
F G
F
G
V
= ±5V & ±15V
= 4pF
= 2k
V
= ±5V & ±15V
S
S
A
= 100
= 10
A
CL
CL
C
R
V
C
R
V
= 4pF
= 2k
= 100mV
L
L
L
L
= 100mV
OUT
P-P
OUT
P-P
A
A
CL
CL
R
= 10kΩ, R = 1kΩ
R
= 10kΩ, R = 1kΩ
F
G
F
G
A
= 1
CL
A
= 1
CL
R
= 0, R = ∞
F
G
R
= 0, R = ∞
F
G
-10
100
-10
100
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 70. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY
FIGURE 71. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY
FN7532.2
May 16, 2011
22
ISL28118, ISL28218
Characterization vs Simulation Results (Continued)
1
1
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-1
-2
-3
-4
-5
-6
-7
-8
-9
R
= OPEN, 100k, 10k
R = OPEN, 100k, 10k
L
L
R
= 1k
R
= 1k
L
L
V
= ±15V
= 4pF
= +1
V
= ±15V
= 4pF
= +1
R
= 499k
R
= 499k
S
S
L
L
C
C
L
R
= 100k
R
= 100k
L
L
L
A
A
V
V
R
= 49.9k
R
= 49.9k
1M
L
L
V
= 100mV
V
= 100mV
OUT
p-p
OUT
p-p
100
1k
10k
100k
1M
10M
100
1k
10k
100k
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 72. CHARACTERIZED GAIN vs FREQUENCY vs RL
FIGURE 73. SIMULATED GAIN vs FREQUENCY vs RL
140
130
120
110
100
90
140
130
120
110
100
90
80
80
70
70
60
60
50
50
40
40
V
= ±15V
V = ±15V
S
SIMULATION
30
20
10
0
30
20
10
0
S
SIMULATION
1m 0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
1m 0.01 0.1
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
FIGURE 74. CHARACTERIZED CMRR vs FREQUENCY
FIGURE 75. SIMULATED CMRR vs FREQUENCY
6
4
6
V
= ±15V
= 1
= 2k
V
= ±15V
= 1
= 2k
S
S
A
A
V
V
4
2
R
C
R
C
L
L
L
L
= 4pF
= 4pF
2
0
0
-2
-4
-6
-2
-4
-6
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
TIME (µs)
TIME (µs)
FIGURE 77. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE
FIGURE 76. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE
FN7532.2
May 16, 2011
23
ISL28118, ISL28218
Characterization vs Simulation Results (Continued)
100
100
V
= ±15V
AND
= ±5V
= 1
= 2k
= 4pF
V
= ±15V
S
S
80
80
AND
V
V
= ±5V
S
S
60
60
A
A
= 1
V
V
40
40
R
C
R
C
= 2k
= 4pF
L
L
L
L
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (µs)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (µs)
FIGURE 78. CHARACTERIZED SMALL-SIGNAL TRANSIENT
RESPONSE
FIGURE 79. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE
20V
10V
0V
VOH = 14.88V
-10V
V
= ±15V
S
R
= 10kΩ
L
VOL = -14.93V
-20V
0
0.5
1.0
TIME (ms)
1.5
2.0
FIGURE 80. SIMULATED OUTPUT VOLTAGE SWING
FN7532.2
May 16, 2011
24
ISL28118, ISL28218
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
FN7532.2
CHANGE
5/9/2011
Page 2: Added NC pin to Pin Descriptions table.
Page 3: Added ISL28218EVAL1Z evaluation board to the Ordering Information table.
Page 12: Added new Output Overhead Voltage plots (Figs. 31,32)
Pages 19 through 24: Added SPICE model schematic, netlist, description and Figs. 66 through 80.
11/12/10
FN7532.1
On page 1: Features Section, added Low input offset voltage and superb offset voltage temperature drift for
ISL28118.
Updated Intersil trademark statement (bottom of page)
On page 3: Removed “coming soon” from ISL28118FBZ. Updated tape & reel note.
On page 4: Change ISL28118 Theta JA value from 158 to 165. Added ISL28118 min/max specs to VOS (input
offset voltage), TCVOS and min specs to CMRR.
On page 5: Added AVOL MIN spec for ISL28118 in dB. Changed existing AVOL spec from V/mV to dB. Added VOL
max spec for ISL28118, IS Typ and Max spec for ISL28118. Changed TS from 18µs to 8.5µs.
On page 6: Added Min Max VOS spec, TCVOS spec for ISL28118. Changed AVOL specs from V/mV to dB.
On page 7: Changed Slew Rate TYP from ±1.2V/µs to ±1V/µs. Added for TS TYP spec = 4µs. Changed min/max
note 8 to “Compliance to datasheet limits is assured by one or more methods: production test, characterization
and/or design.” Added Figs 3 & 4 for ISL28118. Figures 5 & 6 moved to page 8.
On page 8: Added Figures 7 & 8
On page 10: Added Figures 15 & 16 for ISL28118
On page 10, in Figure 19, changed VS from ±5V to ±15V
On page 12 and page 13: Added Figures 27, 28, 31 & 34 for ISL28118
On page 13: Added Figure 35 for ISL28118
On page 14: Figure 41 changed VS from ±18V to ±5V, Figure 42 added RL = 2k, Figure 43 added RL = 10k and
corrected "HD+N" to "THD+N"
On page 15, Figure 44 added RL = 2k, Figure 45 RL = 10k.
On page 17: Added Figure 58 for ISL28118
On page 17, Figure 58 and 59, graph upper left corner changed VS = ±5V to VS = ±15V
On page 17, Figure 61, deleted VS = ±5V
9/16/10
FN7532.0
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISL28118, ISL28218.
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7532.2
May 16, 2011
25
ISL28118, ISL28218
Package Outline Drawing
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 2/10
( 2.30)
( 1.95)
3.00
A
B
( 8X 0.50)
(1.50)
6
PIN 1
INDEX AREA
( 2.90 )
(4X)
0.15
PIN 1
TOP VIEW
(6x 0.65)
( 8 X 0.30)
TYPICAL RECOMMENDED LAND PATTERN
SEE DETAIL "X"
0.10 C
2X 1.950
C
6X 0.65
0.75 ±0.05
0.08 C
1
PIN #1
INDEX AREA
6
SIDE VIEW
1.50 ±0.10
5
8
C
0 . 2 REF
4
8X 0.30 ±0.05
0.10 M C A B
8X 0.30 ± 0.10
0 . 02 NOM.
0 . 05 MAX.
2.30 ±0.10
DETAIL "X"
BOTTOM VIEW
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.20mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
7.
FN7532.2
May 16, 2011
26
ISL28118, ISL28218
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN7532.2
May 16, 2011
27
ISL28118, ISL28218
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 3, 3/10
5
3.0±0.05
A
8
DETAIL "X"
D
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.036
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7532.2
May 16, 2011
28
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明