ISL28408FBZ_技术文档

40V Precision Single Supply Rail-Rail Output Low

Power Operational Amplifiers

ISL28108, ISL28208, ISL28408

Features

The ISL28108, ISL28208 and ISL28408 are single, dual and

quad low power precision amplifiers optimized for single

supply applications. These devices feature a common mode

input voltage range extending to 0.5V below the V- rail, a

rail-to-rail differential input voltage range for use as a

comparator, and rail-to-rail output voltage swing, which make

them ideal for single supply applications where input

operation at ground is important.

• Single or Dual Supply, Rail-to-Rail Output and Below Ground

(V-) input capability

• Rail-to-rail Input Differential Voltage Range for Comparator

Applications

• Single Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V

• Low Current Consumption (V_S= ±5V) . . . . . . . . . . . . . . 165µA

• Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 15.8nV/√Hz

• Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 80fA/√Hz

• Low Input Offset Voltage (ISL28108) . . . . . . . . . . . . . . 150µV

• Superb Temperature Drift

Added features include low offset voltage, and low

temperature drift making them the ideal choice for

applications requiring high DC accuracy. The output stage is

capable of driving large capacitive loads from rail to rail for

excellent ADC driving performance. The devices can operate

for single or dual supply from 3V (±1.5V) to 40V (±20V) and are

fully characterized at ±5V and ±15V. The combination of

precision, low power, and small footprint provides the user with

outstanding value and flexibility relative to similar competitive

parts.

- Voltage Offset TC . . . . . . . . . . . . . . . . . . . . . . 0.1µV/°C, Typ

• Low Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . -13nA Typ

• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C

• No Phase Reversal

Applications

• Precision Instruments

• Medical Instrumentation

• Data Acquisition

Applications for these amplifiers include precision

instrumentation, data acquisition, precision power supply

control, and industrial control.

The ISL28108 single is offered in 8 Ld TDFN, SOIC and MSOP

packages. The ISL28208 dual amplifier is offered in 8 Ld

TDFN, MSOP, and SOIC packages. The ISL28408 is offered in

14 Ld SOIC package. All devices are offered in standard pin

configurations and operate over the extended temperature

range to -40°C to +125°C.

• Power Supply Control

• Industrial Process Control

Related Literature

• AN1658, “ISL28208SOICEVAL2Z Evaluation Board User

Guide”

R

F

500

100kΩ

LOAD

V

= ±15V

S

400

300

200

100

0

+3V

R

-

IN

IN-

to 40V

-

V

OUT

+125°C

V+

ISL28108

10kΩ

R

SENSE

+25°C

-40°C

R

+

V-

IN

IN+

+

10kΩ

GAIN = 10

-100

-200

-300

-400

-500

R

+

REF

100kΩ

V

REF

-16

-15.5 -15 -14.5 -14 13 13.5

14

14.5

15

SINGLE-SUPPLY, LOW-SIDE

CURRENT SENSE AMPLIFIER

INPUT COMMON MODE VOLTAGE (V)

FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE

VOLTAGE, V_S= ±15V

FIGURE 1. TYPICAL APPLICATION CIRCUIT

November 1, 2011

FN6935.3

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL28108, ISL28208, ISL28408

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

(Notes 1, 2, 3)

PART MARKING

28108 FBZ

(°C)

(Pb-Free)

DWG. #

ISL28108FBZ

-40 to +125

8 Ld SOIC

M8.15E

L8.3x3K

ISL28108FRTZ

108Z

8 Ld TDFN

Coming soon

ISL28108FUZ

8108Z

-40 to +125

8 Ld MSOP

8 Ld SOIC

8 Ld TDFN

M8.118B

M8.15E

L8.3x3K

ISL28208FBZ

ISL28208FRTZ

28208 FBZ

208F

Coming soon

ISL28208FUZ

8208Z

-40 to +125

8 Ld MSOP

14 Ld SOIC

M8.118B

M14.15

ISL28408FBZ

ISL28208SOICEVAL2Z

NOTES:

28408 FBZ

Evaluation Board

1. Add “-T*” suffix for tape and reel. Please refer to Tech Brief TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28108, ISL28208, ISL28408. For more information on MSL please

see Tech Brief TB363.

Pin Configurations

ISL28108

(8 LD TDFN)

TOP VIEW

ISL28108

(8 LD MSOP, SOIC)

TOP VIEW

NC

-IN

+IN

V-

1

2

3

4

8

7

6

5

NC

V+

1

2

3

4

8

7

6

5

-IN

+IN

V-

V+

V

- +

OUT

V

OUT

PAD

NC

ISL28208

(8 LD TDFN)

TOP VIEW

ISL28208

(8 LD MSOP, SOIC)

TOP VIEW

V_OUT_A

V+

V

_A

1

2

3

4

8

7

6

5

V+

V

1

2

3

4

8

7

6

5

OUT

PAD

-IN_A

+IN_A

V-

V_OUT_B

-IN_B

-IN_A

+IN_A

V-

_B

OUT

- +

-IN_B

+ -

+IN_B

ISL28408

(14 LD SOIC)

TOP VIEW

V

_A

V

_D

OUT

1

2

3

4

14

13

12

11

10

9

OUT

-IN_A

A

D

-IN_D

- + + -

+IN_A

+IN_D

V -

V +

+IN_B

-IN_B

+IN_C

-IN_C

5

- + + -

B

C

6

7

V

_C

8

V

_B

OUT

FN6935.3

November 1, 2011

2

ISL28108, ISL28208, ISL28408

Pin Descriptions

ISL28108

(8 Ld SOIC,

MSOP, TDFN)

ISL28208

(8 Ld SOIC,

TDFN)

ISL28408

(14 Ld SOIC)

NAME

EQUIVALENT

CIRCUIT

DESCRIPTION

Amplifier non-inverting input

3

-

3

+IN

+IN_A

+IN_B

+IN_C

+IN_D

V-

Circuit 1

-

3

-

5

-

10

12

11

-

4

Circuit 3

Circuit 1

Negative power supply

Amplifier inverting input

2

-

-IN

-

2

-IN_A

-IN_B

-IN_C

-IN_D

V+

-

6

-

9

-

13

4

7

8

Circuit 3

Circuit 2

Positive power supply

Amplifier output

6

-

V_OUT

-

1

V

_OUT_A

_OUT_B

_OUT_C

-

7

V

-

8

-

14

-

V_OUT_D

1, 5, 8

PAD

NC

-

No internal connection

PAD

-

PAD

Thermal Pad - TDFN and QFN packages only. Connect

thermal pad to ground or most negative potential.

V+

CAPACITIVELY

TRIGGERED

ESD CLAMP

OUT

V-

IN-

IN+

V-

CIRCUIT 2

CIRCUIT 3

CIRCUIT 1

FN6935.3

November 1, 2011

3

ISL28108, ISL28208, ISL28408

Table of Contents

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Specifications, V ±15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

S

Electrical Specifications, V ±5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

S

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Input Stage Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Output Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

ISL28108, ISL28208, ISL28408 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Characterization vs Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Package Outline Drawing, M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package Outline Drawing, L8.3x3K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Package Outline Drawing, M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Package Outline Drawing, M14.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

FN6935.3

November 1, 2011

4

ISL28108, ISL28208, ISL28408

Absolute Maximum Ratings

Thermal Information

Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V

Maximum Differential Input Voltage

Thermal Resistance (Typical)

θ

_JA(°C/W)

120

47

θ

_JC(°C/W)

8 Ld SOIC Package (208, Notes 4, 7). . . . . . .

8 Ld SOIC Package (108, Notes 4, 7). . . . . . .

8 Ld TDFN Package (208, Notes 5, 6) . . . . . .

8 Ld TDFN Package (108, Notes 5, 6) . . . . . .

8 Ld MSOP Package (208, Notes 4, 7). . . . . .

8 Ld MSOP Package (108, Notes 4, 7). . . . . .

14 Ld SOIC Package (408, Notes 4, 7). . . . . .

Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

55

60

6

3.5

50

57

37

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42V or V_-- 0.5V to V₊+ 0.5V

Min/Max Input Voltage . . . . . . . . . . . . . . . . . . .42V or V_-- 0.5V to V₊+ 0.5V

Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . Indefinite

ESD Tolerance (ISL28208, ISL28408)

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 6kV

Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 400V

Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV

ESD Tolerance (ISL28108)

45

150

165

71

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .5.5kV

Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . . 300V

Charged Device Model (Tested per JESD22-C110D) . . . . . . . . . . . . . 2kV

Operating Conditions

Ambient Operating Temperature Range. . . . . . . . . . . . . .-40°C to +125°C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V (±1.5V) to 40V (±20V)

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ_JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

5. θ_JAis measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

6. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.

7. For θ_JC, the “case temp” location is taken at the package top center.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise

noted, all tests are at the specified temperature and are pulsed tests, therefore: T_J= T_C= T_A

Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over

S

CM

O

L

A

the operating temperature range, -40°C to +125°C. Temperature data established by characterization.

MIN

MAX

PARAMETER

V_OS

DESCRIPTION

Input Offset Voltage

CONDITIONS

ISL28208 SOIC, TDFN

(Note 8)

-230

TYP

25

(Note 8)

UNIT

µV

230

330

150

270

1.1

ISL28408 SOIC

-330

µV

ISL28108 SOIC, TDFN

-150

10

µV

-270

µV

TCV_OS

Input Offset Voltage Temperature ISL28208 SOIC

Coefficient

0.1

0.2

µV/°C

-40°C to +125°C

ISL28208 TDFN

ISL28408 SOIC

-40°C to +125°C

1.4

1.2

µV/°C

ISL28108 SOIC, TDFN

-40°C to +125°C

0.2

5

ΔV_OS

Input Offset Voltage Match

(ISL28208 only)

-300

-400

-43

300

400

µV

I_B

Input Bias Current

-13

nA

-63

nA

TCI_B

Input Bias Current

0.07

nA/°C

Temperature Coefficient

FN6935.3

November 1, 2011

5

ISL28108, ISL28208, ISL28408

Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over

S

CM

O

L

A

the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)

MIN

MAX

PARAMETER

I_OS

DESCRIPTION

Input Offset Current

CONDITIONS

ISL28208 SOIC, TDFN

(Note 8)

TYP

0

(Note 8)

UNIT

nA

dB

V

-3

-4

-5

3

4

5

ISL28108 SOIC, TDFN

ISL28408 SOIC

0

CMRR

Common-Mode Rejection Ratio

V

_CM= V_--0.5V to V₊-1.8V

119

123

102

123

115

V_CM= V_--0.2V to V₊-1.8V

V_CM= V_-to V₊-1.8V

105

102

V_-- 0.5

V_-

V_CMIR

PSRR

A_VOL

V_OL

Common Mode Input Voltage

Range

Guaranteed by CMRR test

V₊- 1.8

V

Power Supply Rejection Ratio

Open-Loop Gain

V_S= 3V to 40V, V_CMIR= Valid Input Voltage

110

109

117

100

128

124

126

dB

mV

µA

mA

V_O= -13V to +13V, R_L= 10kΩ to ground

Output Voltage Low,

R_L= 10kΩ

R_L= Open

52

70

85

V_OUTto V_-

145

110

150

250

350

V_OH

Output Voltage High,

V₊to V_OUT

I_S

Supply Current/Amplifier

185

270

19

I_SC+

Output Short Circuit Source

Current

R_L= 10Ω to V_-

I_SC-

Output Short Circuit Sink Current R_L= 10Ω to V₊

Supply Voltage Range Guaranteed by PSRR

30

mA

V

V_SUPPLY

3

40

AC SPECIFICATIONS

GBWP

e_np-p

e_n

Gain Bandwidth Product

A_CL= 101, V_O= 100mV_P-P, R_L= 2kΩ

0.1Hz to 10Hz; V_S= +18V

f = 10Hz; V_S= +18V

1.2

580

MHz

nVP-P

nV/√Hz

fA/√Hz

%

Noise Voltage

Noise Voltage Density

Noise Current Density

18

e_n

f = 100Hz; V_S= +18V

16

e_n

f = 1kHz; V_S= +18V

15.8

80

e_n

f = 10kHz; V_S= +18V

i_n

f = 10kHz; V_S= +18V

THD + N

Total Harmonic Distortion + Noise 1kHz, A_V= 1, V_O= 3.5V_RMS, R_L=10kΩ

0.00042

TRANSIENT RESPONSE

SR Slew Rate, V_OUT20% to 80%

A_V= 1, R_L= 2kΩ, V_O= 10V_P-P

0.45

V/µs

FN6935.3

November 1, 2011

6

ISL28108, ISL28208, ISL28408

Electrical Specifications V ±15V, V = 0, V = 0V, R = Open, T = +25°C, unless otherwise noted. Boldface limits apply over

S

CM

O

L

A

the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)

MIN

MAX

PARAMETER

DESCRIPTION

CONDITIONS

(Note 8)

TYP

264

(Note 8)

UNIT

ns

t_r, t_f, Small

Signal

Rise Time, V_OUT10% to 90%

A_V= 1, V_OUT= 100mV_P-P, R_f= 0Ω, R_L= 2kΩ to

V_CM

Fall Time, V_OUT90% to 10%

A_V= 1, V_OUT= 100mV_P-P, R_f= 0Ω, R_L= 2kΩ to

V_CM

254

27

ns

µs

t_s

Settling Time to 0.01%

10V Step; 10% to V_OUT

A_V= -1, V_OUT= 10V_P-P, R_g= R_f=10k, R_L= 2kΩ to

V_CM

Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating

S

CM

O

A

temperature range, -40°C to +125°C. Temperature data established by characterization.

MIN

MAX

PARAMETER

V_OS

DESCRIPTION

Input Offset Voltage

CONDITIONS

ISL28208 SOIC, TDFN

(Note 8)

TYP

25

(Note 8)

UNIT

µV

-230

-330

-150

-270

230

330

150

270

1.1

ISL28408 SOIC

µV

ISL28108 SOIC, TDFN

10

µV

TCV_OS

Input Offset Voltage Temperature

Coefficient

ISL28208 SOIC

-40°C to +125°C

0.1

0.2

µV/°C

ISL28208 TDFN

ISL28408 SOIC

-40°C to +125°C

1.4

1.2

µV/°C

ISL28108 SOIC, TDFN

-40°C to +125°C

0.2

3

ΔV_OS

Input Offset Voltage Match

(ISL28208 only)

-300

-400

-43

300

400

µV

I_B

Input Bias Current

-15

nA

-63

nA

TCI_B

I_OS

Input Bias Current

Temperature Coefficient

-40°C to +125°C

-0.067

0

nA/°C

Input Offset Current

-3

-4

-5

3

4

5

nA

dB

V

ISL28208 SOIC, TDFN

ISL28108 SOIC, TDFN

ISL28408 SOIC

0

CMRR

Common-Mode Rejection Ratio

V_CM= V_--0.5V to V₊-1.8V

101

123

89

V_CM= V_--0.2V to V₊-1.8V

V_CM= V_-to V₊-1.8V

105

100

105

97

123

112

123

112

V_CM= V_-to V₊-1.8V

ISL28408 SOIC

V_CMIR

PSRR

Common Mode Input Voltage

Range

Guaranteed by CMRR test

V_-- 0.5

V_-

V₊- 1.8

V

Power Supply Rejection Ratio

V_S= 3V to 10V, V_CMIR= Valid Input Voltage

110

109

126

123

dB

FN6935.3

November 1, 2011

7

ISL28108, ISL28208, ISL28408

Electrical Specifications V ±5V, V = 0, V = 0V, T = +25°C, unless otherwise noted. Boldface limits apply over the operating

S

CM

O

A

temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued)

MIN

MAX

PARAMETER

A_VOL

DESCRIPTION

Open-Loop Gain

CONDITIONS

(Note 8)

TYP

124

(Note 8)

UNIT

dB

V_O= -3V to +3V, R_L= 10kΩ to ground

117

99

dB

V_OL

V_OH

I_S

Output Voltage Low,

_OUTto V_-

R_L= 10kΩ

R_L= Open

23

30

38

48

mV

µA

V

Output Voltage High,

V₊to V_OUT

65

70

Supply Current/Amplifier

165

240

14

250

350

µA

I_SC+

I_SC-

AC SPECIFICATIONS

Output Short Circuit Source Current R_L= 10Ω to V_-

mA

Output Short Circuit Sink Current

R_L= 10Ω to V₊

22

GBW

e_np-p

e_n

Gain Bandwidth Product

A_CL= 101, V_O= 100mV_P-P, R_L= 2kΩ

1.2

600

18

MHz

Noise Voltage

0.1Hz to 10Hz

f = 10Hz

nV_P-P

Noise Voltage Density

Noise Current Density

nV/√Hz

fA/√Hz

e_n

f = 100Hz

f = 1kHz

16

e_n

15.8

90

e_n

f = 10kHz

i_n

TRANSIENT RESPONSE

SR

Slew Rate, V_OUT20% to 80%

A_V= 1, R_L= 2kΩ, V_O= 4V_P-P

0.4

V/µs

ns

t_r, t_f, Small

Signal

Rise Time, V_OUT10% to 90%

A_V= 1, V_OUT= 100mV_P-P, R_f= 0Ω, R_L= 2kΩ to

V_CM

264

Fall Time, V_OUT90% to 10%

A_V= 1, V_OUT= 100mV_P-P, R_f= 0Ω, R_L= 2kΩ to

V_CM

254

ns

µs

t_s

Settling Time to 0.01%

4V Step; 10% to V_OUT

A_V= -1, V_OUT= 4V_P-P, R_g= R_f=10k, R_L= 2kΩ to

V_CM

14.4

NOTE:

8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN6935.3

November 1, 2011

8

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified.

400

350

300

250

200

150

100

50

400

350

300

250

200

150

100

50

V

= ±5V

V

= ±15V

S

0

V

(µV)

V

(µV)

OS

FIGURE 3. ISL28408 SOIC INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±15V

FIGURE 4. ISL28408 SOIC INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±5V

300

V

= ±15V

V

= ±5V

S

250

200

150

100

250

200

150

100

50

0

50

0

V

(µV)

V

(µV)

OS

FIGURE 5. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION,

V_S= ±15V

FIGURE 6. ISL28208 INPUT OFFSET VOLTAGE DISTRIBUTION,

V_S= ±5V

200

V

= ±5V

V

= ±15V

S

150

100

50

150

100

50

0

V

(µV)

V

(µV)

OS

FIGURE 7. ISL28108 SOIC INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±15V

FIGURE 8. ISL28108 SOIC INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±5V

FN6935.3

November 1, 2011

9

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

25

20

15

10

5

25

20

15

10

5

V

= ±5V

V

= ±15V

S

0

V

(µV)

V

(µV)

OS

FIGURE 9. ISL28108 TDFN INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±15V

FIGURE 10. ISL28108 TDFN INPUT OFFSET VOLTAGE

DISTRIBUTION, V_S= ±5V

30

25

V

= ±15V

V = ±5V

S

25

20

15

10

5

20

15

10

5

0

TCV (µV/C)

OS

FIGURE 11. ISL28408 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

FIGURE 12. ISL28408 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±5V

V

_S= ±15V

V

24

22

20

18

16

14

12

10

8

24

22

20

18

16

14

12

10

8

V

= ±15V

V = ±5V

S

6

4

2

0

TCV (µV/C)

OS

FIGURE 13. ISL28208 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±15V

FIGURE 14. ISL28208 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±5V

V

FN6935.3

November 1, 2011

10

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

24

22

20

18

16

14

12

10

8

24

22

20

18

16

14

12

10

8

V

= ±15V

V = ±5V

S

6

4

2

0

TCV (µV/C)

OS

FIGURE 15. ISL28208 TDFN TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±15V

FIGURE 16. ISL28208 TDFN TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±5V

V

35

30

25

20

15

10

5

30

25

20

15

10

5

V

= ±15V

V

= ±5V

S

0

TCV (µV/C)

OS

FIGURE 17. ISL28108 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±15V

FIGURE 18. ISL28108 SOIC TCV_OSvs NUMBER OF AMPLIFIERS,

V

_S= ±5V

14

12

10

8

14

12

10

8

V

= ±15V

V

= ±5V

S

6

4

2

0

TCV (µV/C)

OS

FIGURE 19. ISL28108 TDFN TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±15V

FIGURE 20. ISL28108 TDFN TCV_OSvs NUMBER OF AMPLIFIERS,

_S= ±5V

V

FN6935.3

November 1, 2011

11

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

70

60

50

40

30

20

10

0

V

= ±21V

V

= ±2.25V

S

-5

-10

-15

-20

-25

V

= ± 15V

S

V

= ±5V

S

V

= ±5V

S

V

= ±15V

S

-10

-20

-30

-40

-50

V

= ±20V

S

V

= ±2.25V

V

= ±1.5V

S

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 21. V_OSvs TEMPERATURE

FIGURE 22. I_BIASvs TEMPERATURE vs SUPPLY

500

400

300

200

100

0

500

400

300

200

100

0

V

= ±5V

S

V

= ±15V

S

+125°C

+25°C

-40°C

+25°C

-40°C

-100

-200

-300

-400

-500

-100

-200

-300

-400

-500

-16 -15.5 -15 -14.5 -14 13 13.5

14

14.5

15

-6

-5.5

-5

-4.5 -4 3

3.5

4

4.5

5

INPUT COMMON MODE VOLTAGE (V)

FIGURE 23. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE

VOLTAGE, V_S= ±15V

FIGURE 24. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE

VOLTAGE, V_S= ±5V

130

V

= ±15V

V = ±5V

S

CHANNEL-B

125

120

115

110

105

100

125

120

115

110

105

100

CHANNEL-A

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 25. CMRR vs TEMPERATURE, V_S= ±15V

FIGURE 26. CMRR vs TEMPERATURE, V_S= ±5V

FN6935.3

November 1, 2011

12

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

120

110

100

90

80

70

60

50

40

30

20

10

0

150

140

130

120

110

100

90

80

70

60

50

PSRR+

V

= ±5V, ±15V

= 1

S

A

V

40

30

20

10

C

R

V

= 4pF

= 10k

L

V

= ±15V

S

SIMULATION

PSRR-

= 1V

SOURCE

P-P

0

10

100

1k

10k

100k

1M

10M

1m 0.01 0.1

1

10 100 1k 10k 100k 1M 10M100M 1G

FREQUENCY (Hz)

FIGURE 27. CMRR vs FREQUENCY, V_S= ±15V

FIGURE 28. PSRR vs FREQUENCY, V_S= ±5V & ±15V

140

135

130

125

120

140

135

130

125

120

V

= ±5V

V

= ±15V

S

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 29. PSRR (DC) vs TEMPERATURE, V_S= ±15V

FIGURE 30. PSRR (DC) vs TEMPERATURE, V_S= ±5V

1

V

= ±5V and ±15V

V

= ±5V and ±15V

S

125°C

0.1

0.01

0.1

0.01

+25°C

-40°C

0.001

0.01

0.1

LOAD CURRENT (mA)

1

10

0.001

0.01

0.1

LOAD CURRENT (mA)

1

10

FIGURE 31. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT,

V_S= ±5V and ±15V

FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT,

V_S= ±5V and ±15V

FN6935.3

November 1, 2011

13

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

5

4

3

2

15

14

13

12

11

+75°C

125°C

-40°C

1

-1

10

-10

0°C

-11

-12

-13

-14

-15

V

= ±5V

= 2

-2

-3

-4

-5

S

+25°C

V

= ±15V

= 2

+25°C

S

A

V

A

+75°C

V

R

V

= R = 100k

F

G

R

= R = 100k

= ±7.5V-DC

F

G

= ±2.5V-DC

IN

V

IN

0

2

4

6

8

10 12 14 16 18 20 22 24

I-FORCE (mA)

0

2

4

6

8

10 12 14 16 18 20 22 24

I-FORCE (mA)

FIGURE 33. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT

_S= ±15V

FIGURE 34. ISL28208 OUTPUT VOLTAGE SWING vs LOAD CURRENT

V_S= ±5V

V

100

90

80

70

60

50

40

30

20

10

0

100

V

R

= ±15V

= 10k

V

= ±5V

R = 10k

L

S

V

_OH(V₊TO V_OUT)

90

80

70

60

50

40

30

20

10

0

L

V

_OH(V₊TO V_OUT)

V

(V

TO V )

OUT -

OL

V

(V

TO V )

-

OL

OUT

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 35. V_OUTHIGH AND LOW vs TEMPERATURE,

_S= ±15V, R_L= 10k

FIGURE 36. V_OUTHIGH AND LOW vs TEMPERATURE,

_S= ±5V, R_L= 10k

V

50

45

40

35

30

25

20

15

10

5

50

45

40

35

30

25

20

15

10

5

V

R

= ±5V

= 10k

V

R

= ±15V

= 10k

S

L

I

-SINK

SC

I

-SINK

SC

I

-SOURCE

SC

I

-SOURCE

SC

0

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (°C)

FIGURE 37. SHORT CIRCUIT CURRENT vs TEMPERATURE,

_S= ±15V

FIGURE 38. SHORT CIRCUIT CURRENT vs TEMPERATURE, V_S= ±5V

V

FN6935.3

November 1, 2011

14

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

6

5

30

28

26

24

22

20

18

16

14

12

10

8

V

= ±5V

= ±5.9V

V

= ±15V

= 1

S

A

V

IN

4

INPUT

3

2

1

OUTPUT

0

-1

-2

-3

-4

-5

-6

6

4

2

0

2

4

6

8

10

12

14

16

18

20

1k

10k

100k

1M

TIME (ms)

FREQUENCY (Hz)

FIGURE 39. MAX OUTPUT VOLTAGE vs FREQUENCY

FIGURE 40. NO PHASE REVERSAL

140

200

180

160

140

120

100

80

60

40

20

0

V

= ± 15V

S

PHASE

130

120

110

100

V

= ±5V

S

GAIN

-20

-40

-60

-80

-100

V

R

= ±15V

= 1MΩ

S

L

SIMULATION

-60 -40 -20

0

20 40 60 80 100 120 140 160

TEMPERATURE (°C)

0.1

1

10 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

FIGURE 41. AV_OLvs TEMPERATURE

FIGURE 42. OPEN-LOOP GAIN, PHASE vs FREQUENCY, V_S= ±15V

70

210

200

190

180

170

160

150

140

130

120

110

100

90

R

= 10kΩ, R = 10Ω

G

F

A

= 1001

CL

60

50

40

30

20

10

0

R

= 10kΩ, R = 100Ω

G

F

V

= ±5V, ±15V

= 4pF

= 2k

S

A

= 101

= 10

CL

C

R

V

L

= 100mV

OUT

P-P

A

R

= 10kΩ, R = 1.1kΩ

F

G

A

= 1

CL

80

R

= 0, R = ∞

F

G

-10

100

70

1k

10k

100k

1M

10M

0

2

4

6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

(V)

V

FREQUENCY (Hz)

SUPPLY

FIGURE 43. SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 44. FREQUENCY RESPONSE vs CLOSED LOOP GAIN

FN6935.3

November 1, 2011

15

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

1

0

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-1

-2

-3

-4

-5

-6

-7

-8

-9

R

= OPEN, 100k, 10k

R

= OPEN, 100k, 10k

L

R

= 1k

R

= 1k

L

R

= 499

R

= 499

V

= ±5V

= 4pF

= +1

L

V

= ±15V

= 4pF

= +1

L

S

C

A

R

= 100

C

A

R

= 100

L

V

R

= 49.9

R

= 49.9

L

V

= 100mV

V

= 100mV

OUT

p-p

OUT

P-P

100

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

100

FREQUENCY (Hz)

FIGURE 45. GAIN vs FREQUENCY vs R_L, V_S= ±15V

FIGURE 46. GAIN vs FREQUENCY vs R_L, V_S= ±5V

1

0

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-1

-2

-3

-4

V

= ±2.5V

= ±5V

S

V

= 10mV

= 50mV

OUT

P-P

-5

-6

-7

-8

-9-

= ±15V

= ±20V

V

OUT

P-P

V

= ±5V

= 4pF

= +1

S

C

R

A

= 4pF

= 10k

= +1

L

V

= 100mV

P-P

C

A

S

OUT

L

V

= 500mV

V

OUT P-P

V

= 100mV

R

= INF

OUT

P-P

L

V

= 1V

P-P

OUT

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FIGURE 47. GAIN vs FREQUENCY vs OUTPUT VOLTAGE

FIGURE 48. GAIN vs FREQUENCY vs SUPPLY VOLTAGE

100

V

= ±15V

V

= ±5V

S

G = 10

10

1

10

1

G = 100

0.10

0.01

0.10

G = 1

0.01

1

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FIGURE 49. OUTPUT IMPEDANCE vs FREQUENCY, V_S= ±15V

FIGURE 50. OUTPUT IMPEDANCE vs FREQUENCY, V_S= ±5V

FN6935.3

November 1, 2011

16

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

100

10

100

10

1

V

= ±5V

V

= ±18V

S

10

INPUT NOISE VOLTAGE

INPUT NOISE CURRENT

INPUT NOISE VOLTAGE

INPUT NOISE CURRENT

1

0.1

0.01

0.1

0.01

0.1

0.01

100k

0.01

100k

0.1

1

10

100

1k

10k

0.1

1

10

100

1k

10k

FREQUENCY (Hz)

FIGURE 51. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs

FREQUENCY, V_S= ±18V

FIGURE 52. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs

FREQUENCY, V_S= ±5V

1000

V

= ±18V

= 10k

V

= ±5V

= 10k

S

800

600

800

600

A

V

400

200

0

-200

-400

-600

-800

-1000

-200

-400

-600

-800

-1000

0

1

2

3

4

5

6

7

8

9

10

0

1

2

3

4

5

6

7

8

9

10

TIME (s)

FIGURE 53. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, V_S= ±18V

FIGURE 54. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, V_S= ±5V

160

200

160

120

80

20

16

12

8

V

= ±15V

V

C

V

= ±15V

= 4pF

= 1V

INPUT

S

A = 100

140

120

100

80

V

L

R = 10k

L

TX

P-P

V

= 100mV

IN

P-P

OVERDRIVE = 1V

OUTPUT

R _

= ∞

TRANSMIT

L

R _

= 10k

RECEIVE

L

60

40

4

R _

= 2k

L

TRANSMIT

20

R _

= 10k

L

RECEIVE

0

20

40

60

80 100 120 140 160 180 200

TIME (µs)

10

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FIGURE 55. ISL28208 CHANNEL SEPARATION vs FREQUENCY, V_S=

±5V, ±15V

FIGURE 56. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,

_S= ±15V

V

FN6935.3

November 1, 2011

17

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

6

5

4

3

2

1

0

60

50

40

30

20

10

0

V

= ±5V

S

A

R

= 100

= 10k

V

INPUT

L

-40

-4

-8

-12

V

= 50mV

IN

P-P

OVERDRIVE = 1V

-80

-120

-160

-200

OUTPUT

V

= ±15V

S

A = 100

V

R = 10k

L

-16

-20

V

= 100mV

IN

P-P

INPUT

60

OVERDRIVE = 1V

0

20

40

60

80 100 120 140 160 180 200

0

20

40

80 100 120 140 160 180 200

TIME (µs)

FIGURE 57. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,

_S= ±15V

FIGURE 58. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,

V_S= ±5V

V

60

0

-10

-20

-30

-40

-50

-60

0

V

= ±15V

S

V

= 100mV

OUT

P-P

50

40

30

20

10

0

-1

-2

-3

-4

-5

-6

A

= -1

V

OUTPUT

A

= 1

A

= 10

V

= ±5V

= 100

= 10k

S

INPUT

A

V

R

V

L

= 50mV

IN

P-P

OVERDRIVE = 1V

0.001

0.010

0.100

1

10

100

0

20

40

60

80 100 120 140 160 180 200

TIME (µs)

LOAD CAPACITANCE (nF)

FIGURE 59. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,

V_S= ±5V

FIGURE 60. OVERSHOOT vs CAPACITIVE LOAD, V_S= ±15V

60

6

V

= ±5V

S

V

A

= ±15V

= 1

V

S

= 100mV

OUT

P-P

50

40

30

20

10

0

4

2

R

C

= 2k

= 4pF

L

A

= -1

V

0

A

= 1

V

A

= 10

V

-2

-4

-6

0.001

0.010

0.100

1

10

100

0

100

200

300

400

TIME (µs)

LOAD CAPACITANCE (nF)

FIGURE 61. OVERSHOOT vs CAPACITIVE LOAD, V_S= ±5V

FIGURE 62. LARGE SIGNAL 10V STEP RESPONSE, V_S= ±15V

FN6935.3

November 1, 2011

18

ISL28108, ISL28208, ISL28408

Typical Performance Curves

V_S= ±15V, V_CM= 0V, R_L= Open, unless otherwise specified. (Continued)

2.4

2.0

1.6

1.2

0.8

100

V

= ±5V

= 1

= 2k

S

V

= ±15V

AND

= ±5V

= 1

= 2k

= 4pF

S

80

A

V

R

C

V

60

L

S

= 4pF

A

V

40

R

C

L

20

0.4

0

-0.4

-0.8

-1.2

-1.6

-2.0

-2.4

-20

-40

-60

-80

-100

0

100

200

300

400

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

TIME (µs)

FIGURE 63. LARGE SIGNAL 4V STEP RESPONSE, V_S= ±5V

FIGURE 64. SMALL SIGNAL TRANSIENT RESPONSE V_S= ±5V, ±15V

FN6935.3

November 1, 2011

19

ISL28108, ISL28208, ISL28408

Applications Information

R

F

V+

Functional Description

The ISL28108, ISL28208, and ISL28408 are single, dual and

quad, 1.2MHz, single supply rail-to-rail output amplifiers with a

common mode input voltage range extending to a range of 0.5V

below the V- rail. Their input stages are optimized for precision

sensing of ground referenced signals in low voltage, single supply

applications. The input stage has the capability of handling large

input differential voltages without phase inversion making them

suitable for high voltage comparator applications. Their bipolar

design features high open loop gain and excellent DC input and

output temperature stability. These op amps feature low

R

-

IN

-

V

-

IN

+

IN

+

V

+

R

IN

L

R

G

V-

FIGURE 65. INPUT ESD DIODE CURRENT LIMITING

quiescent current of 165µA, and a maximum temperature drift

ranging from 1.1µV/°C for the ISL28208 and ISL28408 in the

SOIC package to 1.4µV/°C for the ISL28208 in the TDFN

package and the ISL28408 in the SOIC package (see Figures 11

through 20. All devices are fabricated in a new precision 40V

complementary bipolar DI process and immune from latch-up.

Output Drive Capability

The bipolar rail-to-rail output stage features low saturation levels

that enable an output voltage swing to less than 10mV when the

total output load (including feedback resistance) is held below

50µA (Figures 31 and 32). With ±15V supplies this can be

achieved by using feedback resistor values >300kΩ. The low input

bias and offset currents (-43nA and ±3nA +25°C max

respectively) minimize DC offset errors at these high resistance

values. For example, a balanced 4 resistor gain circuit (Figure 65)

with 1MΩ feedback resistors (R_F, R_G) generates a worst case

input offset error of only ±3mV. Furthermore, the low noise

current reduces the added noise associated with high feedback

resistance.

Operating Voltage Range

The devices are designed to operate over the 3V (±1.5V) to 40V

(±20V) range and are fully characterized at ±5V and ±15V. Both DC

and AC performance remain virtually unchanged over the ±5V to

±15V operating voltage range. Parameter variation with operating

voltage is shown in the “Typical Performance Curves” beginning on

page 9.

The output stage is internally current limited. Output current limit

over-temperature is shown in Figures 37 and 38. The amplifiers

can withstand a short circuit to either rail as long as the power

dissipation limits are not exceeded. This applies to only one

amplifier at a time for the dual op amp. Continuous operation

under these conditions may degrade long-term reliability.

Input Stage Performance

The PNP input stage has a common mode input range extending

up to 0.5V below ground at +25°C (see Figures 23 and 24). Full

amplifier performance is guaranteed down to ground (V-) over the -

40°C to +125°C temperature range. For common mode voltages

down to -0.5V the amplifiers are fully functional, but performance

degrades slightly over the full temperature range. This feature

provides excellent CMRR, AC performance and DC accuracy when

amplifying low level ground referenced signals.

The amplifiers perform well driving capacitive loads (Figures 60

and 61). The unity gain, voltage follower (buffer) configuration

provides the highest bandwidth, but is also the most sensitive to

ringing produced by load capacitance found in BNC cables. Unity

gain overshoot is limited to 30% at capacitance values to 0.33nF.

At gains of 10 and higher, the device is capable of driving more

than 10nF without significant overshoot.

The input stage has a maximum input differential voltage equal

to a diode drop greater than the supply voltage (max 42V) and

does not contain the back-to-back input protection diodes found

on many similar amplifiers. This feature enables the device to

function as a precision comparator by maintaining very high

input impedance for high voltage differential input comparator

voltages. The high differential input impedance also enables the

device to operate reliably in large signal pulse applications

without the need for anti-parallel clamp diodes required on

MOSFET and most bipolar input stage op amps. Thus, input

signal distortion caused by nonlinear clamps under high slew

rate conditions are avoided.

Output Phase Reversal

Output phase reversal is a change of polarity in the amplifier

transfer function when the input voltage exceeds the supply

voltage. These devices are immune to output phase reversal, out

to 0.5V beyond the rail (V_{ABS MAX}) limit (see Figure 40).

In applications where one or both amplifier input terminals are at

risk of exposure to voltages beyond the supply rails, current

limiting resistors may be needed at each input terminal (see

Figure 65 R_IN+, R_IN-) to limit current through the power supply

ESD diodes to 20mA.

FN6935.3

November 1, 2011

20

ISL28108, ISL28208, ISL28408

Unused Channels

ISL28108, ISL28208, ISL28408 SPICE Model

If the application requires only one channel, the user must

configure any unused channel to prevent it from oscillating.

Unused channels can oscillate if the input and output pins are

floating. This will result in higher-than-expected supply currents

and possible noise injection into the channel being used. The

proper way to prevent oscillation is to short the output to the

inverting input, and ground the positive input (Figure 66).

Figure 67 shows the SPICE model schematic and Figure 68 shows

the net list for the SPICE model. The model is a simplified version

of the actual device and simulates important AC and DC

parameters. AC parameters incorporated into the model are: 1/f

and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The

DC parameters are I_OS, total supply current and output voltage

swing. The model uses typical parameters given in the “Electrical

Specifications” Table beginning on page 5. The AVOL is adjusted

for 122dB with the dominant pole at 1Hz. The CMRR is set 128dB,

f = 6kHz. The input stage models the actual device to present an

accurate AC representation. The model is configured for ambient

temperature of +25°C.

-

+

Figures 69 through 83 show the characterization vs simulation

results for the Noise Voltage, Open Loop Gain Phase, Closed Loop

Gain vs Frequency, Gain vs Frequency vs RL, CMRR, Large Signal

10V Step Response, Small Signal 0.05V Step and Output Voltage

Swing ±15V supplies.

FIGURE 66. PREVENTING OSCILLATIONS IN UNUSED CHANNELS

Power Dissipation

It is possible to exceed the +150°C maximum junction

temperatures under certain load and power supply conditions. It

is therefore important to calculate the maximum junction

temperature (T_JMAX) for all applications to determine if power

supply voltages, load conditions, or package type need to be

modified to remain in the safe operating area. These parameters

are related using Equation 1:

LICENSE STATEMENT

The information in this SPICE model is protected under the

United States copyright laws. Intersil Corporation hereby grants

users of this macro-model hereto referred to as “Licensee”, a

nonexclusive, nontransferable licence to use this model as long

as the Licensee abides by the terms of this agreement. Before

using this macro-model, the Licensee should read this license. If

the Licensee does not accept these terms, permission to use the

model is not granted.

(EQ. 1)

T

= T

+ θ xPD

MAX JA MAXTOTAL

JMAX

where:

• P_DMAXTOTALis the sum of the maximum power dissipation of

The Licensee may not sell, loan, rent, or license the macro-

model, in whole, in part, or in modified form, to anyone outside

the Licensee’s company. The Licensee may modify the macro-

model to suit his/her specific applications, and the Licensee may

make copies of this macro-model for use within their company

only.

each amplifier in the package (PD_MAX

)

• PD_MAXfor each amplifier can be calculated using Equation 2:

V

OUTMAX

R

L

------------------------

(EQ. 2)

PD

= V × I

+ (V - V ) ×

OUTMAX

MAX

S

qMAX

S

where:

This macro-model is provided “AS IS, WHERE IS, AND WITH NO

WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,

INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”

• T_MAX= Maximum ambient temperature

• θ_JA= Thermal resistance of the package

• PD_MAX= Maximum power dissipation of 1 amplifier

• V_S= Total supply voltage

In no event will Intersil be liable for special, collateral, incidental,

or consequential damages in connection with or arising out of

the use of this macro-model. Intersil reserves the right to make

changes to the product and the macro-model without prior

notice.

• I_qMAX= Maximum quiescent supply current of 1 amplifier

• V_OUTMAX= Maximum output voltage swing of the application

• R_L= Load resistance

FN6935.3

November 1, 2011

21

ISL28108, ISL28208, ISL28408

*ISL28108_208 Macromodel - covers following

*products

*ISL28108

*ISL28208

*ISL28408

R_R17

*

*Input Stage

Q_Q6

Q_Q7

Q_Q8

Q_Q9

I_I1

2 0 1150

C_C6

*

V-- 28 10e-12

G_G9

G_G10

R_R13

R_R14

C_C3

C_C4

*

V++ 23 28 VMID 314.15e-6

V-- 23 28 VMID 314.15e-6

23 V++ 3.18319e3

V-- 23 3.18319e3

23 V++ 10e-12

V-- 23 10e-12

11 10 9 PNP_input

8 7 9 PNP_input

V-- VIN- 7 PNP_LATERAL

V-- 12 10 PNP_LATERAL

V++ 9 DC 12e-6

V++ 7 DC 6E-6

V++ 10 DC 6E-6

6 VIN- DC 3e-9

7 10 DBREAK

10 7 DBREAK

5 6 5e11

VIN- 5 5e11

V-- 8 6250

*

*Revision History:

* Revision A, LaFontaine March 5th 2011

* Model for Noise, supply currents, CMRR

*128dB f=6kHz ,AVOL 122dB f=1Hz

* SR = 0.45V/us, GBWP 1.2MHz.

I_I2

I_I3

*Output Stage with Correction Current Sources

I_IOS

*D_D1

*D_D2

R_R1

R_R2

R_R3

R_R4

C_Cin1

C_Cin2

C_CinDif

*

G_G11

G_G12

G_G13

G_G14

D_D7

D_D8

D_D9

D_D10

D_D11

D_D12

V_V5

26 V-- VOUT 23 12.5e-3

27 V-- 23 VOUT 12.5e-3

VOUT V++ V++ 23 12.5e-3

V-- VOUT 23 V-- 12.5e-3

23 24 DX

25 23 DX

V-- 26 DY

V++ 26 DX

V++ 27 DX

V-- 27 DY

24 VOUT -0.4

VOUT 25 -0.4

VOUT V++ 80

V-- VOUT 80

*Refer to data sheet "LICENSE STATEMENT"

*Use of this model indicates your acceptance

*with the terms and provisions in the License

*Statement.

*

V-- 11 6250

*Intended use:

V-- VIN- 4.19e-12

V-- 6 4.19e-12

6 VIN- 1.21E-12

*This Pspice Macromodel is intended to give

*typical DC and AC performance characteristics

*under a wide range of external circuit

*configurations using compatible simulation

*platforms – such as iSim PE.

*1st Gain Stage

V_V6

R_R15

R_R16

*

G_G1

G_G2

V_V1

V_V2

D_D3

D_D4

R_R5

R_R6

*

V++ 14 8 11 0.4779867

*Device performance features supported by this

*model

*Typical, room temp., nominal power supply

*voltages used to produce the following

*characteristics:

*Open and closed loop I/O impedances,

*Open loop gain and phase,

*Closed loop bandwidth and frequency

*response,

*Loading effects on closed loop frequency

*response,

*Input noise terms including 1/f effects,

*Slew rate,

*Input and Output Headroom limits to I/O

*voltage swing,

*Supply current at nominal specified supply

*voltages.

V-- 14 8 11 0.4779867

13 14 -6.74

14 15 -6.76

13 V++ DX

V-- 15 DX

14 V++ 1

.model PNP_LATERAL pnp(is=1e-016 bf=250

va=80

+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)

.model PNP_input pnp(is=1e-016 bf=100

va=80

+ ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1)

.model DBREAK D(bv=43 rs=1)

.model DN D(KF=6.69e-9 AF=1)

.MODEL DX D(IS=1E-12 Rs=0.1)

.MODEL DY D(IS=1E-15 BV=50 Rs=1)

.ends ISL28108_208

V-- 14 1

*2nd Gain Stage

G_G3

G_G4

V_V3

V_V4

D_D5

D_D6

R_R7

R_R8

C_C1

C_C2

*

V++ VG 14 VMID 261.748e-6

V-- VG 14 VMID 261.748e-6

16 VG -6.74

VG 17 -6.76

16 V++ DX

V-- 17 DX

VG V++ 7.62283e9

V-- VG 7.62283e9

VG V++ 2.31e-11

V-- VG 2.31e-11

*

*Device performance features NOT supported

*by this model:

*Harmonic distortion effects,

*Output current limiting (current will limit at

*40mA),

*Mid supply Ref

E_E2

E_E3

E_E4

I_ISY

*

V++ 0 V+ 0 1

V-- 0 V- 0 1

VMID V-- V++ V-- 0.5

V+ V- DC 185E-6

*Disable operation (if any),

*Thermal effects and/or over temperature

*parameter variation,

*Limited performance variation vs. supply

*voltage is modeled,

*Part to part performance variation due to

*normal process parameter spread,

*Any performance difference arising from

*different packaging source,

*Load current reflected into the power supply

*current.

*Common Mode Gain Stage with Zero

G_G5

G_G6

G_G7

G_G8

E_EOS

L_L1

L_L2

L_L3

L_L4

R_R9

R_R10

R_R11

R_R12

*

V++ 19 5 VMID 0.6

V-- 19 5 VMID 0.6

V++ VC 19 VMID 0.6

V-- VC 19 VMID 0.6

12 6 VC VMID 1

18 V++ 1.59159E-08

20 V-- 1.59159E-08

21 V++ 1.59159E-08

22 V-- 1.59159E-08

19 18 1e-3

*

* Connections:

+input

*

|

-input

|

+Vsupply

|

-Vsupply

|

output

|

20 19 1e-3

VC 21 1e-3

22 VC 1e-3

.subckt ISL28108_208 Vin+ Vin-V+ V- VOUT

* source ISL28118_218_subckt_check_0

*

*Pole Satge

G_G15

*Voltage Noise

V++ 28 VG VMID 314.15e-6

V-- 28 VG VMID 314.15e-6

28 V++ 3.18319e3

V-- 28 3.18319e3

28 V++ 10e-12

E_En

VIN+ 6 2 0 0.3

1 2 DN

G_G16

R_R19

R_R20

C_C5

D_D13

D_D14

V_V7

1 0 0.1

FIGURE 68. SPICE NET LIST

FN6935.3

November 1, 2011

23

ISL28108, ISL28208, ISL28408

Characterization vs Simulation Results

100

10

0.1

10

0.1

1

10

100

1k

10k

100k

1

10

100

1k

10k

100k

FREQUENCY (Hz)

FIGURE 69. CHARACTERIZED INPUT NOISE VOLTAGE

FIGURE 70. SIMULATED INPUT NOISE VOLTAGE

200

180

160

140

120

100

80

150

100

50

PHASE

60

40

20

0

-20

-40

-60

GAIN

= ±15V

0

GAIN

V

R

= ±15V

= 1MΩ

V

R

S

-50

= 1MΩ

L

SIMULATION

-80

-100

0.1

1

10 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

0.1

1

10 100 1k 10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

FIGURE 71. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs

FREQUENCY

FIGURE 72. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY

70

R

= 10kΩ, R = 10Ω

G

R

= 10kΩ, R = 10Ω

G

F

A

= 1001

CL

60

50

40

30

20

10

0

60

50

40

30

20

10

0

R

= 10kΩ, R = 100Ω

R

= 10kΩ, R = 100Ω

F

G

F

G

V

= ±5V, ±15V

V

= ±5V, ±15V

S

A

= 101

= 10

CL

C

R

V

= 4pF

= 2k

C

R

V

= 4pF

= 2k

L

= 100mV

OUT

P-P

OUT

P-P

A

R

= 10kΩ, R = 1.1kΩ

G

R

= 10kΩ, R = 1.1kΩ

F

G

A

= 1

CL

R

= 0, R = ∞

R

= 0, R = ∞

F

G

F

G

-10

100

-10

100

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FIGURE 74. SIMULATED CLOSED LOOP GAIN vs FREQUENCY

FIGURE 73. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY

FN6935.3

November 1, 2011

24

ISL28108, ISL28208, ISL28408

Characterization vs Simulation Results(Continued)

1

0

1

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

-1

-2

-3

-4

-5

-6

-7

-8

-9

R

= OPEN, 100k, 10k

L

R

= OPEN, 100k, 10k

L

R

= 1k

L

R

= 1k

L

R

= 499

L

R

= 499

V

= ±15V

= 4pF

= +1

V

= ±15V

= 4pF

= +1

L

S

R

= 100

L

C

A

C

A

R

= 100

L

R

= 49.9

V

L

R

= 49.9

L

V

= 100mV

V

= 100mV

OUT

P-P

OUT

P-P

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

100

FREQUENCY (Hz)

FIGURE 75. CHARACTERIZED GAIN vs FREQUENCY vs R_L

FIGURE 76. SIMULATED GAIN vs FREQUENCY vs R_L

150

140

130

120

110

100

90

80

70

60

50

150

100

50

0

40

30

20

10

0

V

= ±15V

V = ±15V

S

SIMULATION

S

SIMULATION

1m 0.01 0.1

1

10 100 1k 10k 100k 1M 10M100M 1G

FREQUENCY (Hz)

1m 0.01 0.1

1

10 100 1k 10k 100k 1M 10M100M 1G

FREQUENCY (Hz)

FIGURE 77. CHARACTERIZED CMRR vs FREQUENCY

FIGURE 78. SIMULATED CMRR vs FREQUENCY

6

4

V

A

R

C

= ±15V

= 1

= 2k

V

A

R

C

= ±15V

= 1

= 2k

S

V

4

2

L

= 4pF

2

0

-2

-4

-6

-2

-4

-6

0

100

200

300

400

0

100

200

300

400

TIME (µs)

FIGURE 80. SIMULATED LARGE SIGNAL 10V STEP RESPONSE

FIGURE 79. CHARACTERIZED LARGE SIGNAL 10V STEP RESPONSE

FN6935.3

November 1, 2011

25

ISL28108, ISL28208, ISL28408

Characterization vs Simulation Results(Continued)

100

80

100

80

V

= ±15V

AND

= ±5V

V

= ±15V

S

AND

V

= ±5V

60

S

A

R

C

= 1

= 2k

= 4pF

A

R

C

= 1

= 2k

= 4pF

V

40

L

20

0

-20

-40

-60

-80

-100

-20

-40

-60

-80

-100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

TIME (µs)

FIGURE 82. SIMULATED SMALL SIGNAL TRANSIENT RESPONSE

FIGURE 81. CHARACTERIZED SMALL SIGNAL TRANSIENT

RESPONSE

20

10

0

VOH = 14.93V

-10

VOL = -14.94V

-20

0

0.5

1.0

1.5

2.0

TIME (m s)

FIGURE 83. SIMULATED OUTPUT VOLTAGE SWING

For additional products, see www.intersil.com/product_tree

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in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

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FN6935.3

November 1, 2011

26

ISL28108, ISL28208, ISL28408

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6935.3

CHANGE

10/19/11

• On page 1, Features: changed Low Input Offset Voltage from 230µV to (ISL28108)……150µV. Added Related

Literature section with AN1658, "ISL28208SOICEVAL2Z Evaluation Board User Guide".

• On page 2, Ordering Information: added ISL28208SOICEVAL2Z evaluation board. Removed "Coming Soon" from

ISL28408FBZ. Corrected Package Dwg. # for TDFN package from L8.3x3A to L8.3x3K. Corrected Package Dwg. #

for MSOP package from M8.118 to M8.118B.

• On page 5, Absolute Maximum Ratings, changed “ESD Tolerance (ISL28208)” to “ESD Tolerance (ISL28208,

ISL28408)”. Added ESD information for ISL28108 as follows:

ESD Tolerance (ISL28108)

Human Body Model (Tested per JESD22-A114F).....5.5kV

Machine Model (Tested per JESD22-A115-C).....300V

Charged Device Model (Tested per JESD22-C110D).....2kV

• On page 5, Thermal Information, changed package temperatures from:

8 Ld SOIC Package (108, 208, Notes 4, 7), θ_JA= 120, θ_JC= 55

8 Ld TDFN Package (108, 208, Notes 5, 6), θ_JA= 47, θ_JC= 6

8 Ld MSOP Package (108, 208, Notes 4, 7), θ_JA= 150, θ_JC= 45

14 Ld SOIC Package (408, Notes 4, 7), θ_JA= -, θ_JA= -

To:

8 Ld SOIC Package (208, Notes 4, 7), θ_JA= 120, θ_JC= 55

8 Ld SOIC Package (108, Notes 4, 7), θ_JA= 120, θ_JC= 60

8 Ld TDFN Package (208, Notes 5, 6), θ_JA= 47, θ_JC= 6

8 Ld TDFN Package (108, Notes 5, 6), θ_JA= 45, θ_JC= 3.5

8 Ld MSOP Package (208, Notes 4, 7), θ_JA= 150, θ_JC= 50

8 Ld MSOP Package (108, Notes 4, 7), θ_JA= 165, θ_JC= 57

14 Ld SOIC Package (408, Notes 4, 7), θ_JA= 71, θ_JC= 37

• On page 5, ±15V Electrical Specifications table, added the following parameters:

-

VOS ISL28108 SOIC, TDFN

TCVOS ISL28108 SOIC, TDFN

IOS ISL28108 SOIC, TDFN

• On page 5 and 6, ±15V Electrical Specifications table, changed the following in Conditions column:

-

VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC”

TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC”

IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC”

• On page 7, ±5V Electrical Specifications table, added the following:

-

VOS ISL28108 SOIC, TDFN

TCVOS ISL28108 SOIC, TDFN

IOS ISL28108 SOIC, TDFN

• On page 7, ±5V Electrical Specifications table, changed the following in Conditions column:

-

VOS: changed “ISL28208 SOIC, TDFN” to “ISL28208 SOIC, TDFN; ISL28408 SOIC”

TCVOS: changed “ISL28208 TDFN” to”ISL28208 TDFN, ISL28408 SOIC”

IOS: changed “ISL28108 SOIC, TDFN” to “ISL28108 SOIC, TDFN; ISL28408 SOIC”

• On page 9 through page 11, added the following to Typical Performance Curves:

-

Figures 3, 4: ISL28408 SOIC Input Offset Distribution Voltage, ±15V and ±5V

Figures 7, 8: ISL28108 SOIC ±15V VOS distribution, and ±5V VOS distribution

Figures 9, 10: ISL28108 TDFN ±15V VOS distribution, and ±5V VOS distribution

Figures 11, 12: ISL28408 SOIC TCVOS vs. number of Amplifiers ±15V and ±5V

Figures 17, 18: ISL28108 SOIC ±15V TCVOS distribution, and ±5V TCVOS distribution

Figures 19, 20: ISL28108 TDFN ±15V TCVOS distribution, and ±5V TCVOS distribution

• On page 20, Applications: minor edits to re-align figures with curves

• On page 21: changed heading from “Using Only One Amplifier to “Unused Channels” and edited for clarity.

• On page 30: changed Package Outline Drawing L8.3x3A to L8.3x3K

• On page 31: changed Package Outline Drawing M8.118 to M8.118B

• On page 32: added Package Outline Drawing M14.15

FN6935.3

November 1, 2011

27

ISL28108, ISL28208, ISL28408

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev. (Continued)

DATE

REVISION

FN6935.2

CHANGE

4/20/11

• Added discussion of ISL28408 throughout datasheet.

• On page 2 in “Ordering Information”: Added new part, “ISL28408FBZ”. Corrected part marking for

ISL28208FRTZ from 208Z to 208F. Added “ISL28408” to Note 3. Under” Pin Configurations,” added

ISL28408 (14 Ld SOIC) pin configuration diagram.

• On page 3: in Pin Descriptions table, added column for ISL28408 14Ld SOIC. Corrected schematic for

Circuit 2.

• On page 5: under “Thermal Information” added "14 Ld SOIC Package (408, Notes 4, 7)" and added

ISL28108 to 8 Ld TDFN and 8 Ld MSOP. Changed θ_JAand θ_JCfor 8 Ld TDFN Package from 48 and 5.5 to 47

and 6. Added Note 6 regarding θ_JC“case temp” measurement, and applied it to 8 Ld TDFN Package.

• On page 5: in Electrical Specifications table, changed TYP spec for TCI_Bfrom 70 pA/° C to 0.07nA/° C. On

page 7, changed TYP spec for TCI_Bfrom -67 pA/° C to -0.067nA/° C. These are not spec changes since the

values are the same.

• On page 13, Figs. 31 and 32: changed y axis units label from (mV) to (V); changed x axis units label from (µA)

to (mA).

• On page 20, under “Output Drive Capability,” para 2, changed "The output stage can swing at moderate

levels of output current (Figures 21 and 22) and the output stage is internally current limited. Output current

limit over-termperature..." to "The output stage is internally current limited. Output current limit over-

temperature..."

3/11/11

FN6935.1

• On page 1, in the first paragraph - added the following after V-rail: "a rail-to-rail differential input voltage

range for use as a comparator,…"

• On page 1 in “Features:

- Added bullet - “Rail-to-rail Input Differential Voltage Range for Comparator Applications”

- Changed Low Noise Current from "100fA/sq.root Hz" to "80fA/sq.root Hz"

• On page 2 in “Ordering Information” - Removed "coming soon" from ISL28208FRTZ part since it is

releasing.

• On page 5, changed “ESD Tolerance (ISL28208, ISL28408)” as follows:

- Human Body Model changed from "3kV" to "6kV"

- Machine Model changed from "300V" to "400V"

- Added JEDEC Test information for all ESD ratings

• On page 5 and page 7, added test conditions for SOIC TCVos specs. Added TCVos specs for TDFN.

• On page 6 changed “Noise Current Density” Typical from "100" to "80"

• On page 20, updated Applications Information Functional Description

• On page 20 Updated Input Stage Performance Section

• On page 20 Updated Output Drive Capability Section

• On page 21 Added ISL28108 AND ISL28208 SPICE MODEL and License Agreement section

• On page 22 Added SPICE NET LIST

• On page 24 Added Characterization vs Simulation Results curves

2/16/11

FN6935.0

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL28108, ISL28208, ISL28408.

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

FN6935.3

November 1, 2011

28

ISL28108, ISL28208, ISL28408

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

4

4.90 ± 0.10

A

DETAIL "A"

0.22 ± 0.03

B

6.0 ± 0.20

3.90 ± 0.10

4

PIN NO.1

ID MARK

5

(0.35) x 45°

4° ± 4°

0.43 ± 0.076

1.27

0.25 M C A B

SIDE VIEW “B”

TOP VIEW

1.75 MAX

1.45 ± 0.1

0.25

GAUGE PLANE

C

SEATING PLANE

0.175 ± 0.075

SIDE VIEW “A

0.10 C

0.63 ±0.23

DETAIL "A"

(0.60)

(1.27)

NOTES:

(1.50)

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

(5.40)

4. Dimension does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

The pin #1 identifier may be either a mold or mark feature.

Reference to JEDEC MS-012.

5.

6.

TYPICAL RECOMMENDED LAND PATTERN

FN6935.3

November 1, 2011

29

ISL28108, ISL28208, ISL28408

Package Outline Drawing

L8.3x3K

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 9/11

2X 1.95

3.00

A

6X 0.65

B

1

PIN #1

INDEX AREA

6

1.50 ±0.10

PIN 1

INDEX AREA

(4X)

0.15

8

4

TOP VIEW

8X 0.25 ±0.05

0.10 M C A

0.40 ± 0.05

B

2.30 ±0.10

BOTTOM VIEW

SEE DETAIL "X"

0.10 C

5

C

0 . 203 REF

C

0.75 ±0.05

0 . 02 NOM.

0 . 05 MAX.

0.08 C

SIDE VIEW

DETAIL "X"

( 2.30)

( 1.95)

NOTES:

( 8X 0.50)

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

(1.50)

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

( 2.90 )

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.20mm from the terminal tip.

PIN 1

Tiebar shown (if present) is a non-functional feature.

5.

6.

(6x 0.65)

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

( 8 X 0.25)

TYPICAL RECOMMENDED LAND PATTERN

Compliant to JEDEC MO-229 WEEC-2 except for the foot length.

7.

FN6935.3

November 1, 2011

30

ISL28108, ISL28208, ISL28408

Package Outline Drawing

M8.118B

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 7/11

5

3.0±0.10mm

A

8

D

4.9±0.20mm

DETAIL "X"

3.0±0.10mm

5

1.10 MAX

0.15 - 0.05mm

PIN# 1 ID

SIDE VIEW 2

1

2

B

0.65mm BSC

TOP VIEW

0.95 REF

0.86±0.05mm

H

GAUGE

PLANE

C

0.25

SEATING PLANE

0.23 - 0.36mm

3°±3°

0.10 ± 0.05mm

0.10 C

0.08

C A-B D

M

0.53 ± 0.10mm

DETAIL "X"

SIDE VIEW 1

(5.80)

NOTES:

1. Dimensions are in millimeters.

(4.40)

(3.00)

2. Dimensioning and tolerancing conform to JEDEC MO-187-AA

and AMSEY14.5m-1994.

3. Plastic or metal protrusions of 0.15mm max per side are not

included.

(0.65)

4. Plastic interlead protrusions of 0.15mm max per side are not

included.

(0.40)

5. Dimensions are measured at Datum Plane "H".

6. Dimensions in ( ) are for reference only.

(1.40)

TYPICAL RECOMMENDED LAND PATTERN

FN6935.3

November 1, 2011

31

ISL28108, ISL28208, ISL28408

Package Outline Drawing

M14.15

14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 1, 10/09

4

0.10 C A-B 2X

8.65

A

3

6

DETAIL"A"

0.22±0.03

D

14

8

6.0

3.9

4

0.10 C D 2X

0.20 C 2X

7

PIN NO.1

ID MARK

(0.35) x 45°

4° ± 4°

5

0.31-0.51

0.25M C A-B D

B

3

6

TOP VIEW

0.10 C

H

1.75 MAX

1.25 MIN

0.25

GAUGE PLANE

SEATING PLANE

C

0.10-0.25

1.27

0.10 C

SIDE VIEW

DETAIL "A"

(1.27)

(0.6)

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.

3. Datums A and B to be determined at Datum H.

(5.40)

4. Dimension does not include interlead flash or protrusions.

Interlead flash or protrusions shall not exceed 0.25mm per side.

5. The pin #1 indentifier may be either a mold or mark feature.

6. Does not include dambar protrusion. Allowable dambar protrusion

shall be 0.10mm total in excess of lead width at maximum condition.

(1.50)

7. Reference to JEDEC MS-012-AB.

TYPICAL RECOMMENDED LAND PATTERN

FN6935.3

November 1, 2011

32


型号：	ISL28408FBZ
厂家：	Intersil
描述：	40V Precision Single Supply Rail-Rail Output Low Power Operational Amplifiers 40V精密单电源轨对轨输出，低功耗运算放大器运算放大器光电二极管
文件：	总32页 (文件大小：1598K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL28408FBZ [INTERSIL]

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