ISL34340 [INTERSIL]
WSVGA 24-Bit Long-Reach Video Serdes with Bidirectional Side-Channel; WSVGA 24位长距离视频串行转换器与侧面的双向通道
| 型号： | ISL34340 |
| 厂家： | 
Intersil |
| 描述： | WSVGA 24-Bit Long-Reach Video Serdes with Bidirectional Side-Channel |
| 文件： | 总10页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL34340
®
Data Sheet
March 7, 2008
FN6255.0
WSVGA 24-Bit Long-Reach Video Serdes
with Bidirectional Side-Channel
Features
• 24-bit RGB transport over single differential pair
The ISL34340 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed
differential signal. This differential signal is converted back to
parallel video at the remote end by the deserializer. It also
transports auxiliary data bidirectionally over the same link
during the video vertical retrace interval.
• Bidirectional auxiliary data transport without extra
bandwidth and over the same differential pair
• 40MHz PCLK transports
- SVGA 800 x 600 @ 70fps, 16% blanking
- WSVGA 1024 x 600 @ 60fps, 8% blanking
• Internal 100Ω termination on high-speed serial lines
• DC balanced 8b/10b line code allows AC-coupling
- Provides immunity against ground shifts
Ordering Information
TEMP.
RANGE
(°C)
• Transmitter amplitude boost and pre-emphasis and
receiver equalization allow for longer cable lengths and
higher data rates
PART
PART
PKG.
DWG. #
NUMBER
MARKING
PACKAGE
ISL34340INZ* ISL34340INZ -40 to +85 64 Ld EPTQFP Q64.10x10B
(Note) (Pb-free)
• Same device for serializer and deserializer simplifies
inventory
*Add “-T13” suffix for tape and reel. Please refer to TB347 for details on
reel specifications.
2
• I C interface
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate PLUS ANNEAL - e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
• High-speed serial lines meet 8kV ESD rating
Applications
• Navigation and display systems
• Video entertainment systems
• Industrial computing terminals
• Remote cameras
Typical Application Diagram
3.3V
1.8V
VDD_IO
3.3V
1.8V
VDD_IO
24
24
10m DIFFERENTIAL
CABLE
RGB
27 nf
27 nf
27 nf
27 nf
RGB
SERIOP
SERIOP
VSYNC
HSYNC
DE
VSYNC
HSYNC
DE
VIDEO
SINK
VIDEO
SOURCE
ISL34340
(serializer mode)
ISL34340
(deserializer mode)
SERION
SERION
PCLK_IN
PCLK_OUT
PCLK_IN
REF_CLK
VDD_IO
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL34340
Pinout
ISL34340
(64 LD EPTQFP)
TOP VIEW
Block Diagram
SCL
SDA
I2C
VCM
GENERATOR
RAM
SERIOP
SERION
PRE-
EMPHASIS
TX
3
V/H/DE
MUX
DEMUX
TDM
8b/10b
RGB
24
RX EQ
VIDEO_TX
(HI)
CDR
PCLK_IN
(REF_CLK when
VIDEO_TX is LO)
x30
PCLK_OUT
÷30
FN6255.0
March 7, 2008
2
ISL34340
Absolute Maximum Ratings
Thermal Information
Supply Voltage
VDD_P to GND_P, VDD_TX to GND_TX,
Thermal Resistance (Typical, Notes 1, 2)
EPTQFP. . . . . . . . . . . . . . . . . . . . . . . .
θ
θ
(°C/W)
4.5
JA
33
JC
VDD_IO to GND_IO . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V
VDD_CDR to GND_CDR, VDD_CR to GND_CR . . -0.5V to 2.5V
Between any pair of GND_P, GND_TX,
GND_IO, GND_CDR, GND_CR . . . . . . . . . . . . . . . -0.1V to 0.1V
3.3V Tolerant LVTTL/LVCMOS Input Voltage . . . . . . . -0.5V to 4.6V
Differential Input Voltage . . . . . . . . . . . . . . .-0.3V to VDD_IO + 0.3V
Differential Output Current . . . . . . . . . . . . . .Short Circuit Protected
LVTTL/LVCMOS Outputs. . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 327mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model
All pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4kV
SERIOP/N (all VDD connected, all GND connected) . . . . . . .8kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P =
,
VDD_AN = 3.3V, T
A =
+25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF.
PARAMETER
POWER SUPPLY VOLTAGE
VDD_CDR, VDD_CR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1.7
3.0
1.8
3.3
1.9
3.6
V
V
VDD_TX, VDD_P, VDD_AN, VDD_IO
SERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current
Analog CDR Supply Current
Digital I/O Supply Current
I
VIDEO_TX = 1
PCLK_IN = 40MHz
17
57
1
mA
mA
mA
mA
mA
mA
mA
mA
DDTX
I
DDCDR
I
2
DDIO
Digital Supply Current
I
20
17
5.5
77
40
DDCR
PLL/VCO Supply Current
I
DDP
Analog Bias Supply Current
Total 1.8V Supply Current
I
DDAN
90
46
Total 3.3V Supply Current
DESERIALIZER POWER SUPPLY CURRENTS
Analog TX Supply Current
Analog CDR Supply Current
Digital I/O Supply Current
I
VIDEO_TX = 0
REF_CLK = 40MHz
24
45
17
32
17
5.4
77
64
mA
mA
mA
mA
mA
mA
mA
mA
DDTX
I
DDCDR
I
25
DDIO
Digital Supply Current
I
DDCR
PLL/VCO Supply Current
I
DDP
Analog BIAS Supply Current
Total 1.8V Supply Current
I
DDAN
90
80
Total 3.3V Supply Current
FN6255.0
March 7, 2008
3
ISL34340
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P =
,
VDD_AN = 3.3V, T
A =
+25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued)
PARAMETER
POWER-DOWN SUPPLY CURRENT
Total 1.8V Power-down Supply Current
Total 3.3V Power-down Supply Current
PARALLEL INTERFACE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RSTB = GND;
spec is per device
0.5
1
mA
mA
High Level Input Voltage
V
2.0
-10
V
V
IH
Low Level Input Voltage
V
0.8
10
IL
IN
Input Leakage Current
I
±0.01
µA
V
High Level Output Voltage
V
I
I
= -2.0mA, VDD_IO = 3V 0.8*VDD_IO
= 2.0mA, VDD_IO = 3V
OH
OH
OL
Low Level Output Voltage
V
0.2*VDD_IO
50
V
OL
Output Short Circuit Current
Output Rise and Fall Times
I
mA
ns
OSC
/t
t
Slew rate control set to min,
C = 8pF
L
1
4
OR OF
Slew rate control set to max,
ns
C = 8pF
L
SERIALIZER PARALLEL INTERFACE
PCLK_IN Frequency
f
6
40
60
MHz
%
IN
PCLK_IN Duty Cycle
t
40
3.6
1.6
50
IDC
Parallel Input Setup Time
t
ns
IS
Parallel Input Hold Time
t
ns
IH
DESERIALIZER PARALLEL INTERFACE
PCLK_OUT Frequency
f
6
40
MHz
%
OUT
PCLK_OUT Duty Cycle
t
50
0.5
±20
ODC
PCLK_OUT Period Jitter (rms)
PCLK_OUT Spread Width
Time to paRallel Output Data Valid
Deserializer Output Latency
t
Clock randomizer off
Clock randomizer on
Relative to PCLK_OUT
%Tpclk
%Tpclk
ns
OJ
t
OSPRD
t
-4.7
4
5.5
14
DV
t
Part-to-part,
9
PCLK
CPD
side-channel disabled
DESERIALIZER REFERENCE CLOCK (REF_CLK IS FED INTO PCLK_IN)
REF_CLK Lock Time
t
100
µs
PLL
REF_CLK to PCLK_OUT Clock Maximum
Frequency Offset
PCLK_OUT is the
recovered clock
1500
600
5000
ppm
HIGH-SPEED TRANSMITTER
HS Differential Output Voltage, Transition Bit
VOD
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
TXCN = 0x00
TXCN = 0x0F
TXCN = 0xF0
TXCN = 0xFF
825
1170
975
990
990
mV
mV
mV
mV
mV
mV
mV
mV
TR
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
1300
825
HS Differential Output Voltage, Non-Transition VOD
Bit
600
NTR
460
975
600
HS Generated Output Common Mode Voltage
V
2.35
V
OCM
FN6255.0
March 7, 2008
4
ISL34340
Electrical Specifications Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V VDD_TX = VDD_P =
,
VDD_AN = 3.3V, T
A =
+25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HS Common Mode Serializer-Deserializer
Voltage Difference
ΔV
20
120
mV
CM
HS Differential Output Impedance
HS Output Latency
R
80
4
100
7
120
10
Ω
PCLK
ps
OUT
t
Part-to-part
LPD
HS Output Rise and Fall Times
HS Differential Skew
t
t
20% to 80%
150
<10
13.4
40
R/ F
t
ps
SKEW
HS Output Random Jitter
t
t
ps
ps
RJ
DJ
rms
P-P
HS Output Deterministic Jitter
HIGH SPEED RECEIVER
HS Differential Input Voltage
HS Generated Input Common Mode Voltage
HS Differential Input Impedance
HS Maximum Jitter Tolerance
V
150
80
mV
P-P
ID
V
2.32
100
V
ICM
R
120
Ω
IN
0.52
UI
P-P
2
I C
2
I C Clock Rate (on SCL)
F
100
400
1
kHz
I2C
2
I C Clock Pulse Width (HI or LO)
1.3
0
µs
µs
µs
ns
ns
ms
2
I C Clock Low to Data Out Valid
2
I C Start/Stop Setup/Hold Time
0.6
100
100
100
2
I C Data in Setup Time
2
I C Data in Hold Time
2
I C Data out Hold Time
Pin Descriptions
DESCRIPTION
PIN NUMBER
PIN NAME
RGBA[7:0],
SERIALIZER
DESERIALIZER
52 to 63,
2 to 13
Parallel video data LVCMOS inputs
Parallel video data LVCMOS outputs
RGBB[7:0], RGBC[7:0]
22
23
HSYNC
Horizontal (line) Sync LVCMOS input
Vertical (frame) Sync LVCMOS input
Video Data Enable LVCMOS input
Pixel clock LVCMOS input
Horizontal (line) Sync LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
High speed differential serial I/O
VSYNC
21
DATAEN
26
PCLK_IN
51
PCLK_OUT
SERIOP/N
HSYNCPOL
Default not used
41, 40
24
High speed differential serial I/O
CMOS input for HSYNC
1: HSYNC is active low
0: HSYNC is active high
25
49
VSYNCPOL
VIDEO_TX
CMOS input for VSYNC
1: VSYNC is active low
0: VSYNC is active high
CMOS input for video flow direction
1: video serializer
0: video deserializer
FN6255.0
March 7, 2008
5
ISL34340
Pin Descriptions (Continued)
DESCRIPTION
PIN NUMBER
29, 30
PIN NAME
SDA, SCL
SERIALIZER
DESERIALIZER
2
I C Interface Pins (I2C DATA, I2C CLK)
2
31-33
I2CA[2:0]
I C Device Address
16
RSTB/PDB
CMOS input for Reset and Power-down. For normal operation this pin must be forced high. When
this pin is forced low, the device will be reset. If this pin stays low the device will be in PD mode.
14
STATUS
CMOS output for Receiver Status:
1: Valid 8b/10b data received
0: otherwise
Note: serializer and deserializer switch roles during side-channel reverse traffic
36
27
REF_RES
GND_P
Analog bias setting resistor connection; use 3.16kΩ ±1% to ground
PLL Ground
48, 64
44, 45
39, 42
37
GND_IO
Digital (Parallel and Control) Ground
Analog (Serial) Data Recovery Ground
Analog (Serial) Output Ground
Analog Bias Ground
GND_CDR
GND_TX
GND_AN
GND_CR
VDD_CR
VDD_TX
17, 18
19, 20
43
Core Logic Ground
Core Logic VDD
Analog (Serial) Output VDD
Analog Bias VDD
38
VDD_AN
VDD_CDR
VDD_IO
46, 47
1, 50
Analog (Serial) Data Recovery VDD
Digital (Parallel and Control) VDD
PLL VDD
28
VDD_P
15, 35
Exposed Pad
TEST_EN, TEST
Exposed Pad
Must be connected to ground
Must be connected to ground
NOTES:
3. Pins with the same name are internally connected together. However, this connection must NOT be used for connecting together external
components or features.
4. The various differently-named Ground pins are internally weakly connected. They must be tied together externally. The different names are
provided to assist in minimizing the current loops involved in bypassing the associated supply VDD pins. In particular, for ESD testing, they
should be considered a common connection.
FN6255.0
March 7, 2008
6
ISL34340
Diagrams
VODTR
VODNTR
TXCN
0x00
0x0F
0xF0
0xFF
FIGURE 1. VOD vs TXCN SETTING
t
IDC
VIDEO_TX = 1
1/f
IN
PCLK_IN
t
t
IH
IS
VALID DATA
VALID DATA
RGB[A:C][7:0]
DATA IGNORED
DATA IGNORED
VALID DATA
t
IS
t
IH
HSYNC
VSYNC
DATAEN
FIGURE 2. PARALLEL VIDEO INPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
FN6255.0
March 7, 2008
7
ISL34340
VIDEO_TX = 0
t
t
ODC
t
OR
OF
1/f
OUT
PCLK_OUT
t
DV
VALID DATA
VALID DATA
RGB[A:C][7:0]
DATA HELD AT PREVIOUS VALUE
VALID DATA
t
DV
HSYNC
VSYNC
DATAEN
FIGURE 3. PARALLEL VIDEO OUTPUT TIMING [HSYNCPOL = 0, VSYNCPOL = 0, PCLKPOL (reg) = 0]
PCB traces need to be adjacent and matched in length (so
Applications
Overview
as to minimize the imbalanced coupling to other traces or
elements), and of a geometry to match the impedance of the
transmitter and receiver, to minimize reflections. Similar care
needs to be applied to the choice of connectors and cables.
A pair of ISL34340 serdes transports 24-bit parallel video
(16-bit parallel video for the ISL34320) along with auxiliary
data over a single 100Ω differential cable either to a display
or from a camera. Auxiliary data is transferred in both
directions and can be used for remote configuration and
telemetry.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines. External termination
cannot be used unless the side-channel is disabled.
SERIO Pin AC-Coupling
The benefits include lower EMI, lower costs, greater
reliability and space savings. The same device can be
configured to be either a serializer or deserializer by setting
one pin (VIDEO_TX), simplifying inventory. RGBA/B/C,
VSYNC, HSYNC, and DATAEN pins are inputs in serializer
mode and outputs in deserializer mode.
AC-coupling minimizes the effects of DC common mode
voltage difference and local power supply variations
between two serdes. The serializer outputs DC balanced
8b/10b line code, which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nf on
the serializer board and 27nf on the deserializer board. The
value of the AC-coupling capacitor is very critical since a
value too small will attenuate the high speed signal at low
clock rate. A value too big will slow down the turn around
time for the side-channel.
The video data presented to the serializer on the parallel
LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel
video at the remote end by the deserializer. The
side-channel data is transferred between the serdes pair
during two lines of the vertical video blanking interval.
Receiver Reference Clock (REF_CLK)
When the side-channel is enabled, there will be a number of
PCLK cycles uncertainty from frame-to-frame. This should
not cause sync problems with most displays, as this occurs
during the vertical front porch of the blanking period. When
properly configured, the serdes link supports end-to-end
The reference clock (REF_CLK) for the PLL is fed into
PCLK_IN pin. REF_CLK is used to recover the clock from
the high speed serial stream. REF_CLK is very sensitive to
any instability. The following conditions must be met at all
times after power is applied to the deserializer, or else the
deserializer may need a manual reset:
10
transport with fewer than one error in 10 bits.
• REF_CLK frequency must within the limits specified
• REF_CLK amplitude must be stable.
Differential Signals and Termination
The ISL34340 serializes the 24-bit parallel data at 30x the
PCLK_IN frequency. The ISL34320 serializes the 16-bit
parallel data at 20x the PCLK_IN frequency. The extra two
bits per word come from the 8b/10b encoding scheme.
A simple 3.3V CMOS crystal oscillator can be used for
REF_CLK.
Power Supply Sequencing
The high bit rate of the differential serial data requires
special care in the layout of traces on PCBs, in the choice
and assembly of connectors, and in the cables themselves.
The 3.3V supply must be higher than the 1.8V supply at all
times, including during power-up and power-down. To meet
FN6255.0
March 7, 2008
8
ISL34340
this requirement, the 3.3V supply must be powered up
before the 1.8V supply.
Capacitors of 0.1µF offer low impedance in the 10MHz to
20MHz region, and 1000pF capacitors in the 100MHz to
200MHz region. In general, one of the lower value capacitors
should be used at each supply pin on the IC. Figure 4 shows
the grounding of the various capacitors to the pin
corresponding to the supply pin. Although all the ground
supplies are tied together, the PCB layout should be
arranged to emulate this arrangement, at least for the
smaller value (high frequency) capacitors, as much as
possible.
For the deserializer, REF_CLK must not be applied before
the device is fully powered up. Applying REF_CLK before
power-up may require the deserializer to be manually reset.
A 10ms delay after the 1.8V supply is powered up
guarantees normal operation.
Power Supply Bypassing
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or
locked to an incoming signal. It is important that the various
supplies (VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well
bypassed over a wide range of frequencies, from below the
typical loop bandwidth of the PLL to approaching the signal
bit rate of the serial data. A combination of different values of
capacitors from 1000pF to 5µF or more with low ESR
characteristics is generally required.
The parallel LVCMOS VDD_IO supply is inherently less
sensitive, but since the RGB and SYNC/DATAEN signals
can all swing on the same clock edge, the current in these
pins and the corresponding GND pins can undergo
substantial current flow changes, so once again, a
combination of different values of capacitors over a wide
range, with low ESR characteristics, is desirable.
A set of arrangements of this type is shown in Figure 4,
where each supply is bypassed with a ferrite-bead-based
choke, and a range of capacitors. A “choke” is preferable to
an “inductor” in this application, since a high-Q inductor will
be likely to cause one or more resonances with the shunt
capacitors, potentially causing problems at or near those
frequencies, while a “lossy” choke will reflect a high
impedance over a wide frequency range.
FIGURE 4. POWER SUPPLY BYPASSING
2
I C Interface
2
The I C interface allows access to internal registers used to
configure the serdes and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart. The upper 3-bits are permanently
set to 011 and the lower 4 bits determined by pins as follows:
The higher value capacitor, in particular, needs to be chosen
carefully, with special care regarding its ESR. Very good
results can be obtained with multilayer ceramic capacitors,
available from many suppliers, and generally in small
outlines (such as the 1210 outline suggested in the
schematic shown in Figure 4), which provide good bypass
capabilities down to a few mΩ at 1MHz to 2MHz. Other
capacitor technologies may also be suitable (perhaps
niobium oxide), but “classic” electrolytic capacitors
0
1
1
I2CA3 I2CA2 I2CA1 I2CA0 R/W
Thus, 16 serdes can reside on the same bus. By convention,
when all address pins are tied low, the device address is
referred to as 0x60.
SCL and SDA are open drain to allow multiple devices to
share the bus. If not used, SCL and SDA should be tied to
VDD_IO.
frequently have ESR values of above 1Ω, that nullify any
decoupling effect above the 1kHz to 10kHz frequency range.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6255.0
March 7, 2008
9
ISL34340
Thin Plastic Quad Flatpack Exposed Pad Plastic Packages (EPTQFP)
D
Q64.10x10B (JEDEC MS-026ACD-HU ISSUE D)
D1
-D-
64 LEAD THIN PLASTIC QUAD FLATPACK EXPOSED
PAD PACKAGE
MILLIMETERS
SYMBOL
MIN
-
MAX
1.20
NOTES
A
A1
A2
b
-
0.05
0.95
0.16
0.17
11.80
9.90
3.46
11.80
9.90
3.46
0.45
0.15
-
-B-
-A-
1.05
-
0.28
6
b1
D
0.23
-
E1
E
12.20
10.10
3.76
3
D1
D2
E
4, 5
-
e
12.20
10.10
3.76
3
E1
E2
L
4, 5
-
0.75
-
N
64
7
PIN 1
e
0.50 BSC
-
TOP VIEW
Rev. 0 2/07
o
o
NOTES:
11 -13
0.020
0.008
1. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
MIN
o
0
MIN
2. All dimensions and tolerances per ANSI Y14.5M-1982.
3. Dimensions D and E to be determined at seating plane -C- .
A2
o
A1
GAGE
PLANE
o
o
0 -7
4. Dimensions D1 and E1 to be determined at datum plane
-H- .
L
o
11 -13
5. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is 0.25mm (0.010 inch) per side.
0.25
0.010
6. Dimension b does not include dambar protrusion. Allowable
dambar protrusion shall not cause the lead width to exceed
the maximum b dimension by more than 0.08mm (0.003
inch).
PIN 1
7. “N” is the number of terminal positions.
SEATING
PLANE
A
-H-
0.08
0.003
E2
-C-
0.08
0.003
D
b
M
C
A-B S
S
b1
0.09/0.16
0.004/0.006
D2
BASE METAL
WITH PLATING
0.09/0.20
BOTTOM VIEW
0.004/0.008
FN6255.0
March 7, 2008
10
相关型号：
ISL34340INZ
SPECIALTY INTERFACE CIRCUIT, PQFP64, 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MS-026ACD-HU, TQFP-64
RENESAS
ISL34340INZ-T13
SPECIALTY INTERFACE CIRCUIT, PQFP64, 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MS-026ACD-HU, TQFP-64
RENESAS
ISL34341INZ-T13
WSVGA 24-Bit Long-Reach Video SERDES with Bi-directional Side-Channel; TQFP64; Temp Range: -40° to 85°C
RENESAS
©2020 ICPDF网 联系我们和版权申明