ISL37231DRAZ-TS [INTERSIL]

10.3125 Gb/s Retiming Dual-Channel Transceiver;


型号：	ISL37231DRAZ-TS
厂家：	Intersil
描述：	10.3125 Gb/s Retiming Dual-Channel Transceiver 接口集成电路
文件：	总9页 (文件大小：320K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

10.3125 Gb/s Retiming Dual-Channel Transceiver

ISL37231

Features

• Industry’s lowest power and highest performance

10.3125Gbps active cable solution for STP and twin-axial

cables

The ISL37231 is an advanced dual-channel, dual-simplex

retimer for active copper cable applications. Endowed with

sophisticated functions, such as media optimized (PCB or

Cable) and adaptive equalization, de-emphasis, and signal

retiming, this IC fortifies sensitive links that break with lesser

retiming solutions. The device contains high performance

mixed signal processing technology to provide a maximally

robust signal integrity solution for datacenter and consumer

applications. Such processing includes up to 25dB of

media-optimized equalization and versatile retiming

capabilities to reset link jitter budgets.

• Supports 64b/66b encoding

• Fully retimed low jitter outputs

• Up to 16.5dB of adjustable (or adaptive) receiver-side

equalization

• 9dB output de-emphasis

• Supports independent SSC on each channel

• On-chip microcontroller and eye monitor

• Multiple loopback modes

The ISL37231 provides this high level of performance while

significantly reducing power consumption relative to other

active cable solutions. At well below 500mW, the operating

power is the lowest in class, and a sleep mode function can be

invoked to reduce the power to a miniscule 3mW.

• Low power (<420mW) operation with 3mW sleep mode

• Ultra-small 5mmx5mm aQFN package

To facilitate ease of system integration, the ISL37231 provides

advanced diagnostic capabilities in the form of loopback and

high-resolution on-chip eye monitor functions, both accessed

via a UART interface.

Applications

• Thunderbolt™ active cables

• Proprietary high-speed active cable assemblies

The ISL37231 is optimized to work in conjunction with the

ISL80083 power management IC, however, it will also operate

with appropriate discrete components (voltage regulators and

a 33Mhz crystal oscillator).

Benefits

• Thinner gauge cable

• Extends cable reach

• Improved BER

ACTIVE CABLE

CABLE CONNECTOR

ISL37231

CABLE CONNECTOR

CABLE MEDIA

ISL37231

EQ CDR

TX1

RX1

EQ CDR DE

AI1

AO1

BI1

AO1

BI2

BO1

CDR EQ

RX1

TX2

BO1

AI2

AI1

TX1

RX2

EQ CDR

AO2

BI2

DE BO2

CDR EQ

µC

DE CDR EQ

AI2

AO2

BO2

TX2

RX2

GND

µC

PWR

ISL80083

EEPROM

ISL80083

FIGURE 1. TYPICAL APPLICATION

January 25, 2013

FN8266.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL37231

Ordering Information

PART NUMBER

(Notes 2, 3)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL37231DRAZ-TS (Note 1)

ISL37231DRAZ-T7 (Note 1)

ISL37231DRAZ

ISL372 31DRAZ

0 to +85

69 Ld High Density Array (aQFN)

package (7” 100 pcs.)

C69.5x5B

ISL372 31DRAZ

69 Ld High Density Array (aQFN)

package (7” 1k pcs.)

C69.5x5B

69 Ld High Density Array (aQFN)

package

NOTES:

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate

- e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL37231. For more information on MSL please see techbrief TB363.

Pin Configuration

ISL37231

(69 LD aQFN)

TOP VIEW

A42

A41

A40

A39

A38

A37

A36

A35

A34

A33

A32

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A10

A11

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

EXPOSED PAD

B10

B11

B12

B13

B14

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

FN8266.1

January 25, 2013

ISL37231

Pin Functions and Definitions

PIN NAME

PIN NUMBER

DIRECTION

DESCRIPTION

High-speed differential input for on-ramp (device to cable) Channel 1, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

AIN1[P,N]

A1, A42

Input

A2, A10, A13, A16,

A17, A20, A23, A30,

A31, A34, A37, A38,

A41, B4, B6, B7, B16,

B19, B20, B26, B27,

Exposed Pad

Ground. For proper electrical and thermal performance, each of these pads must be connected

to the PCB ground plane. For the exposed pad, 3x5 or 4x5 via pattern is recommended,

assuming 0.004" diameter vias.

GND

External 33MHz crystal oscillator input/output. An external 33MHz clock source (1V CMOS logic

level) can optionally be connected XTALP, in which case XTALN must be left floating. A

differential 33MHz clock source (1V CMOS logic levels) can be input on XTALP and XTALN if

OSCMODE (pin A29) is pulled high to 1.8V.

XTAL[P,N]

A3, B1

Input

Auxiliary UART output 1. AUTX1 can be configured via the on-chip microcontroller as either a

UART output or a GPIO pin, with either 1.8V push-pull or 3.3V tolerant open drain voltage levels.

AUTX1

AURX1

EEWE

Output

Input

Auxiliary UART data input 1, 1.8V powered CMOS logic tolerant to 3.3V.

EEPROM write enable open drain output. Externally pulled high to 3.3V via a ≥5kΩ resistor.

Output

Pulled low when the ISL37231 writes to an external EEPROM device via the I²C serial interface.

Thunderbolt CONFIG2 indicator output. 1.8V powered CMOS logic. Pulled high after the

ISL37231 is powered up and stable to indicate to a Thunderbolt controller that a Thunderbolt

cable has been plugged in.

CFIG2

Output

Oscillator enable. CMOS logic, 1.8V. Used as a deep-sleep state indicator. During normal

operation, OSCEN is pulled high. When entering deep-sleep mode, OSCEN is pulled low. Output

is not pulled high again until transitions are detected on the URX input pin (A27).

OSCEN

AUTX2

Auxiliary UART output 2. AUTX2 can be configured via the on-chip microcontroller as either a

UART output or a GPIO pin, with either 1.8V push-pull or 3.3V tolerant open drain voltage levels.

Output

Input

High-speed differential input for off-ramp (cable to device) Channel 1, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

(Note 4)

BIN1[P,N]

A11, A12

High-speed differential output for off-ramp (cable to device) Channel 1, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

BOUT1[N,P]

BOUT2[P,N]

A14, A15

A18, A19

Output

High-speed differential output for off-ramp (cable to device) Channel 2, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

High-speed differential input for off-ramp (cable to device) Channel 2, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

(Note 4)

BIN2[N,P]

A21, A22

Input

Level shift enable output. 1.8V powered CMOS logic. Pulled high to indicate an operational UART

interface to the ISL37231. When pulled low, UTX (pin A28) is set to a high impedance state.

Serial interface clock. Open drain output, externally pulled high to 3.3V via a ≥5kΩ resistor. I²C

LSEN

SCL

A24

A25

A26

A27

Output

clock, recommended clock speed is 400kHz.

Serial interface data. Open drain output, externally pulled high to 3.3V via a ≥5kΩ resistor.

SDA

URX

Bi-directional data from/to I²C bus.

UART data input. 1.8V powered CMOS logic, but URX is 3.3V tolerant. When the ISL37231 is in

“Sleep” mode, a H to L transition on URX causes the ISL37231 to drive OSCEN high.

Input

UART data tri-statable output. 1.8V powered CMOS logic. UTX is set to a high impedance state

when the UART interface is not in use and LSEN is pulled low. If UTX interfaces to a 3.3V powered

UART, then a level translator IC may be needed.

UTX

A28

A29

Output

Oscillator mode. CMOS logic, 1.8V, internally pulled low. When OSCMODE is low, the XTALP and

XTALN input pins (A3 and B1) are configured for operation with an external crystal or with an

external single-ended clock on XTALP (XTALN must be left floating in this latter case). When

OSCMODE is pulled high, the XTALP and XTALN input pins are configured for operation with an

external differential clock.

OSCMODE

Input

FN8266.1

January 25, 2013

ISL37231

Pin Functions and Definitions(Continued)

PIN NAME

PIN NUMBER

DIRECTION

DESCRIPTION

High-speed differential input for on-ramp (PCB to cable) Channel 2, CML. The use of series

220nF, low ESL/ESR, MLCC capacitors with at least 8GHz frequency response is recommended.

AIN2[P,N]

A32, A33

Input

AOUT2[N,P]

AOUT1[P,N]

A35, A36

A39, A40

Output

High-speed differential output for on-ramp (PCB to cable) Channel 2, CML. (Note 4)

High-speed differential output for on-ramp (PCB to cable) Channel 1, CML. (Note 4)

B2, R1, R2, R3, R4

(Note 5)

1.0V analog supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground

is recommended for each of these pins/rails for broad high-frequency noise suppression.

AVDD1

AVDD18

1.8V analog supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground

is recommended for this pin for broad high-frequency noise suppression.

B4, B6, B7, B13, B14,

B19, B20, B26, B27

No connection. Do not connect to these pins.

1.0V digital supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground

is recommended for these pins for broad high-frequency noise suppression.

DVDD

B5, B15

VDDPLLB1

REFRETB1

REXT2

1.8V analog supply voltage for off-ramp Channel 1.

VDDPLL reference return path for off-ramp Channel 1.

External reference resistor connection. Recommended value of 1.18kΩ.

VDDPLL reference return path for off-ramp Channel 2.

1.8V analog supply voltage for off-ramp Channel 2.

B10

B11

B12

B16

REFRETB2

VDDPLLB2

AURX2

Input

Auxiliary UART input 2. CMOS logic, 1.8V (tolerant to 3.3V).

1.8V digital supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground

is recommended for each of these pins for broad high-frequency noise suppression.

VDDPST

B17

RESET

B18

B21

B22

B23

B24

B25

CMOS logic input. 1.8V powered. Resets all internal registers and memory when pulled low.

1.8V analog supply voltage for on-ramp Channel 2.

VDDPLLA2

REFRETA2

REXT1

VDDPLL reference return path for on-ramp Channel 2.

External reference resistor connection. Recommended value of 1.18kΩ.

VDDPLL reference return path for on-ramp Channel 1.

REFRETA1

VDDPLLA1

1.8V analog supply voltage for on-ramp Channel 1.

NOTES:

4. Series coupling capacitors are required at one end of the cable. For best results, place the capacitors at the receiver end of the cable. The use of

220nF low ESL/ESR MLCC capacitors with at least 8GHz frequency response is recommended.

5. Each power bar is independent, so they must all connect to the same 1V supply for proper circuit operation.

FN8266.1

January 25, 2013

ISL37231

Absolute Maximum Ratings

Thermal Information

Supply Voltage (V_DDto GND, 1.0V Rails) . . . . . . . . . . . . . . . . . . . . . . . . 1.1V

Supply Voltage (V_DDto GND, 1.8V Rails) . . . . . . . . . . . . . . . . . . . . . . . 1.98V

1V Pin Input Voltage (AIN, BIN, XTALP) . . . . . . . . . . . . . . . . . . . . . . . . . 1.1V

1.8V Pin Input Voltage (all non 3.3V tolerant logic inputs) . . . . V_DD+ 0.2V

3.3V Tolerant I/O Pin Voltage (EEWE, SCLK, SDA, URX, AUTX, AURX,

RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V

ESD Ratings

Thermal Resistance (Typical)

69 Ld aQFN Package (Notes 6, 7) . . . . . . .

Operating Ambient Temperature Range. . . . . . . . . . . . . . . . 0°C to +85°C

Storage Ambient Temperature Range. . . . . . . . . . . . . . . -55°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

_JA(°C/W)

31.8

_JC(°C/W)

2.5

Human Body Model (All Pins) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25kV

Charged Device Model (All Pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0kV

Machine Model (All Pins). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V

Latch-up (per JEDEC JESD78, Level 2, Class A) . . . . . . . . . . . . . . . . +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTE:

6. θ_JAis measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

7. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Operating Conditions Boldface limits apply across the operating temperature range, 0°C to +85°C.

MIN

MAX

PARAMETER

1.0V Supply Voltage

SYMBOL

CONDITION

(Note 12)

TYP

1.0

(Note 12)

UNITS

AVDD1,

DVDD

0.95

1.71

1.05

1.89

1.8V Supply Voltage

AVDD18,

VDDPLL,

VDDPST

1.8

Operating Ambient Temperature

Baud Rate

T_A

°C

NRZ data applied to any channel

9.95

10.3125

10.4

Gbps

Logic I/O Specifications Boldface limits apply across the operating temperature range, 0°C to +85°C.

MIN

MAX

PARAMETER

Input Leakage Current

SYMBOL

I_LEAK

CONDITION

(Note 12)

TYP

0.1

(Note 12)

UNITS

µA

Pins URX, AURX1, AURX2, RESET

-1

Pull-down Resistor Current

Input HIGH Voltage

I_PULLDOWNOSCMODE. V_IN= V_DD18

103

µA

V_IH

Pins URX, AURX1, AURX2, RESET,

3.4

0.7

OSCMODE

Input LOW Voltage

V_IL

Pins URX, AURX1, AURX2, RESET,

OSCMODE

Output LOW Voltage

Output High Voltage

V_OL

V_OH

I_OL= 2mA

I_OH= 2mA

0.4

1.4

V_DD18

FN8266.1

January 25, 2013

ISL37231

Electrical Characteristics T_A= +25°C, V_DD1= 1.0V, V_DD18= 1.8V, unless otherwise noted

MIN

MAX

PARAMETERS

SYMBOL

I_DD1

CONDITION

(Note 12)

TYP

430

(Note 12) UNITS

NOTES

1.0V Supply Current

(Combination of all 1V

Supplies)

Both lanes active, after equalizer has trained

and is static, no eye monitors enabled

510

No lanes active, but microcontroller awake

Sleep Mode

150

1.8V Supply Current

(Combination of all 1.8V

Supplies)

I_DD18

Both lanes active, after equalizer has trained

and is static, no eye monitors enabled

No lanes active, but microcontroller awake

Sleep Mode

330

-10

-6

µA

Return Loss Limit

(Differential)

_DD11

0.05GHz to 2GHz

_DD22

2GHz to 5.2GHz

5.2GHz to 7GHz

-5

Return Loss Limit (Common

Mode)

S_CC11

_CC22

10MHz to 5GHz

-5

-20

Return Loss Limit (Diff. to

Com. Conversion)

S_CD11

_CD22

10MHz to 5GHz

Input Equalization Range

EQ gain at 5GHz compared to DC. Set to

minimum gain

EQ gain at 5GHz compared to DC. Set to

maximum gain

16.5

1.5

Input Equalization

Increment

10 steps covering the Equalization range

Output De-Emphasis Level

Range

Off-ramp channels optimized for PCB

dielectric loss. On-ramp channels optimized

for cable skin loss. Minimum setting

Off-ramp channels optimized for PCB

dielectric loss. On-ramp channels optimized

for cable skin loss. Maximum setting

De-Emphasis Increment

Number of De-Emphasis

Taps

Output Differential

Amplitude Range

V_OUT

Minimum drive setting

Maximum drive setting

15 Uniform Steps

200

950

mV_P-P

Output Differential

Amplitude Increment

Output Transition Time

t_r, t_f

20% to 80%

Jitter Transfer Function

Bandwidth

MHz

Total Output Jitter

1E-13 BER; PRBS-31; no low frequency input

periodic jitter

UI_P-P

0.3

0.5

SSC Down Spreading

Amplitude Tolerance

SSC Modulation Rate

Tolerance

kHz

33-37

NOTES:

8. The specified Sleep Mode currents can only be achieved when the ISL37231 is used in conjunction with the ISL80083 power management IC.

9. Measured with a Vector Network Analyzer with 100Ω -diff impedance and the ISL37231 input/output impedance at setting 0x07 (i.e. 100Ω-diff).

10. The equalization response includes all effects starting from the IC input pins up to the output of the equalization stage.

11. Three de-emphasis taps composed of: 1 pre-cursor + main + 1 post-cursor.

12. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN8266.1

January 25, 2013

ISL37231

Loopback

Operation

To facilitate system diagnostics, a loopback mode is available for

each signal direction. In particular, for each lane, two loopback

paths are provided:

The ISL37231 is a robust signal conditioner that ensures

maximum performance across a variety of time-varying and

unpredictable environments. Endowed with functions, such as

transmit and receive equalization, signal retiming, and

programmable impedance termination, this IC fortifies sensitive

links that break with other retiming-based solutions. To facilitate

systems analysis, the ISL37231 additionally provides visibility of

link conditions by way of loopback modes, PRBS generators with

error counters, and an on-chip eye-monitor.

• Near-End/PCB Loopback: The received on-ramp signal is

directed back into the off-ramp output driver. This includes

PCB equalization, limiting, retiming, and PCB de-emphasis.

• Far-End/Cable Loopback: The received off-ramp signal is

directed back into the on-ramp output driver. This includes

cable equalization, limiting, retiming, and cable de-emphasis.

Equalization

The ISL37231 equalizes each received signal with a highly

adjustable equalizer.

Eye Monitor

For accurate and detailed analysis of signal integrity, each

channel in the ISL37231 can provide an on-chip eye-diagram of

its respective equalizing filter output. This eye diagram can be

used to evaluate jitter and eye height at the input of the retime

circuit’s slicer.

Each received signal is equalized with a five stage

continuous-time linear filter that can be optimized for either

copper cable skin loss or dielectric loss. The amount of

equalization is selectable between 0dB and 16.5dB of

compensation in increments of 1.5dB. Because the filter is

phase/jitter-optimized, the maximum 16.5dB compensation

level yields very low jitter for its targeted 2m (~20dB) 34AWG

cable length.

The eye monitor (in conjunction with the on-chip microcontroller)

generates up to a 50 pixel x 50 pixel resolution eye-diagram (i.e.

down to 0.02 UI resolution in the time domain and 12mV

resolution in the voltage domain) that can be read over the UART

interface. The output eye diagram represents an estimated

probability density function for the equalized signal under

investigation.

In addition to supporting a wide variety of programmable

settings, all channel equalizers can be trained upon power up to

minimize jitter. The training of all channels is completed within

2.5ms of receiving valid data on the input ports after power up.

Besides providing a full eye-diagram, the Eye-Monitor can also be

directed to output only the temporal and/or voltage eye-opening

for a more concise signal fidelity assessment (i.e., jitter and eye

height, respectively).

Retiming

To provide maximum system robustness, the ISL37231 retimes

each of the four data paths in the device prior to output. With

independent PLLs for each channel, the device can operate each

channel with asynchronous baud rates thereby permitting a high

degree of system flexibility. Examples where such flexibility is

crucial include independent or staggered SSC rates across

different channels and asymmetric transmission where up and

down-stream channels operate at different baud rates.

Polarity Inversion

To accommodate uncertainty in signal polarity (as may be

associated with differential cable receive pairs), each channel

can be independently programmed to invert its polarity.

On-Chip Microcontroller

An internal microcontroller is used to manage the operation of

the ISL37231.

Each retimer has high input jitter tolerance and can output less

than 0.3UI of total jitter (provided the inherent RJ of the test

equipment is de-embedded and no input low-frequency periodic

jitter is present).

The microcontroller communicates with the system host over a

UART interface. Because the ISL37231 UART interface operates

at 1.8V, an interfacing IC (such as the ISL80083) is required for

applications needing 3.3V levels and tri-state (push/pull/no-load)

operation.

Output De-Emphasis

The drive level output of any channel is adjustable from 200 to

950mVppd rail-to-rail (170 to 807.5mVppd eye height) in 16

equal increments.

The microcontroller also includes an I²C interface where the

ISL37231 serves as the master. This I²C bus is used to:

Each driver supports output equalization with one tap of

pre-cursor and one tap of post-cursor de-emphasis. The gains on

the pre and post-cursor taps are adjustable between 0 and -1

relative to the main tap in increments of 1/128. The output

amplitude and de-emphasis for each channel can be

independently programmed to accommodate routing variation

between lanes.

• Instruct a power-regulator providing the 1.0V supply that the

system is entering sleep mode and power can be removed

from non-critical 1.0V rails for maximum power savings during

sleep state.

• Load firmware from an external EEPROM.

FN8266.1

January 25, 2013

ISL37231

Intersil Lane Extenders allow greater reach over existing cabling

About Q:ACTIVE® Technology

while reducing the need for thicker cables. This significantly

reduces cable weight and clutter, increases airflow, and improves

power consumption.

Intersil has long realized that to enable the complex server

clusters of next generation data centers, it is critical to manage

the signal integrity issues of electrical interconnects. To address

this, Intersil has developed its groundbreaking Q:ACTIVE®

product line. By integrating its analog ICs inside cabling

interconnects, Intersil is able to achieve unsurpassed

improvements in reach, power consumption, latency, and cable

gauge size as well as increased airflow in tomorrow’s data

centers. This new technology transforms passive cabling into

intelligent “roadways” that yield lower operating expenses and

capital expenditures for the expanding datacenter.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN8266.1

FN8266.0

CHANGE

January 17, 2013

December 19, 2012

Changed TYP values for “I_DD1” on page 6.

Initial release

About Intersil

Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management

semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,

personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of

our winning team, visit our website and career page at www.intersil.com.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.

Also, please check the product information page to ensure that you have the most updated datasheet: ISL37231

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8266.1

January 25, 2013

ISL37231

Package Outline Drawing

C69.5x5B

69 LEAD aQFN 5X5 PACKAGE WITH 0.40 PITCH

Rev 1, 12/12

MILLIMETER

INCH

SYMBOL MIN NOM. MAX

MIN NOM. MAX

0.85

0.033

PIN 1

CORNER

0.020 0.050 0.080 0.001 0.002 0.003

0.640 0.675 0.710 0.025 0.027 0.028

0.120 0.130 0.140 0.005 0.005 0.006

0.170 0.200 0.230 0.007 0.008 0.009

4.900 5.000 5.100 0.193 0.197 0.201

2.780 2.880 2.980 0.109 0.113 0.117

4.900 5.000 5.100 0.193 0.197 0.201

1.940 2.040 2.140 0.076 0.080 0.084

eee C

0.400

0.016

aaa C

ccc C

TOP VIEW

0.200 0.250 0.300 0.008 0.010 0.012

0.160 0.210 0.260 0.006 0.008 0.010

0.230 0.280 0.330 0.009 0.011 0.013

0.260 0.310 0.360 0.010 0.012 0.014

0.330 0.380 0.430 0.013 0.015 0.017

0.150 0.180 0.210 0.006 0.007 0.008

TOLERANCES OF FORM AND POSITION

SECTION C-C

2.50 PKG.

aaa

bbb

ddd

ccc

eee

fff

0.100

0.050

0.100

0.004

0.002

0.004

2.12

2.00

1.72

1.60

1.41

1.23

1.20

A12 A13 A14 A15 A16 A17 A18 A19 A20 A21

B6 B7 B8 B9 B10 B11 B12B13 B14

A22

A23

A11

A10

PWR1

PWR2

A24

A25

0.95

B15

1.02

A26

A27

B16

B17

0.00

0.92

1.00

C.L(PKG.)

A28

A29

B18

1.02

0.95

fff M C A B

1.20

1.23

1.41

1.60

1.72

2.00

2.12

A30

A31

A32

PWR4

PWR3

NOTE:

B27 B26 B25 B24 B23 B22 B21B20 B19

1. Controlling dimension: mm

A42 A41 A40 A39 A38 A37 A36 A35 A34 A33

2.50 PKG.

"B"

bbb

ddd

C A B

(PIN 1 CORNER)

fff M C A B

DETAIL "B" (3:1)(69X)

BOTTOM VIEW

FN8266.1

January 25, 2013

ISL37231DRAZ-TS [INTERSIL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E