ISL54047IRUZ-T_技术文档

ISL54047

®

Data Sheet

May 31, 2007

FN6503.0

Ultra Low ON-Resistance, High Off-

Isolation, Single Supply, Diff SPST Analog

Switch

Features

• T-Switch Architecture

• OFF-Isolation at 100kHz

The Intersil ISL54047 device is a low ON-resistance, low

voltage, high off-isolation, bidirectional, differential single-

pole/single-throw (SPST) analog switch. It was designed to

operate from a single +1.65V to +4.5V supply. Targeted

applications include battery powered equipment that benefit

- Into 50Ω Load . . . . . . . . . . . . . . . . . . . . . . . . . . . 102dB

- Into 8Ω Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118dB

• ON Resistance (R

)

ON

- V+ = +4.3V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.44Ω

- V+ = +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51Ω

- V+ = +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.98Ω

from low R (0.44Ω) and fast switching speeds (t

= 40ns,

= 35ns). The digital logic input is 1.8V logic-compatible

ON ON

t

OFF

• R

Matching Between Channels . . . . . . . . . . . . . . . . 0.04Ω

Flatness Across Signal Range . . . . . . . . . . . . . . . 0.07Ω

when using a single +3V supply.

ON

• R

The ISL54047 has been designed with a T-switch

architecture. This approach results in maximum off-isolation

while retaining a low impedance signal path when switches

are ON.

• Single Supply Operation . . . . . . . . . . . . . . . +1.65V to +4.5V

• Low Power Consumption (P ). . . . . . . . . . . . . . . <0.45μW

D

• Fast Switching Action (V+ = +4.3V)

The device can be used as a low impedance bypass element

for noisy amplifier circuits.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns

OFF

The ISL54047 has two normally open (NO) SPST switches

that are controlled by a single logic control pin.

• ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

• 1.8V Logic Compatible (+3V supply)

TABLE 1. FEATURES AT A GLANCE

ISL54047

• Low ICC Current when VinH is not at the V+ Raill

• Available in 10 lead 1.8 x 1.4 x 0.5mm μTQFN

• Pb-Free Plus Anneal Available (RoHS Compliant)

Number of Switches

SW

2

SPST

4.3V R

0.44Ω

ON

Applications

4.3V t /t

40ns/35ns

ON OFF

• Battery powered, Handheld, and Portable Equipment

- Cellular/mobile Phones

3V R

0.51Ω

50ns/40ns

ON

3V t /t

- Pagers

ON OFF

- Laptops, Notebooks, Palmtops

1.8V R

0.98Ω

ON

1.8V t /t

• Portable Test and Measurement

• Medical Equipment

70ns/65ns

ON OFF

Package

10 Ld 1.8 x 1.4 x 0.5mm μTQFN

• Audio and Video Switching

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54047

Truth Table

Pinout (Note 1)

ISL54047 (μTQFN)

LOGIC

NO1, NO2

OFF

TOP VIEW

0

1

COM2

7

GND

6

ON

8

5

COM1

IN

N.C.

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

4

9

Pin Descriptions

N.C.

NO2

FUNCTION

System Power Supply Input (+1.65V to +4.5V)

Ground Connection

10

3

N.C.

V+

2

1

GND

IN

V+

NO1

Digital Control Input

NOTE:

COMx

NOx

N.C.

Analog Switch Common Pin

Analog Switch Normally Open Pin

No Connect

1. Switches Shown for Logic “0” Input.

Ordering Information

PART NUMBER

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Note)

PART MARKING

TEMP. RANGE (°C)

ISL54047IRUZ-T

D

-40 to +85

10 Ld 1.8 x 1.4 x 0.5mm μTQFN L10.1.8x1.4A

Tape and Reel

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination

finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-

free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.

FN6503.0

May 31, 2007

2

ISL54047

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5.5V

Input Voltages

NO, IN (Note 2) . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Continuous Current NO, COM. . . . . . . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, COM

Thermal Resistance (Typical)

θ

(°C/W)

143

θ

(°C/W)

61

JA

JC

10 Ld μTQFN Package (Note 3) . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>8kV

MM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>500V

CDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kV

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. Extended operation above the recommended

operating conditions could result in decreased reliability. The Absolute Maximum Ratings are stress only ratings and operation of the device at these or any other

conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NOx, IN, or COMx pins exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

Unless Otherwise Specified

= 1.6V, V

= 0.5V (Note 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

Full

25

0

-

V+

V

Ω

ANALOG

ON Resistance, R

V+ = 3.9V, I

= 100mA, V = 0V to V+,

NO

-

0.45

0.55

0.04

0.07

0.08

-

ON

COM

(See Figure 4)

Full

25

-

Ω

R

Matching Between Channels, V+ = 3.9V, I

COM

ON

= 100mA, V

NO

= Voltage at max R

ON,

-

Ω

ON

ΔR

(Note 7)

Full

25

-

Ω

R

Flatness, R

V+ = 3.9V, I

= 100mA, V = 0V to V+, (Note 6)

NO

-

Ω

ON

FLAT(ON)

COM

Full

25

-

Ω

NO OFF Leakage Current,

V+ = 4.5V, V

= 0.3V, 3V, V

NO

= 3V, 0.3V

-100

-195

-100

-195

100

195

100

195

nA

COM

I

NO(OFF)

Full

25

-

COM ON Leakage Current,

V+ = 4.5V, V

Floating

= 0.3V, 3V, or V

NO

= 0.3V, 3V, or

-

COM

I

COM(ON)

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 3.9V, V

= 3.0V, R =50Ω, C = 35pF,

25

Full

25

-

40

50

-

ns

pC

dB

ON

NO

(See Figure 1)

L

Turn-OFF Time, t

V+ = 3.9V, V

= 3.0V, R =50Ω, C = 35pF,

35

OFF

NO

(See Figure 1)

L

Full

25

45

Charge Injection, Q

OFF Isolation

C

R

= 1.0nF, V = 2V, R = 0Ω, (See Figure 2)

192

102

L

G

= 50Ω, C = 5pF, f = 100kHz, V

= 1V ,

RMS

25

L

COM

(See Figure 3)

OFF Isolation

R

= 50Ω, C = 5pF, f = 1MHz, V

= 1V

,

25

-

81

-95

-

dB

%

L

COM

RMS

(See Figure 3)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 1MHz, V

= 1V

,

L

(See Figure 5)

f = 20Hz to 20kHz, V

= 2V

, R = 600Ω

P-P

0.01

COM

L

FN6503.0

May 31, 2007

3

ISL54047

Electrical Specifications - 4.3V Supply

Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, V

Unless Otherwise Specified (Continued)

= 1.6V, V

= 0.5V (Note 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

NO OFF Capacitance, C

f = 1MHz, V

= V

= 0V, (See Figure 6)

25

-

46

-

pF

OFF

NO

COM

COM ON Capacitance, C

= V

= 0V, (See Figure 6)

25

233

COM(ON)

COM

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.65

4.5

0.1

1

V

Positive Supply Current, I+

V+ = +4.5V, V = 0V

IN

-

μA

Full

25

V+ = +4.5V, V = V+

IN

0.5

1

Full

25

V+ = +4.2V, V = 2.85V

IN

12

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.5

-

V

INL

Input Voltage High, V

1.6

-0.5

INH

Input Current, I

, I

V+ = 4.5V, V = 0V or V+

0.5

μA

INH INL

IN

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified

= 1.4V, V

= 0.5V (Note 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

0.55

-

V+

0.6

0.8

0.07

0.08

0.15

-

V

Ω

ON Resistance, R

V+ = 2.7V, I

(See Figure 4)

= 100mA, V

= 0V to V+,

NO

ON

COM

Full

25

Ω

R

Matching Between Channels, V+ = 2.7V, I

COM

= 100mA, V

NO

= Voltage at max R

ON

,

0.05

-

Ω

ON

ΔR

(Note 7)

ON

Full

25

Ω

R

Flatness, R

V+ = 2.7V, I

= 100mA, V = 0V to V+, (Note 6)

NO

0.1

-

Ω

ON

FLAT(ON)

COM

Full

25

Ω

NO OFF Leakage Current,

V+ = 3.3V, V

= 0.3V, 3V, V

NO

= 3V, 0.3V

0.9

30

0.8

30

nA

COM

I

NO(OFF)

Full

25

-

COM ON Leakage Current,

V+ = 3.3V, V

Floating

= 0.3V, 3V, or V

NO

= 0.3V, 3V, or

-

COM

I

COM(ON)

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 2.7V, V

= 1.5V, R = 50Ω, C = 35pF,

25

Full

25

-

50

60

-

ns

pC

dB

ON

NO

(See Figure 1)

L

Turn-OFF Time, t

V+ = 2.7V, V

= 1.5V, R = 50Ω, C = 35pF,

40

OFF

NO

(See Figure 1)

L

Full

25

50

Charge Injection, Q

OFF Isolation

C

R

= 1.0nF, V = 1.5V, R = 0Ω, (See Figure 2)

115

102

L

G

= 50Ω, C = 5pF, f = 100kHz, V

COM

= 1V

,

25

L

RMS

(See Figure 3)

OFF Isolation

R

= 50Ω, C = 5pF, f = 1MHz, V

= 1V

,

25

-

81

-

dB

L

COM

RMS

(See Figure 3)

Crosstalk (Channel-to-Channel)

R

= 50Ω, C = 5pF, f = 1MHz, V

= 1V

-95

L

COM

(See Figure 5)

FN6503.0

May 31, 2007

4

ISL54047

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, V

Unless Otherwise Specified (Continued)

= 1.4V, V

= 0.5V (Note 4),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

f = 20Hz to 20kHz, V = 2V , R = 600Ω

(°C)

MIN

TYP

MAX

UNITS

Total Harmonic Distortion

NO Capacitance, C

25

-

0.016

48

-

%

pF

COM

P-P

L

f = 1MHz, V

= V

= 0V, (See Figure 6)

25

OFF

COM ON Capacitance, C

NO

COM

= V

25

236

COM(ON)

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, I+

V+ = +3.6V, V = 0V or V+

IN

25

-

0.01

0.52

-

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

25

-

0.5

-

V

INL

Input Voltage High, V

1.4

-0.5

INH

Input Current, I

, I

V+ = 3.3V, V = 0V or V+

IN

Full

0.5

μA

INH INL

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.65V to +2V, GND = 0V, V

Unless Otherwise Specified

= 1.0V, V

= 0.4V (Note 4),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

V+

V

Ω

ON Resistance, R

V+ = 1.65V, I

= 100mA, V = 0V to V+,

NO

1.24

1.34

-

ON

COM

(See Figure 4)

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 1.65V, V

= 1.0V, R =50Ω, C = 35pF,

25

Full

25

-

70

80

-

ns

pC

pF

ON

NO

(See Figure 1)

L

Turn-OFF Time, t

V+ = 1.65V, V

= 1.0V, R =50Ω, C = 35pF,

65

OFF

NO

(See Figure 1)

L

Full

25

75

Charge Injection, Q

C

= 1.0nF, V = 1V, R = 0Ω, (See Figure 2)

53

L

G

NO

G

NO OFF Capacitance, C

f = 1MHz, V

= V

= 0V, (See Figure 6)

25

52

OFF

COM

COM ON Capacitance, C

= V

= 0V, (See Figure 6)

25

237

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

25

-

0.4

-

V

INL

Input Voltage High, V

1.0

-0.5

INH

Input Current, I

, I

V+ = 2.0V, V = 0V or V+

IN

Full

0.5

μA

INH INL

NOTES:

4. V = input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

7. R

matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron

ON

value, between NO1 and NO2.

FN6503.0

May 31, 2007

5

ISL54047

Test Circuits and Waveforms

V+

C

V+

t < 20ns

r

t < 20ns

f

LOGIC

INPUT

50%

0V

NO

0V

V

OUT

t

NO

IN

OFF

SWITCH

INPUT

COM

SWITCH

INPUT

V

OUT

90%

C

L

35pF

R

50Ω

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Logic input waveform is inverted for switches that have the opposite

logic sense.

Repeat test for all switches. C includes fixture and stray

L

capacitance.

R

L

------------------------------

V

= V

OUT

(NO)

R

+ R

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

V

R

OUT

G

COM

NO

SWITCH

OUTPUT

ΔV

OUT

V

OUT

V

GND

IN

G

C

L

V+

0V

ON

LOGIC

INPUT

LOGIC

INPUT

OFF

Q = ΔV

x C

L

OUT

Repeat test for all switches.

FIGURE 2B. TEST CIRCUIT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

V+

C

V+

C

SIGNAL

GENERATOR

R

= V /100mA

1

ON

NO

V

NX

IN

0V or V+

100mA

IN

V

1

COM

ANALYZER

GND

COM

R

L

GND

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

Repeat test for all switches.

FIGURE 4. R

FIGURE 3. OFF ISOLATION TEST CIRCUIT

TEST CIRCUIT

ON

FN6503.0

May 31, 2007

6

ISL54047

Test Circuits and Waveforms (Continued)

V+

C

V+

C

SIGNAL

GENERATOR

50Ω

NO

COM

NO

IN

1

0V or V+

IN

0V or V+

IMPEDANCE

ANALYZER

NO

COM

ANALYZER

N.C.

GND

R

L

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

Repeat test for all switches.

FIGURE 6. CAPACITANCE TEST CIRCUIT

FIGURE 5. CROSSTALK TEST CIRCUIT

Detailed Description

The ISL54047 is a bidirectional, differential single pole/single

throw (SPST) analog switch that offer precise switching

capability from a single 1.65V to 4.5V supply with low

V+

C

OPTIONAL

on-resistance (0.44Ω) and high speed operation (t

=

PROTECTION

ON

RESISTOR

100Ω

40ns, t

OFF

= 35ns). The devices are especially well suited

for portable battery powered equipment due to their low

operating supply voltage (1.65V), low power consumption

(4.5μW max) and the tiny μTQFN package. The ultra low on-

resistance and Ron flatness provide very low insertion loss

and distortion to applications that require signal reproduction.

NO1

N02

COM1

COM2

IN

GND

External V+ Series Resistor

For improved ESD and latch-up immunity Intersil

recommends adding a 100Ω resistor in series with the V+

power supply pin of the ISL54047 IC (see Figure 7).

FIGURE 7. V+ SERIES RESISTOR FOR ENHANCED ESD AND

LATCH-UP IMMUNITY

During an over-voltage transient event, such as occurs

during system level IEC 61000 ESD testing, substrate

currents can be generated in the IC that can trigger parasitic

SCR structures to turn ON, creating a low impedance path

from the V+ power supply to ground. This will result in a

significant amount of current flow in the IC which can

potentially create a latch-up state or permanently damage

the IC. The external V+ resistor limits the current during this

over-stress situation and has been found to prevent latch-up

or destructive damage for many over voltage transient

events.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 8). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Under normal operation the sub-microamp I

current of the

DD

IC produces an insignificant voltage drop across the 100Ω

series resistor resulting in no impact to switch operation or

performance.

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 8). The resistor limits

FN6503.0

May 31, 2007

7

ISL54047

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

2.7V the V level is about 0.53V. This is still above the 1.8V

CMOS guaranteed low output maximum level of 0.5V, but

noise margin is reduced.

IL

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low R

switch. Connecting schottky

ON

diodes to the signal pins as shown in Figure 8 will shunt the

fault current to the supply or to ground thereby protecting the

switch. These schottky diodes must be sized to handle the

expected fault current.

The ISL54047 has been designed to minimize the supply

current whenever the digital input voltage is not driven to the

supply rails (0V to V+). For example driving the device with

2.85V logic (0V to 2.85V) while operating with a 4.2V supply

the device draws only 12μA of current (see Figure 16 for

VIN = 2.85V).

OPTIONAL

SCHOTTKY

DIODE

Frequency Performance

V+

In 50Ω systems, the ISL54047 has a -3dB bandwidth of

27MHz (see Figure 21). The frequency response is very

consistent over a wide V+ range, and for varying analog

signal levels.

OPTIONAL

PROTECTION

RESISTOR

IN

V

X

V

NX

COM

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal feed

through from a switch’s input to its output. Off Isolation is the

resistance to this feed through, while Crosstalk indicates the

amount of feed through from one switch to another. Figure

22 details the high Off Isolation and Crosstalk rejection

provided by this part. At 100kHz, Off Isolation is about 102dB

in 50Ω systems, 118dB into 8Ω, and 124dB into 4Ω,

decreasing approximately 20dB per decade as frequency

increases. Higher load impedances decrease Off Isolation

and Crosstalk rejection due to the voltage divider action of

the switch OFF impedance and the load impedance.

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 8. OVERVOLTAGE PROTECTION

Power-Supply Considerations

The ISL54047 construction is typical of most single supply

CMOS analog switches, in that they have two supply pins:

V+ and GND. V+ and GND drive the internal CMOS

switches and set their analog voltage limits. Unlike switches

with a 4V maximum supply voltage, the ISL54047 5.5V

maximum supply voltage provides plenty of room for the

10% tolerance of 4.3V supplies, as well as room for

overshoot and noise spikes.

Leakage Considerations

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND. One of

these diodes conducts if any analog signal exceeds V+ or

GND.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes the analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

The minimum recommended supply voltage is 1.65V. It is

important to note that the input signal range, switching times,

and on-resistance degrade at lower supply voltages. Refer

to the Electrical Specification Tables on page 5 and Typical

Performance Curves on page 9 for details.

V+ and GND also power the internal logic and level shifters.

The level shifters convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies, because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family are 1.8V CMOS compatible (0.5V and

1.4V) over a supply range of 2.7V to 4.5V (see Figure 18). At

FN6503.0

May 31, 2007

8

ISL54047

Typical Performance Curves T = 25°C, Unless Otherwise Specified

A

0.46

0.44

0.42

0.40

0.38

0.36

0.34

0.56

0.54

0.52

0.50

0.48

0.46

0.44

0.42

0.40

I = 100mA

COM

I

= 100mA

COM

V+ = 2.7V

V+ = 3.9V

V+ = 3V

V+ = 4.3V

V+ = 3.3V

V+ = 4.5V

2

0

1

3

4

5

0

0.5

1

1.5

2

2.5

3

3.5

V

(V)

V

(V)

COM

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 10. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

0.55

1.3

V+ = 4.3V

I

= 100mA

COM

I

= 100mA

COM

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.50

0.45

0.40

0.35

0.30

0.25

V+ = 1.65V

85°C

25°C

V+ = 1.8V

V+ = 2V

-40°C

0

0.5

1

1.5

2

0

1

2

3

4

5

V

(V)

V

(V)

COM

FIGURE 11. ON RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE

0.70

0.60

V+ = 3.3V

COM

V+ = 2.7V

I = 100mA

COM

I

= 100mA

0.65

0.60

0.55

0.50

0.45

0.40

0.35

0.55

0.50

0.45

0.40

0.35

0.30

85°C

25°C

85°C

25°C

-40°C

1.5

0

0.5

1

1.5

(V)

2

2.5

3

0

0.5

1

2

2.5

3

3.5

V

(V)

V

COM

FIGURE 13. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 14. ON RESISTANCE vs SWITCH VOLTAGE

FN6503.0

May 31, 2007

9

ISL54047

Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)

A

1.1

V+ = 1.8V

200

I

= 100mA

COM

85°C

25°C

-40°C

V+ = 4.2V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

150

100

50

0

1

2

3

4

5

0

0.5

1

1.5

2

V

(V)

IN

V

(V)

COM

FIGURE 15. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 16. SUPPLY CURRENT vs VLOGIC VOLTAGE

1.1

800

600

V

INH

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

400

V+ = 4.3V

200

0

V+ = 1.8V

-200

V+ = 3V

-400

-600

V

INL

-800

-1000

1.5

2.0

2.5

3.0

V+ (V)

3.5

4.0

4.5

0

1

2

3

4

V

(V)

COM

FIGURE 18. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE

200

150

+85°C

100

+85°C

+25°C

-40°C

50

-40°C

0

1.0

0

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

V+ (V)

FIGURE 19. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 20. TURN-OFF TIME vs SUPPLY VOLTAGE

FN6503.0

May 31, 2007

10

ISL54047

Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)

A

1

0

V+ = 4.3V

0

R

= 50Ω

L

-1

-2

-3

-4

-5

-6

-7

-8

-9

-20

-40

20

GAIN

40

-60

60

-80

80

ISOLATION

-100

-120

-140

100

120

140

CROSSTALK

V+ = 4.3V

R

= 50Ω

= 0.2V

L

V

to 2V

IN

P-P

0.01

0.1

1

10

100

1k

10k

100k

1M

10M

100M 500M

FREQUENCY (MHz)

FREQUENCY (Hz)

FIGURE 21. FREQUENCY RESPONSE

FIGURE 22. CROSSTALK AND OFF ISOLATION

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

114

PROCESS:

Submicron CMOS

FN6503.0

May 31, 2007

11

ISL54047

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

L10.1.8x1.4A

D

A

B

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC

PACKAGE

6

MILLIMETERS

INDEX AREA

N

E

SYMBOL

MIN

0.45

NOMINAL

MAX

0.55

NOTES

2X

0.10 C

A

A1

A3

b

0.50

-

1

2

2X

0.10 C

-

0.05

-

TOP VIEW

0.127 or 0.15 REF

-

0.15

1.75

1.35

0.20

1.80

1.40

0.40 BSC

0.40

0.50

10

0.25

1.85

1.45

5, 9

0.10 C

D

-

C

A

0.05 C

SEATING PLANE

E

-

e

-

A1

L

0.35

0.45

0.55

9

SIDE VIEW

L1

N

-

2

(DATUM A)

PIN #1 ID

Nd

Ne

θ

2

3

NX L

5

NX b

10X

1

2

3

L1

0.10 M C A B

0

-

12

4

0.05 M C

Rev. 1 1/06

(DATUM B)

5

NOTES:

7

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

e

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

BOTTOM VIEW

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

C

L

(A1)

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX (b)

5

L

9

e

7. Maximum package warpage is 0.05mm.

SECTION "C-C"

8. Maximum allowable burrs is 0.076mm in all directions.

TERMINAL TIP

C C

9. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

10. JEDEC Reference MO-255.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6503.0

May 31, 2007

12


型号：	ISL54047IRUZ-T
厂家：	Intersil
描述：	Ultra Low ON-Resistance, High Off- Isolation, Single Supply, Diff SPST Analog Switch 超低导通电阻，高场外隔离，单电源，差SPST模拟开关开关
文件：	总12页 (文件大小：451K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54047IRUZ-T [INTERSIL]

相关型号：

ISL54048

ISL54048IRUZ-T

ISL54048_0706

ISL54049

ISL54049IRUZ-T

ISL54050

ISL54050IRUZ-T

ISL54050IRUZ-T7

ISL54050_0706

ISL54051

ISL54051IHZ-T

ISL54051IHZ-T