ISL54053IRUZ-T_技术文档

ISL54053

®

Data Sheet

March 16, 2007

FN6460.0

Ultra Low ON-Resistance, Low Voltage,

Single Supply, SPDT Analog Switch

Features

• Drop In replacement for the NLAS5123

• ON-resistance (r

The Intersil ISL54053 device is a low ON-resistance, low

voltage, bidirectional, single pole/double throw (SPDT)

analog switch designed to operate from a single +1.8V to

+5.5V supply. Targeted applications include battery powered

)

ON

- V

= +5.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8Ω

= +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1Ω

= +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3Ω

CC

equipment which benefit from low r

(0.8Ω) and fast

= 10ns). The digital logic

ON

switching speeds (t

ON

= 24ns, t

OFF

• r

matching between channels . . . . . . . . . . . . . . . . 0.004Ω

flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . 0.04Ω

ON

input is 1.8V logic compatible when using a single +3.0V

supply.

• r

ON

• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V

• Fast switching action (+4.5V Supply)

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins may be

limited and digital geometries are not well suited to analog

switch performance. This part may be used to “mux-in”

additional functionality while reducing ASIC design risk. The

ISL54053 is offered in the 6 Ld 1.2mmx1.0mmx0.5mm

µTDFN package, alleviating board space limitations.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns

OFF

• Guaranteed break-before-make

• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV

• 1.8V CMOS logic compatible (+3V supply)

• Available in 6 lead µTDFN package

The ISL54053 is a committed SPDT that consists of one

normally open (NO) and one normally closed(NC) switch. This

configuration can also be used as a 2-to-1 multiplexer.

• Pb-free plus anneal available (RoHS compliant)

TABLE 1. FEATURES AT A GLANCE

ISL54053

Applications

• Battery powered, handheld, and portable equipment

- Cellular/mobile phones

Number of Switches

SW

1

SPDT or 2-1 MUX

2.3Ω

- Pagers

1.8V r

ON

- Laptops, notebooks, palmtops

1.8V t /t

ON OFF

68ns/45ns

1.1Ω

• Portable test and measurement

• Medical equipment

3V r

ON

3V t /t

29ns/12ns

0.8Ω

ON OFF

5V r

• Audio and video switching

ON

5V t /t

Ordering Information

24ns/10ns

6 Ld μTDFN

ON OFF

PART

NUMBER

(Note)

TEMP.

RANGE

(°C)

Packages

PART

MARKING

PACKAGE

(Pb-Free)

PKG.

DWG. #

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

ISL54053IRUZ-T

C

-40 to +85 6 Ld µTDFN L6.1.2x1.0A

TapeandReel

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL54053

Pin Descriptions

Pinout (Note 1)

ISL54053

(6 LD µTDFN)

TOP VIEW

FUNCTION

System Power Supply Input (+1.8V to +5.5V)

Ground Connection

V+

GND

IN

1

2

3

6

5

4

IN

NO

Digital Control Input

GND

NC

V+

COM

NO

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

COM

NC

NOTE:

1. Switches Shown for Logic “0” Input.

Truth Table

LOGIC

PIN NC

On

PIN NO

Off

0

1

Off

On

NOTE: Logic “0” ≤ 0.5V. Logic “1” ≥ 1.4V with a 3.0V supply.

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March 16, 2007

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ISL54053

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.0V

Input Voltages

NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Output Voltages

COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)

Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating

Thermal Resistance (Typical, Note 3)

θ

(°C/W)

175

JA

6 Ld μTDFN Package . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>6kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . .>200V

Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . .>1000V

Operating Conditions

V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+

V

(Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+

IN

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

Unless Otherwise Specified

= 2.4V, V

= 0.8V (Notes 4, 6),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

0.86

1

V+

V

Ω

ON-Resistance, r

V+ = 4.5V, I

= 100mA, V

or V

= 0V to V+,

= 2.5V

-

ON

COM

(See Figure 5)

NO

NC

Full

25

-

Ω

r

Matching Between Channels,

V+ = 4.5V, I

COM

= 100mA, V

or V

-

0.004

0.04

0.06

5

-

Ω

ON

Δr

NO

NC

ON

Full

25

-

Ω

r

Flatness, r

V+ = 4.5V, I

(Note 7)

= 100mA, V

or V = 0V to V+,

NC

-

Ω

ON

FLAT(ON)

COM

NO

Full

25

-

Ω

NO or NC OFF Leakage Current,

or I

V+ = 5.5V, V

= 0.3V, 5V, V

NO

or V

NC

= 5V, 0.3V

-10

-150

-20

-300

10

150

20

300

nA

COM

I

NO(OFF)

NC(OFF)

Full

25

-

COM ON Leakage Current,

V+ = 5.5V, V

or floating

= 0.3V, 5V, or V

NO

or V

= 0.3V, 5V,

9

COM

NC

I

COM(ON)

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

Full

-

V+ = 4.5V, V

(See Figure 1, Note 8)

or V

= 3.0V, R = 50Ω, C = 35pF

25

Full

25

-

24

30

10

15

10

-

ns

ON

NO

NC

L

Turn-OFF Time, t

V+ = 4.5V, V

or V

= 3.0V, R = 50Ω, C = 35pF

NC L L

OFF

NO

(See Figure 1, Note 8)

Full

Break-Before-Make Time Delay, t

V+ = 5.5V, V

or V

= 3.0V, R = 50Ω, C = 35pF

NC L L

D

NO

(See Figure 3, Note 8)

Charge Injection, Q

OFF Isolation

V

= 0V, R = 0Ω, C = 1.0nF (See Figure 2)

25

-

26

80

-

pC

dB

G

L

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

L

COM

RMS

(See Figure 4)

Crosstalk (Channel-to-Channel)

Total Harmonic Distortion

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-

-83

-

dB

%

L

COM

RMS

(See Figure 6)

f = 20Hz to 20kHz, V

= 0.5V , R = 600Ω

P-P

0.03

COM

L

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ISL54053

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

Unless Otherwise Specified (Continued)

= 2.4V, V

= 0.8V (Notes 4, 6),

(NOTE 5)

INH

INL

TEMP (NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

MHz

pF

-3dB Bandwidth

R

= 50Ω

25

-

190

16

-

L

NO or NC OFF Capacitance, C

V+ = 4.5V, f = 1MHz, V

(See Figure 7)

or V

= V

= 0V

25

OFF

NO

NC

COM

COM ON Capacitance, C

V+ = 4.5V, f = 1MHz, V

(See Figure 7)

25

-

48

-

pF

COM(ON)

COM

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.8

-

0.075

-

5.5

0.1

2.5

V

Positive Supply Current, I+

V+ = 5.5V, V = 0V or V+

IN

-

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.8

-

V

INL

Input Voltage High, V

2.4

-0.1

INH

Input Current, I

, I

V+ = 5.5V, V = 0V or V+

IN

0.1

μA

INH INL

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

Unless Otherwise Specified

= 1.4V, V

= 0.5V (Notes 4, 6),

INH

INL

TEMP (NOTE 5)

(NOTE 5)

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

MAX

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

V+

1.2

V

Ω

ON-Resistance, r

V+ = 3.0V, I

= 100mA, V

or V

= 0V to V+,

= 1.5V

1.1

ON

COM

(See Figure 5)

NO

NC

Full

25

-

1.5

r

Matching Between Channels,

V+ = 3.0V, I

COM

= 100mA, V

or V

0.004

0.14

0.35

0.4

ON

Δr

NO

NC

ON

Full

25

-

0.04

-

r

Flatness, r

V+ = 3.0V, I

(Note 7)

= 100mA, V

or V = 0V to V+,

NC

ON

FLAT(ON)

COM

NO

Full

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 2.7V, V

(See Figure 1, Note 8)

or V

= 1.5V, R = 50Ω, C = 35pF

25

Full

25

-

29

35

12

17

10

-

ns

ON

NO

NC

L

Turn-OFF Time, t

V+ = 2.7V, V

or V

= 1.5V, R = 50Ω, C = 35pF

NC L L

OFF

NO

(See Figure 1, Note 8)

Full

Break-Before-Make Time Delay, t

V+ = 3.6V, V

or V

= 1.5V, R = 50Ω, C = 35pF

NC L L

D

NO

(See Figure 3, Note 8)

Charge Injection, Q

OFF Isolation

V

= 0V, R = 0Ω, C = 1.0nF (See Figure 2)

25

-

32

80

-

pC

dB

G

L

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

L

COM

RMS

(See Figure 4)

Crosstalk (Channel-to-Channel)

R

= 50Ω, C = 5pF, f = 100kHz, V

= 1V

25

-

-83

-

dB

L

COM

RMS

(See Figure 6)

Total Harmonic Distortion

-3dB Bandwidth

f = 20Hz to 20kHz, V

= 0.5V , R = 600Ω

P-P

25

-

0.03

190

16

-

%

MHz

pF

COM

L

R

= 50Ω

L

NO or NC OFF Capacitance, C

f = 1MHz, V

or V

= V

= 0V (See Figure 7)

OFF

NO

NC

COM

COM ON Capacitance, C

= V

48

pF

COM(ON)

NC

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.5

-

V

INL

Input Voltage High, V

1.4

-0.1

INH

Input Current, I

, I

V+ = 3.6V, V = 0V or V+

IN

0.1

μA

INH INL

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ISL54053

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.8V, GND = 0V, V

Unless Otherwise Specified

= 1V, V

= 0.4V (Notes 4, 6),

INL

INH

TEMP (NOTE 5)

(NOTE 5)

MAX

PARAMETER

TEST CONDITIONS

(°C)

MIN

TYP

UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

25

0

-

V+

V

Ω

ON-Resistance, r

V+ = 1.8V, I

= 10mA, V

or V = 0V to V+,

NC

2.33

2.54

-

ON

COM

(See Figure 5)

NO

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t

V+ = 1.8V, V

(See Figure 1, Note 8)

or V

= 1.5V, R = 50Ω, C = 35pF

25

Full

25

-

68

93

45

71

15

-

ns

ON

NO

NC

L

Turn-OFF Time, t

V+ = 1.8V, V

or V

= 1.5V, R = 50Ω, C = 35pF

NC L L

OFF

NO

(See Figure 1, Note 8)

Full

Break-Before-Make Time Delay, t

Charge Injection, Q

V+ = 1.8V, V

or V

= 1.5V, R = 50Ω, C = 35pF

NC L L

D

NO

(See Figure 3, Note 8)

V

= 0, R = 0Ω, C = 1.0nF (See Figure 2)

25

-

18

-

pC

G

L

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.4

-

V

INL

Input Voltage High, V

NOTES:

1

INH

4. V = input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

8. Guaranteed by design.

Test Circuits and Waveforms

V+

V

t < 20ns

r

t < 20ns

f

INH

C

LOGIC

INPUT

50%

V

INL

t

V

OFF

OUT

NO or NC

SWITCH

INPUT

COM

SWITCH

INPUT

V

Nx

0V

V

OUT

IN

90%

C

L

35pF

R

50Ω

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

t

ON

Repeat test for all switches. C includes fixture and stray

L

Logic input waveform is inverted for switches that have the opposite

logic sense.

capacitance.

R

L

----------------------------

V

= V

OUT

(NO or NC)

R

+ r

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

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ISL54053

Test Circuits and Waveforms (Continued)

V+

C

SWITCH

OUTPUT

ΔV

OUT

V

R

OUT

G

COM

NO or NC

GND

V

OUT

V

INH

ON

LOGIC

INPUT

OFF

V

G

IN

V

C

L

INL

LOGIC

INPUT

Q = ΔV

x C

L

OUT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2B. TEST CIRCUIT

FIGURE 2. CHARGE INJECTION

V+

C

NO

V

INH

OUT

NX

COM

LOGIC

INPUT

NC

C

L

35pF

R

50Ω

L

V

INL

IN

GND

LOGIC

INPUT

90%

SWITCH

OUTPUT

V

OUT

0V

t

D

C

includes fixture and stray capacitance.

L

FIGURE 3A. MEASUREMENT POINTS

FIGURE 3B. TEST CIRCUIT

FIGURE 3. BREAK-BEFORE-MAKE TIME

V+

C

r

= V /100mA

1

ON

SIGNAL

GENERATOR

NO or NC

V

NX

100mA

IN

V

INL

or V

0V or V+

INH

IN

V

1

COM

ANALYZER

GND

R

L

FIGURE 4. OFF ISOLATION TEST CIRCUIT

FIGURE 5. r

TEST CIRCUIT

ON

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ISL54053

Test Circuits and Waveforms (Continued)

V+

C

V+

C

V

50Ω

NO or NC

COM

NO or NC

or V

INH

IN

1

IN

INL

SIGNAL

GENERATOR

IMPEDANCE

ANALYZER

0V or V+

COM

NC or NO

GND

ANALYZER

GND

R

L

FIGURE 6. CROSSTALK TEST CIRCUIT

FIGURE 7. CAPACITANCE TEST CIRCUIT

purpose of using a low r

switch. Connecting schottky

Detailed Description

ON

diodes to the signal pins (as shown in Figure 8) will shunt the

fault current to the supply or to ground thereby protecting the

switch. These schottky diodes must be sized to handle the

expected fault current.

The ISL54053 is a bidirectional, single pole/double throw

(SPDT) analog switch which offers precise switching

capability from a single 1.8V to 5.5V supply with low

on-resistance (0.8Ω) and high speed operation (t

= 24ns,

= 10ns). The device is especially well suited for portable

ON

t

OFF

battery powered equipment due to its low operating supply

voltage (1.8V), low power consumption (5.5μW), low leakage

currents (300nA max) and the small μTDFN package. The low

OPTIONAL

SCHOTTKY

DIODE

V+

on-resistance and r

and distortion to application that require signal reproduction.

flatness provide very low insertion loss

OPTIONAL

ON

PROTECTION

RESISTOR

IN

V

X

Supply Sequencing and Overvoltage Protection

V

NX

COM

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to GND (see

Figure 8). To prevent forward biasing these diodes, V+ must

be applied before any input signals, and the input signal

voltages must remain between V+ and GND.

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 8. OVERVOLTAGE PROTECTION

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Power-Supply Considerations

The ISL54053 construction is typical of most single supply

CMOS analog switches, in that they have two supply pins:

V+ and GND. V+ and GND drive the internal CMOS

switches and set their analog voltage limits. Unlike switches

with a 4.5V maximum supply voltage, the ISL54053 5.5V

maximum supply voltage provides plenty of room for the

10% tolerance of 4.3V supplies, as well as room for

overshoot and noise spikes.

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 8). The resistor limits

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

The minimum recommended supply voltage is 1.8V but the

part will operate with a supply below 1.8V. It is important to

note that the input signal range, switching times, and

on-resistance degrade at lower supply voltages. Refer to the

electrical specification tables and Typical Performance

Curves on page 8 for details.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

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March 16, 2007

7

ISL54053

V+ and GND also power the internal logic and level shifters.

the resistance to this feedthrough, while crosstalk indicates

the amount of feedthrough from one switch to another.

Figure 17 details the high off isolation and crosstalk rejection

provided by this family. At 100kHz, off isolation is about 80dB

in 50Ω systems, decreasing approximately 20dB per decade

as frequency increases. Higher load impedances decrease

off isolation and crosstalk rejection due to the voltage divider

action of the switch OFF impedance and the load

impedance.

The level shifters convert the input logic levels to switched

V+ and GND signals to drive the analog switch gate

terminals.

This family of switches cannot be operated with bipolar

supplies because the input switching point becomes

negative in this configuration.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and 1.4V)

over a supply range of 2V to 5V (see Figure 15). At 5V the

Leakage Considerations

ESD protection diodes are internally connected between each

analog-signal pin and both V+ and GND. One of these diodes

conducts if any analog signal exceeds V+ or GND.

V

level is about 1.2V. This is still below the 1.8V CMOS

IH

guaranteed high output minimum level of 1.4V, but noise

margin is reduced.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or GND. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

V+ or GND and the analog signal. This means their leakages

will vary as the signal varies. The difference in the two diode

leakages to the V+ and GND pins constitutes the analog-

signal-path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and V+ or GND.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, the ISL54053 has a -3dB bandwidth of

190MHz (see Figure 16). The frequency response is very

consistent over a wide V+ range, and for varying analog

signal levels.

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off isolation is

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

2.5

1.0

I

= 100mA

COM

0.9

0.8

0.7

0.6

0.5

0.4

V+ = 1.8V

2.0

1.5

+85°C

+25°C

V+ = 2.7V

V+ = 3V

1.0

0.5

0

V+ = 4.5V

V+ = 5V

-40°C

0.3

0.2

V+ = 5V

I

= 100mA

COM

0

1

2

3

4

5

0

1

2

3

4

5

V

(V)

V

(V)

COM

FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE

FN6460.0

March 16, 2007

8

ISL54053

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

1.5

3.0

2.5

2.0

1.5

1.0

0.5

V+ = 1.8V

= 10mA

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

I

COM

+85°C

+25°C

+85°C

+25°C

-40°C

1.5

V+ = 3.0V

= 100mA

0.6

0.5

I

COM

0

0.5

1.0

2.0

2.5

3.0

0

0.5

1.0

1.5

1.8

V

(V)

V

(V)

COM

FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE

100

90

80

-40°C

80

70

60

50

40

30

20

10

0

60

-40°C

40

+25°C

+85°C

+25°C

20

0

+85°C

-40°C

2.8

1.8

2.8

3.8

4.8

3.8

4.8

1.8

V+ (V)

FIGURE 13. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 14. TURN-OFF TIME vs SUPPLY VOLTAGE

1.6

GAIN

0

1.4

-1

-2

-3

1.2

1.0

0.8

V

INH

V

INL

0.6

0.4

0.2

V+ = 5.0V

R

= 50Ω

L

IN

V

= 0.2V

to 2V

P-P

1M

FREQUENCY (Hz)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0.01k

0.1k

10M

100M

1G

V+ (V)

FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE

FIGURE 16. FREQUENCY RESPONSE

FN6460.0

March 16, 2007

9

ISL54053

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0

V+ = 1.8V to 5.5V

40

V+ = 3.0V

-20

30

20

10

-40

-60

-40

ISOLATION

0

CROSSTALK

-60

-10

V+ = 1.8V

V+ = 5V

-20

-30

-80

V+ = 3.0V

-40

-50

-60

-100

-120

-100

-120

0

1

2

3

4

5

1k

10k

100k

1M

10M

100M 500M

V

(V)

FREQUENCY (Hz)

COM

FIGURE 17. CROSSTALK AND OFF ISOLATION

FIGURE 18. CHARGE INJECTION vs SWITCH VOLTAGE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

57

PROCESS:

Submicron CMOS

FN6460.0

March 16, 2007

10

ISL54053

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

L6.1.2x1.0A

A

E

B

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

PIN 1

REFERENCE

D

SYMBOL

MIN

0.45

-

NOMINAL

MAX

0.55

0.05

NOTES

2X

0.10 C

A

A1

A3

b

0.50

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

0.95

1.15

0.20

0.25

1.05

1.25

5

DETAIL A

0.10 C

0.08 C

D

1.00

-

A

E

1.20

-

7X

e

0.40 BSC

-

C

A1 A3

L

0.30

0.40

0.35

0.40

0.50

-

SEATING

PLANE

SIDE VIEW

L1

N

0.45

-

4X

e

DETAIL B

6

3

-

2

5X

L

Ne

θ

3

1

3

0

12

4

L1

Rev. 2 8/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

6

4

b 6X

0.10 C A B

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

0.05 C

NOTE 3

BOTTOM VIEW

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

0.1x45°

CHAMFER

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

A3

A1

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

DETAIL A

DETAIL B PIN 1 LEAD

1.00

1.40

0.20

0.30

0.35

0.45

0.20

0.40

10

LAND PATTERN

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6460.0

March 16, 2007

11


型号：	ISL54053IRUZ-T
厂家：	Intersil
描述：	Ultra Low ON-Resistance, Low Voltage, Single Supply, SPDT Analog Switch 超低导通电阻，低电压，单电源， SPDT模拟开关开关光电二极管
文件：	总11页 (文件大小：377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL54053IRUZ-T [INTERSIL]

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