ISL54054 [INTERSIL]
Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST/1:2 Distribution Analog Switch; 超低导通电阻,低电压,单电源,单路SPST / 1 : 2的分布模拟开关型号: | ISL54054 |
厂家: | Intersil |
描述: | Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST/1:2 Distribution Analog Switch |
文件: | 总12页 (文件大小:431K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL54054, ISL54055
®
Data Sheet
March 21, 2007
FN6461.0
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Single SPST/1:2
Distribution Analog Switch
Features
• ON-resistance (r ) (Signal Pins Connected)
ON
- V
- V
- V
= +5.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34Ω
= +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51Ω
= +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1Ω
CC
CC
CC
The Intersil ISL54054 and ISL54055 devices consist of low
ON-resistance, low voltage, bi-directional SPST analog
switches designed to operate from a single +1.8V to +5.5V
supply. These devices have an unique architecture. They
have two signal pins (pin 1 and pin 3) that are
simultaneously connected or disconnected to a common pin
(pin 4) under the control of a single logic control pin (pin 6).
The ISL54054 switches are OFF when the logic is low and
ON when the logic is high. The ISL54055 switches are ON
when the logic is low and OFF when the logic is high. This
architecture allows these devices to be used as a single
SPST switch or as a distribution switch to distribute a single
source to two different loads.
• r
ON
flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . 0.13Ω
• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V Supply)
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
OFF
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V logic compatible (+3V supply)
• Available in 6 lead μTDFN Package
• Pb-free plus anneal available (RoHS compliant)
SPST operation is achieved by using one of the signal pins
while floating the other signal pin or by externally connecting
the two signal pins together. When both signal pins are tied
Applications
together, the r
0.5Ω (when operated with a 5V supply).
of the SPST is reduced by half, from 1Ω to
• Battery powered, handheld and portable equipment
- Cellular/mobile phones
ON
- Pagers
Targeted applications include battery powered equipment
- Laptops, notebooks, palmtops
that benefit from low r
and fast switching speeds (t
digital logic input is 1.8V logic compatible when using a
single 2.7V to +3.6V supply and TTL compatible when the
supply is > +3.6V.
resistance, excellent r
flatness,
= 12ns). The
ON
ON
= 12ns, t
OFF
ON
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
The ISL54054 and the ISL54055 are offered in a 6 Ld
1.2mmx1.0mmx0.5mm μTDFN package, alleviating board
space limitations.
The ISL54054 has two normally open (NO) switches and the
ISL54055 has two normally closed (NC) switches.
Ordering Information
PART
NUMBER
(Note)
TEMP.
RANGE
(°C)
TABLE 1. FEATURES AT A GLANCE
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54054
1
ISL54055
1
Number of Switches
SW
ISL54054IRUZ-T
D
-40 to +85 6 Ld μTDFN
L6.1.2x1.0A
Tape and Reel
NO
NC
ISL54055IRUZ-T
E
-40 to +85 6 Ld μTDFN
L6.1.2x1.0A
1.8V r
ON
1.1Ω
1.1Ω
Tape and Reel
1.8V t /t
ON OFF
115ns/90ns
0.51Ω
115ns/90ns
0.51Ω
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
3V r
ON
3V t /t
22ns/17ns
0.34Ω
22ns/17ns
0.34Ω
ON OFF
5V r
ON
5V t /t
12ns/12ns
12ns/12ns
ON OFF
Packages
6 Ld μTDFN
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54054, ISL54055
Pinouts (Note 1)
ISL54054
(6 LD μTDFN)
TOP VIEW
ISL54055
(6 LD μTDFN)
TOP VIEW
1
6
5
4
IN
1
6
5
4
NO
IN
NC
GND
NC
GND
NO
2
3
2
3
V+
V+
COM
COM
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
Pin Descriptions
ISL54054
ISL54055
PIN
FUNCTION
LOGIC
Both NO Switches Both NC Switches
V+
GND
IN
System Power Supply Input (+1.8V to +5.5V)
Ground Connection
0
1
Off
On
On
Off
Digital Control Input
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
NC
FN6461.0
March 21, 2007
2
ISL54054, ISL54055
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.0V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . .±600mA
ESD Rating
Thermal Resistance (Typical, Note 3)
θ
(°C/W)
175
JA
6 Ld μTDFN Package . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>6kV
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . .>200V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . .>1000V
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
V
(Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+
IN
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Notes 4, 6),
INH
INL
TEMP (NOTE 5)
(NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
V+
V
Ω
ON-Resistance, r
V+ = 4.5V, I
= 100mA, V
= 100mA, V
= 100mA, V
= 100mA, V
or V
or V
or V
or V
= 0V to V+,
= 0V to V+,
= 0V to V+,
= 0V to V+,
-
0.36
0.49
0.12
0.13
0.85
1.1
0.25
0.25
5
-
ON
(Nx Inputs Connected)
COM
(See Figure 4)
NO
NO
NO
NO
NC
NC
NC
NC
Full
25
-
-
Ω
r
Flatness, r
FLAT(ON)
V+ = 4.5V, I
(Note 7)
-
-
-
Ω
ON
(Nx Inputs Connected)
COM
Full
25
-
Ω
ON-Resistance, r
(Single Nx Input)
V+ = 4.5V, I
(See Figure 4)
-
-
-
Ω
ON
COM
Full
25
-
Ω
r
Flatness, r
V+ = 4.5V, I
(Note 7)
-
-
Ω
ON
FLAT(ON)
COM
(Single Nx Input)
Full
25
-
-
Ω
NO or NC OFF Leakage Current,
or I
V+ = 5.5V, V
= 0.3V, 5V, V
NO
or V
NC
= 5V, 0.3V
-10
-150
-20
-300
10
150
20
300
nA
nA
nA
nA
COM
I
NO(OFF)
NC(OFF)
Full
25
-
COM ON Leakage Current,
V+ = 5.5V, V
or floating
= 0.3V, 5V, or V
NO
or V
= 0.3V, 5V,
9
COM
NC
I
COM(ON)
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Full
-
V+ = 4.5V, V
or V
or V
= 3.0V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
-
12
15
12
15
71
74
-
-
-
-
-
-
ns
ns
ns
ns
pC
dB
ON
NO
(See Figure 1)
NC
NC
L
L
Turn-OFF Time, t
V+ = 4.5V, V
= 3.0V, R = 50Ω, C = 35pF
L L
OFF
NO
(See Figure 1)
Full
25
Charge Injection, Q
V = 0V, R = 0Ω, C = 1.0nF (See Figure 2)
G G L
OFF Isolation
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
L
L
COM
RMS
(Nx Inputs Connected)
(See Figure 3)
OFF Isolation
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
-
83
-
dB
L
L
COM
RMS
(Single Nx Input)
(See Figure 3)
FN6461.0
March 21, 2007
3
ISL54054, ISL54055
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Notes 4, 6),
(NOTE 5)
INH
INL
TEMP (NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
-3dB Bandwidth
(Nx Inputs Connected)
R
R
= 50Ω
= 50Ω
25
-
72
138
30
-
MHz
L
-3dB Bandwidth
(Single Nx Input)
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
MHz
pF
L
NO or NC OFF Capacitance, C
(Nx Inputs Connected)
f = 1MHz, V
or V
or V
or V
or V
= V
= V
= V
= V
= 0V
= 0V
= 0V
= 0V
OFF
NO
(See Figure 5)
NC
NC
NC
NC
COM
COM
COM
COM
COM ON Capacitance, C
(Nx Inputs Connected)
f = 1MHz, V
62
pF
COM(ON)
NO
(See Figure 5)
NO or NC OFF Capacitance, C
(Single Nx Input)
f = 1MHz, V
16
pF
OFF
NO
(See Figure 5)
COM ON Capacitance, C
(Single Nx Input)
f = 1MHz, V
89
pF
COM(ON)
NO
(See Figure 5)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.8
-
-
-
5.5
0.5
1.0
V
Positive Supply Current, I+
V+ = 5.5V, V = 0V or V+
IN
-
-
μA
μA
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.8
-
V
V
INL
Input Voltage High, V
2.4
-1
INH
Input Current, I
, I
V+ = 5.5V, V = 0V or V+
IN
1
μA
INH INL
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V
Unless Otherwise Specified
= 1.4V, V
= 0.5V (Notes 4, 6),
INH
INL
TEMP (NOTE 5)
(NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
-
-
-
-
-
-
-
V+
0.65
1.0
0.4
0.5
1.7
2.0
0.6
0.7
V
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
ON-Resistance, r
V+ = 2.7V, I
= 100mA, V
= 100mA, V
= 100mA, V
= 100mA, V
or V
or V
or V
or V
= 0V to V+,
= 0V to V+,
= 0V to V+,
= 0V to V+,
0.57
0.73
0.2
0.2
1.3
1.6
0.4
0.4
ON
(Nx Inputs Connected)
COM
(See Figure 4)
NO
NO
NO
NO
NC
NC
NC
NC
Full
25
r
Flatness, r
FLAT(ON)
V+ = 2.7V, I
(Note 7)
ON
(Nx Inputs Connected)
COM
COM
Full
25
ON-Resistance, r
(Single Nx Input)
V+ = 2.7V, I
(See Figure 4)
ON
Full
25
r
Flatness, r
V+ = 2.7V, I
(Note 7)
ON
FLAT(ON)
COM
(Single Nx Input)
Full
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
or V
= 1.5V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
-
22
25
17
20
42
74
-
-
-
-
-
-
ns
ns
ns
ns
pC
dB
ON
NO
(See Figure 1)
NC
NC
L
L
Turn-OFF Time, t
V+ = 2.7V, V
= 1.5V, R = 50Ω, C = 35pF
L L
OFF
NO
(See Figure 1)
Full
25
Charge Injection, Q
V = 0V, R = 0Ω, C = 1.0nF (See Figure 2)
G G L
OFF Isolation
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
L
L
COM
RMS
(Nx Inputs Connected)
(See Figure 3)
OFF Isolation
(Single Nx Input)
R
= 50Ω, C = 5pF, f = 100kHz, V
= 1V
25
25
-
-
83
30
-
-
dB
pF
L
L
COM
RMS
(See Figure 3)
NO or NC OFF Capacitance, C
(Nx Inputs Connected)
f = 1MHz, V
or V
NC
= V
= 0V
COM
OFF
NO
(See Figure 5)
FN6461.0
March 21, 2007
4
ISL54054, ISL54055
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 1.4V, V
= 0.5V (Notes 4, 6),
(NOTE 5)
INH
INL
TEMP (NOTE 5)
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
MAX
UNITS
COM ON Capacitance, C
(Nx Inputs Connected)
f = 1MHz, V
or V
or V
or V
= V
= V
= V
= 0V
= 0V
= 0V
25
-
62
16
89
-
pF
COM(ON)
NO
(See Figure 5)
NC
NC
NC
COM
COM
COM
NO or NC OFF Capacitance, C
(Single Nx Input)
f = 1MHz, V
25
25
-
-
-
-
pF
pF
OFF
NO
(See Figure 5)
COM ON Capacitance, C
(Single Nx Input)
f = 1MHz, V
COM(ON)
NO
(See Figure 5)
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-1
INH
Input Current, I
, I
V+ = 3.6V, V = 0V or V+
IN
1
μA
INH INL
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, V
Unless Otherwise Specified
= 1.8V, V
= 0V (Notes 4, 6),
INL
INH
TEMP (NOTE 5)
(NOTE 5)
MAX
PARAMETER
TEST CONDITIONS
(°C)
MIN
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
V+
V
Ω
Ω
Ω
Ω
ON-Resistance, r
V+ = 1.8V, I
Pins 1 and 3 connected, (See Figure 4)
= 100mA, V
or V
= 0V to V+,
or V = 0V to V+
NC
1.1
1.3
2.3
2.53
-
-
-
-
ON
(Nx Inputs Connected)
COM
NO
NC
Full
25
-
ON-Resistance, r
(Single Nx Input)
V+ = 1.8V, I
= 100mA, V
-
ON
COM
(See Figure 4)
NO
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.8V, V
or V
or V
= 1.5V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
115
246
90
-
-
-
-
-
ns
ns
ns
ns
pC
ON
NO
(See Figure 1)
NC
NC
L
L
Turn-OFF Time, t
V+ = 1.8V, V
= 1.5V, R = 50Ω, C = 35pF
L L
OFF
NO
(See Figure 1)
Full
25
192
22
Charge Injection, Q
NOTES:
V = 0V, R = 0Ω,C = 1.0nF (See Figure 2)
G G L
4. V = input voltage to perform proper function.
IN
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
FN6461.0
March 21, 2007
5
ISL54054, ISL54055
Test Circuits and Waveforms
V+
V
t < 20ns
r
t < 20ns
f
INH
C
LOGIC
INPUT
50%
V
INL
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
COM
SWITCH
INPUT
V
NO
0V
V
OUT
90%
90%
C
L
35pF
R
50Ω
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
R
L
----------------------------
V
= V
OUT
(NO or NC)
R
+ r
(ON)
FIGURE 1A. MEASUREMENT POINTS
L
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
ΔV
V
OUT
R
G
OUT
COM
NO or NC
GND
V
OUT
V
INH
ON
ON
LOGIC
INPUT
V
G
IN
OFF
C
L
V
INL
LOGIC
INPUT
Q = ΔV
x C
L
OUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
C
C
r
= V /100mA
1
ON
SIGNAL
GENERATOR
NO or NC
NO or NC
V
NX
100mA
IN
0V or V+
V
or V
INH
INL
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FIGURE 4. r
TEST CIRCUIT
ON
FN6461.0
March 21, 2007
6
ISL54054, ISL54055
Test Circuits and Waveforms (Continued)
V+
C
V
NO or NC
or V
INH
IN
INL
IMPEDANCE
ANALYZER
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Detailed Description
The Intersil ISL54054 and ISL54055 devices consist of low
ON-resistance, low voltage, bi-directional analog switches
designed to operate from a single +1.8V to +5.5V supply.
With a single supply of 5V the typical on-resistance is only
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 6). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
0.34Ω, with a typical turn-on and turn-off time of: t
= 12ns,
= 12ns. The devices are especially well suited for
ON
t
OFF
portable battery powered equipment due to its low operating
supply voltage (1.8V), low power consumption (5.5μW), low
leakage currents (300nA max) and the tiny μTDFN package.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
These devices have an unique architecture. They have two
signal pins (pin 1 and pin 3) that are simultaneously
connected or disconnected to a single common pin (pin 4)
under the control of a single logic control pin (pin 6). The
ISL54054 switches are OFF when the logic is low and ON
when the logic is high. The ISL54055 are ON when the logic
is low and OFF when the logic is high. This architecture
allows these devices to be used as a single SPST switch or
as a distribution switch to distribute a single source to two
different loads.
purpose of using a low r
switch. Connecting schottky
ON
diodes to the signal pins (as shown in Figure 6) will shunt the
fault current to the supply or to ground, thereby protecting
the switch. These schottky diodes must be sized to handle
the expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
SPST operation is achieved by using one of the Nx signal
pins while floating the other Nx signal pin or by externally
connecting the two Nx signal pins together. When both
X
V
NX
COM
signal pins are tied together, the r
of the SPST is reduced
ON
by half, from 1Ω to 0.5Ω (when operated with a 5V supply).
GND
OPTIONAL
SCHOTTKY
DIODE
The ISL54054 is a normally open (NO) SPST analog switch.
The ISL54055 is a normally closed (NC) SPST analog
switch.
FIGURE 6. OVERVOLTAGE PROTECTION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 6). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
FN6461.0
March 21, 2007
7
ISL54054, ISL54055
Power-Supply Considerations
High-Frequency Performance
The construction of the ISL54054 and the ISL54055 is
typical of most single supply CMOS analog switches in that
they have two supply pins: V+ and GND. V+ and GND drive
the internal CMOS switches and set their analog voltage
limits. Unlike switches with a 4.5V maximum supply voltage,
the ISL54054 and the ISL54055’s 5.5V maximum supply
voltage provides plenty of room for the 10% tolerance of
4.5V supplies, as well as room for overshoot and noise
spikes.
In 50Ω systems, the ISL54054 and the ISL54055 have a -
3dB bandwidth of 72MHz with Nx pins connected and
138MHz for a single Nx input (see Figure 20). The frequency
response is very consistent over a wide V+ range, and for
varying analog signal levels.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough. Figure 21 details the high
off isolation rejection provided by this family. At 100kHz, off
isolation in 50Ω systems is about 74dB with Nx pins
connected and 83dB with a single Nx input, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease off isolation rejection due
to the voltage divider action of the switch OFF impedance
and the load impedance.
The minimum recommended supply voltage is 1.8V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
Curves on page for details.
V+ and GND also power the internal logic and level shiftier.
The level shiftier converts the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Logic-Level Thresholds
This switch family is 1.8V logic compatible (0.5V and 1.4V)
over a supply range of 2.5V to 5V (see Figure 19). At 5V the
V
level is about 1.38V. This is still below the 1.8V CMOS
IH
guaranteed high output minimum level of 1.4V, but noise
margin is reduced. At 1.8V operation the V level is around
0.1V and can only be used in 1.8V applications with minimal
ground bounce.
IL
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
Typical Performance Curves T = +25°C, Unless Otherwise Specified
A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1.2
V+ = 1.8V
= 100mA
I
= 100mA
COM
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
I
COM
V+ = 1.8V
+85°C
+25°C
-40°C
V+ = 2.7V
V+ = 3V
V+ = 4.5V
V+ = 5V
0
1
2
3
4
5
0
0.5
1.0
(V)
1.5
1.8
V
(V)
V
COM
COM
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (NX PINS CONNECTED)
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
FN6461.0
March 21, 2007
8
ISL54054, ISL54055
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
V+ = 5V
= 100mA
V+ = 3V
= 100mA
I
I
COM
COM
+85°C
+85°C
+25°C
-40°C
+25°C
-40°C
0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
0
1
2
V
3
4
5
V
(V)
(V)
COM
COM
FIGURE 9. ON-RESISTANCE VS SWITCH VOLTAGE
(NX PINS CONNECTED)
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
3.0
2.3
V+ = 1.8V
I
= 100mA
COM
I
= 100mA
COM
2.1
1.9
1.7
1.5
1.3
1.1
0.9
2.5
2.0
1.5
1.0
0.5
V+ = 1.8V
+85°C
+25°C
-40°C
V+ = 2.7V
V+ = 3V
V+ = 4.5V
0.7
0.5
V+ = 5V
0
0.5
1.0
(V)
1.5
1.8
0
1
2
3
4
5
V
(V)
V
COM
COM
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (SINGLE NX INPUT)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
1.6
1.1
V+ = 5V
V+ = 3V
I
= 100mA
COM
I
= 100mA
COM
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
1.4
1.2
1.0
0.8
0.6
0.4
+85°C
+25°C
+85°C
+25°C
-40°C
-40°C
0
0.5
1.0
1.5
COM
2.0
2.5
3.0
0
1
2
V
3
4
5
V
(V)
(V)
COM
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
FN6461.0
March 21, 2007
9
ISL54054, ISL54055
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
200
180
160
140
120
30
25
20
15
10
5
-40°C
+25°C
100
80
+85°C
+25°C
60
40
+85°C
-40°C
2.5
20
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
1.5
2.0
3.0
3.5
4.0
4.5
5.0
5.5
V+ (V)
V+ (V)
FIGURE 15. TURN ON TIME vs SUPPLY VOLTAGE (ISL54054)
FIGURE 16. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54054)
250
30
-40°C
200
25
+85°C
150
20
+25°C
25°C
100
15
-40°C
10
85°C
50
0
1.5
5
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
V+ (V)
V+ (V)
FIGURE 17. TURN ON TIME vs SUPPLY VOLTAGE (ISL54055)
FIGURE 18. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54055)
V+ = 5V
1.6
1.4
1.2
V
INH
1.0
0.8
0
SINGLE NX INPUT
V
INL
-3
NX PINS CONNECTED
0.6
0.4
-6
-9
0.2
0
R
V
= 50Ω
IN
L
= 0.2V
to 2.8V
P-P
P-P
0.1k
1M
10M
FREQUENCY (Hz)
100M
500M
1.5
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 20. FREQUENCY RESPONSE
FN6461.0
March 21, 2007
10
ISL54054, ISL54055
Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)
A
10
V+ = 1.8V to 5.5V
140
20
30
40
50
60
70
80
90
R
= 50Ω
L
V
= 1V
IN
P-P
120
100
80
V+ = 5V
Nx PINS CONNECTED
60
40
20
0
V+ = 3V
SINGLE Nx INPUT
100
110
V+ = 1.8V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
1k
10k
100k
1M
10M
100M 500M
V
COM
FREQUENCY (Hz)
FIGURE 21. OFF ISOLATION
FIGURE 22. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
57
PROCESS:
Submicron CMOS
FN6461.0
March 21, 2007
11
ISL54054, ISL54055
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
L6.1.2x1.0A
A
E
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
D
SYMBOL
MIN
0.45
-
NOMINAL
MAX
0.55
0.05
NOTES
2X
0.10 C
A
A1
A3
b
0.50
-
-
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
0.95
1.15
0.20
0.25
1.05
1.25
5
DETAIL A
0.10 C
0.08 C
D
1.00
-
A
E
1.20
-
7X
e
0.40 BSC
-
C
A1 A3
L
0.30
0.40
0.35
0.40
0.50
-
SEATING
PLANE
SIDE VIEW
L1
N
0.45
-
4X
e
DETAIL B
6
3
-
2
5X
L
Ne
θ
3
1
3
0
12
4
L1
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
6
4
b 6X
0.10 C A B
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
0.05 C
NOTE 3
BOTTOM VIEW
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
0.1x45°
CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
A3
A1
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
DETAIL A
DETAIL B PIN 1 LEAD
1.00
1.40
0.20
0.30
0.35
0.45
0.20
0.40
10
LAND PATTERN
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6461.0
March 21, 2007
12
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