ISL54405_技术文档

ISL54405

®

Data Sheet

June 5, 2008

FN6699.1

CD/MP3 Quality Stereo 2:1 Multiplexer

with Click and Pop Elimination

Features

• Clickless Audio Switching

• 2V Signal Switching from 3.3V or 5V Supply

The Intersil ISL54405 is a single supply, bidirectional, dual

single-pole/double-throw (SPDT) ultra low distortion, high

OFF-Isolation analog switch that can pass analog signals that

are positive and negative with respect to ground. It is primarily

targeted at consumer and professional audio switching

applications such as Computer Sound Cards and Home

Theater products. The inputs can accommodate ground

RMS

• -106dB THD+N into 20kΩ Load @ 2V

RMS

• -108dB THD+N into 32Ω Load @ 3.9mW

• Signal to Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >124dBV

• ±0.01dB Insertion Loss at 1kHz, 20kΩ Load

• ±0.007dB Gain Variation 20Hz to 20kHz

• 125dB Signal Muting into 20kΩ Load

referenced signals up to 2V

while operating from a single

RMS

3.3V or 5V DC supply. The digital logic inputs are 1.8V

logic-compatible when using a single 3.3V or 5V supply. It can

be used in both AC or DC coupled ground referenced

applications.

• 90dB PSRR 20Hz to 20kHz

• Single Supply Operation . . . . . . . . . . . . . . . . . . . . 3.3V or 5V

• Available in 16 Ld TSSOP, 16 Ld TQFN, and 16 Ld µTQFN

• Pb-Free (RoHS Compliant)

The ISL54405 features a soft-switch feature and click/pop

circuitry at each signal pin that eliminates clicks and pops

associated with power-up/down conditions of the preceding

amplifier outputs.

Applications

With -106dB THD+N performance with a 2V

RMS

signal into

• Computer Sound Cards

20kΩ load, superior signal muting, high PSRR and very flat

frequency response the ISL54405 meets the exacting

requirements of consumer and professional audio engineers.

• Home Theater Audio Products

• SACD/DVD Audio

The ISL54405 is available in 16 Ld TSSOP, 16 Ld 3mmx3mm

TQFN, and 16 Ld 2.6mmx1.8mm µTQFN packages. Its

specified for operation over the -40°C to +85°C temperature

range.

• DVD Player Audio Output Switching

• Headsets for MP3/Cellphone Switching

• Hi-Fi Audio Switching Application

TABLE 1. FEATURES AT A GLANCE

ISL54405

Block Diagram

5V_Supply

ISL54405

VDD

Number of Switches

Switch Type

2

SPDT or 2 to 1 MUX

±0.01dB

DIR_SEL

CAP_SS

LOGIC

AND

CLICK/POP

CONTROL

AC/DC

MUTE

SEL

Insertion Loss

THD+N, 2V

, 20kΩLoad

-106dB

RMS

L1

L2

OFF-Isolation (MUTE)

125dB

L

Packages

16 Ld TSSOP, 16 Ld 3x3 TQFN,

16 Ld 2.6x1.8 µTQFN

R1

R2

R

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

GND

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

For 5V operation connect the 5V_Supply pin to 5V and float the

VDD pin. For 3.3V operation connect the VDD pin to 3.3V and float

the 5V_Supply pin.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL54405

Pinouts (Note 1)

ISL54405

(16 LD µTQFN)

TOP VIEW

ISL54405

(16 LD TQFN)

TOP VIEW

16

15

14

13

16

15

14

13

1

2

3

4

12

11

10

9

MUTE

L

L1

L2

R1

R2

1

2

3

4

12

11

10

9

MUTE

L1

L2

R1

R2

L

R

SEL

5

6

7

8

5

6

7

8

ISL54405

(16 LD TSSOP)

TOP VIEW

5V_Supply

AC/DC

MUTE

L

1

2

3

4

5

6

7

8

16 VDD

15 CAP_SS

14 L1

13 L2

R

12 R1

SEL

11 R2

10 GND

GND

9

GND

DIR_SEL

NOTE:

1. See Page 1 for ISL54405 Block Diagram.

FN6699.1

June 5, 2008

2

ISL54405

Truth Table

INPUTS

OUTPUTS

COM (L,R)

C/P Shunts

L1, R1

C/P Shunts

L2, R2

C/P Shunts

AC/DC

DIR

X

0

MUTE

SEL

0

L1, R1

ON

L2, R2

OFF

ON

0

1

0

1

0

1

0

1

OFF

ON

OFF

ON

OFF

ON

1

OFF

ON

X

0

OFF

ON

0

1

OFF

ON

OFF

ON

0

X

0

OFF

ON

1

OFF

1

OFF

1

X

OFF

NOTE: MUTE, AC/DC, DIR: Logic “0” ≤ 0.5V, Logic “1” ≥ 1.4V or Float with a 3.3V Supply or 5V supply.

SEL: Logic “0” ≤0.5V, Logic “1” ≥ 1.4V with a 3.3V Supply or 5V supply.

X = Don’t Care

Pin Descriptions (Continued)

Pin Descriptions

FUNCTION

SEL

Input Select Control Pin

VDD

System Power Supply Pin (+3V to +3.6V)

(Float pin for 5V applications)

AC/DC

DIR_SEL

R

AC/DC Select Control Pin

DIRECTION Select Control Pin

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

5V_Supply 5V Supply Pin (+4.5V to +5.5V)

(Float pin for 3.3V applications)

GND

CAP_SS

MUTE

Ground Connection

L

Soft-Start Capacitor Pin

Signal Mute Control Pin

L2, R2

L1, R1

Ordering Information

PACKAGE

(Pb-Free)

PKG.

DWG. #

PART NUMBER

PART MARKING

54405 IVZ

TEMP. RANGE (°C)

ISL54405IVZ

(Note 2)

-40 to +85

16 Ld TSSOP

M16.173

ISL54405IVZ-T*

(Note 2)

54405 IVZ

-40 to +85

16 Ld TSSOP

ISL54405IRTZ (Note 2)

05TZ

-40 to +85

16 Ld 3x3 TQFN

L16.3x3A

ISL54405IRTZ-T*

(Note 2)

ISL54405IRUZ-T*

(Note 3)

GAD

-40 to+ 85

16 Ld µTQFN

L16.2.6x1.8A

*Please refer to TB347 for details on reel specifications.

NOTES:

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%

matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering

operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu

plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020

FN6699.1

June 5, 2008

3

ISL54405

Absolute Maximum Ratings

Thermal Information

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V

5V_Supply to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Input Voltages

Thermal Resistance (Typical)

θ

(°C/W)

θ

(°C/W)

JC

JA

16 Ld TSSOP Package (Note 5) . . . . .

16 Ld TQFN Package (Notes 6, 7). . . .

16 Ld µTQFN Package (Note 6) . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

150

75

93

N/A

11

N/A

SEL, MUTE, AC/DC, DIR_SEL (Note 4) . . -0.3 to ((V ) + 0.3V)

DD

L1, L2, R1, R2 (Note 4) . . . . . . . . . . . . . . . . -3.1 to ((V ) + 0.3V

DD

Output Voltages

R, L (Note 4). . . . . . . . . . . . . . . . . . . . . . . . -3.1 to ((V ) + 0.3V)

DD

Continuous Current L1, L2, R1, R2 or L, R . . . . . . . . . . . . . ±300mA

Peak Current L1, L2, R1, R2 or L, R

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA

ESD Rating:

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5kV

Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>200V

Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>2kV

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. Signals on L1, L2, R1, R2, MUTE, SEL, AC/DC, DIR_SEL, R, and L exceeding V

or GND by specified amount are clamped. Limit current to

DD

maximum current ratings.

5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

7. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications - 3.3V Supply Test Conditions: V = +3.0V to +3.6V, GND = 0V, V

= V = GND,

AC/DC

DD

= Float, V

DIR_SEL

= 20kΩ, f = 1kHz,

V

= 2V

, R

5V_SUPPLY

= V

SIGNAL

= 1.4V, V

RMS LOAD

= V = 0.5V, CAP_SS = 0.1µF, (Note 8),

SELH

MUTEH

SELL

MUTEL

Unless Otherwise Specified.

TEM

SUPPL

Y

P

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 9, 10)

TYP

(Notes 9, 10) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

3.3V,

5V

Full

-

2

-

V

RMS

V

ANALOG

ON-Resistance, r

V

= 3.3V, I or I = 80mA, V or V =

Lx Rx

3.3V

3.6V

25

Full

25

-

1.9

2.6

-

Ω

ON

DD

R

L

-2.828V to +2.828V (See Figure 4)

-

r

Matching Between

V

= 3.3V, I or I = 80mA, V or V = Voltage

Lx Rx

-

0.023

0.045

0.003

0.009

300

-

Ω

ON

Channels, Δr

DD

at max r

R

L

over -2.828V to +2.828V (Note 13)

ON

Full

25

-

0.01

-

Ω

r

Flatness, r

FLAT(ON)

V

= 3.3V, I or I = 80mA, V or V = -2.828V,

Lx Rx

-

Ω

ON

DD

R

L

0V, +2.828V (Note 11)

Full

25

-

225

-

Ω

L, R, Lx, Rx Pull-down

Resistance

Measure Current, calculate Resistance.

DYNAMIC CHARACTERISTICS

THD+N

V

= 3.6V, V or V = -2.83V, 2.83V, V or

375

-

kΩ

DD

Lx

Rx

AC/DC

L

= -2.83V, 2.83V, V

= 0V, V

= 3.6V,

R

MUTE

Full

345

V

R

= 2V

, f = 1kHz, A-weighted Filter,

3.3V,

5V

25

-

-106

-113

-116

-100

>124

-

dB

SIGNAL

RMS

= 20kΩ

LOAD

V

R

= 1.9V

= 20kΩ

, f = 1kHz, A-weighted Filter,

SIGNAL

RMS

LOAD

V

R

= 1.8V

, f = 1kHz, A-weighted Filter,

SIGNAL

= 20kΩ

LOAD

V

R

= 0.707V

, f = 1kHz, A-weighted Filter,

RMS

SIGNAL

= 32Ω

LOAD

SNR

f = 20Hz to 20kHz, A-weighted Filter, Inputs

grounded, R

3.3V,

5V

dBV

= 20kΩ or 32Ω

LOAD

FN6699.1

June 5, 2008

4

ISL54405

Electrical Specifications - 3.3V Supply Test Conditions: V = +3.0V to +3.6V, GND = 0V, V

= V = GND,

AC/DC

DD

= Float, V

DIR_SEL

= 20kΩ, f = 1kHz,

V

= 2V

, R

5V_SUPPLY

= V

SIGNAL

= 1.4V, V

RMS LOAD

= V = 0.5V, CAP_SS = 0.1µF, (Note 8),

SELH

MUTEH

SELL

MUTEL

Unless Otherwise Specified. (Continued)

TEM

SUPPL

P

MIN

MAX

PARAMETER

TEST CONDITIONS

= 20kΩ

Y

(°C) (Notes 9, 10)

TYP

±0.01

±0.007

(Notes 9, 10) UNITS

Insertion Loss, G

f = 1kHz, R

LOAD

3.3V

25

-

dB

ON

Gain vs Frequency, G

f = 20Hz to 20kHz, R

= 20kΩ, Reference to

f

LOAD

G

at 1kHz

ON

Stereo Channel Imbalance f = 20Hz to 20kHz, R

L1 and R1, L2 and R2

= 20kΩ

3.3V

25

-

±0.003

120

-

dB

LOAD

OFF-Isolation (Muting)

f = 20Hz to 22kHz, L = R = 2V

, R

RMS LOAD

= 20kΩ,

3.3V,

5V

MUTE = AC/DC = 3.3V, DIR_SEL = GND,

SEL = “X”

f = 20Hz to 22kHz, L1, R1, L2, R2 = 2V

, R

RMS LOAD

25

-

120

-

dB

= 20kΩ, MUTE = AC/DC = DIR_SEL = 3.3V,

SEL = “X”

f = 20Hz to 22kHz, V or V = 0.7V

,

25

-

125

120

-

dB

L

R

RMS

R

= 32Ω

LOAD

Crosstalk (Channel-to-

Channel)

R = 20kΩ, f = 20Hz to 20kHz, V

= 2V ,

RMS

3.3V

L

SIGNAL

Signal source impedance = 20Ω, Note: Crosstalk is

inversely proportional to source impedance.

R = 32Ω, f = 20Hz to 20kHz, V

SIGNAL

= 0.7V

25

-

120

-

dB

L

RMS

Signal source impedance = 20Ω, Note: Crosstalk is

inversely proportional to source impedance.

PSRR

f = 1kHz, V

SIGNAL

= 100mV

, Inputs Grounded

3.3V,

5V

25

-

110

90

-

dB

RMS

f = 20kHz, V

Grounded

= 100mV

, Inputs

RMS

SIGNAL

Bandwidth, -3dB

ON to Mute Time,

R

= 50Ω

3.3V

25

-

230

50

-

MHz

ns

LOAD

CAP_SS = 0.1µF

T

TRANS-OM

Mute to ON Time,

CAP_SS = 0.1µF

(Selectable via Soft-Start Capacitor Value)

3.3V

3.6V

3.3V

25

-

58

45

50

45

100

70

10

27

-

ms

μs

ns

T

TRANS-MO

Turn-ON Time, t

V

= 3.3V, V or V = 1.5V, V

Lx Rx

= 0V,

ON

DD

MUTE

R

= 20kΩ, (See Figure 1)

L

Turn-OFF Time, t

V

= 3.3V, V or V = 1.5V, V

Lx Rx

OFF

DD

R

= 20kΩ, (See Figure 1)

L

Break-Before-Make Time

Delay, t

V

= 3.6V, V or V = 1.5V, V

Lx Rx

μs

dB

pF

DD

R

= 20kΩ, See Figure 2

D

L

OFF-Isolation

R

= 50Ω, f = 1MHz, V or V = 1V

,

L

R

RMS

(See Figure 3)

Crosstalk (Channel-to-

Channel)

R

L

= 50Ω, f = 1MHz, V or V = 1V

L

R

(See Figure 5)

Lx, Rx OFF Capacitance,

f = 1MHz, V or V = V or V = 0V

Lx

Rx

L

R

C

(See Figure 6)

OFF

L, R ON Capacitance,

f = 1MHz, V or V = V

Lx Rx

= 0V (See Figure 6)

COM

C

COM(ON)

POWER SUPPLY CHARACTERISTICS

Power Supply Range, VDD 5V_Supply = Float

3.3V

5V

Full

3

-

3.6

5.5

V

Power Supply Range,

5V_Supply

V

= Float

4.5

DD

FN6699.1

June 5, 2008

5

ISL54405

Electrical Specifications - 3.3V Supply Test Conditions: V = +3.0V to +3.6V, GND = 0V, V

= V = GND,

AC/DC

DD

= Float, V

DIR_SEL

= 20kΩ, f = 1kHz,

V

= 2V

, R

5V_SUPPLY

= V

SIGNAL

= 1.4V, V

RMS LOAD

= V = 0.5V, CAP_SS = 0.1µF, (Note 8),

SELH

MUTEH

SELL

MUTEL

Unless Otherwise Specified. (Continued)

TEM

SUPPL

P

MIN

MAX

PARAMETER

TEST CONDITIONS

Y

(°C) (Notes 9, 10)

TYP

54

(Notes 9, 10) UNITS

Positive Supply Current, I+

V

= +3.6V, V

= 0V, V

= 0V or V

DD

3.6V

25

Full

25

-

65

-

μA

DD

MUTE

SEL

59

= V , V

DD SEL

= 0V or V

3.6V

14

18

-

DD

Full

25

15

= 0V, V

= 1.8V

55

65

-

SEL

Full

58

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

,

3.3V,

5V

Full

-

0.5

-

V

SELL

V

MUTEL

Input Voltage High, V

,

3.3V,

5V

1.4

SELH

V

MUTEH

Input Current, I

, I

SELH SELL

V

= 3.6V, V

= 0V, V

= 0V or V

= 0V,

3.6V

Full

-0.5

-1.3

0.01

-0.7

0.5

0.3

µA

DD

MUTE

SEL

DD

Input Current, I

,

V

, V

= V

DD

AC/DCL

AC/DC DIR_SEL

I

= Float, V

DIR_SELL

MUTE

SEL

Input Current, I

,

V

= 3.6V, V

, V

= V

,

3.6V

Full

-0.5

0.01

0.5

µA

AC/DCH

DD

AC/DC DIR_SEL

= 0V, V = 0V

DD

I

DIR_SELH

MUTE

SEL

Input Current, I

NOTES:

V

= 3.6V, V

= V , V

DD MUTE

= 0V

3.6V

Full

-1.3

-0.5

-0.7

0.3

0.5

µA

MUTEL

MUTEH

DD

SEL

= 0V, V = V

0.01

MUTE

DD

8. V = input voltage to perform proper function.

IN

9. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

11. Flatness is defined as the difference between maximum and minimum value of ON-resistance at the specified analog signal voltage points.

12. Limits established by characterization and are not production tested.

13. r

matching between channels is calculated by subtracting the channel with the highest max r

value from the channel with lowest max r

ON

value.

Test Circuits and Waveforms

V

DD

C

V

t < 20ns

r

t < 20ns

f

DD

LOGIC

INPUT

50%

0V

V

OUT

t

Lx OR Rx

OFF

SWITCH

INPUT

L or R

SWITCH

INPUT

V

Lx OR Rx

SEL

V

OUT

90%

C

L

R

LOGIC

INPUT

L

GND MUTE

SWITCH

OUTPUT

0V

t

ON

Repeat test for all switches. C includes fixture and stray

L

Logic input waveform is inverted for switches that have the opposite

logic sense.

capacitance.

R

L

-----------------------

V

= V

OUT

(Lx or Rx)

R

+ r

ON

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FN6699.1

June 5, 2008

6

ISL54405

Test Circuits and Waveforms (Continued)

FIGURE 1. SWITCHING TIMES

V

DD

C

V

DD

0V

LOGIC

INPUT

Lx

Rx

V

OUT

NX

R OR L

C

R

L

90%

SWITCH

OUTPUT

SEL

V

OUT

0V

MUTE

GND

t

LOGIC

INPUT

D

FIGURE 2A. MEASUREMENT POINTS

Repeat test for all switches. C includes fixture and stray

L

capacitance.

FIGURE 2B. TEST CIRCUIT

FIGURE 2. BREAK-BEFORE-MAKE TIME

V

DD

C

V

DD

C

SIGNAL

GENERATOR

MUTE

r

= V /80mA

1

Lx or Rx

ON

Lx or Rx

V

NX

SEL 0V OR V

DD

0V OR V

DD

80mA

SEL

V

1

L, R

ANALYZER

GND

L, R

R

L

GND

MUTE

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

Repeat test for all switches.

FIGURE 3. OFF-ISOLATION TEST CIRCUIT

FIGURE 4. r

TEST CIRCUIT

ON

V

DD

C

V

DD

C

SIGNAL

GENERATOR

Lx OR Rx

SEL

L, R

Lx or Rx

0V OR V

DD

SEL

0V OR V

DD

IMPEDANCE

ANALYZER

Lx or Rx

MUTE

L, R

ANALYZER

NC

GND

MUTE

R

L

Signal direction through switch is reversed, worst case values

are recorded. Repeat test for all switches.

Repeat test for all switches.

FIGURE 5. CROSSTALK TEST CIRCUIT

FIGURE 6. CAPACITANCE TEST CIRCUIT

FN6699.1

June 5, 2008

7

ISL54405

Sound Card AC Coupled Application Block Diagrams

FLOAT

3.3V

5V_Supply

VDD

ISL54405

DIR_SEL

SOFT-START

CAPACITOR

LOGIC

AND

CLICK/POP

CONTROL

CAP_SS

AC/DC

MUTE

LOGIC

0.1µF

SEL

µCONTROLLER

L1

L

L1

L2

FRONT PANEL

L

LINE OUT

OR

AUDIO

R1

HEAD-PHONE

JACK

CODEC

R1

R2

R

L2

R2

BACK PANEL

LINE OUT

OR

HEAD-PHONE

JACK

GND

FLOAT

3.3V

5V_Supply

VDD

ISL54405

DIR_SEL

SOFT-START

CAPACITOR

LOGIC

AND

CLICK/POP

CONTROL

CAP_SS

AC/DC

MUTE

LOGIC

0.1µF

SEL

µCONTROLLER

L

L1

R1

L1

L2

L

FRONT PANEL

AUDIO

LINE OUT

OR

CODEC

R1

R2

HEAD-PHONE

JACK

R

L2

R2

AUDIO

GND

CODEC

The ISL54405 has special circuitry to eliminate click and

pops in the speakers during power-up and power-down of

the audio CODEC drivers, during removal and insertion of

headphones, and while switching between sources and

loads.

Detailed Description

The ISL54405 is a single supply, bi-directional, dual single

pole/double throw (SPDT) ultra low distortion, high

off-isolation analog switch. It was designed to operate from

either a 3.3V or 5V single supply. When operated with a 3.3V

or 5V single supply, the switches can accommodate

The ISL54405 was designed primarily for consumer and

professional audio switching applications such as computer

sound cards and home theater products. The “Application

Block Diagrams” on this page show two typical sound card

applications. In the upper block diagram the ISL54405 is being

used to route a single stereo source to either the front or back

panel line outs of the computer sound card. In the lower block

diagram the ISL54405 is being used to multiplex two stereo

sources to a single line out of the computer sound card.

±2.83V

(2V ) ground reference analog signals. The

PEAK

RMS

switch r

flatness across this range is extremely small

ON

resulting in excellent THD+N performance (0.0006% with

20kΩ load and 0.0014% with 32Ω load at 707mV ). The

RMS

T-Type configuration of the switch cells prevents signals

from getting through to the output when a switch is in the

OFF-state providing for superior mute performance

(>120dB) in audio applications.

FN6699.1

June 5, 2008

8

ISL54405

SPDT Switch Cell Architecture and Performance

Characteristics

Supply Voltage, Signal Amplitude, Grounding

The power supply connected at VDD or the 5V_SUPPLY pin

provides power to the ISL54405 part. The ISL54405 is a

single supply device that was designed to be operated with a

3.3V ±10% DC supply connected at the VDD pin or a 5V

±10% DC supply connected at the 5V_SUPPLY pin.

The normally open (L , R ) and normally closed (L , R ) of

2

1

the SPDT switches are T-Type switches that have a typical

of 1.9Ω and an off-isolation of >120dB. The low on-

r

ON

resistance (1.9Ω) and r

flatness (0.003Ω) provide very low

ON

insertion loss and minimal distortion to applications that

require hi-fidelity signal reproduction.

It was specifically designed to accept ground referenced

2V

(± 2.828V ) audio signals at its signal pins while

RMS

PEAK

The SPDT switch cells have internal charge pumps that

allow for signals to swing below ground. They were

specifically designed to pass audio signals that are ground

driving either 10k/20kΩ receiver loads or 32Ω headphone

loads.

When using the part in a 3.3V application the 5V_Supply pin

should be left floating. A 0.1µF decoupling capacitor should

be connected from the VDD pin to ground to minimize power

supply noise and transients. This capacitor should be

located as close to the pin as possible.

referenced and have a swing of ± 2.828V

while driving

PEAK

either 10k/20kΩ (receiver) or 32Ω (headphone) loads.

Each switch cell incorporates special circuitry to gradually

decrease the switch resistance when transitioning from the

OFF-state (high impedance) to the ON state (1.9Ω). The

gradual decrease in the switch resistance provides for a slow

ramp of the voltage at the load side of the switch which helps

to eliminate click and pops in the speaker by suppressing the

transient during switching events. The output voltage ramp

time is determined by the capacitor value of the soft-start

capacitor connected at the CAP_SS pin. With a 0.1µF

ceramic chip capacitor the ramp time is approximately

4.6V/s. The slow ramping of the signal at the output can be

disabled by floating the CAP_SS pin.

The part also has a 5V supply pin (5V_Supply) to allow it to

be used in 5V ±10% applications. Special circuitry within the

device converts the 5V, connected at the 5V_Supply pin, too

3.3V to properly power the internal circuitry of the device.

When using the part in a 5V application the VDD pin should

be left floating. A 0.1µF decoupling capacitor should be

connected from the 5V_Supply pin to ground to minimize

power supply noise. This capacitor should be located as

close to the pin as possible.

In addition to the slow ramp feature (soft-start feature) of the

in line switches, the part has special click and pop (C/P)

Grounding of the ISL54405 should follow a star configuration

(see Figure 7). All grounds of the IC should be directly

connected to the power supply ground return without

cascading to other grounds. This configuration isolates

shunt currents of the Click and Pop transients from the IC

ground and optimizes device performance.

shunt circuitry at each of the signal pins (L, R, L , L , R ,

1

2

1

and R ). A pin’s C/P shunt circuitry is activated or de-

2

activated depending on the logic levels applied at the AC/DC

and DIR_SEL control pins. This shunt circuitry serves two

functions:

+3.3V

1. In an AC coupled application they are activated and

directed to the source side of the switch to suppress or

eliminate click/pop noise in the speaker load when

powering up or down of the audio CODEC drivers.

VDD

MUTE

GND2

SEL

LOGIC

CONTROL

GND3

AC/DC

2. For superior muting the C/P shunt circuitry is activated

and directed to the load side of the switch which gives

>120dB of off-isolation when driving a 10k/20kΩ receiver

load with an audio signal in the range of 20Hz to 22kHz.

0.1µF

DIR_SEL

L1

L2

L

R

R1

R2

If the AC/DC pin is driven LOW, all C/P shunt circuitry at all

the signal pins (L, R, L1, R1, L2, and R2) are deactivated

and not operable.

ISL54405

GND1

If the AC/DC pin is driven HIGH then the logic at the

DIR_SEL pin will determine whether the L and R (COM) C/P

shunt circuitry is activated or the L1, L2, R1, and R2 (NOx,

NCx) C/P shunt circuitry is activated. When the DIR_SEL is

driven LOW, the L1, R1, L2, R2 C/P shunt circuitry will be

activated while the L and R C/P shunt circuitry will be

deactivated. When the DIR_SEL is driven HIGH the L and R

C/P shunt circuitry will be activated while the L1, R1, L2, R2

C/P shunt circuitry will be deactivated. Note: Shunt circuitry

that is activated will be turned ON when a switch cell is

turned OFF and will be OFF when a switch cell is turned ON.

FIGURE 7. STAR GROUNDING CONFIGURATION

Mute Operation

When the MUTE logic pin is driven HIGH the part will go into

the Mute State. In the Mute State all switches of the SPDTs

are OPEN while the T-Shunt switches are closed. In addition

any activated click and pop shunt circuitry at the signal pins

is turned ON.

See “Logic Control” on page 10 for more details.

FN6699.1

June 5, 2008

9

ISL54405

MUTE TO ON

activated on the source side of the switch. See “Click and

Pop Operation” on page 11.

When the Mute pin is driven LOW the ISL54405 will

transition to the ON-state in the following sequence:

When using the switch for muting of the audio signal the C/P

shunt circuitry should be de-activated on the source side of

the switch and directed to the load side of the switch for best

possible off-isolation.

1. All active shunt switches turn-off quickly.

2. The resistance of the switches selected by the SEL pin

will gradually decrease in resistance. They will decrease

from their high OFF-resistance to their ON-resistance of

1.9Ω. This gradual decrease in resistance will allow for

the voltage at the load to increase gradually. The voltage

ramp rate at the load is determined by the value of the

capacitor connected at the CAP_SS pin. See Figures 27

and 28 in the “Typical Performance Curves” beginning on

page 13.

Logic Control

The ISL54405 has four logic control pins; the AC/DC,

DIR_SEL, MUTE, and SEL. The MUTE and SEL control pins

determine the state of the switches. The AC/DC and

DIR_SEL control pins determine the location of the C/P

(click/pop) shunt circuitry and if it will be active or not. See

“Truth Table” on page 3.

Table 2 indicates how the signal ramp rate at the load

changes as you change the CAP_SS capacitor value. It also

shows how the mute turn-on time is affected.

The ISL54405 logic is 1.8V CMOS compatible (Low ≤ 0.5V

and High ≥ 1.4V) over a supply range of 3.0V to 3.6V at the

VDD pin or 4.5V to 5.5V at the 5V_SUPPLY pin. This allows

control via 1.8V or 3V µcontroller.

TABLE 2. SIGNAL RAMP-RATE LOAD CHANGE WITH

CAP SS

CAPACITOR

SEL, MUTE CONTROL PINS

VALUE

No Capacitor

0.05µF

RAMP RATE

6250V/s

10.3V/s

TURN-ON TIME

65µs

The state of the SPDT switches of the ISL54405 device is

determined by the voltage at the MUTE pin and the SEL pin.

30ms

The SEL control pin is only active when MUTE is logic “0”.

The MUTE has an internal pull-up resistor to the internal

3.3V supply rail and can be driven high or tri-stated(floated)

by the µprocessor.

0.1µF

4.6V/s

58ms

ON TO MUTE

When the Mute pin is driven HIGH the switches will turn OFF

quickly (50ns) and the active shunt switches will turn ON

quickly. Note: There is no gradual ramping of the switch

resistance in this direction.

These pins are 1.8V logic compatible. When powering the

part by the VDD pin the logic voltage can be as high as the

V

voltage which is typically 3.3V. When powering the part

DD

by the 5V_SUPPLY pin the logic voltage can be as high as

the 5V_SUPPLY voltage which is typically 5V.

OFF-ISOLATION IN THE MUTE STATE

Logic Levels:

When in the mute state, the level of OFF-Isolation across the

audio band is dependent on the signal amplitude, external

loading, and location of the activated C/P (click/pop) shunt

circuitry. During muting the logic of the ISL54405 can be

configured to activate the C/P shunt circuitry on the load side

of the switch or on the source side of the switch, or

deactivated on both sides of the switch.

MUTE = Logic “0” (Low) when ≤ 0.5V

MUTE = Logic “1” (High) when ≥1.4V or Floating

SEL = Logic “0” (Low) when ≤ 0.5V

SEL = Logic “1” (High) when ≥1.4V

AC/DC AND DIR_SEL CONTROL PINS

The ISL54405 contains C/P (click/pop) shunt circuitry on its

COM pins (L, R) and on its signal pins (L1, R1, L2, R2). The

activation of this circuitry and whether it is located on the

COM or signal side of the switch is determined by the logic

levels applied at the AC/DC and DIR_SEL pins. The

DIR_SEL control pin is only active when AC/DC is logic “1”.

Note: Any activated C/P shunt circuitry is ON when in the

mute state (MUTE = Logic “1”) and OFF in the audio state

(MUTE = Logic “0”).

With a 0.707V

signal driving a 32Ω headphone load the

RMS

location of the C/P shunt circuitry has little effect on the

off-isolation performance (> 120dB of off-isolation in all

configurations). See Figure 11 in the “Typical Performance

Curves” beginning on page 13.

With a 2V

RMS

signal driving a 20kΩ amplifier load the best

off-isolation is achieved by placing the C/P shunt circuitry on

the load side of the switch (>120dB across the audio band).

The off-isolation decreases when placing the C/P shunt

circuitry on the source side of the switch (>85dB across the

audio band). See Figure 10 in the “Typical Performance

Curves” beginning on page 13.

When AC/DC is logic “0”, all of the C/P shunt circuitry on

both sides of the switch is deactivated and not operable.

When AC/DC is logic “1” then the DIR_SEL logic level

determines whether the shunt circuitry will be activated on

the COM side of the switch or on the signal side of the

switch. When DIR_SEL = Logic “1” the C/P shunts on the

Note: For AC coupled applications when powering up or

down of the audio codecs the C/P shunts should be

FN6699.1

June 5, 2008

10

ISL54405

COM side (L,R) are activated and inoperable on the signal

Once the driver DC bias has reached VDD/2 and the

transient on the switch side of the DC blocking capacitor has

been discharged to ground through the C/P shunt circuitry,

the switches can be turned ON and connected through to the

speaker loads without generating an undesirable click/pop in

the speakers.

side (L1, R1, L2, R2) of the switch. When DIR_SEL = Logic

“0” the C/P shunts are activated on the signal side (L1, R1,

L2, R2) and inoperable on the COM side (L, R).

Logic Levels:

AC/DC, DIR_SEL = Logic “0” (Low) when ≤ 0.5V

AC/DC, DIR_SEL = Logic “1” (High) when ≥1.4V or Floating.

With a typical DC blocking capacitor of 220µF and the C/P

shunt circuitry designed to have a resistance of 40Ω,

allowing a 100ms wait time to discharge the transient before

placing the switch in the Audio mode will prevent the

transient from getting through to the speaker load. See

Figures 25 and 26 in the “Typical Performance Curves”

beginning on page 13.

The AC/DC and DIR_SEL have internal pull-up resistors to

the internal 3.3V supply rail and can be driven high or

tri-stated (floated by the µprocessor). They should be driven

to ground for a logic “0” (Low). Note: For 5V applications, the

AC/DC and DIR_SEL pins should never be driven to the

external 5V rail. They need to be driven with 1.8V logic or 3V

logic circuit.

DC COUPLED CLICK AND POP OPERATION

The ISL54405 can pass ground referenced audio signals

which allows it to be directly connected to audio drivers that

output ground referenced audio signals, eliminating the need

for a DC blocking capacitor.

AC Coupled or DC Coupled Operation

The Audio CODEC drivers can be directly coupled to the

ISL54405 when the audio signals from the drivers are

ground referenced or do not have a significant DC offset

voltage, < 50mV. Otherwise the signal should be AC coupled

to the ISL54405 part.

Audio drivers that swing around ground however do

generate some DC offset, from a few millivolts to tens of

millivolts. When switching between audio channels or muting

the audio signal these small DC offset levels of the drivers

can generate a transient that can cause un-wanted clicks

and pops in the speaker loads.

CLICK AND POP OPERATION

The ISL54405 has special circuitry to eliminate click and

pops in the speakers during power-up and power-down of

the Audio CODEC Drivers and during removal and insertion

of headphones.

In a DC coupled application the C/P shunt resistors placed at

the source side of the switch have no effect in eliminating the

transients at the speaker loads when transitioning in and out

of the mute state or switching between channels. In fact

having these C/P shunts active on the source side only

increase un-neccesary power consumption. So, for DC

coupled connection the C/P shunt circuitry should not be

applied at the source (driver) side of the switch.

A different click and pop scheme is required depending on

whether the audio CODEC drivers are AC coupled or DC

coupled to the inputs of the ISL54405 part.

AC COUPLED CLICK AND POP OPERATION

Single supply audio drivers have their signal biased at a DC

offset voltage, usually at 1/2 the DC supply voltage of the

driver. As this DC bias voltage comes up or goes down

during power up or down of the driver a transient can be

coupled into the speaker load through the DC blocking

capacitor (see the “Application Block Diagrams” on page 8).

For DC coupled applications the ISL54405 has a special

soft-start feature that slowly ramps the DC offset voltage

from the audio driver to the speaker load when turning ON a

switch channel. The ramp rate at the load is determined by

the capacitor value connected at the CAP_SS pin.

When a driver is OFF and suddenly turned ON the rapidly

changing DC bias voltage at the output of the driver will

cause an equal voltage at the input side of the switch due to

the fact that the voltage across the blocking capacitor cannot

change instantly. If the switch is in Audio mode or there is no

low impedance path to discharge the capacitor voltage at the

input of the switch, before turning on the switch, a transient

discharge will occur in the speaker, generating a Click and

pop noise.

Lab experimentation has shown that if you can slow the

voltage ramp rate at the speaker to < 10V/s, you can

eliminate click/pop noise in a speaker. A soft-start capacitor

value of 0.1µF provides for 4.5V/s ramp rate and is

recommended. See Figures 27 and 28 in the “Typical

Performance Curves” beginning on page 13.

See “MUTE to ON” section on page 10 for more detail of

how soft-start works.

Proper elimination of a click/pop transient at the speaker

load while powering up or down of the audio driver requires

that the ISL54405 have its C/P shunts activated on the

source side of the switch and then placed in Mute mode.

This allows the transient generated by the audio drivers to

be discharged through the Click and Pop shunt circuitry.

Supply Sequencing and Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes or diode stacks from the pin to V

DD

and to GND (see Figure 8). To prevent forward biasing these

FN6699.1

June 5, 2008

11

ISL54405

.

diodes, V

must be applied before any input signals, and

the signal voltages must remain between V and -3V and

DD

and ground.

OPTIONAL

SCHOTTKY

DIODE

the logic voltage must remain between V

DD

If these conditions cannot be guaranteed, then precautions

must be implemented to prohibit the current and voltage at

the logic pin and signal pins from exceeding the maximum

ratings of the switch. The following two methods can be used

to provided additional protection to limit the current in the

event that the voltage at a signal pin goes below ground by

V

DD

OPTIONAL

PROTECTION

RESISTOR

LOGIC

INPUT

V

NX

COM

more than -3V or above the V

rail and the logic pin goes

rail.

DD

below ground or above the V

GND

DD

OPTIONAL

SCHOTTKY

DIODE

Logic inputs can be protected by adding a 1kΩ resistor in

series with the logic input (see Figure 8). The resistor limits

the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

FIGURE 8. OVERVOLTAGE PROTECTION

High-Frequency Performance

In 50Ω systems, the ISL54405 has a -3dB bandwidth of

230MHz (see Figure 29). The frequency response is very

consistent over varying analog signal levels.

This method is not acceptable for the signal path inputs.

Adding a series resistor to the switch input defeats the

purpose of using a low r

switch. Connecting Schottky

ON

diodes to the signal pins (as shown in Figure 8) will shunt the

fault current to the supply or to ground thereby protecting the

switch. These Schottky diodes must be sized to handle the

expected fault current and to clamp when the voltage

reaches the overvoltage limit.

An OFF-switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal

feedthrough from a switch’s input to its output. Off-Isolation

is the resistance to this feedthrough, while crosstalk

indicates the amount of feedthrough from one switch to

another. Figure 30 details the high Off-Isolation and crosstalk

rejection provided by this part. At 1MHz, Off-Isolation is

about 100dB in 50Ω systems, decreasing approximately

20dB per decade as frequency increases. Higher load

impedances decrease off-Isolation and Crosstalk rejection

due to the voltage divider action of the switch off impedance

and the load impedance.

FN6699.1

June 5, 2008

12

ISL54405

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

80

3.0

V

R

= 3.3V OR V_Supply = 5V

DD

V

= 3.3V

C/P SHUNT ON SIGNAL SIDE

DD

= 20kΩ

LOAD

VSIGNAL = 2V

90

100

110

120

130

140

150

160

170

+85°C

I

= 80mA

COM

RMS

2.5

2.0

1.5

1.0

0.5

0

+25°C

-40°C

NO C/P SHUNT

C/P SHUNT ON LOAD SIDE

-3

-2

-1

0

1

2

3

20

50

100 200

500 1k

2k

5k

10k 20k

V

(V)

COM

FREQUENCY (Hz)

FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 10. OFF-ISOLATION, 2V

SIGNAL, 20kΩLoad

RMS

80

-80

-85

-90

-95

V

= 3.3V OR V_Supply = 5V

DD

V

= 3.3V

DD

90

100

110

120

130

140

150

160

170

180

R

= 32Ω

LOAD

VSIGNAL = 0.707V

R

= 20kΩ

LOAD

VSIGNAL = 2V

RMS

-100

-105

-110

-115

-120

-125

-130

-135

-140

-145

-150

-155

-160

-165

-170

C/P SHUNT ON SIGNAL SIDE

No C/P SHUNT

C/P SHUNT ON LOAD SIDE

20

50

100 200

500 1k

2k

5k

10k 20k

20

50

100 200

500 1k

2k

5k

10k 20k

FREQUENCY (Hz)

FIGURE 11. OFF-ISOLATION, 0.707V

SIGNAL, 32Ω LOAD

FIGURE 12. CHANNEL-TO-CHANNEL CROSSTALK

RMS

-80

-85

0.050

V

= 3.3V

DD

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0.000

V

= 3.3V

DD

-90

-95

R

= 20kΩ

LOAD

R

= 32Ω

LOAD

VSIGNAL = 0.707V

V

= 2V

RMS

SIGNAL

RMS

-100

-105

-110

-115

-120

-125

-130

-135

-140

-145

-150

20

50 100 200

500 1k 2k

FREQUENCY (Hz)

5k 10k 20k

20

100

1k

FREQUENCY (Hz)

10k 20k

FIGURE 13. CHANNEL-TO-CHANNEL CROSSTALK

FIGURE 14. INSERTION LOSS vs FREQUENCY

FN6699.1

June 5, 2008

13

ISL54405

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0.020

0.05

V

= 3.3V

DD

V

= 3.3V

DD

R

= 20kΩ

0.04

0.03

LOAD

0.015

0.010

0.005

0

R

= 20kΩ

LOAD

VSIGNAL = 2V

RMS

RELATIVE TO 1kHz

RMS

0.02

L2 AND R2

L1 AND R1

0.01

0.00

-0.01

-0.02

-0.03

-0.04

-0.05

-0.005

-0.010

-0.015

-0.020

20

100

1k

FREQUENCY (Hz)

10k 20k

20

100

1k

10k 20k

FREQUENCY (Hz)

FIGURE 15. GAIN vs FREQUENCY

FIGURE 16. STEREO IMBALANCE vs FREQUENCY

0.0020

-90

V = 3.3V

DD

V

R

= 3.3V

DD

-92

-94

R

= 32Ω

LOAD

A-WEIGHTED FILTER

-96

0.0010

0.0009

0.0008

0.0007

0.0006

-98

-100

-102

-104

-106

-108

-110

-112

-114

-116

-118

-120

0.0005

1V

P-P

1V

0.0004

P-P

510mV

P-P

0.0003

0.0002

510mV

P-P

0.0001

20

50

100 200

500

1k

2k

5k

10k 20k

20

50 100 200

500

1k

2k

5k

10k 20k

FREQUENCY (Hz)

FIGURE 17. THD+N vs SIGNAL LEVELS vs FREQUENCY

FIGURE 18. THD+N vs SIGNAL LEVELS vs FREQUENCY

0.0010

0.0009

0.0008

0.0007

0.0006

-100

V

R

= 3.3V

V

= 3.3V

-101

-102

-103

-104

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

-116

-117

-118

-119

-120

DD

= 20kΩ

R

= 20kΩ

LOAD

A-WEIGHTED FILTER

LOAD

A-WEIGHTED FILTER

2V

RMS

0.0005

0.0004

2V

RMS

1.9V

0.0003

0.0002

RMS

1.9V

RMS

1.8V

1.5V

1.8V

RMS

1.5V

RMS

0.0001

20

50

100 200

500 1k

FREQUENCY (Hz)

2k

5k

10k 20k

20

50

100 200

500 1k

2k

5k

10k 20k

FREQUENCY (Hz)

FIGURE 19. THD+N vs SIGNAL LEVELS vs FREQUENCY

FIGURE 20. THD+N vs SIGNAL LEVELS vs FREQUENCY

FN6699.1

June 5, 2008

14

ISL54405

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

0.00100

0.00095

0.00090

0.00085

0.00080

0.00075

0.00070

0.00065

0.00060

0.00055

0.00050

0.00045

0.00040

0.00035

0.00030

0.00025

0.00020

0.00015

0.00010

-100

-101

-102

-103

-104

-105

-106

-107

-108

-109

-110

-111

-112

-113

-114

-115

-116

-117

-118

-119

-120

V

R

= 3.3V

= 20kΩ

V

R

= 3.3V

= 20kΩ

DD

2V

RMS

LOAD

10Hz TO 30k FILTER

LOAD

10Hz to 30k FILTER

1.9V

RMS

2V

RMS

1.7V

TO 1.8V

RMS

1.9V

RMS

1.7V

TO 1.8V

RMS

1.6V

RMS

1.5V

RMS

1.6V

1.5V

RMS

20

50

100 200

500 1k

2k

5k 10k 20k

20

50

100 200

500 1k

2k

5k

10k 20k

FREQUENCY (Hz)

FIGURE 21. THD+N vs SIGNAL LEVELS vs FREQUENCY

FIGURE 22. THD+N vs SIGNAL LEVELS vs FREQUENCY

-60

-65

-50

-55

-60

-65

-70

-75

5V_Supply = 5VDC + 100MV

SIGNAL

RMS

V

= 3.3VDC + 100mV

SIGNAL

DD

RMS

-70

-75

R

= 20kΩ OR 32Ω

LOAD

R

= 20kΩ OR 32Ω

LOAD

INPUTS GROUNDED

-80

-85

-80

-85

-90

-95

-90

AUDIO MODE

-100

-105

-110

-115

-120

-125

-130

-135

-140

-95

-100

-105

-110

-115

-120

-125

-130

-135

-140

AUDIO MODE

MUTE MODE

(C/P SHUNT ON LOADSIDE)

MUTE MODE

(C/P SHUNT ON LOADSIDE)

20

50 100 200

500 1k 2k

FREQUENCY (Hz)

5k 10k 20k 40k

20

50 100 200

500 1k

2k

5k 10k 20k 40k

FREQUENCY (Hz)

FIGURE 24. PSRR vs FREQUENCY

FIGURE 23. PSRR vs FREQUENCY

7

6

7

6

2V/DIV

MUTE 2V/DIV

MUTE

VDD/2

5

2V/DIV

VDD/2

4

3

2

1

0

L

200mV/DIV

L

200mV/DIV

IN

-1

-2

-3

-4

-5

-6

-7

-1

-2

-3

-4

-5

-6

-7

L

200mV/DIV

OUT

L

200mV/DIV

OUT

-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

0

0.1 0.2 0.3 0.4

-0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1

0

0.1 0.2 0.3 0.4

TIME (s) 100ms/DIV

FIGURE 25. 20kΩ AC COUPLED CLICK/POP REDUCTION

FIGURE 26. 32Ω AC COUPLED CLICK/POP REDUCTION

FN6699.1

June 5, 2008

15

ISL54405

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

80

60

40

20

0

LEFT INPUT

60

40

4.6V/s

10.3V/s

LEFT OUTPUT

RIGHT OUTPUT

LEFT OUTPUT

RIGHT OUTPUT

20

0

-20

-40

-60

-80

-20

-40

-60

-80

RIGHT INPUT

= 3.3V

RIGHT INPUT

V

DD

V

= 3.3V

DD

CAP_SS = 0.1µF

-100 -80 -60 -40 -20

TIME (ms)

CAP_SS = 0.05µF

-100 -80 -60 -40 -20

TIME (ms)

0

20

40

60

80

100

0

20

40

60

80 100

FIGURE 28. SOFT-START (0.05µF) CLICK/POP REDUCTION

FIGURE 27. SOFT-START (0.1µF) CLICK/POP REDUCTION

0

V

R

= 3.3V

= 50Ω

DD

LOAD

V

R

= 3.3V

= 50Ω

DD

LOAD

0

-1

-2

-3

20

-20

40

-40

CROSSTALK

60

-60

80

-80

ISOLATION

100

120

-100

-120

1k

10k

100k

1M

10M

100M 500M

1

10

100

300

FREQUENCY (Hz)

FREQUENCY (MHz)

FIGURE 30. CROSSTALK AND OFF-ISOLATION

FIGURE 29. FREQUENCY RESPONSE

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

3376

PROCESS:

Submicron CMOS

FN6699.1

June 5, 2008

16

ISL54405

Thin Shrink Small Outline Plastic Packages (TSSOP)

M16.173

N

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

MIN

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

GAUGE

PLANE

SYMBOL

MAX

0.043

0.006

0.037

0.012

0.008

0.201

0.177

MIN

-

MAX

1.10

0.15

0.95

0.30

0.20

5.10

4.50

NOTES

A

A1

A2

b

-

0.002

0.033

0.0075

0.0035

0.193

0.169

0.05

0.85

0.19

0.09

4.90

4.30

-

1

2

3

-

L

0.25

0.010

0.05(0.002)

SEATING PLANE

A

9

-A-

c

-

D

3

-C-

E1

e

4

α

0.026 BSC

0.65 BSC

-

A2

e

A1

c

E

0.246

0.020

0.256

0.028

6.25

0.50

6.50

0.70

-

b

0.10(0.004)

L

6

0.10(0.004) M

C

A M B S

N

16

7

o

0

8

0

8

-

α

NOTES:

Rev. 1 2/02

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.15mm (0.006

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact. (Angles in degrees)

FN6699.1

June 5, 2008

17

ISL54405

Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)

L16.2.6x1.8A

D

A

B

16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

6

INDEX AREA

SYMBOL

MIN

0.45

NOMINAL

MAX

0.55

NOTES

N

E

A

A1

A3

b

0.50

-

2X

0.10 C

1 2

-

0.05

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

2.55

1.75

0.20

2.60

1.80

0.40 BSC

0.40

0.50

16

0.25

2.65

1.85

5

D

-

0.10 C

E

-

C

A

0.05 C

SEATING PLANE

e

-

L

0.35

0.45

0.55

-

A1

L1

N

-

SIDE VIEW

2

Nd

Ne

θ

4

3

e

4

3

PIN #1 ID

L1

1 2

0

-

12

4

NX L

Rev. 4 8/06

NOTES:

5

NX b

16X

(DATUM B)

(DATUM A)

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

0.10 M C A B

0.05 M C

3. Nd and Ne refer to the number of terminals on D and E side,

respectively.

BOTTOM VIEW

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

C

L

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

(A1)

NX (b)

5

L

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

e

SECTION "C-C"

TERMINAL TIP

C C

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

3.00

1.80

1.40

0.90

1.40

2.20

0.40

0.20

0.40

0.50

10

LAND PATTERN

FN6699.1

June 5, 2008

18

ISL54405

Thin Quad Flat No-Lead Plastic Package (TQFN)

Thin Micro Lead Frame Plastic Package (TMLFP)

)

2X

L16.3x3A

0.15

E1/2

A2

C A

D

A

16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

9

D/2

MILLIMETERS

D1

SYMBOL

MIN

NOMINAL

MAX

0.80

0.05

0.80

NOTES

D1/2

A

A1

A2

A3

b

0.70

0.75

-

2X

N

0.15 C

B

-

6

INDEX

AREA

-

9

1

2

3

E/2

9

0.20 REF

9

E1

E

B

0.18

1.35

0.23

0.30

1.65

5, 8

D

3.00 BSC

-

2X

D1

D2

E

2.75 BSC

9

0.15 C

B

2X

1.50

7, 8, 10

TOP VIEW

SIDE VIEW

0.15 C

A

3.00 BSC

-

0

4X

E1

E2

e

2.75 BSC

9

A

/ /

0.10 C

0.08 C

C

1.50

7, 8, 10

0.50 BSC

-

A1

A3

SEATING PLANE

k

0.20

0.30

-

0.40

16

4

-

9

L

0.50

8

5

NX b

N

2

0.10 M C A B

4X P

D2

8

7

Nd

Ne

P

3

NX k

(DATUM B)

4

3

2

N

-

0.60

12

9

4X P

θ

-

9

1

2

(DATUM A)

Rev. 0 6/04

(Ne-1)Xe

REF.

3

E2

6

NOTES:

INDEX

AREA

7

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

E2/2

8

NX L

8

N

e

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

9

CORNER

OPTION 4X

(Nd-1)Xe

REF.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

BOTTOM VIEW

A1

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX b

5

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

SECTION "C-C"

C

L

C

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

L

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

L

10

L1

10

L1

e

10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2

and D2 MAX dimension.

C

TERMINAL TIP

FOR ODD TERMINAL/SIDE

FOR EVEN TERMINAL/SIDE

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6699.1

June 5, 2008

19


型号：	ISL54405
厂家：	Intersil
描述：	CD/MP3 Quality Stereo 2:1 Multiplexer with Click and Pop Elimination CD / MP3音质立体声2 ： 1多路复用器与杂音消除复用器 CD
文件：	总19页 (文件大小：957K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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