ISL54503IRUZ-T [INTERSIL]
+1.8V to +5.5V, 2.5ヘ, Single SPDT Analog Switch; + 1.8V至+ 5.5V ， 2.5Ω ，单SPDT模拟开关
| 型号： | ISL54503IRUZ-T |
| 厂家： | 
Intersil |
| 描述： | +1.8V to +5.5V, 2.5ヘ, Single SPDT Analog Switch |
| 文件： | 总11页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL54503
®
Data Sheet
August 29, 2007
FN6551.1
+1.8V to +5.5V, 2.5Ω, Single SPDT Analog
Switch
Features
• ON-resistance (r
)
ON
The Intersil ISL54503 device is a low ON-resistance, low
voltage, bidirectional, single pole/double throw (SPDT)
analog switch designed to operate from a single +1.8V to
+5.5V supply. Targeted applications include battery powered
equipment that benefit from low ON-resistance (2.5Ω) and
- V
- V
- V
= +5.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5Ω
= +3.0V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0Ω
= +1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0Ω
CC
CC
CC
• r
matching between channels . . . . . . . . . . . . . . . . . . .3mΩ
flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . . 0.6Ω
ON
fast switching speeds (t
= 25ns, t = 15ns). The digital
• r
ON
OFF
ON
logic input is 1.8V CMOS compatible when using a single +3V
supply.
• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V Supply)
Cell phones, for example, often face ASIC functionality
limitations. The number of analog input or GPIO pins may be
limited and digital geometries are not well suited to analog
switch performance. This part may be used to “mux-in”
additional functionality while reducing ASIC design risk. The
ISL54503 is offered in the 6 Ld 1.2mmx1.0mmx0.4mm pitch
µTDFN package, alleviating board space limitations.
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
OFF
• Guaranteed break-before-make
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• 1.8V CMOS logic compatible (+3V supply)
• Available in 6 Ld µTDFN package
The ISL54503 is a committed SPDT that consist of one
normally open (NO) and one normally closed (NC) switch.
This configuration can also be used as a 2-to-1 multiplexer.
• Pb-free available (RoHS compliant)
Applications
TABLE 1. FEATURES AT A GLANCE
ISL54503
• Battery powered, handheld, and portable equipment
- Cellular/mobile phones
Number of Switches
SW
1
SPDT or 2-1 MUX
6Ω
- Pagers
- Laptops, notebooks, palmtops
1.8V r
ON
• Portable Test and Measurement
• Medical Equipment
1.8V t /t
ON OFF
65ns/40ns
3Ω
• Audio and video switching
3V r
ON
3V t /t
30ns/20ns
2.5Ω
ON OFF
5V r
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
ON
5V t /t
25ns/15ns
6 Ld µTDFN
ON OFF
Package
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL54503
Ordering Information
PART NUMBER
(Note)
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
PART MARKING
ISL54503IRUZ-T*
3
-40 to +85
6 Ld μTDFN (Tape and Reel) L6.1.2x1.0A
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and
NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Descriptions
Pinout (Note 1)
ISL54503
(6 LD μTDFN)
TOP VIEW
NAME
PIN
FUNCTION
System Power Supply Input (+1.8V to +5.5V)
Ground Connection
V+
5
GND
IN
2
1
6
5
4
IN
NO
6
Digital Control Input
GND
NC
2
3
V+
COM
NO
4
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
1
COM
NC
3
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
LOGIC
PIN NC
ON
PIN NO
OFF
0
1
OFF
ON
NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
FN6551.1
August 29, 2007
2
ISL54503
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.5V
Input Voltages
Thermal Resistance (Typical, Notes 3, 4)
6 Ld µTDFN Package . . . . . . . . . . . . .
θ
(°C/W)
θ
(°C/W)
JA
239.2
JC
111.6
NO, NC, IN (Note 2) . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Output Voltages
COM (Note 2) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>300V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .>1400V
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Analog Signal Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
V
(Digital Logic Input Voltage (IN) . . . . . . . . . . . . . . . . . 0V to V+
IN
Temperature Range
ISL54503IRUZ . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified.
= 2.0V, V
= 0.8V (Note 5),
INL
INH
TEMP
(°C)
MIN
(Notes 6, 7)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
V+
2.5
3
V
Ω
ON-Resistance, r
V+ = 4.5V, I
COM
(Note 9, See Figure 5)
= 100mA, V
or V
= 0V to V+,
= 2.5V
-
2.2
ON
NO
NC
Full
25
-
-
Ω
r
Matching Between Channels, V+ = 4.5V, I
COM
= 100mA, V
or V
-
-
0.003
0.1
0.15
0.65
0.7
25
Ω
ON
Δr
NO
NC
(Note 9)
ON
Full
25
-
0.6
-
Ω
r
Flatness, r
V+ = 4.5V, I
(Notes 8, 9)
= 100mA, V
or V = 0V to V+,
NC
-
Ω
ON
FLAT(ON)
COM
NO
Full
25
-
Ω
NO or NC OFF Leakage Current, V+ = 5.5V, V
= 0.3V, 5V, V
NO
or V
NC
= 5V, 0.3V
-25
-150
-30
-300
1.5
-
nA
nA
nA
nA
COM
I
or I
NO(OFF)
NC(OFF)
Full
25
150
30
COM ON Leakage Current,
V+ = 5.5V, V
or Floating
= 0.3V, 5V, or V
NO
or V
= 0.3V, 5V,
2.8
-
COM
NC
I
COM(ON)
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
Full
300
V+ = 4.5V, V
or V
= 3.0V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
25
25
15
16
15
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
(See Figure 1, Note 9)
Turn-OFF Time, t
V+ = 4.5V, V
or V
= 3.0V, R = 50Ω, C = 35pF
NC L L
OFF
NO
(See Figure 1, Note 9)
Full
Full
Break-Before-Make Time Delay, t V+ = 5.5V, V
or V
= 3.0V, R = 50Ω, C = 35pF
NC L L
D
NO
(See Figure 3, Note 9)
Charge Injection, Q
OFF Isolation
V
= 0V, R = 0Ω, C = 1.0nF (See Figure 2)
25
25
-
-
24
70
-
-
pC
dB
G
G
L
R
= 50Ω, C = 5pF, f = 1MHz, V = 1V
COM P-P
L
L
(See Figure 4)
Total Harmonic Distortion
Total Harmonic Distortion
-3dB Bandwidth
f = 20Hz to 20kHz, V
f = 20Hz to 20kHz, V
= 2V , R = 32Ω
P-P
25
25
25
25
-
-
-
-
0.15
0.014
250
7
-
-
-
-
%
%
COM
COM
L
= 2V , R = 600Ω
P-P
L
R = 50Ω
MHz
pF
L
NO or NC OFF Capacitance,
V+ = 4.5V, f = 1MHz, V
(See Figure 7)
or V
= V
= 0V
COM
NO
NC
C
OFF
FN6551.1
August 29, 2007
3
ISL54503
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V
Unless Otherwise Specified. (Continued)
= 2.0V, V
= 0.8V (Note 5),
INL
INH
TEMP
(°C)
MIN
(Notes 6, 7)
MAX
PARAMETER
TEST CONDITIONS
V+ = 4.5V, f = 1MHz, V or V = V = 0V
COM
TYP
(Notes 6, 7) UNITS
COM ON Capacitance,
25
-
18
-
pF
NO
NC
C
(See Figure 7)
COM(ON)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
1.65
-
5.5
0.1
2.5
V
Positive Supply Current, I+
V+ = 5.5V, V = 0V or V+
IN
-
-
0.028
1.1
μA
μA
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
0.8
-
V
V
INL
Input Voltage High, V
2.4
-0.1
INH
Input Current, I
, I
INH INL
V+ = 5.5V, V = 0V or V+
IN
0.053
0.1
μA
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V
Unless Otherwise Specified
= 1.4V, V
= 0.5V (Note 5),
INH
INL
TEMP
(°C)
MIN
(Notes 6, 7)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
-
-
-
-
-
V+
3.5
4.5
0.15
0.2
1.1
1.2
V
Ω
Ω
Ω
Ω
Ω
Ω
ON-Resistance, r
ON
V+ = 2.7V, I
COM
(Note 9, See Figure 5)
= 100mA, V
or V
= 0V to V+,
= 1.5V
3.3
NO
NC
Full
25
-
r
Matching Between Channels, V+ = 2.7V, I
COM
= 100mA, V
or V
0.006
ON
Δr
NO
NC
(Note 9)
ON
Full
25
-
1
-
r
Flatness, r
V+ = 2.7V, I
(Notes 8, 9)
= 100mA, V
or V = 0V to V+,
NC
ON
FLAT(ON)
COM
NO
Full
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
(See Figure 1, Note 9)
or V
= 1.5V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
30
30
20
20
18
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
Turn-OFF Time, t
OFF
V+ = 2.7V, V
or V
= 1.5V, R = 50Ω, C = 35pF
NC L L
NO
(See Figure 1, Note 9)
Full
Full
Break-Before-Make Time Delay, t V+ = 3.0V, V
or V
= 1.5V, R = 50Ω, C = 35pF
NC L L
D
NO
(See Figure 3, Note 9)
Charge Injection, Q
OFF Isolation
V
= 0V, R = 0Ω, C = 1.0nF (See Figure 2)
25
25
-
-
16
70
-
-
pC
dB
G
G
L
R
= 50Ω, C = 5pF, f = 1MHz, V = 1V
COM P-P
L
L
(See Figure 4)
Total Harmonic Distortion
Total Harmonic Distortion
-3dB Bandwidth
f = 20Hz to 20kHz, V
f = 20Hz to 20kHz, V
= 2V , R = 32Ω
P-P
25
25
25
25
-
-
-
-
0.36
0.03
250
6
-
-
-
-
%
%
COM
L
= 2V , R = 600Ω
P-P
COM
L
Signal = 0dBm, R = 50Ω
MHz
pF
L
NO or NC OFF Capacitance,
f = 1MHz, V
or V
= V
= 0V (See Figure 7)
= 0V (See Figure 7)
NO
NC
COM
COM
C
OFF
COM ON Capacitance,
f = 1MHz, V
or V
= V
25
-
18
-
pF
NO
NC
C
COM(ON)
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ V+ = 3.6V, V = 0V or V+
25
-
-
0.013
0.7
-
-
μA
μA
IN
Full
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
Full
Full
Full
-
-
-
0.5
-
V
V
INL
Input Voltage High, V
1.4
-0.1
INH
Input Current, I
, I
INH INL
V+ = 3.6V, V = 0V or V+
IN
0.058
0.1
μA
FN6551.1
August 29, 2007
4
ISL54503
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, V
Unless Otherwise Specified
= 1V, V
= 0.4V (Note 5),
INL
INH
TEMP
(°C)
MIN
(Notes 6, 7)
MAX
PARAMETER
TEST CONDITIONS
TYP
(Notes 6, 7) UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
ANALOG
Full
25
0
-
-
6
-
V+
6.5
7
V
Ω
Ω
ON-Resistance, r
ON
V+ = 1.8V, I
= 10mA, V
or V
= 0V to V+,
NC
COM
(Note 9, See Figure 5)
NO
Full
-
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 1.8V, V
(See Figure 1, Note 9)
or V
= 1.5V, R = 50Ω, C = 35pF
25
Full
25
-
-
-
-
-
65
95
40
65
44
-
-
-
-
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
Turn-OFF Time, t
OFF
V+ = 1.8V, V
or V
= 1.5V, R = 50Ω, C = 35pF
NC L L
NO
(See Figure 1, Note 9)
Full
Full
Break-Before-Make Time Delay, t V+ = 1.8V, V
or V
= 1.5V, R = 50Ω, C = 35pF
NC L L
D
NO
(See Figure 3, Note 9)
Charge Injection, Q
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, V
V
= 0, R = 0Ω, C = 1.0nF (See Figure 2)
25
-
8.2
-
pC
G
G
L
Full
Full
-
-
-
0.4
-
V
V
INL
Input Voltage High, V
NOTES:
1
INH
5. V = input voltage to perform proper function.
IN
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
8. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
9. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V+
V+
t < 20ns
r
t < 20ns
f
C
LOGIC
INPUT
50%
0V
t
V
OFF
OUT
NO or NC
SWITCH
INPUT
COM
SWITCH
INPUT
V
NO
0V
V
OUT
IN
90%
90%
C
L
35pF
R
50Ω
LOGIC
INPUT
L
GND
SWITCH
OUTPUT
t
ON
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
R
L
----------------------------
V
= V
OUT
(NO or NC)
R
+ r
(ON)
L
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
FN6551.1
August 29, 2007
5
ISL54503
Test Circuits and Waveforms (Continued)
V+
C
SWITCH
OUTPUT
V
R
OUT
G
ΔV
OUT
COM
NO OR NC
GND
V
OUT
V
INH
ON
V
ON
G
IN
LOGIC
INPUT
C
L
OFF
V
INL
LOGIC
INPUT
Q = ΔV
x C
L
OUT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
C
NO
V+
0V
V
V
OUT
NX
COM
LOGIC
INPUT
NC
C
L
R
L
50Ω
35pF
IN
GND
LOGIC
INPUT
90%
SWITCH
OUTPUT
V
OUT
0V
t
D
C
includes fixture and stray capacitance.
L
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3B. TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
V+
V+
C
C
*
r
= V /I
1
ON
1
SIGNAL
GENERATOR
NO OR NC
NO OR NC
V
NX
V
OR V
INH
INL
IN
V
IN
1
I
0V OR V+
1
100mA
COM
COM
GND
ANALYZER
GND
R
L
*
I
= 10mA AT V+ = 1.8V
1
FIGURE 4. OFF ISOLATION TEST CIRCUIT
FIGURE 5. r
TEST CIRCUIT
ON
FN6551.1
August 29, 2007
6
ISL54503
Test Circuits and Waveforms (Continued)
V+
V+
C
C
V
NO OR NC
50Ω
NO OR NC
COM
OR V
INH
IN
INL
IN
1
IMPEDANCE
ANALYZER
SIGNAL
GENERATOR
0V OR V+
COM
GND
NC OR NO
ANALYZER
GND
R
L
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
V+
C
The ISL54503 is a bidirectional, single pole/double throw
(SPDT) analog switch that offers precise switching capability
from a single 1.8V to 5.5V supply with low ON-resistance
OPTIONAL
PROTECTION
RESISTOR
100Ω
(2.5Ω) and high speed operation (t
= 25ns, t = 15ns).
ON
OFF
NO
NC
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.8V), low power consumption (0.15µW), low leakage
currents (300nA max), and the small µTDFN package. The
COM
IN
low ON-resistance and r
flatness provide very low insertion
GND
ON
loss and distortion to application that require signal
reproduction.
External V+ Series Resistor
FIGURE 8. V+ SERIES RESISTOR FOR ENHANCED ESD AND
LATCH-UP IMMUNITY
For improved ESD and latch-up immunity Intersil
recommends adding a 100Ω resistor in series with the V+
power supply pin of the ISL54050 IC (see Figure 8).
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 9). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND.
During an overvoltage transient event (such as occurs
during system level IEC 61000 ESD testing), substrate
currents can be generated in the IC that can trigger parasitic
SCR structures to turn ON, creating a low impedance path
from the V+ power supply to ground. This will result in a
significant amount of current flow in the IC, which can
potentially create a latch-up state or permanently damage
the IC. The external V+ resistor limits the current during this
over-stress situation and has been found to prevent latch-up
or destructive damage for many overvoltage transient
events.
If these conditions cannot be guaranteed then precautions
must be implemented to prohibit the current and voltage at
the logic pin and signal pins from exceeding the maximum
ratings of the switch. The following two methods can be used
to provide additional protection to limit the current in the
event that the voltage at a signal pin or logic pin goes below
ground or above the V+ rail.
Under normal operation, the sub-microamp I
current of
DD
the IC produces an insignificant voltage drop across the
100Ω series resistor resulting in no impact to switch
operation or performance.
Logic inputs can easily be protected by adding a 1kΩ resistor in
series with the input (see Figure 9). The resistor limits the input
current below the threshold that produces permanent damage,
and the sub-microamp input current produces an insignificant
voltage drop during normal operation.
FN6551.1
August 29, 2007
7
ISL54503
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
purpose of using a low r
switch. Connecting Schottky
ON
diodes to the signal pins (as shown in Figure 9) will shunt the
fault current to the supply or to ground, thereby protecting
the switch. These Schottky diodes must be sized to handle
the expected fault current.
High-Frequency Performance
In 50Ω systems, the ISL54503 has a -3dB bandwidth of
250MHz (see Figure 17). The frequency response is very
consistent over a wide V+ range, and for varying analog
signal levels.
OPTIONAL
SCHOTTKY
DIODE
V+
An OFF switch behaves like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to output. Off isolation is
the resistance of this signal feedthrough. Figure 18 details
the high off isolation provided by the ISL54503. At 1MHz, off
isolation is about 70dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease off isolation due to the
voltage divider action of the switch OFF impedance and the
load impedance.
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
V
NX
COM
GND
OPTIONAL
SCHOTTKY
DIODE
Leakage Considerations
FIGURE 9. OVERVOLTAGE PROTECTION
ESD protection diodes are internally connected between each
analog-signal pin and both V+ and GND. One of these diodes
conducts if any analog signal exceeds V+ or GND.
Power-Supply Considerations
The ISL54503 construction is typical of most single supply
CMOS analog switches, in that they have two supply pins:
V+ and GND. V+ and GND drive the internal CMOS
switches and set their analog voltage limits. Unlike switches
with a 4V maximum supply voltage, the ISL54503 5.5V
maximum supply voltage provides plenty of room for the
10% tolerance of 3.6V supplies, as well as room for
overshoot and noise spikes.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analog-
signal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
The minimum recommended supply voltage is 1.8V but the
part will operate with a supply below 1.8V. It is important to
note that the input signal range, switching times, and
ON-resistance degrade at lower supply voltages. Refer to
the “Electrical Specifications” tables starting on page 3 and
the “Typical Performance Curves” starting on page 9 for
details.
V+ and GND also power the internal logic and level shifters.
The level shifters convert the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.5V and 1.4V)
over a supply range of 2V to 3.6V (see Figure 16). At 3.6V
the V level is about 0.95V. This is still below the 1.8V
IH
CMOS guaranteed high output minimum level of 1.4V, but
noise margin is reduced.
FN6551.1
August 29, 2007
8
ISL54503
Typical Performance Curves T = 25°C, Unless Otherwise Specified
A
3.0
2.5
2.0
1.5
1.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
I
= 100mA
COM
V+ = 2.7V
+85°C
+25°C
-40°C
V+ = 3V
V+ = 4.5V
V+ = 5V
V+ = 4.5V
= 100mA
0.5
0.0
I
COM
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
1
2
3
4
5
V
(V)
V
(V)
COM
COM
FIGURE 10. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
8
5.0
V+ = 1.8V
= 10mA
V+ = 2.7V
I
COM
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
I
= 100mA
COM
7
6
5
4
3
2
1
+85°C
+85°C
+25°C
-40°C
+25°C
-40°C
0
0.5
1.0
1.5
(V)
2.0
2.5
0
0.2 0.4 0.6 0.8
1.0 1.2 1.4 1.6 1.8
(V)
2.0
V
V
COM
COM
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
100
70
-40°C
-40°C
90
80
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
+25°C
+25°C
+85°C
+85°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
V+ (V)
V+ (V)
FIGURE 14. TURN-ON TIME vs SUPPLY VOLTAGE
FIGURE 15. TURN-OFF TIME vs SUPPLY VOLTAGE
FN6551.1
August 29, 2007
9
ISL54503
Typical Performance Curves T = 25°C, Unless Otherwise Specified (Continued)
A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-1
-2
-3
-4
-5
V+ = 1.8V TO 5.5V
= 1V
V
COM
P-P
V
INH
-6
-7
-8
V
INL
-9
-10
-11
-12
-13
1.5
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
FIGURE 17. FREQUENCY RESPONSE
-20
25
20
15
10
5
V+ = 1.8V TO 5.5V
-30
-40
-50
-60
-70
-80
0
V+ = 5V
-5
-90
V+ = 1.8V
V+ = 3.3V
-10
-15
-20
-100
-110
-120
1k
10k
100k
1M
10M
100M
1G
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
(V)
V
FREQUENCY (Hz)
COM
FIGURE 18. OFF ISOLATION
FIGURE 19. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
PROCESS:
Submicron CMOS
FN6551.1
August 29, 2007
10
ISL54503
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
L6.1.2x1.0A
A
E
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
D
SYMBOL
MIN
0.45
-
NOMINAL
MAX
0.55
0.05
NOTES
2X
0.10 C
A
A1
A3
b
0.50
-
-
-
2X
0.10 C
0.127 REF
-
TOP VIEW
0.15
0.95
1.15
0.20
0.25
1.05
1.25
5
DETAIL A
0.10 C
0.08 C
D
1.00
-
A
E
1.20
-
7X
e
0.40 BSC
-
C
A1 A3
L
0.30
0.40
0.35
0.40
0.50
-
SEATING
PLANE
SIDE VIEW
L1
N
0.45
-
4X
e
DETAIL B
6
3
-
2
5X
L
Ne
θ
3
1
3
0
12
4
L1
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
6
4
b 6X
0.10 C A B
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
0.05 C
NOTE 3
BOTTOM VIEW
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
0.1x45°
CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
A3
A1
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
DETAIL A
DETAIL B PIN 1 LEAD
1.00
1.40
0.20
0.30
0.35
0.45
0.20
0.40
10
LAND PATTERN
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6551.1
August 29, 2007
11
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