ISL54504IHZ-T_技术文档

+1.8V to +5.5V, 2.5Ω, Single SPST Analog Switches

ISL54504, ISL54505

Features

• ON-resistance (r

)

The Intersil ISL54504 and ISL54505 devices are low

ON-resistance, low voltage, bidirectional, single

pole/single throw (SPST) analog switches designed to

operate from a single +1.8V to +5.5V supply. Targeted

applications include battery powered equipment that

ON

- V

= +5.0V. . . . . . . . . . . . . . . . . . . . . 2.5Ω

= +3.0V. . . . . . . . . . . . . . . . . . . . . 4.0Ω

= +1.8V. . . . . . . . . . . . . . . . . . . . . 7.0Ω

CC

benefit from low r

flatness (0.6Ω), and fast switching speeds (t

resistance (2.5Ω), excellent r

• r flatness (+4.5V Supply) . . . . . . . . . . . . . 0.6Ω

ON

• Single supply operation . . . . . . . . +1.8V to +5.5V

• Fast switching action (+4.5V Supply)

ON

= 25ns,

ON

t

= 15ns). The digital logic input is 1.8V CMOS

OFF

compatible when using a single +3V supply.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns

. . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns

ON

Cell phones, for example, often face ASIC functionality

limitations. The number of analog input or GPIO pins

may be limited and digital geometries are not well suited

to analog switch performance. This family of parts may

be used to switch in additional functionality while

reducing ASIC design risk. The ISL54504 and ISL54505

are offered in a 6 Ld 1.2mmx1.0mmx0.4mm pitch

µTDFN package and a 6 Ld SOT-23 package, alleviating

board space limitations.

OFF

• ESD HBM rating. . . . . . . . . . . . . . . . . . . . . . . 6kV

• 1.8V CMOS logic compatible (+3V supply)

• Available in 6 Ld µTDFN and 6Ld SOT-23 Packages

• Pb-free available (RoHS compliant)

Applications

• Battery powered, handheld, and portable equipment

- Cellular/mobile phones

The ISL54504 has one normally open (NO) switch and

ISL54505 has one normally closed (NC) switch.

- Pagers

- Laptops, notebooks, palmtops

TABLE 1. FEATURES AT A GLANCE

ISL54504

1

ISL54505

1

• Portable Test and Measurement

• Medical Equipment

• Audio and video switching

Number of Switches

SW

NO

NC

1.8V r

ON

6Ω

Related Literature

1.8V t

/t

ON OFF

65ns/40ns

4Ω

65ns/40ns

4Ω

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

3V r

ON

3V t

/t

ON OFF

30ns/20ns

2.5Ω

30ns/20ns

2.5Ω

5V r

ON

5V t

/t

25ns/15ns

ON OFF

Package

6 Ld µTDFN, 6 Ld SOT-23

October 23, 2009

FN6552.2

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL54504, ISL54505

Ordering Information

PART NUMBER

(Notes 1, 4)

PART

MARKING

TEMP. RANGE

PACKAGE

(Tape and Reel) (Pb-Free)

(°C)

PKG. DWG. #

L6.1.2x1.0A

MDP0038

ISL54504IRUZ-T (Note 2)

ISL54504IHZ-T (Note 3)

ISL54505IRUZ-T (Note 2)

ISL54505IHZ-T (Note 3)

NOTES:

4

-40 to +85

6 Ld μTDFN

4504

5

6 Ld SOT-23

6 Ld μTDFN

L6.1.2x1.0A

MDP0038

4505

6 Ld SOT-23

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach

materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free

soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the

Pb-free requirements of IPC/JEDEC J STD-020.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach

materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), please see device information page for ISL54504, ISL54505. For more information on

MSL please see techbrief TB363.

Pin Configurations (Note 5)

ISL54504

(6 LD μTDFN)

TOP VIEW

ISL54504

(6 LD SOT-23)

TOP VIEW

1

2

3

6

5

4

IN

NO

GND

N.C.

IN

1

2

3

6

GND

COM

V+

5

4

NO

COM

ISL54505

(6 LD μTDFN)

(6 LD SOT-23)

TOP VIEW

1

2

3

6

5

4

IN

N.C.

GND

NC

IN

1

2

3

6

GND

COM

V+

5

4

N.C.

COM

NC

NOTE:

5. Switches Shown for Logic “0” Input.

Truth Table

Pin Descriptions

LOGIC

ISL54504

ISL54505

PIN NAME

FUNCTION

System Power Supply Input (+1.8V to +5.5V)

Ground Connection

0

1

Off

On

Off

V+

GND

IN

NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.

Digital Control Input

COM

NO

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

No Connect

NC

N.C.

FN6552.2

October 23, 2009

2

ISL54504, ISL54505

Absolute Maximum Ratings

Thermal Information

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6.5V

Input Voltages

NO, NC, IN (Note 4) . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Output Voltages

COM (Note 4) . . . . . . . . . . . . . . . . -0.5V to ((V+) + 0.5V)

Continuous Current NO, NC, or COM. . . . . . . . . . . . ±300mA

Peak Current NO, NC, or COM

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±600mA

ESD Rating

Thermal Resistance (Typical)

θ

(°C/W) θ (°C/W)

JC

JA

6 Ld µTDFN Package (Notes 7, 9). .

6 Ld SOT-23 Package (Note 8, 10) .

Maximum Junction Temperature (Plastic Package). . +150°C

Maximum Storage Temperature Range. . . . . -65°C to +150°C

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

239.2

260

111.6

120

Operating Conditions

V+ (Positive DC Supply Voltage). . . . . . . . . . . 1.8V to 5.5V

Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . 0V to V+

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . >6kV

Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . >300V

Charged Device Model . . . . . . . . . . . . . . . . . . . . .>2.2kV

V

(Digital Logic Input Voltage (IN) . . . . . . . . . . . 0V to V+

IN

Temperature Range. . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact

product reliability and result in failures not covered by warranty.

NOTES:

6. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum

current ratings.

7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”

JA

features. See Tech Brief TB379.

8. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief

JA

TB379 for details.

9. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

10. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

INH

(Note 11), Unless Otherwise Specified. Boldface limits apply over the oper-

= 2.0V, V

= 0.8V

INL

ating temperature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 4.5V, I

= 100mA, V

or

= 0V to V+, (Note 15, See Figure 4)

25

Full

25

-

2.2

-

2.5

3

Ω

ON

COM

NO

V

NC

-

r

Flatness, r

V+ = 4.5V, I

= 100mA, V

NO

or

0.6

-

0.65

0.7

25

Ω

ON

FLAT(ON)

COM

= 0V to V+, (Notes 14, 15)

V

NC

Full

25

-

Ω

NO or NC OFF Leakage

Current, I or

V+ = 5.5V, V

= 0.3V, 5V, V

NO

or

-25

-150

1.5

-

nA

COM

= 5V, 0.3V

NC

V

NO(OFF)

Full

150

I

NC(OFF)

COM ON Leakage

Current, I

V+ = 5.5V, V

COM

= 0.3V, 5V, or V

or

25

-30

2.8

-

30

nA

NO

V

= 0.3V, 5V, or Floating

COM(ON)

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 4.5V, V

NC

Full

-300

300

or V

NC

= 3.0V, R = 50Ω,

25

Full

25

-

25

15

16

15

-

ns

ON

NO

L

C = 35pF (See Figure 1, Note 15)

L

Turn-OFF Time, t

OFF

V+ = 4.5V, V

NO

or V = 3.0V, R = 50Ω,

NC L

C = 35pF (See Figure 1, Note 15)

L

Full

Break-Before-Make Time V+ = 5.5V, V

NO

or V = 3.0V, R = 50Ω,

NC L

Delay, t

C = 35pF (See Figure 3, Note 15)

D

L

Charge Injection, Q

V

= 0V, R = 0Ω, C = 1.0nF

25

-

24

70

-

pC

dB

G

L

(See Figure 2)

OFF Isolation

R = 50Ω, C = 5pF, f = 1MHz,

L

V

= 1V

(See Figure 3)

COM

P-P

FN6552.2

October 23, 2009

3

ISL54504, ISL54505

Electrical Specifications - 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, V

(Note 11), Unless Otherwise Specified. Boldface limits apply over the oper-

= 2.0V, V

= 0.8V

INL

INH

ating temperature range, -40°C to +85°C. (Continued)

TEMP

MIN

MAX

PARAMETER

Total Harmonic

Distortion

TEST CONDITIONS

(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS

f = 20Hz to 20kHz, V

= 2V

,

P-P

25

-

0.15

-

%

COM

R = 32Ω

L

Total Harmonic

Distortion

f = 20Hz to 20kHz, V

R = 600Ω

= 2V

,

0.014

COM

P-P

L

-3dB Bandwidth

NO or NC OFF

Signal = 0dBm, R = 50Ω

25

-

250

7

-

MHz

pF

L

V+ = 4.5V, f = 1MHz, V

or

= 0V (See Figure 5)

NO

Capacitance, C

V

= V

NC COM

OFF

COM ON Capacitance,

V+ = 4.5V, f = 1MHz, V

or

25

-

18

-

pF

NO

= 0V (See Figure 5)

C

V

= V

COM(ON)

NC COM

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

25

1.8

-

5.5

0.1

2.5

V

Positive Supply Current, V+ = 5.5V, V = 0V or V+

IN

I+

-

0.028

1.1

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.8

-

V

INL

Input Voltage High, V

2.4

-0.1

INH

, I

Input Current, I

V+ = 5.5V, V = 0V or V+

IN

0.053

0.1

μA

INH INL

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

INH

(Note 11), Unless Otherwise Specified. Boldface limits apply over the oper-

ating temperature range, -40°C to +85°C.

= 1.4V, V

= 0.5V

INL

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

µTDFN

V+ = 2.7V, I

= 100mA, V

or

= 0V to V+, (Note 15, See Figure 4)

25

Full

25

-

3.3

-

3.5

4.5

3.6

4.5

1.1

1.2

1.3

Ω

ON

COM

NO

V

NC

ON-Resistance, r

SOT-23

V+ = 2.7V, I

= 100mA, V

or

= 0V to V+, (Note 15, See Figure 4)

3.3

-

ON

COM

NO

V

NC

Full

25

r

Flatness, r

V+ = 2.7V, I

COM

= 100mA, V

NO

or

1

ON

µTDFN

FLAT(ON)

V

= 0V to V+, (Notes 7, 15)

NC

Full

25

-

r

Flatness, r

V+ = 2.7V, I

COM

= 100mA, V

NO

or

1

ON

SOT-23

V

= 0V to V+, (Notes 7, 15)

NC

Full

-

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 2.7V, V

or V

= 1.5V, R = 50Ω,

25

Full

25

-

30

20

16

-70

-

ns

pC

dB

ON

NO

NC

L

C = 35pF (See Figure 1, Note 15)

L

Turn-OFF Time, t

OFF

V+ = 2.7V, V

NO

L

or V

= 1.5V, R = 50Ω,

L

NC

C = 35pF (See Figure 1, Note 15)

Full

25

Charge Injection, Q

OFF Isolation

V = 0V, R = 0Ω,C = 1.0nF (See Figure 2)

G G L

R = 50Ω, C = 5pF, f = 1MHz,

25

L

P-P

V

= 1V

(See Figure 3)

COM

Total Harmonic

Distortion

f = 20Hz to 20kHz, V

COM

= 2V , R = 32Ω

P-P

25

-

0.36

0.03

-

%

L

Total Harmonic

Distortion

f = 20Hz to 20kHz, V

R = 600Ω

= 2V ,

P-P

COM

L

FN6552.2

October 23, 2009

4

ISL54504, ISL54505

Electrical Specifications - 3V Supply

Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, V

(Note 11), Unless Otherwise Specified. Boldface limits apply over the oper-

ating temperature range, -40°C to +85°C. (Continued)

= 1.4V, V = 0.5V

INL

INH

TEMP

MIN

MAX

PARAMETER

-3dB Bandwidth

NO or NC OFF

TEST CONDITIONS

Signal = 0dBm, R = 50Ω

(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS

25

-

250

6

-

MHz

pF

L

f = 1MHz, V

or V

= V

= 0V

NO

(See Figure 5)

NC

COM

Capacitance, C

OFF

COM OFF Capacitance,

f = 1MHz, V

25

-

15

18

-

pF

NO

(See Figure 5)

C

COM(OFF)

COM ON Capacitance,

f = 1MHz, V

NO

(See Figure 5)

C

COM(ON)

POWER SUPPLY CHARACTERISTICS

Positive Supply Current, V+ = 3.6V, V = 0V or V+

IN

I+

25

-

0.013

0.7

-

μA

Full

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

INL

Full

-

0.5

-

V

Input Voltage High, V

INH

1.4

-0.1

Input Current, I

, I

V+ = 3.6V, V = 0V or V+

IN

0.058

0.1

μA

INH INL

Electrical Specifications - 1.8V Supply

Test Conditions: V+ = +1.8V, GND = 0V, V

INH

Unless Otherwise Specified. Boldface limits apply over the operating tem-

= 1V, V

= 0.4V (Note 11),

INL

perature range, -40°C to +85°C.

TEMP

MIN

MAX

PARAMETER

TEST CONDITIONS

(°C) (Notes 12, 13) TYP (Notes 12, 13) UNITS

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range,

Full

0

-

V+

V

ANALOG

ON-Resistance, r

V+ = 1.8V, I

= 10mA, V

or

25

-

6

-

6.5

Ω

ON

COM NO

V

= 0V to V+ (Note 15, See Figure 4)

NC

DYNAMIC CHARACTERISTICS

Turn-ON Time, t V+ = 1.8V, V

Full

7

or V

NC

= 1.5V, R = 50Ω,

25

Full

25

-

65

95

40

65

8.2

-

ns

pC

ON

NO

L

C = 35pF (See Figure 1, Note 15)

L

Turn-OFF Time, t

OFF

V+ = 1.8V, V

NO

or V = 1.5V, R = 50Ω,

NC L

C = 35pF (See Figure 1, Note 15)

L

Full

25

Charge Injection, Q

V

= V+/2, R = 0Ω, C = 1.0nF

G G L

(See Figure 2)

DIGITAL INPUT CHARACTERISTICS

Input Voltage Low, V

Full

-

0.4

V

INL

Input Voltage High, V

NOTES:

1

-

INH

11. V = input voltage to perform proper function.

IN

12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this

data sheet.

13. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.

14. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal

range.

15. Limits established by characterization and are not production tested.

FN6552.2

October 23, 2009

5

ISL54504, ISL54505

Test Circuits and Waveforms

V+

t

< 20ns

r

f

C

LOGIC

INPUT

50%

0V

t

V

L

OFF

OUT

NO OR NC

SWITCH

INPUT

COM

SWITCH

INPUT

V

NO

0V

V

OUT

90%

IN

90%

C

R

LOGIC

INPUT

L

GND

SWITCH

OUTPUT

35pF

50Ω

t

ON

Logic input waveform is inverted for switches that have the

opposite logic sense.

Repeat test for all switches. C includes fixture and stray

L

capacitance.

R

L

----------------------------

V

= V

OUT

(NO or NC)

R

+ r

(ON)

L

FIGURE 1A. MEASUREMENT POINTS

FIGURE 1B. TEST CIRCUIT

FIGURE 1. SWITCHING TIMES

V+

C

SWITCH

OUTPUT

ΔV

V

R

OUT

G

COM

NO OR NC

GND

V

OUT

V

INH

ON

LOGIC

INPUT

V

G

IN

OFF

C

L

V

INL

LOGIC

INPUT

Q = ΔV

x C

L

OUT

FIGURE 2A. MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

FIGURE 2B. TEST CIRCUIT

V+

C

V+

*

r

= V /I

1 1

ON

C

NO OR NC

SIGNAL

GENERATOR

NO OR NC

V

NX

V

OR V

INH

INL

IN

V

1

I

1

IN

0V OR V+

100mA

COM

GND

COM

ANALYZER

GND

R

L

*

I

= 10mA AT V+ = 1.8V

1

FIGURE 3. OFF ISOLATION TEST CIRCUIT

FIGURE 4. r TEST CIRCUIT

ON

FN6552.2

October 23, 2009

6

ISL54504, ISL54505

Test Circuits and Waveforms(Continued)

V+

C

NO OR NC

V

OR V

IN

INL

INH

IMPEDANCE

ANALYZER

COM

GND

FIGURE 5. CAPACITANCE TEST CIRCUIT

Detailed Description

V+

C

The ISL54504 and ISL54505 are bidirectional, single

pole/single throw (SPST) analog switches. They offer

precise switching capability from a single 1.8V to 5.5V

supply with low ON-resistance (2.5Ω) and high speed

OPTIONAL

PROTECTION

RESISTOR

100Ω

operation (t

= 25ns, t = 15ns). The devices are

NO

NC

ON

OFF

COM

especially well suited for portable battery powered

equipment due to their low operating supply voltage

(1.8V), low power consumption (0.15µW), low

leakage currents (300nA max) and tiny µTDFN and

SOT-23 packages.

IN

GND

The ISL54504 is a single normally open (NO) SPST

analog switch. The ISL54505 is a single normally

closed (NC) SPST analog switch.

FIGURE 6. V+ SERIES RESISTOR FOR ENHANCED

ESD AND LATCH-UP IMMUNITY

External V+ Series Resistor

For improved ESD and latch-up immunity, Intersil

recommends adding a 100Ω resistor in series with the

V+ power supply pin of the ISL54504, ISL54505 IC

(see Figure 6).

Supply Sequencing And Overvoltage

Protection

With any CMOS device, proper power supply

sequencing is required to protect the device from

excessive input currents, which might permanently

damage the IC. All I/O pins contain ESD protection

diodes from the pin to V+ and to GND (see Figure 7).

To prevent forward biasing these diodes, V+ must be

applied before any input signals, and the input signal

voltages must remain between V+ and GND.

During an overvoltage transient event (such as occurs

during system level IEC 61000 ESD testing), substrate

currents can be generated in the IC that can trigger

parasitic SCR structures to turn ON, creating a low

impedance path from the V+ power supply to ground.

This will result in a significant amount of current flow in

the IC, which can potentially create a latch-up state or

permanently damage the IC. The external V+ resistor

limits the current during this over-stress situation and

has been found to prevent latch-up or destructive

damage for many overvoltage transient events.

If these conditions cannot be guaranteed then

precautions must be implemented to prohibit the

current and voltage at the logic pin and signal pins

from exceeding the maximum ratings of the switch.

The following two methods can be used to provide

additional protection to limit the current in the event

that the voltage at a signal pin or logic pin goes below

ground or above the V+ rail.

Under normal operation the sub-microamp I

DD

current

of the IC produces an insignificant voltage drop across

the 100Ω series resistor resulting in no impact to

switch operation or performance.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 7). The

resistor limits the input current below the threshold

that produces permanent damage and the sub-

FN6552.2

October 23, 2009

7

ISL54504, ISL54505

microamp input current produces an insignificant

voltage drop during normal operation.

Logic-Level Thresholds

This switch family is 1.8V CMOS compatible (0.5V and

1.4V) over a supply range of 2V to 3.6V (see

This method is not acceptable for the signal path

inputs. Adding a series resistor to the switch input

Figure 14). At 3.6V the V level is about 0.95V. This is

IH

still below the 1.8V CMOS guaranteed high output

minimum level of 1.4V, but noise margin is reduced.

defeats the purpose of using a low r

switch.

ON

Connecting Schottky diodes to the signal pins (as

shown in Figure 7) will shunt the fault current to the

supply or to ground, thereby protecting the switch.

These Schottky diodes must be sized to handle the

expected fault current.

The digital input stages draw supply current whenever

the digital input voltage is not at one of the supply

rails. Driving the digital input signals from GND to V+

with a fast transition time minimizes power dissipation.

High-Frequency Performance

OPTIONAL

SCHOTTKY

DIODE

In 50Ω systems, the ISL54504/ISL54505 has a -3dB

bandwidth of 250MHz (see Figure 15). The frequency

response is very consistent over a wide V+ range and

for varying analog signal levels.

V+

OPTIONAL

PROTECTION

RESISTOR

IN

V

X

An OFF switch behaves like a capacitor and passes

higher frequencies with less attenuation, resulting in

signal feedthrough from a switch’s input to output. Off

isolation is the resistance of this signal feedthrough.

Figure 16 details the high off isolation provided by the

ISL54504, ISL54505. At 1MHz, off isolation is about

70dB in 50Ω systems, decreasing approximately 20dB

per decade as frequency increases. Higher load

impedances decrease off isolation due to the voltage

divider action of the switch OFF impedance and the

load impedance.

V

NX

COM

GND

OPTIONAL

SCHOTTKY

DIODE

FIGURE 7. OVERVOLTAGE PROTECTION

Power-Supply Considerations

Leakage Considerations

The ISL54504, ISL54505 construction is typical of

most single supply CMOS analog switches in that they

have two supply pins: V+ and GND. V+ and GND drive

the internal CMOS switches and set their analog

voltage limits. Unlike switches with a 4V maximum

supply voltage, the ISL54504, ISL54505 5.5V

maximum supply voltage provides plenty of room for

the 10% tolerance of 3.6V supplies, as well as room for

overshoot and noise spikes.

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and GND.

One of these diodes conducts if any analog signal

exceeds V+ or GND.

Virtually all the analog leakage current comes from the

ESD diodes to V+ or GND. Although the ESD diodes on

a given signal pin are identical and therefore fairly well

balanced, they are reverse biased differently. Each is

biased by either V+ or GND and the analog signal. This

means their leakages will vary as the signal varies. The

difference in the two diode leakages to the V+ and

GND pins constitutes the analog-signal-path leakage

current. All analog leakage current flows between each

pin and one of the supply terminals, not to the other

switch terminal. This is why both sides of a given

switch can show leakage currents of the same or

opposite polarity. There is no connection between the

analog signal paths and V+ or GND.

The minimum recommended supply voltage is 1.8V but

the part will operate with a supply below 1.8V. It is

important to note that the input signal range, switching

times, and ON-resistance degrade at lower supply

voltages. Refer to the “Electrical Specifications” tables

starting on page 3 and the “Typical Performance

Curves” starting on page 9 for details.

V+ and GND also power the internal logic and level

shiftier. The level shiftier converts the input logic levels

to switched V+ and GND signals to drive the analog

switch gate terminals.

This family of switches cannot be operated with bipolar

supplies because the input switching point becomes

negative in this configuration.

FN6552.2

October 23, 2009

8

ISL54504, ISL54505

Typical Performance Curves T = +25°C, Unless Otherwise Specified.

A

3.0

2.5

2.0

1.5

1.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

I

= 100mA

COM

V+ = 2.7V

+85°C

+25°C

-40°C

V+ = 3V

V+ = 4.5V

V+ = 5V

V+ = 4.5V

= 100mA

0.5

0.0

I

COM

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

0

1

2

3

4

5

V

(V)

V

COM

FIGURE 8. ON-RESISTANCE vs SUPPLY VOLTAGE vs

SWITCH VOLTAGE

FIGURE 9. ON-RESISTANCE vs SWITCH VOLTAGE

5.0

8

V+ = 2.7V

V+ = 1.8V

I

= 10mA

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

I

= 100mA

COM

7

6

5

4

3

2

1

+85°C

+25°C

-40°C

+25°C

-40°C

0

0.5

1.0

1.5

(V)

2.0

2.5

0

0.2

0.4

0.6

0.8

1.0 1.2

(V)

1.4

1.6

1.8

2.0

V

COM

FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE

FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE

100

70

-40°C

90

60

50

80

70

+25°C

40

60

50

30

+85°C

40

+85°C

20

30

20

10

0

10

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V+ (V)

FIGURE 12. TURN-ON TIME vs SUPPLY VOLTAGE

FIGURE 13. TURN-OFF TIME vs SUPPLY VOLTAGE

FN6552.2

October 23, 2009

9

ISL54504, ISL54505

Typical Performance Curves T = +25°C, Unless Otherwise Specified. (Continued)

A

1.4

0

-1

-2

-3

-4

-5

V+ = 1.8V TO 5.5V

= 1V

1.2

1.0

0.8

0.6

0.4

0.2

V

COM

P-P

V

INH

-6

-7

-8

V

INL

-9

-10

-11

-12

-13

1.5

2.0

2.5

3.0

3.5

V+ (V)

4.0

4.5

5.0

5.5

100k

1M

10M

100M

1G

FREQUENCY (Hz)

FIGURE 14. DIGITAL SWITCHING POINT vs SUPPLY

VOLTAGE

FIGURE 15. FREQUENCY RESPONSE

25

20

15

10

5

-20

V+ = 1.8V TO 5.5V

-30

-40

-50

-60

-70

-80

0

V+ = 5V

-5

-90

V+ = 1.8V

V+ = 3.3V

-10

-15

-20

-100

-110

-120

0.0 0.5

1.0 1.5

2.0 2.5

3.0

3.5

4.0

4.5

5.0

1k

10k

100k

1M

10M

100M

1G

V

(V)

COM

FREQUENCY (Hz)

FIGURE 17. CHARGE INJECTION vs SWITCH VOLTAGE

FIGURE 16. OFF ISOLATION

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

GND

TRANSISTOR COUNT:

PROCESS:

Submicron CMOS

FN6552.2

October 23, 2009

10

ISL54504, ISL54505

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

L6.1.2x1.0A

A

E

B

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

MILLIMETERS

PIN 1

REFERENCE

D

SYMBOL

MIN

0.45

-

NOMINAL

MAX

0.55

0.05

NOTES

2X

0.10 C

A

A1

A3

b

0.50

-

2X

0.10 C

0.127 REF

-

TOP VIEW

0.15

0.95

1.15

0.20

0.25

1.05

1.25

5

DETAIL A

0.10 C

0.08 C

D

1.00

-

A

E

1.20

-

7X

e

0.40 BSC

-

C

A1 A3

L

0.30

0.40

0.35

0.40

0.50

-

SEATING

PLANE

SIDE VIEW

L1

N

0.45

-

4X

e

DETAIL B

6

3

-

2

5X

L

Ne

θ

3

1

3

0

12

4

L1

Rev. 2 8/06

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

6

4

b 6X

0.10 C A B

3. Ne refers to the number of terminals on E side.

4. All dimensions are in millimeters. Angles are in degrees.

0.05 C

NOTE 3

BOTTOM VIEW

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

0.1x45°

CHAMFER

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Maximum package warpage is 0.05mm.

8. Maximum allowable burrs is 0.076mm in all directions.

9. JEDEC Reference MO-255.

A3

A1

10. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

DETAIL A

DETAIL B PIN 1 LEAD

1.00

1.40

0.20

0.30

0.35

0.45

0.20

0.40

10

LAND PATTERN

FN6552.2

October 23, 2009

11

ISL54504, ISL54505

SOT-23 Package Family

MDP0038

e1

D

SOT-23 PACKAGE FAMILY

A

MILLIMETERS

SOT23-5

6

4

N

SYMBOL

SOT23-6

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

6

TOLERANCE

MAX

A

A1

A2

b

1.45

0.10

1.14

0.40

0.14

2.90

2.80

1.60

0.95

1.90

0.45

0.60

5

±0.05

E1

E

±0.15

2

3

±0.05

0.15

2X

C

D

c

±0.06

1

2

3

0.20

2X

C

D

Basic

5

e

E

Basic

E1

e

Basic

0.20

C

A-B

D

M

B

b

NX

Basic

e1

L

Basic

±0.10

L1

N

Reference

Rev. F 2/07

0.15

2X

C

A-B

1

3

D

NOTES:

C

1. Plastic or metal protrusions of 0.25mm maximum per side are not

included.

A2

SEATING

PLANE

2. Plastic interlead protrusions of 0.25mm maximum per side are not

included.

A1

0.10

NX

C

3. This dimension is measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

5. Index area - Pin #1 I.D. will be located within the indicated zone

(SOT23-6 only).

6. SOT23-5 version has no center lead (shown as a dashed line).

(L1)

H

A

GAUGE

PLANE

0.25

c

+3°

-0°

L

0°

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6552.2

October 23, 2009

12


型号：	ISL54504IHZ-T
厂家：	Intersil
描述：	+1.8V to +5.5V, 2.5OHM, Single SPST Analog Switches + 1.8V至+ 5.5V ， 2.5OHM ，单SPST模拟开关开关光电二极管
文件：	总12页 (文件大小：329K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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