ISL55002IB-T13 [INTERSIL]
High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifiers; 高电源电压220MHz的单位增益稳定运算放大器
| 型号： | ISL55002IB-T13 |
| 厂家： | 
Intersil |
| 描述： | High Supply Voltage 220MHz Unity-Gain Stable Operational Amplifiers |
| 文件： | 总14页 (文件大小：697K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL55002, ISL55004
®
Data Sheet
July 15, 2005
FN7497.1
High Supply Voltage 220MHz Unity-Gain
Stable Operational Amplifiers
Features
• 220MHz -3dB bandwidth
The ISL55002 and ISL55004 are high speed, low power, low
cost monolithic operational amplifiers. The ISL55002 and
ISL55004 are unity-gain stable and feature a 300V/µs slew
rate and 220MHz bandwidth while requiring only 9mA of
supply current.
• Unity-gain stable
• Low supply current: 9mA @ V = ±15V
S
• Wide supply range: ±2.5V to ±15V dual-supply and 5V to
30V single-supply
The power supply operating range of the ISL55002 and
ISL55004 is from ±15V down to ±2.5V. For single-supply
operation, the ISL55002 and ISL55004 operate from 30V
down to 5V.
• High slew rate: 300V/µs
• Fast settling: 75ns to 0.1% for a 10V step
• Wide output voltage swing: -12.75V/+13.6V with V =
S
±15V, R = 1kΩ
L
The ISL55002 and ISL55004 also feature an extremely wide
• Low cost, enhanced replacement for the AD847 and
LM6361
output voltage swing of -12.75V/+13.4V with V = ±15V and
S
R = 1kΩ.
L
• Pb-free plus anneal available (RoHS compliant)
At a gain of +1, the ISL55002 and ISL55004 have a -3dB
bandwidth of 220MHz with a phase margin of 50°. Because
of its conventional voltage-feedback topology, the ISL55002
and ISL55004 allow the use of reactive or non-linear
elements in its feedback network. This versatility combined
with low cost and 140mA of output-current drive makes the
ISL55002 and ISL55004 an ideal choice for price-sensitive
applications requiring low power and high speed.
Applications
• Video amplifiers
• Single-supply amplifiers
• Active filters/integrators
• High speed sample-and-hold
• High speed signal processing
• ADC/DAC buffers
The ISL55002 is available in an 8-pin SO package and the
ISL55004 in a 14-pin SO (0.150”) package. All are specified
for operation over the full -40°C to +85°C temperature range.
• Pulse/RF amplifiers
• Pin diode receivers
• Log amplifiers
• Photo multiplier amplifiers
• Difference amplifiers
Pinouts
ISL55002
(8-PIN SO)
TOP VIEW
ISL55004
[14-PIN SO (0.150”)]
TOP VIEW
OUT
IN1-
IN1+
VS-
1
2
3
4
8
7
6
5
VS+
OUT1
IN1-
1
2
3
4
5
6
7
14 OUT4
13 IN4-
12 IN4+
11 VS-
OUT2
IN2-
-
+
-
-
+
+
+
+
-
-
IN1+
VS+
+
-
IN2+
IN2+
IN2-
10 IN3+
9
8
IN3-
OUT2
OUT3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL55002, ISL55004
Ordering Information
TAPE &
REEL
PART NUMBER
ISL55002IB
PACKAGE
8-Pin SO
8-Pin SO
8-Pin SO
PKG. DWG. #
-
7”
13”
-
M8.15
M8.15
M8.15
M8.15
ISL55002IB-T7
ISL55002IB-T13
ISL55002IBZ
(See Note)
8-Pin SO
(Pb-Free)
ISL55002IBZ-T7
(See Note)
8-Pin SO
(Pb-Free)
7”
13”
-
M8.15
M8.15
ISL55002IBZ-T13
(See Note)
8-Pin SO
(Pb-Free)
ISL55004IB
14-Pin SO
(0.150”)
M14.15
M14.15
M14.15
M14.15
ISL55004IB-T7
ISL55004IB-T13
14-Pin SO
(0.150”)
7”
13”
-
14-Pin SO
(0.150”)
ISL55004IBZ
(See Note)
14-Pin SO
(0.150”)
(Pb-Free)
ISL55004IBZ-T7
(See Note)
14-Pin SO
(0.150”)
7”
M14.15
M14.15
(Pb-Free)
ISL55004IBZ-T13
(See Note)
14-Pin SO
(0.150”)
(Pb-Free)
13”
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
FN7497.1
2
July 15, 2005
ISL55002, ISL55004
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage (V ). . . . . . . . . . . . . . . . . . . . . . . . . . ±16.5V or 33V
Power Dissipation (P ) . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
D
S
IN)
Input Voltage (V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±V
Operating Temperature Range (T ). . . . . . . . . . . . . .-40°C to +85°C
A
S
Differential Input Voltage (dV ). . . . . . . . . . . . . . . . . . . . . . . . .±10V
IN
Operating Junction Temperature (T ) . . . . . . . . . . . . . . . . . . +150°C
J
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA
Storage Temperature (T ) . . . . . . . . . . . . . . . . . . .-65°C to +150°C
ST
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
V = ±15V, R = 1kΩ, T = 25°C, unless otherwise specified.
S L A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
mV
µV/°C
µA
V
Input Offset Voltage
V
= ±15V
1.2
5
OS
S
TCV
Average Offset Voltage Drift
Input Bias Current
OS
I
I
V
V
= ±15V
= ±15V
0.6
0.2
3.5
2
B
S
S
Input Offset Current
µA
OS
TCI
Average Offset Current Drift (Note 1)
Open-loop Gain
TBD
21000
100
90
nA/°C
V/V
dB
OS
A
V
V
V
V
= ±15V, V
= ±10V, R = 1kΩ
12000
75
VOL
S
OUT
L
PSRR
CMRR
CMIR
Power Supply Rejection Ratio
Common-mode Rejection Ratio
Common-mode Input Range
Output Voltage Swing
= ±5V to ±15V
S
= ±10V, V
= 0V
OUT
75
dB
CM
= ±15V
13
V
S
V
V +, R = 1kΩ
13.3
-12.6
9.6
13.4
-12.75
10.7
-8.2
140
9
V/V
V/V
V/V
V/V
mA
mA
MΩ
pF
OUT
O
L
V -, R = 1kΩ
O
L
V +, R = 150Ω
O
L
V -, R = 150Ω
-6.5
80
O
L
I
I
Output Short Circuit Current
Supply Current (per amplifier)
Input Resistance
T
= 25°C
SC
A
V
= ±15V, no load
S
9.5
S
R
C
R
2.0
3.2
IN
Input Capacitance
A
= +1 @10MHz
= +1
V
1
IN
V
Output Resistance
A
50
mΩ
V
OUT
PSOR
Power Supply Operating Range
Dual supply
±2.25
4.5
±15
30
Single supply
V
NOTE:
1. Measured from T
MIN
to T .
MAX
AC Electrical Specifications
V
= ±15V, A = +1, R = 1kΩ unless otherwise specified.
S
V
L
PARAMETER
DESCRIPTION
CONDITION
= ±15V, A = +1
MIN
TYP
220
55
MAX
UNIT
MHz
MHz
MHz
MHz
MHz
°
BW
-3dB Bandwidth (V
= 0.4V
)
V
V
V
V
V
OUT
PP
S
S
S
S
S
V
= ±15V, A = -1
V
= ±15V, A = +2
53
V
= ±15V, A = +5
V
17
GBWP
PM
Gain Bandwidth Product
Phase Margin
= ±15V
70
R
= 1kΩ, C = 5pF
55
L
L
FN7497.1
3
July 15, 2005
ISL55002, ISL55004
AC Electrical Specifications
V
= ±15V, A = +1, R = 1kΩ unless otherwise specified. (Continued)
S
V
L
PARAMETER
SR
FPBW
DESCRIPTION
Slew Rate (Note 1)
Full-power Bandwidth (Note 2)
CONDITION
MIN
TYP
300
9.5
MAX
UNIT
V/µs
MHz
ns
260
V
V
= ±15V
S
S
t
Settling to +0.1% (A = +1)
V
= ±15V, 10V step
75
S
dG
dP
Differential Gain (Note 3)
Differential Phase
NTSC/PAL
NTSC/PAL
10kHz
0.01
0.05
12
%
°
eN
Input Noise Voltage
Input Noise Current
nV/√Hz
pA/√Hz
iN
10kHz
1.5
NOTES:
1. Slew rate is measured on rising edge.
2. For V = ±15V, V = 10V , for V = ±5V, V
= 5V . Full-power bandwidth is based on slew rate measurement using FPBW = SR / (2π
PP
S
OUT
PP
S
OUT
* V
).
PEAK
3. Video performance measured at V = ±15V, A = +2 with two times normal video level across R = 150Ω. This corresponds to standard video
S
V
L
levels across a back-terminated 75Ω load. For other values or R , see curves.
L
Typical Performance Curves
FIGURE 1. OPEN-LOOP GAIN vs FREQUENCY
FIGURE 2. OPEN-LOOP PHASE vs FREQUENCY
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS NON-
INVERTING GAIN SETTINGS
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS INVERTING
GAIN SETTINGS
FN7497.1
4
July 15, 2005
ISL55002, ISL55004
Typical Performance Curves
FIGURE 5. PHASE vs FREQUENCY FOR VARIOUS NON-
INVERTING GAIN SETTINGS
FIGURE 6. PHASE vs FREQUENCY FOR VARIOUS
INVERTING GAIN SETTINGS
350
A =+2
V
R =500Ω
F
R =500Ω
L
300
C =5pF
L
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
250
200
150
100
0
2
4
6
8
10 12 14 16 18
SUPPLY VOLTAGES (±V)
FIGURE 7. GAIN BANDWIDTH PRODUCT vs SUPPLY
FIGURE 8. SLEW RATE vs SUPPLY
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS R
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS R
LOAD
LOAD
(A = +1)
(A = +2)
V
V
FN7497.1
July 15, 2005
5
ISL55002, ISL55004
Typical Performance Curves
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS C
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS C
LOAD
LOAD
(A = +1)
V
(A = +2)
V
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS R
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS R
FEEDBACK
FEEDBACK
(A = +1)
(A = +2)
V
V
5
3
A =+1
V
R =0Ω
F
R =500Ω
L
V =±2.5V
S
C =5pF
L
V =±5V
S
1
V =±15V
S
-1
-3
-5
V =±10V
S
100K
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS INVERTING
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS SUPPLY
SETTINGS
INPUT CAPACITANCE (C
)
IN
FN7497.1
July 15, 2005
6
ISL55002, ISL55004
Typical Performance Curves
FIGURE 17. COMMON-MODE REJECTION RATIO (CMRR)
-20
FIGURE 18. POWER SUPPLY REJECTION RATIO (PSRR)
V =±15V
S
A =+1
V
-30
-40
-50
-60
-70
-80
-90
-100
THD
R =0Ω
F
R =500Ω
L
C =5pF
L
V
=2V
OUT
P-P
2ND HD
3RD HD
10M
500K
1M
40M
FREQUENCY (Hz)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FIGURE 20. HARMONIC DISTORTION vs OUTPUT VOLTAGE
(A = +1)
V
(A = +2)
V
FIGURE 21. OUTPUT SWING vs FREQUENCY FOR VARIOUS
GAIN SETTINGS
FIGURE 22. OUTPUT SWING vs SUPPLY VOLTAGE FOR
VARIOUS GAIN SETTINGS
FN7497.1
July 15, 2005
7
ISL55002, ISL55004
Typical Performance Curves
20% to 80%
80% to 20%
20% to 80% 80% to 20%
FIGURE 23. LARGE SIGNAL RISE AND FALL TIMES
FIGURE 24. SMALL SIGNAL RISE AND FALL TIMES
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.2
SO14
1
0.8
0.6
0.4
0.2
0
1.042W
781mW
θ
=120°C/W
JA
SO8
θ
=160°C/W
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 25. SUPPLY CURRENT vs SUPPLY VOLTAGE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
CONDUCTIVITY TEST BOARD
1.8
1.6
1.420W
1.4
SO14
JA
1.2
θ
=88°C/W
1.136W
1
0.8
0.6
0.4
0.2
0
SO8
θ
=110°C/W
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7497.1
July 15, 2005
8
ISL55002, ISL55004
(usually between 5Ω to 50Ω) can be placed in series with the
Product Description
output to eliminate most peaking. However, this will reduce
the gain slightly. If the gain setting is greater than 1, the gain
The ISL55002 and ISL55004 are wide bandwidth, low
power, and low offset voltage feedback operational
amplifiers. These devices are internally compensated for
closed loop gain of +1 or greater. Connected in voltage
follower mode and driving a 500Ω load, the -3dB bandwidth
is around a 220MHz. Driving a 150Ω load and a gain of 2,
the bandwidth is about 90MHz while maintaining a 300V/µs
slew rate.
resistor R can then be chosen to make up for any gain loss
G
which may be created by the additional series resistor at the
output.
When used as a cable driver, double termination is always
recommended for reflection-free performance. For those
applications, a back-termination series resistor at the
amplifier's output will isolate the amplifier from the cable and
allow extensive capacitive drive. However, other applications
may have high capacitive loads without a back-termination
resistor. Again, a small series resistor at the output can help
to reduce peaking.
The ISL55002 and ISL55004 are designed to operate with
supply voltage from +15V to -15V. That means for single
supply application, the supply voltage is from 0V to 30V. For
split supplies application, the supply voltage is from ±15V.
The amplifier has an input common-mode voltage range
from 1.5V above the negative supply (V - pin) to 1.5V below
Output Drive Capability
S
the positive supply (V + pin). If the input signal is outside the
S
The ISL55002 and ISL55004 do not have internal short
circuit protection circuitry. They have a typical short circuit
current of 140mA. If the output is shorted indefinitely, the
power dissipation could easily overheat the die or the current
could eventually compromise metal integrity. Maximum
reliability is maintained if the output current never exceeds
±60mA. This limit is set by the design of the internal metal
interconnect. Note that in transient applications, the part is
robust.
above specified range, it will cause the output signal to be
distorted.
The outputs of the ISL55002 and ISL55004 can swing from
-12.75V to +13.4V for V = ±15V. As the load resistance
S
becomes lower, the output swing is lower.
Choice Of Feedback Resistor And Gain Bandwidth
Product
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the amplifier's phase
margin is reduced. This causes ringing in the time domain
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75Ω resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
and peaking in the frequency domain. Therefore, R can't be
F
Power Dissipation
very big for optimum performance. If a large value of R
F
With the high output drive capability of the ISL55002 and
ISL55004, it is possible to exceed the 150°C absolute
maximum junction temperature under certain load current
conditions. Therefore, it is important to calculate the
maximum junction temperature for an application to
determine if load conditions or package types need to be
modified to assure operation of the amplifier in a safe
operating area.
must be used, a small capacitor in the few Pico farad range
in parallel with R can help to reduce the ringing and
F
peaking at the expense of reducing the bandwidth. For gain
of +1, R = 0 is optimum. For the gains other than +1,
F
optimum response is obtained with R with proper selection
F
of R and R (see Figures15 and 16 for selection.)
F
G
Video Performance
For good video performance, an amplifier is required to
maintain the same output impedance and the same
frequency response as DC levels are changed at the output.
This is especially difficult when driving a standard video load
of 150Ω, because of the change in output current with DC
level. The dG and dP of this device is about 0.01% and
0.05°, while driving 150Ω at a gain of 2. Driving high
impedance loads would give a similar or better dG and dP
performance.
The maximum power dissipation allowed in a package is
determined according to:
T
– T
AMAX
JMAX
PD
= --------------------------------------------
MAX
Θ
JA
Where:
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
Driving Capacitive Loads and Cables
• θ = Thermal resistance of the package
JA
The ISL55002 and ISL55004 can drive 47pF loads in parallel
with 500Ω with less than 3dB of peaking at gain of +1 and as
much as 100pF at a gain of +2 with under 3db of peaking. If
less peaking is desired in applications, a small series resistor
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
FN7497.1
9
July 15, 2005
ISL55002, ISL55004
For sourcing:
Sullen Key High Pass Filter
n
V
Again this useful filter benefits from the characteristics of the
ISL55002 and ISL55004. The transfer function is very similar
to the low pass so only the results are presented (See Figure
29).
OUTi
-----------------
PD
= V × I
+
+
(V – V
) ×
MAX
S
SMAX
S
OUTi
∑
R
Li
i = 1
For sinking:
n
PD
= V × I
(V
– V ) × I
OUTi S LOADi
MAX
S
SMAX
∑
i = 1
Where:
• V = Supply voltage
S
• I
SMAX
= Maximum quiescent supply current
• V
• R
= Maximum output voltage of the application
OUT
= Load resistance tied to ground
LOAD
• I
LOAD
= Load current
• N = number of amplifiers (max = 2)
By setting the two PD equations equal to each other, we
MAX
can solve the output current and R
overheat.
to avoid the device
LOAD
Power Supply Bypassing Printed Circuit Board
Layout
As with any high frequency device, a good printed circuit
board layout is necessary for optimum performance. Lead
lengths should be as short as possible. The power supply
pin must be well bypassed to reduce the risk of oscillation.
For normal single supply operation, where the V - pin is
S
connected to the ground plane, a single 4.7µF tantalum
capacitor in parallel with a 0.1µF ceramic capacitor from V +
S
to GND will suffice. This same capacitor combination should
be placed at each supply pin to ground if split supplies are to
be used. In this case, the V - pin becomes the negative
S
supply rail.
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance. Minimizing parasitic capacitance
at the amplifier's inverting input pin is very important. The
feedback resistor should be placed very close to the
inverting input pin. Strip line design techniques are
recommended for the signal traces.
Application Circuits
Sullen Key Low Pass Filter
A common and easy to implement filter taking advantage of
the wide bandwidth, low offset and low power demands of
the ISL55002 and ISL55004. A derivation of the transfer
function is provided for convenience (See Figure 28).
FN7497.1
10
July 15, 2005
ISL55002, ISL55004
RB
RA
V
K = 1+
Vo = K
2
5V
1
C
5
V1
R2C2s +1
Vo
1nF
C
V1− Vi
R1
Vo − Vi
1
C1s
1
K − V1
1+
+
= 0
R2
1nF
R
R
2
1
K
V+
V-
+
-
H(s) =
V
OUT
2
1kΩ
1kΩ C
2
V
R1C1R2C2s + ((1− K)R1C1+ R1C2 + R21C2)s +1
1
R
7
1nF
1
1kΩ
H(jw) =
2
1− w R1C1R2C2 + jw((1− K)R1C1+ R1C2 + R2C2)
R
B
Holp = K
1kΩ
R
1
A
C
5
wo =
1kΩ
R1C1R2C2
1nF
1
Q =
R1C1
R2C2
R1C2
R2C1
R2C2
R1C1
V
5V
3
(1− K)
+
+
Holp = K
Equations simplify if we let all
components be equal R=C
1
RC
1
Q =
wo =
3 − K
FIGURE 28. SULLEN KEY LOW PASS FILTER
V
2
Holp = K
5V
1
C
5
wo =
R1C1R2C2
1nF
1
C
1
Q =
R1C1
R1C2
R2C1
R2C2
R1C1
(1− K)
+
+
1nF
R2C2
R
R
2
1
V+
V-
+
-
V
OUT
1kΩ
1kΩ C
2
V
1
R
7
1nF
1kΩ
R
K
4 − K
B
Holp =
wo =
1kΩ
R
A
C
Equations simplify if we let
all components be equal R=C
2
RC
2
5
1kΩ
1nF
Q =
V
3
4 − K
5V
FIGURE 29. SULLEN KEY HIGH PASS FILTER
FN7497.1
11
July 15, 2005
ISL55002, ISL55004
Differential Output Instrumentation Amplifier
e
e
= –(1 + 2R ⁄ R )(e – e )
e
= (1 + 2R ⁄ R )(e – e )
o4 2 G 1 2
o3
o
2
G
1
2
The addition of a third amplifier to the conventional three
amplifier instrumentation amplifier introduces the benefits of
differential signal realization, specifically the advantage of
using common-mode rejection to remove coupled noise and
ground potential errors inherent in remote transmission. This
configuration also provides enhanced bandwidth, wider
output swing and faster slew rate than conventional three
amplifier solutions with only the cost of an additional
amplifier and few resistors.
= –2(1 + 2R ⁄ R )(e – e )
2
G
1
2
2f
A
C1, 2
A
= –2(1 + 2R ⁄ R
G
)
Di
2
BW = -----------------
Di
Strain Gauge
The strain gauge is an ideal application to take advantage of
the moderate bandwidth and high accuracy of the ISL55002
and ISL55004. The operation of the circuit is very
straightforward. As the strain variable component resistor in
the balanced bridge is subjected to increasing strain, its
resistance changes, resulting in an imbalance in the bridge.
A voltage variation from the referenced high accuracy
source is generated and translated to the difference amplifier
through the buffer stage. This voltage difference as a
function of the strain is converted into an output voltage.
A
+
1
R
R
3
3
e
1
-
A
3
R
e 3
2
o
-
+
+
R
R
3
3
REF
R
e
o
G
R
R
3
3
A
4
R
2
-
+
-
e 4
o
A
2
R
R
3
3
-
+
e
2
+
-
V
2
5V
C
6
VARIABLE SUBJECT
TO STRAIN
1nF
1kΩ
+
-
R
R
1kΩ
1kΩ
17
18
V
R
R
16
5
15
V+
V-
+
-
0V
1kΩ
1kΩ
V
OUT
(V1+V2+V3+V4)
R
L
1kΩ
1kΩ
R
F
1kΩ
C
12
1nF
+
-
V
4
5V
FN7497.1
12
July 15, 2005
ISL55002, ISL55004
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
INCHES
MILLIMETERS
0.25(0.010)
M
B M
H
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-B-
-
1
2
3
9
L
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
SEATING PLANE
A
3
-A-
o
h x 45
D
4
0.050 BSC
1.27 BSC
-
-C-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
α
µ
e
5
A1
C
B
L
6
0.10(0.004)
N
α
8
8
7
0.25(0.010) M
C A M B S
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN7497.1
13
July 15, 2005
ISL55002, ISL55004
Small Outline Plastic Packages (SOIC)
N
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
INCHES
MILLIMETERS
0.25(0.010)
M
B M
H
E
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
-
1
2
3
L
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
SEATING PLANE
A
3
-A-
o
h x 45
D
4
0.050 BSC
1.27 BSC
-
-C-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
α
µ
e
A1
5
C
B
0.10(0.004)
L
6
0.25(0.010) M
C A M B S
N
α
14
14
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7497.1
14
July 15, 2005
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