ISL59114 [INTERSIL]
YC (S-video) to Composite Video Driver with LPF; YC （ S端子），以复合视频驱动器与低通滤波器
| 型号： | ISL59114 |
| 厂家： | 
Intersil |
| 描述： | YC (S-video) to Composite Video Driver with LPF |
| 文件： | 总10页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59114
®
Data Sheet
September 21, 2006
FN6184.2
YC (S-video) to Composite Video Driver
with LPF
Features
• 3rd order 9MHz reconstruction filter
• 40V/µs slew rate
The ISL59114 is a YC (S-video) reconstruction filter with a
-3dB roll-off frequency of 9MHz and summer amplifier to
create the composite video signal. Operating from a single
supply ranging from +2.5V to +3.6V and drawing only 4.5mA
quiescent current, the ISL59114 is ideally suited for low
power, battery-operated applications. Additionally, an enable
pin shuts the part down in under 14ns.
• Low supply current = 4.5mA
• Maximum Power-down current <0.5µA
• Supplies from 2.5V to 3.6V
• Rail-to-rail output
The ISL59114 is designed to meet the bandwidth and very
low power requirements of battery-operated communication,
instrumentation, and modern industrial applications such as
video on demand, cable set-top boxes, MP3 players, and
HDTV. The ISL59114 is offered in a space-saving µTQFN
Pb-free package guaranteed to a 0.6mm maximum height
constraint and specified for operation from -40°C to +85°C
temperature range.
• µTQFN package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Video amplifiers
• Portable and handheld products
• Communications devices
• Video on demand
• Cable set-top boxes
• Satellite set-top boxes
• MP3 players
Pinout
ISL59114
(10 LD µTQFN)
TOP VIEW
GND
10
• HDTV
• Personal video recorder
Y
Y
OUT
9
1
2
IN
Block Diagram
EN
CVBS
8
CLAMP
OUT
+
-
C
C
3
4
7
IN
OUT
65mV
-
YIN
9MHz
9MHz
+
x2
x2
x2
YOUT
1uA
EN
CY
EN
500mV
6
CVBS
65mV
-
+
CIN
COUT
5
ENCY
VDD
+
+
65mV
ENCLAMP
ENCVBS
-
+
CVBSOUT
Ordering Information
PART NUMBER (Note)
PART MARKING
TAPE AND REEL
TEMP. RANGE (°C)
PACKAGE (Pb-Free)
PKG. DWG. #
L10.2.1x1.6A
ISL59114IRUZ-T7
FJ
7”
-40 to +85
10 Ld µTQFN
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL59114
Absolute Maximum Ratings (T = +25°C)
A
Supply Voltage from V
DD
Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C
to GND . . . . . . . . . . . . . . . . . . . . . . . 4.2V
+0.3V to GND -0.3V
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications
V
= 3.3V, T = +25°C, R = 150Ω to GND, unless otherwise specified.
A L
DD
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Supply Voltage Range
2.5
3.6
4.0
V
DD
I
I
I
Quiescent Supply Current - CY Amps
Enabled
V
= 500mV, EN = V , EN
CY DD CVBS
= GND,
3.1
4.5
mA
DD_CY
IN
no load
Quiescent Supply Current
V
= 500mV, EN
CY
= EN
= V ,
DD
6.0
mA
DD
IN
no load
CVBS
Shutdown Supply Current
Y Input Clamp Voltage
EN
= EN
= 0V
0.1
-15
1
0.5
10
µA
mV
µA
mA
MΩ
mV
kΩ
nA
mV
mV
V/V
V/V
%
DD_OFF
CY
CVBS
= -100µA
Y
V
I
-30
0.6
Y_CLAMP
Y_DOWN
Y_UP
I
I
Y input Clamp Discharge Current
Y Input Clamp Charge Current
Y Input Resistance
V
V
= 0.5V
1.6
-3.0
Y
Y
= -0.1V
-3.4
R
0.5V < V < 1V
10
500
2.0
Y
Y
V
C Input Clamp Voltage
V
V
V
= 0.05V, I = 0A
550
2.5
700
3.0
C_CLAMP
Y
Y
Y
C
R
C Input Resistance
= 0.05V, 0.25V < V < 0.75V
C
C
I
C Input Bias Current
= 0.3V
-200
100
60
-2
200
200
200
2.04
2.04
1.75
3
C
V
V
Y Input Sync Detect Voltage
Output Level Shift Voltage
Voltage Gain, C-Y channel
Voltage Gain, CVBS channel
C-to-Y Channel Gain Mismatch
C/Y-to-CVBS Channel Gain Mismatch
DC Power Supply Rejection
DC Power Supply Rejection
Output Voltage High Swing
Output Short-Circuit Current
150
130
1.99
1.98
±0.5
±0.7
60
Y_SYNC
OLS
V
= 0V, no load
= 150Ω
IN
A
R
R
1.95
1.93
-1.75
-3
V_CY
L
L
A
= 150Ω
V_CVBS
∆A
V_CY
∆A
%
V_CVBS
PSRR
PSRR
V
V
V
V
= 2.5V to 3.6V
= 2.5V to 3.6V
40
dB
dB
V
_CY
DD
25
35
_CVBS
DD
V
= 2V, R = 150Ω to GND
2.85
100
-0.2
3.2
OH
IN
IN
L
I
I
= 2V, to GND through 10Ω
145
0.001
mA
µA
V
SC
ENABLE
EN , EN
CY CVBS
Input Current
0V < V
< 3.3V
+0.2
0.8
EN
V
V
Disable Threshold
IL
Enable Threshold
2.0
5.0
V
IH
R
Shutdown Output Impedance
EN = 0V, DC
7.5
kΩ
kΩ
OUT
EN = 0V, f = 4.5MHz
3.4
FN6184.2
September 21, 2006
2
ISL59114
Electrical Specifications
V
= 3.3V, T = +25°C, R = 150Ω to GND, unless otherwise specified. (Continued)
DD
A
L
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
±0.1dB Bandwidth
R
= 75Ω, R = 150Ω, C = 5pF
5.6
3.9
8.8
7.8
-28.5
-30.6
0.10
0.5
5.4
65
MHz
MHz
MHz
MHz
dB
0.1dB
3dB
SOURCE
SOURCE
SOURCE
SOURCE
L
L
R
R
R
= 500Ω, R = 150Ω, C = 5pF
L L
BW
-3dB Bandwidth
= 75Ω, R = 150Ω, C = 5pF
L L
= 500Ω, R = 150Ω, C = 5pF
L
L
Normalized Stopband Gain
f = 27MHz, R
f = 27MHz, R
= 75Ω
SOURCE
= 500Ω
dB
SOURCE
dG
dP
Differential Gain
Differential Phase
Group Delay Variation
Signal to Noise Ratio
Enable Time
NTSC and PAL
NTSC and PAL
f = 100kHz, 5MHz
100% white signal
%
°
D/DT
SNR
ns
dB
T
T
V
V
= 500mV, V
= 500mV, V
to 1%
200
14
ns
ON
IN
IN
OUT
OUT
Disable Time
to 1%
ns
OFF
+SR
-SR
Positive Slew Rate
Negative Slew Rate
Fall Time
20% to 80%, V = 1V step
IN
30
40
50
V/µs
V/µs
ns
80% to 20%, V = 1V step
IN
-30
-40
25
-50
t
t
2.5V
2.5V
, 80% - 20%
STEP
F
Rise Time
, 20% - 80%
STEP
22
ns
R
Connection Diagram
+
-
S-video cable
65mV
YIN
YOUT
-
+
Y (luminance)
9MHz
9MHz
x2
x2
x2
YOUT
75
0.1uF
75
1uA
500mV
65mV
CIN
COUT
-
C (chrominance)
+
COUT
0.1uF
75
75
75
+
+
65mV
ENCLAMP
ENCY
CVBSOUT
75
-
+
CVBSOUT
uC or
tie to 3.3V
ENCVBS
Note:
ENCLAMP is high for AC coupled inputs (as shown)
ENCLAMP is low for DC coupled inputs
FN6184.2
September 21, 2006
3
ISL59114
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
2
Y
Luminance input
IN
EN
CLAMP
Enable clamp. Tie high for AC coupled inputs. Tie low for DC coupled inputs.
3
C
Chrominance input
IN
4
EN
Enable chrominance and luminance outputs
Positive power supply
Enable composite video output
Chrominance output
CY
5
V
DD
6
EN
CVBS
OUT
7
C
8
CVBS
Composite video output
Luminance output
OUT
9
Y
OUT
10
GND
Ground
Typical Performance Curves
5
0
5
0
-3dB BW @ 8.8MHz
-28dB BW @ 27MHz
-0.1dB BW @ 5.6MHz
-5
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
V
R
= +3.3V
= 150Ω
V
R
= +3.3V
= 150Ω
DD
L
DD
L
-30
-35
35M
1M
10M
100k
100k
1M
FREQUENCY RESPONSE (Hz)
10M 25M
FREQUENCY RESPONSE (Hz)
FIGURE 2. GAIN vs FREQUENCY -3dB POINT
FIGURE 1. GAIN vs FREQUENCY -0.1dB
2
1
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
C
= 470pF
V
R
= +3.3V
V
R
= +3.3V
= 150Ω
= 100kHz
L
DD
L
DD
L
= 150Ω
F
IN
0
-1
-2
-3
-4
-5
-6
C
= 100pF
L
C
= 10pF
L
25M
0.0
0.5
1.0
1.5
2.0
(V
2.5
3.0
3.5
4.0
100k
1M
FREQUENCY RESPONSE (Hz)
10M
V
)
IN P-P
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS C
FIGURE 4. MAXIMUM OUTPUT MAGNITUDE vs INPUT
MAGNITUDE
LOAD
FN6184.2
September 21, 2006
4
ISL59114
Typical Performance Curves (Continued)
0
-10
-20
-30
-40
-50
-60
-70
-80
270
V
= +3.3V
V
R
= +3.3V
= 150Ω
DD
DD
L
180
90
0
-90
-180
-270
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. PSRR vs FREQUENCY
FIGURE 5. PHASE vs FREQUENCY
-30
-40
-50
-60
-70
-80
-90
-100
V
= +3.3V
DD
Y
TO C
OUT
IN
C
TO Y
IN
OUT
100k
1M
FREQUENCY (Hz)
10M
50M
FIGURE 8. ISOLATION vs FREQUENCY
FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY
7
6
5
4
3
2
1
0
NO LOAD
NO INPUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
FIGURE 9. MAXIMUM OUTPUT vs LOAD RESISTANCE
FIGURE 10. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN6184.2
September 21, 2006
5
ISL59114
Typical Performance Curves (Continued)
3.6
3.0
2.4
1.8
1.2
0.6
0.0
3.5
3.0
2.5
V
R
V
= +3.3V
= 150Ω
DD
L
= 1V
OUT
P-P
V
= +3.3V
= 150Ω
= 2.5V
DD
R
V
L
2.0
1.5
1.0
0.5
0.0
OUT
P-P
POSITIVE SLEW
RATE = 41.1V/µs
T
= 26.4ns
RISE
NEGATIVE SLEW
RATE = -40.8V/µs
T
= 26.9ns
FALL
-60
0
60 120 180 240 300 360 420 480
TIME (ns)
-120 -60
0
60 120 180 240 300 360 420 480 540
TIME (ns)
FIGURE 12. SLEW RATE
FIGURE 11. LARGE SIGNAL STEP RESPONSE
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
V
R
= +3.3V
DD
L
V
= +3.3V
DD
= 150Ω
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
R
= 150Ω
L
DISABLE SIGNAL
ENABLE SIGNAL
OUTPUT SIGNAL
-20 -10
OUTPUT SIGNAL
60 90 120 150 180 210
TIME (ns)
-60 -30
0
30
0
10
20
30
40
TIME (ns)
FIGURE 13. ENABLE TIME
FIGURE 14. DISABLE TIME
-30
-40
-50
-60
-70
-80
-20
THD
V
R
= +3.3V
= 150Ω
DD
-30
-40
-50
-60
-70
-80
L
V
= 2V
OUT
P-P
THD
rd
3
HD
rd
3
HD
nd
2
HD
nd
2
HD
1.0
0.5
1.5
2.0
2.5
3.0
1M
10M
FREQUENCY (Hz)
OUTPUT VOLTAGE (V
)
P-P
FIGURE 15. HARMONIC DISTORTION vs FREQUENCY
FIGURE 16. HARMONIC DISTORTION vs OUTPUT VOLTAGE
FN6184.2
September 21, 2006
6
ISL59114
Typical Performance Curves (Continued)
16
14
12
10
8
V
R
= +3.3V
= 150Ω
V
R
= +3.3V
= 150Ω
DD
L
DD
L
6
4
2
80
140
200
260
320
380
440
500
INPUT RESISTANCE (Ω)
FIGURE 18. -3dB BANDWIDTH vs INPUT RESISTANCE
FIGURE 17. GROUP DELAY vs FREQUENCY
44
V
R
= 1V
P-P
IN
= 150Ω
43
42
41
40
39
38
37
L
POSITIVE SLEW RATE
NEGATIVE SLEW RATE
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
FIGURE 19. SLEW RATE vs SUPPLY VOLTAGE
100
10
2
4
6
8
1
2
4
6
8
1
2
4
10kHz
100kHz
1MHz
4.2MHz
FREQUENCY (Hz)
FIGURE 20. UNWEIGHTED NOISE FLOOR
FN6184.2
September 21, 2006
7
ISL59114
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE
THERMAL CONDUCTIVITY TEST BOARD -
QFN EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
JEDEC JESD51-3 AND SEMI G42-88
(SINGLE LAYER) TEST BOARD
0.8
3
2.5
2
0.7
0.6
515mW
0.5
0.4
0.3
0.2
0.1
0
1.5
1
775mW
0.5
0
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
The Sallen Key Low Pass Filter
Application Information
The Sallen Key is a classic low pass configuration. This
provides a very stable low pass function, and in the case of
the ISL59114, a three-pole roll-off at 9MHz. The three-pole
function is accomplished with an RC low pass network placed
in series with and before the Sallen Key. One pole provided by
the RC network and poles two and three provided by the
Sallen Key for a nice three-pole roll-off at 9MHz.
The ISL59114 is a single-supply rail-to-rail triple (two in,
three out) video amplifier with internal sync tip clamps, a
typical -3dB bandwidth of 9MHz and slew rate of about
40V/µs. The Y and C channels are internally mixed to create
a third CVBS (composite) video output. This part is ideally
suited for applications requiring high composite and s-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59114 is optimized for portable video applications.
Output Coupling
The ISL59114 can be AC or DC coupled to its output. When
AC coupling, a 220µF coupling capacitor is recommended to
ensure that low frequencies are passed, preventing video
“tilt” or “droop” across a line.
Internal Sync Clamp
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59114’s internal sync clamp makes it possible to DC
couple the output to a video load, eliminating the need for
any AC coupling capacitors, saving board space, cost, and
eliminating any “tilt” or offset shift in the output signal. The
trade off is larger supply current draw, since the DC
component of the signal is now dissipated in the load
resistor. Typical load current for AC coupled signals is 5mA
compared to 10mA for DC coupling.
The ISL59114 features an internal sync clamp and offset
function that level shifts the entire video signal to the
optimum level before it reaches the amplifiers’ input stage.
These features also help avoid saturation of the output stage
of the amplifier by setting the signal closer to the best
voltage range.
Output Drive Capability
The simplified block diagram on the front page shows the
basic operation of the ISL59114’s sync clamp. The Y input’s
AC-coupled video sync signal is pulled negative by a current
source at the input. When the sync tip goes below the
comparator threshold, the comparator output goes high,
pulling up on the Y input through the diode, forcing current
into the coupling capacitor until the voltage at the Y input is
again 0V, and the comparator turns off. This forces the sync
tip clamp to always be 0V, setting the offset for the entire
video signal.
The ISL59114 does not have internal short circuit protection
circuitry. If the output is shorted indefinitely, the power
dissipation could easily overheat the die or the current could
eventually compromise metal integrity. Maximum reliability is
maintained if the output current never exceeds ±40mA. This
limit is set by the design of the internal metal interconnect.
Note that for transient short circuits, the part is robust.
Short circuit protection can be provided externally with a
back match resistor in series with the output placed close as
possible to the output pin. In video applications this would be
a 75Ω resistor and will provide adequate short circuit
protection to the device. Care should still be taken not to
stress the device with a short at the output.
FN6184.2
September 21, 2006
8
ISL59114
Power Dissipation
Power Supply Bypassing Printed Circuit Board
Layout
With the high output drive capability of the ISL59114, it is
possible to exceed the +125°C absolute maximum junction
temperature under certain load current conditions.
Therefore, it is important to calculate the maximum junction
temperature for an application to determine if load conditions
or package types need to be modified to assure operation of
the amplifier in a safe operating area.
As with any modern operational amplifier, a good printed
circuit board layout is necessary for optimum performance.
Lead lengths should be as short as possible. The power
supply pin must be well bypassed to reduce the risk of
oscillation. For normal single supply operation, a single
4.7µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor from V + to GND will suffice.
S
The maximum power dissipation allowed in a package is
determined according to:
Printed Circuit Board Layout
For good AC performance, parasitic capacitance should be
kept to minimum. Use of wire wound resistors should be
avoided because of their additional series inductance. Use
of sockets should also be avoided if possible. Sockets add
parasitic inductance and capacitance that can result in
compromised performance.
T
– T
AMAX
JMAX
PD
= --------------------------------------------
MAX
Θ
JA
Where:
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
T
AMAX
Θ
= Thermal resistance of the package
JA
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the load, or:
for sourcing:
V
OUT
R
L
---------------
PD
= V × I
+ (V – V
) ×
MAX
S
SMAX
S
OUT
for sinking:
PD
= V × I
+ (V
– V ) × I
OUT S LOAD
MAX
S
SMAX
Where:
V = Supply voltage
S
I
= Maximum quiescent supply current
SMAX
V
= Maximum output voltage of the application
OUT
R
= Load resistance tied to ground
LOAD
I
= Load current
LOAD
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6184.2
September 21, 2006
9
ISL59114
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
L10.2.1x1.6A
D
A
B
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
6
MILLIMETERS
INDEX AREA
N
E
SYMBOL
MIN
0.45
NOMINAL
MAX
0.55
NOTES
2X
0.10 C
A
A1
A3
b
0.50
-
1
2
2X
0.10 C
-
-
0.05
-
TOP VIEW
0.127 REF
-
0.15
2.05
1.55
0.20
0.25
2.15
1.65
5
0.10 C
0.05 C
D
2.10
-
C
A
E
1.60
-
SEATING PLANE
e
0.50 BSC
-
A1
k
0.20
0.35
-
0.40
10
4
-
-
SIDE VIEW
L
0.45
-
(DATUM A)
N
2
PIN #1 ID
Nd
Ne
θ
3
4xk
1
2
NX L
1
3
N
0
-
12
4
(DATUM B)
Rev. 3 6/06
N-1
NOTES:
5
NX b
e
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
0.10 M C A B
0.05 M C
3
(ND-1) X e
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
C
L
(A1)
NX (b)
L
5
7. Maximum package warpage is 0.05mm.
e
8. Maximum allowable burrs is 0.076mm in all directions.
9. Same as JEDEC MO-255UABD except:
SECTION "C-C"
TERMINAL TIP
C C
No lead-pull-back, "A" MIN dimension = 0.45 not 0.50mm
"L" MAX dimension = 0.45 not 0.42mm.
FOR ODD TERMINAL/SIDE
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
b
2.50
1.75
0.05 MIN
L
2.00
0.80
0.275
0.10 MIN
0.25
0.50
DETAIL “A” PIN 1 ID
10
LAND PATTERN
FN6184.2
September 21, 2006
10
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