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ISL59441IAZ-T13 [INTERSIL]

900MHz Multiplexing Amplifier; 900MHz的复用放大器
ISL59441IAZ-T13
型号： ISL59441IAZ-T13
厂家： Intersil    Intersil
描述：

900MHz Multiplexing Amplifier
900MHz的复用放大器

放大器
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ISL59441  
®
Data Sheet  
September 21, 2005  
FN6163.2  
900MHz Multiplexing Amplifier  
Features  
• 900MHz (-3dB) Bandwidth (A = 1, V  
The ISL59441 is 900MHz bandwidth 4:1 multiplexing  
amplifier designed primarily for video switching. This Mux  
amp has a user-settable gain and also features a high speed  
three-state function to enable the output of multiple devices  
to be wired together. All logic inputs have pull-downs to  
ground and may be left floating. The ENABLE pin, when  
pulled high, sets the ISL59441 to the low current power-down  
mode for power sensitive applications - consuming just 5mW.  
= 100mV  
)
P-P  
V
OUT  
• 230MHz (-3dB) Bandwidth (A = 2, V  
V
= 2V )  
P-P  
OUT  
• Slew Rate (A = 1, R = 500Ω, V  
= 4V) . . . . .1349V/µs  
= 5V) . . . . .1927V/µs  
V
L
OUT  
OUT  
• Slew Rate (A = 2, R = 500Ω, V  
V
L
• Adjustable Gain  
• High Speed Three-State Output (HIZ)  
TABLE 1. CHANNEL SELECT LOGIC TABLE  
• Low Current Power-Down . . . . . . . . . . . . . . . . . . . . .5mW  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
S1  
0
S0  
0
ENABLE  
HIZ  
0
OUTPUT  
IN0  
0
0
0
0
1
0
Applications  
• HDTV/DTV Analog Inputs  
0
1
0
IN1  
1
0
0
IN2  
1
1
0
IN3  
• Video Projectors  
X
X
X
X
X
1
Power Down  
High Z  
• Computer Monitors  
• Set-top Boxes  
• Security Video  
Pinout  
ISL59441 (16 LD QSOP)  
• Broadcast Video Equipment  
TOP VIEW  
NIC  
1
2
3
4
5
6
7
8
ENABLE  
HIZ  
IN-  
Ordering Information  
16  
IN0  
NIC  
IN1  
PART  
TAPE &  
PKG.  
15  
14  
13  
12  
11  
10  
9
PART NUMBER MARKING REEL  
PACKAGE  
DWG. #  
ISL59441IA  
59441IA  
59441IA  
59441IA  
59441IAZ  
-
7”  
13”  
-
16 Ld QSOP MDP0040  
16 Ld QSOP MDP0040  
16 Ld QSOP MDP0040  
-
OUT  
V+  
+
ISL59441IA-T7  
ISL59441IA-T13  
GND  
IN2  
V-  
ISL59441IAZ  
(Note)  
16 Ld QSOP MDP0040  
(Pb-free)  
NIC  
IN3  
S1  
ISL59441IAZ-T7 59441IAZ  
(Note)  
7”  
16 Ld QSOP MDP0040  
(Pb-free)  
S0  
ISL59441IAZ-T13 59441IAZ  
(Note)  
13”  
16 Ld QSOP MDP0040  
(Pb-free)  
Functional Diagram  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
EN0  
IN-  
S0  
S1  
IN0  
EN1  
OUT  
-
+
IN1  
IN2  
DECODE  
EN2  
EN3  
IN3  
AMPLIFIER BIAS  
HIZ  
ENABLE  
ENABLE pin must be low in order to activate the HIZ state  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2005. All Rights Reserved.  
1
All other trademarks mentioned are the property of their respective owners.  
ISL59441  
Absolute Maximum Ratings (T = 25°C)  
A
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11V  
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- -0.5V, V+ +0.5V  
Supply Turn-on Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs  
IN- Input Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA  
Digital & Analog Input Current (Note 1) . . . . . . . . . . . . . . . . . . 50mA  
Output Current (Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
ESD Rating  
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C  
Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves  
θ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves  
JA  
Human Body Model (Per MIL-STD-883 Method 3015.7). . . . 2.5kV  
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTE:  
1. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values.  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests  
are at the specified temperature and are pulsed tests, therefore: T = T = T  
A
J
C
Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T = 25°C, R = 500Ω to GND unless otherwise specified.  
A
L
PARAMETER  
DESCRIPTION  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
GENERAL  
±I Enabled  
Supply Current  
No load, V = 0V, ENABLE Low  
IN  
15  
17  
1
19.5  
1.5  
10  
mA  
mA  
µA  
V
S
I
Disabled  
Disabled Supply Current I+  
Disabled Supply Current I-  
Positive Output Swing  
Negative Output Swing  
Output Current  
No load, V = 0V, ENABLE High  
IN  
0.6  
S
No load, V = 0V, ENABLE High  
IN  
3
V
V
V
= 2V, R = 500Ω, A = 2  
2.8  
3.9  
-4  
OUT  
IN  
IN  
L
V
= -2V, R = 500Ω, A = 2  
-3.5  
±180  
18  
V
L
V
I
R
= 10Ω to GND  
±80  
0
±130  
9
mA  
mV  
µA  
µA  
MΩ  
Ω
OUT  
L
V
Output Offset Voltage  
Input Bias Current  
OS  
Ib+  
Ib-  
V
V
= 0V  
= 0V  
-4  
-2.5  
16  
1.4  
0.2  
10  
2
-1.5  
28  
IN  
IN  
Feedback Input Bias Current  
Output Resistance  
-28  
R
HIZ = logic high, (DC), A = 1  
V
out  
HIZ = logic low, (DC), A = 1  
V
R
Input Resistance  
V
V
V
= ±3.5V  
MΩ  
V/V  
µA  
IN  
IN  
A
or A  
Voltage Gain  
= ±1.5V, R = 500Ω, R = R = 600Ω  
1.99  
-35  
2.01  
35  
CL  
V
IN  
L
F
G
ITRI  
LOGIC  
Output Current in Three-State  
= 0V  
OUT  
V
V
Input High Voltage (Logic Inputs)  
Input Low Voltage (Logic Inputs)  
Input High Current (Logic Inputs)  
Input Low Current (Logic Inputs)  
2
V
V
H
L
0.8  
135  
10  
I
I
55  
90  
2
µA  
µA  
IH  
IL  
AC GENERAL  
- 3dB BW  
-3dB Bandwidth  
A
= 1, R = 301Ω, V  
= 200mV  
,
900  
230  
MHz  
MHz  
V
L
F
OUT  
P-P  
C
= 1.6pF, C = 0.6pF  
G
A
= 2, R = R = 205Ω, V  
OUT  
= 2V  
,
P-P  
V
F
G
C
= 1.6pF, C = 0.6pF  
G
L
FN6163.2  
2
September 21, 2005  
ISL59441  
Electrical Specifications V+ = +5V, V- = -5V, GND = 0V, T = 25°C, R = 500Ω to GND unless otherwise specified. (Continued)  
A
L
PARAMETER  
DESCRIPTION  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
0.1dB BW  
0.1dB Bandwidth  
A
= 1, R = 301Ω, V  
= 200mV  
,
90  
MHz  
V
L
F
OUT  
P-P  
C
= 1.6pF, C = 0.6pF  
G
A
= 2, R = R = 205Ω, V  
OUT  
= 2V  
,
32  
MHz  
V
L
F
G
P-P  
C
= 1.6pF, C = 0.6pF  
G
dG  
Differential Gain Error  
Differential Phase Error  
NTC-7, R = 150, C = 1.6pF, A = 1  
0.01  
0.01  
0.02  
0.02  
1349  
%
%
L
L
V
NTC-7, R = 150, C = 1.6pF, A = 2  
L
L
V
dP  
NTC-7, R = 150, C = 1.6pF, A = 1  
°
L
L
V
NTC-7, R = 150, C = 1.6pF, A = 2  
°
L
L
V
+SR  
Slew Rate  
Low to High  
25% to 75%, A = 1, V  
= 5V, R = 500Ω,  
V/µs  
V
OUT  
OUT  
OUT  
OUT  
L
C = 1.6pF  
L
25% to 75%, A = 2, V  
= 5V, R = 500Ω,  
1927  
1135  
1711  
V/µs  
V/µs  
V/µs  
V
L
C
= 1.6pF  
L
-SR  
Slew Rate  
High to Low  
25% to 75%, A = 1, V  
= 5V, R = 500Ω,  
L
V
C = 1.6pF  
L
25% to 75%, A = 2, V  
= 5V, R = 500Ω,  
L
V
C
= 1.6pF  
L
PSRR  
ISO  
Power Supply Rejection Ratio  
Channel Isolation  
DC, PSRR V+ and V- combined  
-50  
-57  
75  
dB  
dB  
f = 10MHz, Ch-Ch X-Talk and Off Isolation,  
C
= 1.6pF  
L
SWITCHING CHARACTERISTICS  
V
Channel-to-Channel Switching Glitch  
ENABLE Switching Glitch  
V
V
V
= 0V, C = 1.6pF, A = 2  
1
mV  
mV  
mV  
GLITCH  
IN  
IN  
IN  
L
V
P-P  
P-P  
P-P  
= 0V, C = 1.6pF, A = 2  
935  
255  
24  
L
V
HIZ Switching Glitch  
= 0V, C = 1.6pF, A = 2  
L V  
t
t
Channel Switching Time Low to High  
1.2V logic threshold to 10% movement of  
analog output  
ns  
SW-L-H  
SW-H-L  
Channel Switching Time High to Low  
1.2V logic threshold to 10% movement of  
analog output  
19  
ns  
TRANSIENT RESPONSE  
t
t
Rise & Fall Time, 10% to 90%  
A
= 1, R = 301Ω, V  
= 100mV ,  
P-P  
0.44  
1.23  
4.5  
ns  
ns  
ns  
%
R, F  
V
L
F
OUT  
C
= 1.6pF, C = 0.6pF  
G
A
= 2, R = R = 205Ω, V  
= 2V  
= 2V  
,
P-P  
V
F
G
OUT  
OUT  
C
= 1.6pF, C = 0.6pF  
G
L
t
0.1% Settling Time  
Overshoot  
A
= 2, R = R = 205Ω, V  
,
P-P  
S
V
F
G
C
= 1.6pF, C = 0.6pF  
G
L
O
A
= 1, R = 301Ω, V  
= 100mV  
,
9.52  
8.81  
0.48  
0.69  
0.54  
0.74  
S
V
F
OUT  
P-P  
C
= 1.6pF, C = 0.6pF  
L
G
A
= 2, R = R = 205Ω, V  
OUT  
= 2V  
,
%
V
F
G
P-P  
C
= 1.6pF, C = 0.6pF  
G
L
t
t
Propagation Delay - Low to High,  
10% to 10%  
A
= 1, R = 301Ω, V  
= 100mV  
,
ns  
ns  
ns  
ns  
PLH  
PHL  
V
F
OUT  
P-P  
C
= 1.6pF, C = 0.6pF  
L
G
A
= 2, R = R = 205Ω, V  
OUT  
= 2V  
,
V
F
G
P-P  
C
= 1.6pF, C = 0.6pF  
G
L
Propagation Delay- High to Low,  
10% to 10%  
A
= 1, R = 301Ω, V  
= 100mV  
,
V
F
OUT  
P-P  
C
= 1.6pF, C = 0.6pF  
L
G
A
= 2, R = R = 205Ω, V  
OUT  
= 2V  
,
V
F
G
P-P  
C
= 1.6pF, C = 0.6pF  
G
L
FN6163.2  
3
September 21, 2005  
ISL59441  
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified.  
S
L
A
5
4
3
2
1
0
5
4
3
2
1
0
A
OUT  
R
= 1  
A
= 1  
V
V
V
= 200mV  
P-P  
V
= 200mV  
P-P  
= 1.6pF  
OUT  
= 301Ω  
F
C
R
L
F
C
= 9.7pF  
L
= 301Ω  
C
= 7.2pF  
L
R
= 500Ω  
L
R
= 1kΩ  
L
C
= 5.5pF  
L
-1  
-2  
-3  
-4  
-5  
-1  
-2  
-3  
-4  
-5  
C
= 1.6pF  
L
R
= 150Ω  
L
R
= 75Ω  
C
INCLUDES 1.6pF  
L
L
BOARD CAPACITANCE  
100  
1000  
1
10  
100  
1
10  
1000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 1. SMALL SIGNAL GAIN vs FREQUENCY vs C  
FIGURE 2. SMALL SIGNAL GAIN vs FREQUENCY vs R  
L
L
5
5
A
= 2  
A
= 2  
V
V
4
3
2
1
0
4
3
2
1
0
V
= 2V  
OUT P-P  
R
V
= 2V  
OUT  
P-P  
= R = 205Ω  
G
F
C
R
= 1.6pF  
L
= R = 205Ω  
G
F
C
= 9.7pF  
L
-1  
-2  
-3  
-4  
-5  
-1  
-2  
-3  
-4  
-5  
C
= 7.2pF  
L
R
= 1kΩ  
L
R
= 150Ω  
L
C
= 5.5pF  
L
R
= 500Ω  
L
C
INCLUDES 1.6pF  
L
C
= 1.6pF  
BOARD CAPACITANCE  
L
R
= 75Ω  
L
1000  
1
10  
100  
100  
1
10  
1000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs C  
FIGURE 4. LARGE SIGNAL GAIN vs FREQUENCY vs R  
L
L
0.8  
0.8  
C
= 9.7pF  
L
R = 1kΩ  
L
A
OUT  
R
= 1  
V
0.7  
0.6  
0.5  
0.4  
0.3  
0.7  
0.6  
0.5  
0.4  
0.3  
V
= 200mV  
P-P  
R
= 500Ω  
L
= 301Ω  
F
C
= 5.5pF  
C
= 7.2pF  
L
L
R
= 150Ω  
L
0.2  
0.1  
0
0.2  
0.1  
0
A
V
= 1  
V
= 200mV  
P-P  
OUT  
C
= 1.6pF  
R = 75Ω  
L
L
C
= 1.6pF  
C
INCLUDES 1.6pF  
L
F
L
-0.1  
-0.2  
-0.1  
-0.2  
R
= 301Ω  
BOARD CAPACITANCE  
100  
1000  
1
10  
100  
1
10  
1000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 5. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs C  
FIGURE 6. SMALL SIGNAL 0.1dB GAIN vs FREQUENCY vs R  
L
L
FN6163.2  
4
September 21, 2005  
ISL59441  
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)  
S
L
A
0.2  
0.1  
0
0.2  
0.1  
0
C
= 9.7pF  
L
-0.1  
-0.2  
-0.3  
-0.1  
-0.2  
-0.3  
C
= 7.2pF  
L
R
= 150Ω  
L
C
= 5.5pF  
L
R
= 1kΩ  
L
C
= 1.6pF  
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
L
-0.4  
-0.5  
-0.6  
-0.7  
-0.8  
A
V
R
= 2  
OUT  
= R = 205Ω  
R
= 500Ω  
V
L
= 2V  
P-P  
A
= 2  
V
R
L
= 75Ω  
G
F
V
C
= 2V  
P-P  
OUT  
= 1.6pF  
C
INCLUDES 1.6pF  
L
L
R
= R = 205Ω  
F
BOARD CAPACITANCE  
G
100  
1000  
1
10  
100  
1
10  
1000  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 7. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs C  
FIGURE 8. LARGE SIGNAL 0.1dB GAIN vs FREQUENCY vs R  
-10  
L
L
20  
A
= 2  
V
A
= 2  
-20  
-30  
-40  
V
V
= 1V  
IN  
P-P  
10  
0
V
= 200mV  
= 1.6pF  
IN  
P-P  
C
R
= 1.6pF  
L
C
R
L
= R = 205Ω  
G
F
= R = 205Ω  
G
F
-10  
-20  
-30  
-40  
-50  
-60  
CROSSTALK  
-70  
-50  
-80  
PSRR (V+)  
-60  
-70  
-80  
-90  
OFF ISOLATION  
PSRR (V-)  
100  
-100  
-110  
0.3  
1
10  
1000  
0.001  
0.01  
0.1  
1
3
6 10  
100  
500  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 9. PSRR CHANNELS  
FIGURE 10. CROSSTALK AND OFF ISOLATION  
24  
60  
50  
40  
30  
20  
A
1, R = 500Ω  
A
1, R = 500Ω  
V =  
F
V = F  
20  
16  
12  
8
4
0
10  
0
1
10  
100  
1
10  
100  
0.1  
0.1  
FREQUENCY (kHz)  
FREQUENCY (kHz)  
FIGURE 11. INPUT NOISE vs FREQUENCY  
FIGURE 12. INPUT NOISE vs FREQUENCY  
FN6163.2  
September 21, 2005  
5
ISL59441  
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)  
S
L
A
S0, S1  
S0, S1  
0
0
0
0
V
OUT  
V
OUT  
20ns/DIV  
20ns/DIV  
FIGURE 13. CHANNEL TO CHANNEL SWITCHING GLITCH  
= 0V, A = 2  
FIGURE 14. CHANNEL TO CHANNEL TRANSIENT RESPONSE  
= 1V, A = 2  
V
V
IN  
IN  
V
V
ENABLE  
ENABLE  
0
0
0
V
OUT  
V
OUT  
0
20ns/DIV  
20ns/DIV  
FIGURE 15. ENABLE SWITCHING GLITCH V = 0V, A = 2  
IN  
FIGURE 16. ENABLE TRANSIENT RESPONSE V = 1V, A = 2  
IN  
V
V
HIZ  
HIZ  
0
0
0
V
V
OUT  
0
OUT  
20ns/DIV  
20ns/DIV  
FIGURE 17. HIZ SWITCHING GLITCH V = 0V, A = 2  
IN  
FIGURE 18. HIZ TRANSIENT RESPONSE V = 1V, A = 2  
IN  
V
V
FN6163.2  
September 21, 2005  
6
ISL59441  
Typical Performance Curves V = ±5V, R = 500Ω to GND, T = 25°C, unless otherwise specified. (Continued)  
S
L
A
160  
2.4  
2
A
C
= 1  
V
= 1.6pF  
120  
80  
L
R
= 301Ω  
= 500Ω  
F
L
1.6  
1.2  
0.8  
0.4  
0
R
40  
0
-40  
-80  
A
= 2  
V
C
= 1.6pF  
L
-0.4  
-0.8  
R
R
= R = 205Ω  
-120  
-160  
G
L
F
= 500Ω  
TIME (4ns/DIV)  
TIME (4ns/DIV)  
FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE  
FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE  
JEDEC JESD51-3 LOW EFFECTIVE THERMAL  
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
1.2  
CONDUCTIVITY TEST BOARD  
1.4  
1.2  
1
893mW  
1
0.8  
0.6  
0.4  
0.2  
0
0.8  
633mW  
0.6  
0.4  
0.2  
0
0
25  
50  
75 85 100  
125  
150  
0
25  
50  
75 85 100  
125  
150  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
100  
A
= 1, V  
= 2, V  
= 100mV  
P-P  
V
OUT  
OUT  
A
= 2V  
V
P-P  
10  
1
A
1
V =  
A
2
V =  
0.1  
0.1  
1
10  
100  
1000  
FREQUENCY (MHz)  
FIGURE 23. R  
vs FREQUENCY  
OUT  
FN6163.2  
7
September 21, 2005  
ISL59441  
Pin Descriptions  
EQUIVALENT  
CIRCUIT  
PIN NUMBER PIN NAME  
DESCRIPTION  
1, 3, 7  
2
NIC  
IN0  
IN1  
GND  
IN2  
IN3  
S0  
Not Internally Connected; it is recommended this pin be tied to ground to minimize crosstalk  
Circuit 1  
Circuit 1  
Circuit 4  
Circuit 1  
Circuit 1  
Circuit 2  
Circuit 2  
Circuit 4  
Circuit 4  
Circuit 3  
Circuit 1  
Circuit 2  
Input for channel 0  
4
Input for channel 1  
5
Ground pin  
6
Input for channel 2  
8
Input for channel 3  
9
Channel selection pin LSB (binary logic code)  
Channel selection pin MSB (binary logic code)  
Negative power supply  
Positive power supply  
Output  
10  
11  
12  
13  
14  
15  
S1  
V-  
V+  
OUT  
IN-  
Inverting input of output amplifier  
HIZ  
Output disable (active high); there are internal pull-down resistors, so the device will be active with  
no connection; “HI” puts the output in high impedance state  
16  
ENABLE  
Circuit 2  
Device enable (active low); there are internal pull-down resistors, so the device will be active with  
no connection; "HI" puts device into power-down mode  
V+  
V+  
21K  
33K  
+
-
IN  
LOGIC PIN  
1.2V  
GND.  
V-  
V-  
CIRCUIT 1.  
CIRCUIT 2.  
V+  
V+  
OUT  
CAPACITIVELY  
GND  
COUPLED  
ESD CLAMP  
V-  
V-  
CIRCUIT 3.  
CIRCUIT 4.  
AC Tes t Circuits  
ISL59441  
ISL59441  
R
R
R
F
F
R
G
G
A
= 1, 2  
A
= 1, 2  
V
V
TEST  
TEST  
R
S
R
EQUIPMENT  
EQUIPMENT  
S
V
V
IN  
IN  
50Ω or 75Ω  
475Ω  
or  
50Ω  
50Ω  
or  
50Ω  
or  
50Ω  
or  
C
50Ω  
or  
C
L
L
or  
462.5Ω  
75Ω  
75Ω  
75Ω  
75Ω  
75Ω  
FIGURE 24A. TEST CIRCUIT FOR MEASURING WITH A 50Ω OR  
75Ω INPUT TERMINATED EQUIPMENT  
FIGURE 24B. BACKLOADED TEST CIRCUIT FOR VIDEO  
CABLE APPLICATION. BANDWIDTH AND  
LINEARITY FOR R LESS THAN 500Ω WILL BE  
L
DEGRADED.  
NOTE: Figure 24A illustrates the optimum output load when connecting to input terminated equipment. Figure 24B illustrates backloaded test circuit  
for video cable applications.  
FN6163.2  
8
September 21, 2005  
ISL59441  
Application Circuits  
301Ω  
*C  
C
+ C  
T OUT  
L =  
C
-
V
OUT  
V
IN  
+
C
OUT  
0pF  
T
R
500Ω  
L =  
50Ω  
1.6pF  
0.6pF  
C
G
PC BOARD  
CAPACITANCE  
*C : TOTAL LOAD CAPACITANCE  
L
0.4pF < C < 0.7pF  
G
C : TRACE CAPACITANCE  
T
OUT  
C
: OUTPUT CAPACITANCE  
FIGURE 25A. GAIN OF 1 APPLICATION CIRCUIT  
205Ω  
*C  
C
+ C  
T OUT  
L =  
205Ω  
-
V
OUT  
V
IN  
+
C
C
OUT  
0pF  
T
R
500Ω  
L =  
50Ω  
1.6pF  
0.6pF  
C
G
PC BOARD  
CAPACITANCE  
0.4pF < C < 0.7pF  
G
FIGURE 25B. GAIN OF 2 APPLICATION CIRCUIT  
Capacitance at the Output  
Application Information  
General  
The output amplifier is optimized for capacitance to ground  
(C ) directly on the output pin. Increased capacitance  
L
The ISL59441 is a 4:1 mux that is ideal as a matrix element  
in high performance switchers and routers. The ISL59441 is  
optimized to drive 5pF in parallel with a 500Ω load. The  
capacitance can be split between the PCB capacitance and  
an external load capacitance. Its low input capacitance and  
high input resistance provide excellent 50Ω or 75Ω  
terminations.  
causes higher peaking with an increase in bandwidth. The  
optimum range for most applications is ~1.0pF to ~6pF. The  
optimum value can be achieved through a combination of  
PC board trace capacitance (C ) and an external capacitor  
T
(C  
. A good method to maintain control over the output  
OUT)  
pin capacitance is to minimize the trace length (C ) to the  
T
next component, and include a discrete surface mount  
capacitor (C  
) directly at the output pin.  
OUT  
Parasitic Effects on Frequency Performance  
Capacitance at the Inverting Input  
The AC performance of current-feedback amplifiers in the  
non-inverting gain configuration is strongly affected by stray  
capacitance at the inverting input. Stray capacitance from  
the inverting input pin to the output (C ), and to ground (C ),  
increase gain peaking and bandwidth. Large values of either  
capacitance can cause oscillation. The ISL59441 has been  
optimized for a 0.4pF to 0.7pF capacitance (C ).  
Capacitance (C ) to the output should be minimized. To  
F
achieve optimum performance the feedback network  
resistor(s) must be placed as close to the device as possible.  
Trace lengths greater than 1/4 inch combined with resistor  
pad capacitance can result in inverting input to ground  
capacitance approaching 1pF. Inverting input and output  
traces should not run parallel to each other. Small size  
surface mount resistors (604 or smaller) are recommended.  
Feedback Resistor Values  
The AC performance of the output amplifier is optimized with  
the feedback resistor network (R , R ) values  
F
G
recommended in the application circuits. The amplifier  
bandwidth and gain peaking are directly affected by the  
value(s) of the feedback resistor(s) in unity gain and gain >1  
configurations. Transient response performance can be  
tailored simply by changing these resistor values. Generally,  
lower values of R and R increase bandwidth and gain  
F
G
G
F
G
peaking. This has the effect of decreasing rise/fall times and  
increasing overshoot.  
Ground Connections  
For the best isolation and crosstalk rejection, the GND pin  
and NIC pins must connect to the GND plane.  
FN6163.2  
9
September 21, 2005  
ISL59441  
Therefore, adequate current limiting on the digital and  
analog inputs is needed to prevent damage during the time  
the voltages on these inputs are more positive than V+.  
Control Signals  
S0, S1, ENABLE, HIZ - These pins are TTL/CMOS  
compatible control inputs. The S0 pin selects which one of  
the inputs connect to the output. The ENABLE, HIZ pins are  
used to disable the part to save power and three-state the  
output amplifiers, respectively. For control signal rise and fall  
times less than 10ns the use of termination resistors close to  
the part will minimize transients coupled to the output.  
HIZ State  
An internal pull-down resistor connected to the HIZ pin  
ensures the device will be active with no connection to the  
HIZ pin. The HIZ state is established within approximately  
30ns (Figure 18) by placing a logic high (>2V) on the HIZ  
pin. If the HIZ state is selected, the output is a high  
impedance 1.4MΩ. Use this state to control the logic when  
more than one mux shares a common output.  
Power-Up Considerations  
The ESD protection circuits use internal diodes from all pins  
the V+ and V- supplies. In addition, a dV/dT- triggered clamp  
is connected between the V+ and V- pins, as shown in the  
Equivalent Circuits 1 through 4 section of the Pin Description  
table. The dV/dT triggered clamp imposes a maximum  
supply turn-on slew rate of 1V/µs. Damaging currents can  
flow for power supply rates-of-rise in excess of 1V/µs, such  
as during hot plugging. Under these conditions, additional  
methods should be employed to ensure the rate of rise is not  
exceeded.  
In the HIZ state the output is three-stated, and maintains its  
high Z even in the presence of high slew rates. The supply  
current during this state is basically the same as the active  
state.  
ENABLE & Power Down States  
The enable pin is active low. An internal pull-down resistor  
ensures the device will be active with no connection to the  
ENABLE pin. The Power Down state is established when a  
logic high (>2V) is placed on the ENABLE pin. In the Power  
Down state, the output has no leakage but has a large  
capacitance (on the order of 15pF), and is capable of being  
back-driven. Under this condition, large incoming slew rates  
can cause fault currents of tens of mA. Do not use this  
state as a high Z state for applications driving more than  
one mux on a common output.  
Consideration must be given to the order in which power is  
applied to the V+ and V- pins, as well as analog and logic  
input pins. Schottky diodes (Motorola MBR0550T or  
equivalent) connected from V+ to ground and V- to ground  
(Figure 26) will shunt damaging currents away from the  
internal V+ and V- ESD diodes in the event that the V+  
supply is applied to the device before the V- supply.  
If positive voltages are applied to the logic or analog video  
input pins before V+ is applied, current will flow through the  
internal ESD diodes to the V+ pin. The presence of large  
decoupling capacitors and the loading effect of other circuits  
connected to V+, can result in damaging currents through  
the ESD diodes and other active circuits within the device.  
Limiting the Output Current  
No output short circuit current limit exists on this part. All  
applications need to limit the output current to less than  
50mA. Adequate thermal heat sinking of the parts is also  
required.  
V+ SUPPLY  
SCHOTTKY  
V+  
EXTERNAL  
V+  
V-  
PROTECTION  
CIRCUITS  
LOGIC  
LOGIC  
CONTROL  
S0  
POWER  
GND  
V- V+  
GND  
V+  
SIGNAL  
V+  
V-  
OUT  
IN0  
DE-COUPLING  
CAPS  
IN1  
V-  
V-  
V- SUPPLY  
FIGURE 26. SCHOTTKY PROTECTION CIRCUIT  
FN6163.2  
10  
September 21, 2005  
ISL59441  
PC Board Layout  
The frequency response of this circuit depends greatly on  
the care taken in designing the PC board. The following are  
recommendations to achieve optimum high frequency  
performance from your PC board.  
• The use of low inductance components such as chip  
resistors and chip capacitors is strongly recommended.  
• Minimize signal trace lengths. Trace inductance and  
capacitance can easily limit circuit performance. Avoid  
sharp corners, use rounded corners when possible. Vias  
in the signal lines add inductance at high frequency and  
should be avoided. PCB traces greater than 1" begin to  
exhibit transmission line characteristics with signal rise/fall  
times of 1ns or less. High frequency performance may be  
degraded for traces greater than one inch, unless strip  
lines are used.  
• Match channel-channel analog I/O trace lengths and  
layout symmetry. This will minimize propagation delay  
mismatches.  
• Maximize use of AC de-coupled PCB layers. All signal I/O  
lines should be routed over continuous ground planes (i.e.  
no split planes or PCB gaps under these lines). Avoid vias  
in the signal I/O lines.  
• Use proper value and location of termination resistors.  
Termination resistors should be as close to the device as  
possible.  
• When testing use good quality connectors and cables,  
matching cable types and keeping cable lengths to a  
minimum.  
• Minimum of 2 power supply de-coupling capacitors are  
recommended (1000pF, 0.01µF) as close to the device as  
possible. Avoid vias between the cap and the device  
because vias add unwanted inductance. Larger caps can  
be farther away. When vias are required in a layout, they  
should be routed as far away from the device as possible.  
• The NIC pins are placed on both sides of the input pins.  
These pins are not internally connected to the die. It is  
recommended these pins be tied to ground to minimize  
crosstalk.  
FN6163.2  
11  
September 21, 2005  
ISL59441  
QSOP Package Outline Drawing  
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at  
<http://www.intersil.com/design/packages/index.asp>  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN6163.2  
12  
September 21, 2005  

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