ISL59531IKZ [INTERSIL]

16x16 Video Crosspoint with Differential Inputs; 16×16视频交叉点,差分输入
ISL59531IKZ
型号: ISL59531IKZ
厂家: Intersil    Intersil
描述:

16x16 Video Crosspoint with Differential Inputs
16×16视频交叉点,差分输入

文件: 总21页 (文件大小:1195K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ISL59531  
®
Data Sheet  
March 21, 2006  
FN6251.0  
PRELIMINARY  
16x16 Video Crosspoint with Differential  
Inputs  
Features  
• 16x16 non-blocking switch with differential inputs and  
outputs  
The ISL59531 is a 16x16 integrated video crosspoint switch  
matrix with differential input and On-Screen Display (OSD)  
insertion. The ISL59531 is ideal for routing video signals in  
security and video-on-demand systems. This device  
operates from a single +5V supply. Any output of the 16  
video inputs cable can be switched to any of the 16 outputs.  
OSD information can be inserted into any output through an  
internal, dedicated fast 2:1 mux (15ns switching times)  
located before the output buffer. Also, any input can be  
broadcast to all 16 outputs. Each output can be tri-stated  
and its gain set to +1 or +2 through the SPI interface.  
• Operates from a single +5V supply  
• Output gain switchable +1 or +2  
• SPI digital interface  
• Tri-state output  
• -90dB Isolation at 6MHz  
• 0.025%/0.05° dG/dP  
• Pb-free plus anneal available (RoHS compliant)  
The ISL59531 offers a -3dB signal bandwidth of 320MHz.  
The differential gain and differential phase of 0.025%, along  
with 0.1dB flatness out to 50MHz, making the ISL59531  
suitable for many video applications.  
Applications  
• Security camera switching  
• RGB routing  
The switch matrix configuration and output buffer gain are  
programmed through an SPI/QSPI™-compatible three-wire  
serial interface. The ISL59531 interface is set up to facilitate  
both fast updates and initialization. On power-up, all outputs  
are initialized in the disabled state to avoid output conflicts  
within the user system. The ISL59531 has single-supply  
signal operation. It can accommodate input common mode  
voltages from 0V to 3.5V and 0V to 4V at the outputs.  
• HDTV routing  
Ordering Information  
PART  
NUMBER  
TAPE & REEL  
PACKAGE  
PKG. DWG. #  
ISL59531IKZ  
(See Note)  
-
356-Pin BGA  
(Pb-free)  
V356.27x27  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
The ISL59531 is available in a 356-pin BGA package and  
specified over an extended -40°C to +85°C temperature  
range.  
The ISL59530 is a single-ended input version of this device.  
For capacitor-coupled applications, the ISL59530 inputs  
include a clamp circuit that restores the input level to an  
externally applied reference.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2006. All Rights Reserved.  
All other trademarks mentioned are the property of their respective owners.  
ISL59531  
Pinout  
ISL59531  
(356-PIN BGA)  
TOP VIEW  
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20  
A
B
C
D
E
F
In12  
In13  
In14  
In15  
Over15  
Out15  
Vover15  
Vs  
Over14  
Out14  
Vover14  
Vs  
Out13  
Over13  
Vover13  
Vs  
Out12  
Over12  
Vover12  
Inb12  
Inb13  
Inb14  
Inb15  
In11 Inb11 Vlogic Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs Vover11 Out11 Over11  
Vs  
In10 Inb10  
Vs  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd Gnd  
Vs Vover10Out10Over10  
G
H
J
Sout Vs  
Vs  
In9 Inb9 Reset Vs  
Senb Vs  
Vs Vover9 Over9 Out9  
Vs  
K
L
In8 Inb8 Clock Vs  
Vs Vover8Over8 Out8  
Sdi  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
M
N
P
R
T
In7 Inb7 Ref  
Vs Vover7 Out7 Over7  
Vs  
In6 Inb6  
In5 Inb5  
Vs Vover6 Out6 Over6  
Vs  
Vs Vover5 Over5 Out5  
U
V
W
Y
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
Vs  
In4 Inb4  
Inb3  
Spare1Spare0  
Diode Vover0  
Over0  
Vover1  
Over1  
Out1  
Vover2  
Out2  
Vover3  
Out3  
Vover4 Over4 Out4  
Inb2  
In2  
Inb1  
In1  
Inb0  
In0  
In3  
Out0  
Over2  
Over3  
= Empty location (unpopulated)  
= Ballgrid  
Pad name "GND" is the same as package or ball name "ground" or "G"  
Pad name "VS" is the same as package or ball name "power" or "P"  
Pad X, Y is from pad center. All pads are 70µ by 70µ  
FN6251.0  
2
March 21, 2006  
ISL59531  
Absolute Maximum Ratings (T = 25°C)  
A
Supply Voltage between V and GND. . . . . . . . . . . . . . . . . . . . 5.5V  
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 40mA  
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests  
are at the specified temperature and are pulsed tests, therefore: T = T = T  
A
J
C
DC Electrical Specifications  
V = 5V  
S
PARAMETER  
DESCRIPTION  
CONDITION  
MIN  
4.5  
TYP  
MAX  
5.5  
5.5  
1.03  
2.06  
1.5  
1.0  
3.5  
4.0  
0
UNIT  
V
V
Supply Range  
S
D
V
Digital Supply  
Gain  
Establishes serial output high level  
= 1, R = 500Ω  
1.2  
V
A
A
0.97  
1.94  
-1.5  
1
2
V/V  
V/V  
%
V
V
L
A = 2, R = 150Ω  
V
L
GM  
Gain Matching (to average of all other  
outputs)  
A
= 1  
= 2  
= 1  
1
V
A
0.5  
%
V
V
V
Input Voltage Range  
Output Voltage Range  
Input Bias Current  
A
0
V
IN  
V
A
= 2, R = 150Ω  
0
V
OUT  
V
L
I
-10  
-25  
-70  
60  
25  
-5  
0
µA  
mV  
mV  
mA  
mA  
dB  
mA  
mA  
mA  
mA  
B
V
Output Offset Voltage  
A
= 1  
= 2  
25  
OS  
V
A
0
70  
V
I
Output Current  
Sourcing, R = 10to GND  
100  
35  
80  
312  
140  
0.8  
7
OUT  
L
Sinking, R to 2.5V  
L
PSRR  
Power Supply Rejection Ratio  
Supply Current  
I
Enabled, all outputs enable, no load current  
Enable, all outputs disable, no load current  
Disabled  
375  
1.1  
S
Supply current per output channel  
AC Electrical Specifications  
PARAMETER  
BW -3dB  
BW 0.1dB  
SR  
DESCRIPTION  
CONDITION  
MIN  
TYP  
320  
50  
MAX  
UNIT  
MHz  
MHz  
V/µs  
ns  
3dB Bandwidth  
0.1dB Bandwidth  
Slew Rate  
V
V
V
V
= 200mV , A = 2  
P-P  
OUT  
OUT  
OUT  
OUT  
V
= 200mV , A = 2  
P-P  
V
= 2V , A = 2  
P-P  
360  
520  
12  
V
T
Settling Time to 0.1%  
Switching Glitch, Peak  
Overlay Delay Time  
Diff Gain  
= 2V , A = 2  
P-P  
S
V
Glitch  
A
= 1  
40  
mV  
V
T
Beginning of output transition  
6
ns  
over  
dG  
dP  
Xt  
A
= 2, R = 150Ω  
0.025  
0.05  
-85  
42  
%
V
L
Diff Phase  
A
= 2, R = 150Ω  
°
V
L
Hostile Crosstalk  
Input Noise Voltage  
6MHz  
dB  
V
nV/Hz  
N
FN6251.0  
3
March 21, 2006  
ISL59531  
Pin Descriptions (Continued)  
Pin Descriptions  
NAME  
NUMBER  
DESCRIPTION  
NAME  
INB2  
IN2  
NUMBER  
W4  
Y4  
DESCRIPTION  
Complementary input  
IN13  
A3  
Input  
INPUT TEST  
BAR  
NONE  
Manufacturing test pin - leave open  
Input  
INB3  
IN3  
W2  
Y2  
Complementary input  
Input  
GND  
GND  
VS  
GND  
GND  
VS  
Ground  
Ground  
REF  
GND  
SDI  
M3  
GND  
L3  
Output reference  
Ground  
Power supply  
Power supply  
VS  
VS  
Serial data input  
Power supply  
Complementary input  
Input  
VLOGIC  
D3  
Logic power supply for serial output  
driver  
VS  
VS  
V2  
INB4  
IN4  
INB14  
IN14  
B5  
A5  
Complementary input  
Input  
V1  
INB5  
IN5  
T2  
Complementary input  
Input  
INB15  
B7  
Complementary input  
Input  
T1  
IN15  
A7  
VS  
VS  
GND  
P2  
Power supply  
Ground  
VSL  
VS  
Power supply  
Ground  
GND  
INB6  
IN6  
VGL  
GND  
VS  
Complementary input  
Input  
VS  
Power supply  
Ground  
P1  
GND  
GND  
A11  
C11  
B11  
A13  
C13  
B13  
GND  
VS  
INB7  
IN7  
M2  
M1  
K3  
Complementary input  
Input  
OVER15  
VOVER15  
OUT15  
OVER14  
VOVER14  
OUT14  
GND  
Overlay logic control  
Overlay analog input  
Output  
CLOCK  
VS  
Serial data clock  
Power supply  
Serial enable-inverted  
Ground  
VS  
J3  
Overlay logic control  
Overlay analog input  
Output  
SENB  
GND  
INB8  
IN8  
GND  
K2  
Complementary input  
Input  
Ground  
K1  
VS  
Power supply  
Output  
INB9  
IN9  
H2  
Complementary input  
Input  
OUT13  
VOVER13  
OVER13  
OUT12  
VOVER12  
OVER12  
GND  
A15  
C15  
B15  
A17  
C17  
B17  
GND  
NONE  
VS  
H1  
Overlay analog input  
Overlay logic control  
Output  
VS  
VS  
GND  
F2  
Power supply  
Ground  
GND  
INB10  
IN10  
INB11  
IN11  
RESET  
VS  
Complementary input  
Input  
Overlay analog input  
Overlay logic control  
Ground  
F1  
D2  
Complementary input  
Input  
D1  
OUT TEST 3  
VS  
Manufacturing test pin - leave open  
Power supply  
Overlay logic control  
Overlay analog input  
Output  
H3  
Reset input  
VS  
G3  
GND  
B1  
Power supply  
Serial data output  
Ground  
OVER11  
VOVER11  
OUT11  
OVER10  
VOVER10  
OUT10  
D20  
D18  
D19  
F20  
F18  
F19  
SOUT  
GND  
INB12  
IN12  
INB13  
Complementary input  
Input  
Overlay logic control  
Overlay analog input  
Output  
A1  
B3  
Complementary input  
FN6251.0  
March 21, 2006  
4
ISL59531  
Pin Descriptions (Continued)  
Pin Descriptions (Continued)  
NAME  
NUMBER  
GND  
VS  
DESCRIPTION  
NAME  
VOVER0  
OVER0  
VS  
NUMBER  
V10  
W10  
VS  
DESCRIPTION  
GND  
Ground  
Overlay analog input  
VS  
Power supply  
Overlay logic control  
Power supply  
OUT9  
H20  
H18  
H19  
K20  
K18  
K19  
NONE  
GND  
VS  
Output  
VOVER9  
OVER9  
OUT8  
Overlay analog input  
Overlay logic control  
Output  
OUT TEST 0  
GND  
NONE  
GND  
Y8  
Manufacturing test pin - leave open  
Ground  
IN0  
Input  
VOVER8  
OVER8  
OUT TEST 2  
GND  
Overlay analog input  
Overlay logic control  
Manufacturing test pin - leave open  
Ground  
INB0  
W8  
Complementary input  
Input  
IN1  
Y6  
INB1  
W6  
Complementary input  
DIODE  
V9  
Anode of a ground-connected diode:  
useful for measuring die temperature  
VS  
Power supply  
VS  
GND  
VS  
GND  
VS  
Power supply  
OVER7  
VOVER7  
OUT7  
M20  
M18  
M19  
P20  
P18  
P19  
GND  
VS  
Overlay logic control  
Overlay analog input  
Output  
Ground  
VS  
Power supply  
GND  
GND  
V6  
Ground  
OVER6  
VOVER6  
OUT6  
Overlay logic control  
Overlay analog input  
Output  
SPARE0  
SPARE1  
Not assigned-do not connect  
Not assigned-do not connect  
V5  
GND  
Ground  
VS  
Power supply  
OUT5  
T20  
Output  
VOVER5  
OVER5  
OUT4  
T18  
Overlay analog input  
Overlay logic control  
Output  
T19  
V20  
V18  
V19  
VS  
VOVER4  
OVER4  
VS  
Overlay analog input  
Overlay logic control  
Power supply  
OUT TEST 1  
GND  
NONE  
GND  
Y16  
V16  
W16  
Y14  
V14  
W14  
VS  
Manufacturing test pin - leave open  
Ground  
OVER3  
VOVER3  
OUT3  
Overlay logic control  
Overlay analog input  
Output  
OVER2  
VOVER2  
OUT2  
Overlay logic control  
Overlay analog input  
Output  
VS  
Power supply  
GND  
GND  
Y12  
V12  
W12  
Y10  
Ground  
OUT1  
Output  
VOVER1  
OVER1  
OUT0  
Overlay analog input  
Overlay logic control  
Output  
FN6251.0  
5
March 21, 2006  
ISL59531  
Typical Performance Curves  
15pF  
V =+5V  
15pF  
s
V
=+5V  
= 2  
S
A
= 1  
V
A
V
R
= 100Ω  
L
R
= 100Ω  
L
10pF  
INPUT_CH 0  
INPUT_CH 0  
OUTPUT_CH 0  
10pF  
OUTPUT_CH 0  
4.7pF  
0pF  
4.7pF  
0pF  
FIGURE 1. FREQUENCY RESPONSE - VARIOUS C , A = 1,  
FIGURE 2. FREQUENCY RESPONSE - VARIOUS C , A = 2,  
L V  
L
V
MUX MODE  
MUX MODE  
V
=+5V  
S
V
=+5V  
= 1  
S
A
= 2  
= 0  
V
A
V
C
L
C
= 0pF  
L
INPUT_CH 0  
150Ω  
150Ω  
INPUT_CH 0  
50Ω  
50Ω  
OUTPUT_CH 0  
OUTPUT_CH 0  
500Ω  
1.03kΩ  
500Ω  
1.03kΩ  
FIGURE 3. FREQUENCY RESPONSE - VARIOUS R , A = 1,  
FIGURE 4. FREQUENCY RESPONSE - VARIOUS R , A = 2,  
L V  
L
V
MUX MODE  
MUX MODE  
Overlay mode  
Overlay mode  
A
= 2  
V
A
= 1  
V
R
= 100Ω  
L
R
= 100Ω  
L
C =0pF  
L
C =0pF  
L
INPUT_CH 15  
INPUT_CH 15  
OUTPUT_CH 15  
OUTPUT_CH 31  
FIGURE 5. FREQUENCY RESPONSE - OVERLAY INPUT,  
= 1  
FIGURE 6. FREQUENCY RESPONSE - OVERLAY INPUT,  
= 2  
A
A
V
V
FN6251.0  
6
March 21, 2006  
ISL59531  
Typical Performance Curves (Continued)  
V
=+5V  
= 2  
V
=+5V  
= 1  
S
S
15pF  
10pF  
A
A
V
V
R
= 100Ω  
R
= 100Ω  
L
L
15pF  
10pF  
INPUT_CH 0  
INPUT_CH 0  
OUTPUT_CH 0  
OUTPUT_CH 0  
4.7pF  
4.7pF  
0pF  
0pF  
FIGURE 7. FREQUENCY RESPONSE - VARIOUS C , A = 1,  
FIGURE 8. FREQUENCY RESPONSE - VARIOUS C , A = 2,  
L V  
L
V
BROADCAST MODE  
BROADCAST MODE  
V
A
=+5V  
V
=+5V  
= 1  
S
S
= 2  
A
V
V
50Ω  
C
= 0pF  
C
= 0pF  
L
L
150Ω  
INPUT_CH 0  
INPUT_CH 0  
150KΩ  
50Ω  
OUTPUT_CH 0  
OUTPUT_CH 0  
503Ω  
503kΩ  
1.03KΩ  
1.03kΩ  
FIGURE 9A. FREQUENCY RESPONSE - VARIOUS R , A = 1,  
FIGURE 10. FREQUENCY RESPONSE - VARIOUS R , A = 2,  
L
V
L
V
BROADCAST MODE  
BROADCAST MODE  
A
L
L
= 2  
A
L
L
= 1  
V
V
ADJACENT  
INPUT_CH14  
OUTPUT_CH15  
ADJACENT  
INPUT_CH14  
OUTPUT_CH15  
R
C
= 100Ω  
= 0  
R
C
= 100Ω  
= 0  
ALL HOSTILE  
INPUT_CH0  
ALL HOSTILE  
INPUT_CH0  
OUTPUT_CH31  
OUTPUT_CH15  
FIGURE 11. CROSSTALK - A = 1  
V
FIGURE 12. CROSSTALK - A = 2  
V
FN6251.0  
7
March 21, 2006  
ISL59531  
Typical Performance Curves (Continued)  
V
=+5V  
S
THD  
A =2  
V
THD  
R =100Ω  
L
INPUT_CH 0  
OUTPUT_CH 0  
FREQUENCY = 1MHz  
2nd HD  
V
=+5V  
S
A =2  
2nd HD  
V
R =100Ω  
L
INPUT_CH 0  
3rd HD  
OUTPUT_CH 0  
3rd HD  
V
=2V  
OP-P  
FIGURE 13. HARMONIC DISTORTION vs FREQUENCY  
FIGURE 14. HARMONIC DISTORTION vs V  
OUT_P-P  
FIGURE 15. DISABLE OUTPUT IMPEDANCE  
FIGURE 16. ENABLE OUTPUT IMPEDANCE  
MUX MODE  
A
= 1  
V
R
= 100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FALL TIME  
2.65ns  
RISE TIME  
2.35ns  
MUX MODE  
A
= 1  
V
R
= 100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FIGURE 17. RISE TIME - A = 1  
V
FIGURE 18. FALL TIME - A = 1  
V
FN6251.0  
8
March 21, 2006  
ISL59531  
Typical Performance Curves (Continued)  
MUX MODE  
A
= 2  
V
R
= 100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FALL TIME  
2.35ns  
RISE TIME  
2.19ns  
MUX MODE  
A
= 2  
V
R
= 100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FIGURE 19. RISE TIME - A = 2  
FIGURE 20. FALL TIME - A = 2  
V
V
MUX MODE  
A
= 1  
V
R =100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
SLEW RATE  
-436V/µs  
SLEW RATE  
448V/µs  
MUX MODE  
A
= 1  
V
R =100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FIGURE 21. RISING SLEW RATE - A = 1  
V
FIGURE 22. FALLING SLEW RATE - A = 1  
V
MUX MODE  
A
= 2  
V
R =100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
SLEW RATE  
-511V/µs  
SLEW RATE  
531V/µs  
MUX MODE  
A
= 2  
V
R =100Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
FIGURE 23. RISING SLEW RATE - A = 2  
V
FIGURE 24. FALLING SLEW RATE - A = 2  
V
FN6251.0  
March 21, 2006  
9
ISL59531  
Typical Performance Curves (Continued)  
OUTPUT  
OUTPUT  
OVERLAY  
LOGIC  
OVERLAY  
LOGIC  
INPUT  
INPUT  
FIGURE 25. OVERLAY SWITCH TURN-ON DELAY TIME  
FIGURE 26. OVERLAY SWITCH TURN-OFF DELAY TIME  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 27. DIFFERENTIAL GAIN, A = 2  
V
FIGURE 28. DIFFERENTIAL PHASE, A = 2  
V
A
= 2  
A
= 2  
V
V
R
= 150Ω  
R
= 150Ω  
L
L
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 29. DIFFERENTIAL GAIN, A = 2  
V
FIGURE 30. DIFFERENTIAL PHASE, A = 2  
V
FN6251.0  
March 21, 2006  
10  
ISL59531  
Typical Performance Curves (Continued)  
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 15  
OUTPUT_CH15  
OSC = 40mV  
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 31. DIFFERENTIAL GAIN, A = 1  
V
FIGURE 32. DIFFERENTIAL PHASE, A = 1  
V
A
= 1  
A
= 1  
V
V
R
= 150Ω  
R
= 150Ω  
L
L
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
INPUT_CH 15  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 33. DIFFERENTIAL GAIN, A = 1  
V
FIGURE 34. DIFFERENTIAL GAIN, A = 1  
V
A
= 2  
A
= 2  
V
V
R
= 150Ω  
R
= 150Ω  
L
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 35. DIFFERENTIAL GAIN, A = 2  
V
FIGURE 36. DIFFERENTIAL PHASE, A = 2  
V
FN6251.0  
March 21, 2006  
11  
ISL59531  
Typical Performance Curves (Continued)  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 37. DIFFERENTIAL GAIN, A = 2  
FIGURE 38. DIFFERENTIAL PHASE, A = 2  
V
V
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 39. DIFFERENTIAL GAIN, A = 1  
FIGURE 40. DIFFERENTIAL PHASE, A = 1  
V
V
A
= 1  
A
= 1  
V
V
R
= 150Ω  
R
= 150Ω  
L
L
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
INPUT_CH 00  
OUTPUT_CH 15  
OSC = 40mV  
FIGURE 41. DIFFERENTIAL GAIN, A = 1  
V
FIGURE 42. DIFFERENTIAL PHASE, A = 1  
V
FN6251.0  
March 21, 2006  
12  
ISL59531  
Typical Performance Curves (Continued)  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 00  
OSC = 40mV  
A
= 2  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 00  
OSC = 40mV  
FIGURE 43. DIFFERENTIAL GAIN, OVERLAY, A = 2  
FIGURE 44. DIFFERENTIAL PHASE, OVERLAY, A = 2  
V
V
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 00  
OSC = 40mV  
A
= 1  
V
R
= 150Ω  
L
INPUT_CH 00  
OUTPUT_CH 00  
OSC = 40mV  
FIGURE 45. DIFFERENTIAL GAIN, OVERLAY, A = 1  
V
FIGURE 46. DIFFERENTIAL PHASE, OVERLAY, A = 1  
V
FN6251.0  
March 21, 2006  
13  
ISL59531  
3dB Bandwidth, MUX Mode, A = 1, R = 100[MHz]  
V
L
INPUT CHANNELS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
255  
244  
257  
264  
255  
253  
247  
253  
255  
241  
235  
223  
220  
211  
199  
193  
229  
217  
229  
210  
222  
221  
224  
190  
180  
186  
183  
174  
176  
171  
174  
175  
169  
168  
164  
161  
160  
160  
222  
169  
168  
171  
175  
177  
177  
178  
184  
187  
188  
186  
188  
192  
192  
194  
197  
152  
233  
190  
212  
189  
207  
193  
166  
160  
169  
171  
167  
173  
170  
178  
183  
182  
185  
186  
185  
189  
193  
238  
2
235  
204  
3
217  
219  
4
220  
202  
5
218  
237  
6
226  
230  
231  
210  
157  
163  
168  
165  
7
227  
236  
235  
240  
218  
239  
223  
223  
228  
236  
240  
241  
223  
242  
219  
222  
217  
235  
211  
213  
8
9
10  
11  
12  
13  
14  
15  
236  
230  
207  
185  
225  
217  
209  
202  
205  
198  
214  
207  
224  
223  
212  
217  
197  
197  
216  
186  
177  
225  
3dB Bandwidth, MUX Mode, A = 2, R = 100[MHz]  
V
L
INPUT CHANNELS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
295  
268  
277  
279  
269  
263  
259  
263  
262  
253  
253  
246  
241  
236  
233  
227  
316  
290  
290  
397  
384  
405  
395  
220  
211  
216  
213  
201  
201  
196  
201  
203  
194  
194  
187  
184  
182  
178  
183  
288  
183  
192  
196  
192  
196  
196  
205  
212  
210  
215  
213  
216  
220  
220  
223  
240  
299  
250  
385  
234  
396  
291  
188  
183  
196  
196  
192  
200  
200  
211  
216  
214  
216  
217  
225  
225  
230  
293  
2
300  
289  
3
408  
392  
4
391  
402  
5
407  
298  
6
404  
398  
394  
388  
283  
407  
411  
410  
7
411  
407  
307  
308  
402  
402  
387  
383  
412  
412  
307  
300  
402  
403  
387  
385  
413  
415  
398  
394  
8
9
10  
11  
12  
13  
14  
15  
417  
293  
276  
385  
367  
412  
400  
412  
396  
391  
379  
272  
244  
419  
413  
279  
274  
396  
385  
407  
230  
324  
FN6251.0  
14  
March 21, 2006  
ISL59531  
3dB Bandwidth, Broadcast Mode, A = 1, R = 100[MHz]  
V
L
INPUT CHANNELS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
215  
214  
210  
212  
206  
203  
201  
204  
204  
202  
196  
194  
193  
191  
189  
187  
198  
195  
195  
183  
184  
188  
172  
178  
174  
171  
171  
169  
165  
163  
167  
167  
164  
160  
157  
156  
151  
151  
153  
151  
152  
153  
157  
157  
159  
159  
167  
171  
170  
169  
171  
171  
174  
175  
178  
145  
157  
145  
140  
146  
144  
144  
158  
158  
159  
164  
164  
164  
164  
170  
175  
174  
178  
174  
178  
178  
178  
181  
2
188  
147  
3
178  
143  
4
174  
150  
5
177  
161  
6
156  
160  
161  
157  
151  
156  
160  
160  
7
187  
187  
182  
183  
170  
172  
170  
171  
175  
176  
168  
172  
157  
160  
151  
155  
158  
161  
154  
159  
8
9
10  
11  
12  
13  
14  
15  
170  
169  
161  
160  
162  
157  
156  
160  
170  
167  
164  
166  
172  
173  
162  
164  
155  
161  
149  
167  
179  
167  
3dB Bandwidth, Broadcast Mode, A = 2, R = 100[MHz]  
V
L
INPUT CHANNELS  
0
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
0
1
234  
232  
228  
229  
223  
219  
217  
220  
220  
218  
220  
212  
211  
209  
208  
205  
216  
215  
209  
199  
204  
205  
190  
196  
193  
189  
191  
186  
183  
181  
183  
184  
181  
176  
174  
174  
170  
167  
166  
169  
169  
171  
175  
177  
177  
178  
184  
187  
188  
186  
188  
192  
192  
194  
197  
160  
172  
162  
158  
163  
161  
161  
178  
178  
178  
182  
183  
183  
183  
189  
193  
193  
192  
192  
195  
195  
196  
198  
2
204  
164  
3
196  
163  
4
193  
168  
5
192  
177  
6
174  
175  
177  
174  
167  
173  
178  
178  
7
204  
205  
198  
199  
189  
190  
190  
191  
192  
193  
184  
188  
174  
178  
169  
173  
174  
178  
172  
178  
8
9
10  
11  
12  
13  
14  
15  
185  
176  
187  
195  
179  
171  
177  
184  
179  
172  
176  
179  
187  
184  
181  
185  
191  
191  
181  
182  
160  
185  
FN6251.0  
15  
March 21, 2006  
ISL59531  
Block Diagram  
VS+ VOVERn OVERn  
16  
16  
LOGIC  
OVERLAY  
INPUT  
CONTROL  
-
+
V
0
IN  
POWER-ON  
SWITCH  
MATRIX  
16 INPUTS  
16 OUTPUTS  
-
+
V
15  
IN  
REF  
A
V
+1, +2  
OUTPUT  
ENABLE  
POWER-ON  
SDI  
CLK  
SPI INTERFACE, REGISTER  
SDO  
ENA  
ENA signal. While the ENA is low, the data on the SDI (serial  
data input) pin is shifted into the 16-bit shift register on the  
positive edge of the SCLK (serial clock) signal. The LSB  
(bit 0) is loaded first and the MSB (bit 15) is loaded last (see  
Table 1). After the full 16-bit data has been loaded, the ENA  
is pulled high and the addressed output channel is updated.  
The SCLK is disabled internally when the ENA is high. The  
SCLK must be low before the ENA is pulled low.  
General Description  
The ISL59531 is a 16x16 integrated video crosspoint switch  
matrix with differential input and output buffers and On-  
Screen Display (OSD) insertion. This device operates from a  
single +5V supply. Any output can be switched to any of the  
16 input video signal sources and OSD information through  
an internal, dedicated fast 2:1 mux located before the output  
buffer. Also, any one input can be broadcast to all 16  
outputs.  
The Serial Timing Diagram and parameters table show the  
timing requirements for three-wire signals.  
Each output X is defined as:  
Voutx = Avx*(INx-INBx+REF)  
Where Avx = 1, or Avx = 2. Note that all REF’s are common  
between channels and must be externally well buffered  
and/or bypassed.  
The ISL59531 offers a -3dB signal bandwidth of 320MHz.  
The differential gain and differential phase of 0.025% and  
0.05° respectively, along with 0.1dB flatness out to 50MHz.  
The switch matrix configuration and output buffer gain are  
programmed through an SPI/QSPI™-compatible, three-wire  
serial interface. The ISL59531 interface is set up to facilitate  
both fast updates and initialization. On power-up, all facilities  
are initialized in the disabled state to avoid output conflicts  
within the user system.  
Digital Interface  
The ISL59531 uses a simple 3-wire SPI compliant digital  
interface to program the outputs. The ISL59531 can support  
the clock rate up to 5MHz.  
Serial Interface  
The ISL59531 is programmed through a three-wire serial  
interface. The start and stop conditions are defined by the  
FN6251.0  
16  
March 21, 2006  
ISL59531  
Serial Timing Diagram  
t
E
ENA  
T
t
t
t
t
SE  
r
f
HE  
SCLK  
t
t
HD  
t
SD  
w
B14  
B15  
SDI  
B0  
B1  
B2  
B12-B2  
t
MSB  
LSB  
LOAD MSB FIRST, LSB LAST  
TABLE 1. SERIAL TIMING PARAMETERS  
PARAMETER  
RECOMMENDED OPERATING RANGE  
DESCRIPTION  
T
200ns  
20ns  
20ns  
20ns  
20ns  
0.50 * T  
Clock Period  
t
ENA Hold Time  
ENA Setup Time  
Data Hold Time  
HE  
t
SE  
t
HD  
t
Data Setup Time  
Clock Pulse Width  
SD  
t
W
Programming Model  
The device has power-on reset that disables outputs, disables test mode, and turns off analog currents. To start up the device the  
control word is sent:  
TABLE 2. CONTROL WORD FORMAT  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
1
1
1
-
-
-
-
0
--0  
0
0
0
0
0
Power on  
Common  
output enable  
It is important to always program control bits 2-8 as zeros to avoid activating test modes designed for device manufacturing.The  
clamp bit activates the input clamp and bleed current sink and works only in the single-ended version.  
To enable individual outputs, the output enable control word is sent. There are 16 enables to set; this is done with serial words  
controlling four at a time. The output enable control word format is:  
TABLE 3. OUTPUT ENABLE FORMAT  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
-
-
-
N1  
N0  
-
O
-
O
-
O
-
O
n
n+3  
n+2  
n+1  
The O bits represent output enables of eight individual registers. The N1 and N0 bits represent a two bit binary number which is  
x
N1N0  
used in setting n = 2  
. For instance, to access the control bit of the 5th output enable, we send the word:  
TABLE 4. OUTPUT ENABLE WORD OF 2ND GROUP OF OUTPUTS  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
1
-
-
-
0
1
-
O
O
-
1
-
O
4
7
-
6
Individual output enables are ended with the control register’s common output enable bit and the power on bit.  
FN6251.0  
17  
March 21, 2006  
ISL59531  
Gain Setting  
The gain of each output may be set to 1 or 2 using the gain set word. It is in the same format as the output enable control word:  
TABLE 5. GAIN SET FORMAT  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
1
0
-
-
-
N1  
N0  
-
G
-
G
-
G
-
G
n
n+3  
n+2  
n+1  
Input to Output Selection  
Individual outputs receive their input selection choice using the input/output control word. Its format is:  
TABLE 6. INPUT/OUTPUT WORD  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
0
0
I
I
I
I
0
-
-
-
O
O
O
O
0
0
3
2
1
0
3
2
1
For a given binarily selected output, as specified by the O's, an input channel is assigned by the binarily selected I's. Sixteen  
transmissions of the input/output control words will be required to set up all outputs. Note that B8 and B0 must be logic 0.  
Broadcast Mode  
The broadcast mode routs one input to all 16 outputs. It has a memory bit that remembers its state. The configuration of  
input/output assignments that existed before setting broadcast mode is kept in memory and when broadcast mode is disabled the  
previous configuration is restored. The broadcast control word format is:  
TABLE 7. BROADCAST WORD  
B15  
B14  
B13  
B12  
B11  
B10  
B9  
B8  
B7  
B6  
B5  
B4  
B3  
B2  
B1  
B0  
0
1
1
I
I
I
I
0
0
-
-
-
-
-
-
-
EB  
3
2
1
EB sets or resets the broadcast mode memory bit. The I's binarily select the input channel to be broadcast to all outputs. Note that  
B8 must be logic 0.  
mode. In addition, output buffer gain of +2 has higher  
bandwidth than gain of +1 due to internal device  
compensation. Therefore, the highest bandwidth set-up is  
multiplexer mode and output buffer gain of +2.  
Bandwidth Considerations  
Wide frequency response (high bandwidth) in a video  
system means better video resolution. Four sets of  
frequency response curves are shown in Figure 47.  
Depending on the switch configurations, one can get  
between 250MHz to 350MHz bandwidth. A short discussion  
of the trade-offs follows—including matrix configuration,  
output buffer gain selection, channel selection, and loading.  
The relative location of the input and output channel also has  
significant impact on the device bandwidth. Again this is due  
to the layout of the device. When the input and output  
channels are further away, there are additional parasitics as  
a result of the distance and lower bandwidth results.  
2
Mux, Av = 2  
The bandwidth does not change significantly with resistive  
loading as shown in figure 3 in the typical performance  
curves. However, it does change greatly with capacitance  
loading, Figure 4 in typical performance curves. This is most  
significant when laying out the PCB. If the PCB trace  
between the output of the crosspoint switch and the back  
termination resistor is not minimized, additional parasitic  
capacitance severely distorts the frequency response.  
0
-2  
Mux, Av = 1  
Broadcast,  
Av = 2  
Broadcast,  
-4  
Av = 1  
-6  
-8  
-10  
1
10  
100  
1000  
To emphasize how critical the PCB layout is to performance,  
let’s compare the two boards presented in figures 48 and 49.  
Figure 48 shows a larger engineering evaluation board  
where the termination resistor is far away from the device  
because of the use of a socket. The board in figure 48 is a  
demoboard without the socket. The parasitic capacitance of  
the demoboard is about 2.7pF less.  
Frequency [MHz]  
FIGURE 47. FREQUENCY RESPONSE FOR VARIOUS MODES  
In multiplexer mode, the input only drives one output  
channel, while in broadcast mode the same input drives all  
16 outputs. The parasitic capacitance of all 16 channels  
loads down the input and reduces bandwidth in broadcast  
18  
ISL59531  
Linear Operating Region  
In addition to bandwidth, one must also be very careful with  
operating the device at its linear operating region. Figure 50  
shows differential gain curve. The ISL59534 is a single  
supply 5V device with its linear region is between 0.1 and  
2V.  
FIGURE 48. ENGINEERING EVALUATION BOARD  
FIGURE 50. DIFFERENTIAL GAIN RESPONSE  
Power Dissipation and Thermal Resistance  
With a large number of switches, it is possible to exceed the  
150°C absolute maximum junction temperature under  
certain load current conditions. Therefore, it is important to  
calculate the maximum junction temperature for an  
application to determine if load conditions or package types  
need to be modified to assure operation of the crosspoint  
switch in a safe operating area.  
The maximum power dissipation allowed in a package is  
determined according to:  
T
T  
AMAX  
JMAX  
PD  
= --------------------------------------------  
MAX  
Θ
JA  
Where:  
• T  
• T  
= Maximum junction temperature = 125°C  
= Maximum ambient temperature = 85°C  
JMAX  
FIGURE 49. CUSTOMER DEMOBOARD  
AMAX  
θ = Thermal resistance of the package  
JA  
To prove that the parasitic capacitance is the largest  
contributor to the difference in bandwidth of the two boards,  
we added 2.7pF at the output of the demoboard. Figure 50  
shows the similarity in frequency response of the  
engineering evaluation board alongside the demoboard  
piggybacked with 2.7pF.  
The maximum power dissipation actually produced by an IC  
is the total quiescent supply current times the total power  
supply voltage, plus the power in the IC due to the load, or:  
n
V
OUTi  
-----------------  
PD  
= V × I  
+
(V V  
OUTi  
) ×  
MAX  
S
SMAX  
S
R
Li  
i = 1  
19  
ISL59531  
Where:  
• V = Supply voltage = 5V  
S
• I  
SMAX  
= Maximum quiescent supply current = 375mA  
= Maximum output voltage of the application = 2V  
• V  
• R  
OUT  
= Load resistance tied to ground = 150  
LOAD  
• n = 1 to 15 channels  
n
V
OUTi  
-----------------  
PD  
= V × I  
+
(V V  
OUTi  
) ×  
= 2.52W  
MAX  
S
SMAX  
S
R
Li  
i = 1  
The reqired θ to dissipate 2.52W is:  
JA  
T
T  
AMAX  
JMAX  
--------------------------------------------  
= 15.9C/W)  
Θ
=
JA  
PD  
MAX  
Table 8 shows θ thermal resistance results for various  
JA  
airflows. At the thermal resistance equation shows, the  
required thermal resistance depends on the maximum  
ambient temperature.  
TABLE 8. θ THERMAL RESISTANCE [°C/W]  
JA  
Airflow [LFM]  
0
250  
500  
750  
18  
14.3  
13.0  
12.6  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
20  
356 Ld PBGA Package  

相关型号:

ISL59532

32x32 Video Crosspoint
INTERSIL

ISL59532IKEZ

32x32 Video Crosspoint
INTERSIL

ISL59532_07

32x32 Video Crosspoint
INTERSIL

ISL59532_0708

32x32 Video Crosspoint
INTERSIL

ISL59533

32x32 Video Crosspoint with Differential Inputs
INTERSIL

ISL59533IKEZ

32x32 Video Crosspoint with Differential Inputs
INTERSIL

ISL59534

32x16 Video Crosspoint
INTERSIL

ISL59534IKEZ

32x16 Video Crosspoint
INTERSIL

ISL59534_0708

32x16 Video Crosspoint
INTERSIL

ISL5957

14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter
INTERSIL

ISL5957EVAL1

14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter
INTERSIL

ISL5957IA

14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter
INTERSIL