ISL59920 [INTERSIL]
Triple Analog Video Delay Lines; 三重模拟视频延迟线
| 型号： | ISL59920 |
| 厂家： | 
Intersil |
| 描述： | Triple Analog Video Delay Lines |
| 文件： | 总16页 (文件大小：811K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL59920, ISL59921, ISL59922, ISL59923
®
Data Sheet
August 31, 2010
FN6826.2
Triple Analog Video Delay Lines
Features
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that provide skew compensation
between three high-speed signals. These parts are ideal for
compensating for the skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable (with differing electrical lengths on
each twisted pair) when transmitting analog video.
• 30, 31, 46.5, or 62ns Total Delay
• 1.0, 1.5, or 2.0ns Delay Step Increments
• Very Low Offset Voltage
• Drop-in Compatible with the EL9115
• Low Power Consumption
Using a simple serial interface, the ISL59920, ISL59921,
ISL59922, and ISL59923’s delays are programmable in
steps of 2, 1.5, 1, or 2ns (respectively) for up to a total delay
of 62, 46.5, 31, or 30ns (respectively) on each channel. The
gain of the video amplifiers can be set to x1 (0dB) or x2
(6dB) for back-termination. The delay lines require a ±5V
supply.
• 20 Ld QFN Package
• Pb-Free (RoHS Compliant)
Applications
• Skew Control for RGB Video Signals
• Generating Programmable High-speed Analog Delays
Ordering Information
MAX
TYPICAL POWER
PART NUMBER
(Note)
PART
MARKING
DELAY
(ns)
DELAY STEP
SIZE (ns)
DISSIPATION
(mW)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL59920IRZ*
ISL59921IR*
ISL59922IRZ*
ISL59923IRZ*
59920 IRZ
62
46.5
31
2.0
1.5
1.0
2.0
645
645
645
540
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
20 Ld 5mmx5mm QFN
L20.5x5C
59921 IRZ
59922 IRZ
59923 IRZ
L20.5x5C
L20.5x5C
L20.5x5C
30
*Add “-T7” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinout
ISL59920, ISL59921, ISL59922, ISL59923
(20 LD 5X5 QFN)
TOP VIEW
V
1
2
3
4
5
15 R
OUT
SP
R
14 GNDO
IN
THERMAL
PAD
13 G
OUT
GND
12 V
SMO
G
IN
V
11 B
OUT
SM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL59920, ISL59921, ISL59922, ISL59923
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage (V + to V -) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Thermal Resistance (Typical, Note 1)
θ
JA
(°C/W)
31
S
S
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Classification
20 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000V
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V
Recommended Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
R
= V
= +5V, V
= V
= -5V, GAIN = 2, T = +25°C, exposed die plate = -5V, x2 = 5V,
SP
SPO
SM
SMP A
= 150Ω on all video outputs, unless otherwise specified.
LOAD
DESCRIPTION
Nominal Delay Increment (Note 2)
PARAMETER
CONDITION
MIN TYP MAX
UNIT
ns
d
ISL59920
ISL59921
ISL59922
ISL59923
ISL59920
ISL59921
ISL59922
ISL59923
1.8
1.4
0.9
1.8
55
2
2.2
t
1.5 1.7
ns
1
2
1.2
2.3
68
ns
ns
t
Maximum Delay
62
ns
MAX
42.5 46.5 53.5
ns
26.5
26.5
31 38.5
30 34.5
1
ns
ns
D
Delay Difference Between Channels for Same
Delay Settings On All Channels
ns
ELDT
t
Propagation Delay
ISL59920, ISL59923, measured input to
output, delay setting = 0ns
10
8
ns
ns
ns
PD
ISL59921, measured input to output, delay
setting = 0ns
ISL59922, measured input to output, delay
setting = 0ns
7
BW -3dB
BW ±0.1dB
SR
3dB Bandwidth, 0ns Delay Time
±0.1dB Bandwidth, 0ns Delay Time
Slew Rate
ISL59920, ISL59923
ISL59921
153
200
230
50
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
V/µs
V/µs
ISL59922
ISL59920, ISL59923
ISL59921
60
ISL59922
50
ISL59920, 20-80, delay = 0ns
ISL59921, 20-80, delay = 0ns
ISL59922, 20-80, delay = 0ns
ISL59923; 20-80, delay = 0ns
550
640
700
550
FN6826.2
August 31, 2010
2
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
V
R
= V
= +5V, V
= V = -5V, GAIN = 2, T = +25°C, exposed die plate = -5V, x2 = 5V,
SMP A
SP
SPO
SM
= 150Ω on all video outputs, unless otherwise specified. (Continued)
LOAD
DESCRIPTION
Transient Response Time
PARAMETER
CONDITION
MIN TYP MAX
UNIT
t
- t
ISL59920, 20% to 80%, for any delay, 1V step
delay = 0ns
1.7
ns
R
F
ISL59921, 20% to 80%, for any delay, 1V step
delay = 0ns
1.6
1.43
1.7
ns
ns
ns
ISL59922, 20% to 80%, for any delay, 1V step
delay = 0ns
ISL59923, 20% to 80%, for any delay, 1V step
delay = 0ns
V
Voltage Overshoot
For any delay, response to 1V step input
4
3
%
OVER
Settling Time Output Settling after Delay Change / Offset
Calibration
Output settling time from rising edge of
SENABLE
µs
THD
Total Harmonic Distortion
1V
10MHz sinewave, offset by +0.2V at
-43 -38
-80 -63
dB
dB
dB
P-P
mid delay setting
X
Crosstalk
Stimulate G, measure R/B at 1MHz,
ISL59920, ISL59921, ISL59923
ISL59922
-78 -59
2
V
Output Noise
Bandwidth = 150MHz
mV
RMS
N
G_0
Gain Zero Delay
1.74
1.67
1.6
1.8 1.92
1.8 1.97
V/V
V/V
V/V
%
G_m
Gain Mid Delay
G_f
Gain Full Delay
1.8
2
DG_m0
DG_f0
DG_fm
Difference in Gain, 0 to Mid
Difference in Gain, 0 to Full
Difference in Gain, Mid to Full
Input Voltage Range
-8
0.6 7.5
-1.8 10
-1.7 7.5
1.1
-12
-10
-0.7
%
%
V
ISL59920, Gain remains > 90% of nominal,
Gain = 2
V
IN
ISL59921, Gain remains > 90% of nominal,
Gain = 2
-0.7
-0.7
-0.7
1.04
1.04
1.15
V
V
V
ISL59922, Gain remains > 90% of nominal,
Gain = 2
ISL59923, Gain remains > 90% of nominal,
Gain = 2
I
R
, G , B Input Bias Current
ISL59920, ISL59921
ISL59922, ISL59923
3
6
8
8
µA
µA
B
IN IN IN
1.5
-25
V
Output Offset Voltage
Output Impedance
Post offset calibration (Note 4), Delay = 0ns
and Delay = Full
-4
+20
mV
OS
Z
ISL59920, ISL59921, Enabled,
Chip enable = 5V
4.5
3.5
5.4 6.3
6.3
Ω
Ω
OUT
ISL59922, ISL59923, Enabled,
Chip enable = 5V
Disabled, Chip enable = 0V
8
MΩ
dB
dB
mA
V
+PSRR
-PSRR
Rejection of Positive Supply
Rejection of Negative Supply
Output Drive Current
Logic High
-42 -29
-58 -46
I
10Ω load, 0.5V drive
Switch high threshold
Switch low threshold
43
53
70
OUT
V
V
1.6
IH
IL
Logic Low
0.8
V
FN6826.2
August 31, 2010
3
ISL59920, ISL59921, ISL59922, ISL59923
Electrical Specifications
V
R
= V
= +5V, V
= V = -5V, GAIN = 2, T = +25°C, exposed die plate = -5V, x2 = 5V,
SMP A
SP
SPO
SM
= 150Ω on all video outputs, unless otherwise specified. (Continued)
LOAD
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX
UNIT
POWER SUPPLY CHARACTERISTICS
V+
V-
V
V
, V
SP SPO
Positive Supply Range
Negative Supply Range
+4.5
-4.5
98
+5.5
-5.5
V
, V
SM SMO
V
I
I
Positive Supply Current (Note 3)
ISL59920
115 127
125 146
90 106
13 15.3
13 16.3
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
SP
ISL59921, ISL59922
ISL59923
98
74
Positive Output Supply Current (Note 3)
ISL59920
11.3
11.3
9.9
SPO
ISL59921, ISL59922
ISL59923
13
16
I
I
Negative Supply Current (Note 3)
-35.45 -31 -26
-15.5 -13 -11
-17.5 -13 -9.5
0.9
SM
Negative Output Supply Current (Note 3)
ISL59920, ISL59921, ISL59922
ISL59923
SMO
I
Supply Current (Note 3)
Increase in I per unit step in delay per
SP
channel
Δ SP
I
Positive Supply Standby Current (Note 3)
Chip enable = 0V
2.6
mA
STANDBY
SERIAL INTERFACE CHARACTERISTICS
t
t
Max SCLOCK Frequency
Maximum programming clock speed
10
10
MHz
ns
MAX
SENABLE to SCLOCK falling edge setup time.
See Figure 33.
SENABLE falling edge should occur at least
SEN_SETUP
t
ns after previous (ignored) clock
SEN_SETUP
and t
before next (desired) clock.
SEN_SETUP
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have
indeterminate effect.
t
Minimum Separation Between SENABLE rising
If SENABLE is taken low less than 3µs after it
3
µs
SEN_CYCLE
edge and next SENABLE falling edge. See Figure 33. was taken high, there is a small possibility that
an offset correction will not be initiated.
NOTES:
2. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
3. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
4. Offset measurements are referred to 75Ω load as shown in Figure 1.
75Ω
VIN
VOUT
VOS
x2 -
75Ω
FIGURE 1. V
MEASUREMENT CONDITIONS
OS
FN6826.2
August 31, 2010
4
ISL59920, ISL59921, ISL59922, ISL59923
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1
2
V
+5V for delay circuitry and input amp
Red channel video input
0V for delay circuitry supply
Green channel video input
-5V for input amp
SP
R
IN
3
GND
4
G
IN
5
V
SM
6
B
Blue channel video input
IN
7
CENABLE
SENABLE
SDATA
Chip Enable input, active high: logical high enables chip, low disables chip
Serial Enable input, active low: logical low enables serial communication
Serial Data input, logic threshold 1.2V: data to be programmed into chip
Serial Clock input: Clock to enter data; logical; data written on negative edge
Blue channel video output
8
9
10
11
12
13
14
15
16
17
18
19
20
SCLOCK
B
OUT
V
-5V for video output buffers
SMO
G
Green channel video output
OUT
GNDO
0V reference for input and output buffers
R
V
Red channel video output
OUT
+5V for video output buffers
SPO
TESTB
TESTG
TESTR
X2
Blue channel phase detector output
Green channel phase detector output
Red channel phase detector output
Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
Thermal Pad
MUST be tied to -5V. For best thermal conductivity also tie to a larger -5V copper plane (inner
or bottom). Use many vias to minimize thermal resistance between thermal pad and copper
plane. Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND
planes together.
FN6826.2
August 31, 2010
5
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves
2
1
2
1
0ns
0ns
20ns
20ns
0
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
40ns
62ns
40ns
62ns
10ns
10ns
30ns
30ns
50ns
50ns
V
= 700mV
V
= 700mV
IN
GAIN = 2
P-P
IN
GAIN = 1
P-P
100k
1M
10M
FREQUENCY (Hz)
100M
1G
1G
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 2. ISL59920 FREQUENCY RESPONSE (GAIN = 1)
FIGURE 3. ISL59920 FREQUENCY RESPONSE (GAIN = 2)
2
2
0
0ns
0ns
0
10.5ns
46.5ns
10.5ns
21ns
-2
-2
-4
46.5ns
21ns
-4
-6
30ns
-6
30ns
-8
-8
V
= 700mV
P-P
IN
GAIN = 1
V
= 700mV
P-P
IN
GAIN = 2
-10
-10
100k
1M
10M
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
FREQUENCY (Hz)
FIGURE 4. ISL59921 FREQUENCY RESPONSE (GAIN = 1)
FIGURE 5. ISL59921 FREQUENCY RESPONSE (GAIN = 2)
4
2
4
0ns
0ns
10ns
2
0
0
10ns
-2
-2
31ns
31ns
20ns
-4
-6
-4
-6
20ns
-8
-8
V
= 700mV
P-P
V
= 700mV
P-P
IN
GAIN = 1
IN
GAIN = 2
-10
-10
100k
1M
10M
100M
1G
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 6. ISL59922 FREQUENCY RESPONSE (GAIN = 1)
FIGURE 7. ISL59922 FREQUENCY RESPONSE (GAIN = 2)
FN6826.2
August 31, 2010
6
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
2
2
0
0ns
0ns
0
10ns
10ns
-2
-2
-4
-4
30ns
30ns
20ns
20ns
-6
-6
-8
-8
V
= 700mV
P-P
V
= 700mV
IN
GAIN = 2
IN
GAIN = 1
P-P
1M
-10
-10
100k
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 8. ISL59923 FREQUENCY RESPONSE (GAIN = 1)
FIGURE 9. ISL59923 FREQUENCY RESPONSE (GAIN = 2)
250
OUTPUT REFERRED
GAIN = 2
SENABLE
200
150
100
50
TIMEBASE: 500ns/div
SENABLE: 1V/div
OUTPUT: 100mV/div
GAIN: 1
OUTPUT
0
0M
100M
200M
300M
400M
500M
600M
FREQUENCY (Hz)
FIGURE 10. OFFSET CORRECTION DAC ADJUST
FIGURE 11. ISL59920 NOISE SPECTRUM (10k TO 500MHz)
250
200
150
100
200
180
160
140
120
100
80
60
50
40
OUTPUT REFERRED
OUTPUT REFERRED
GAIN = 2
20
GAIN = 2
0
0
0M
100M
200M
300M
400M
500M
600M
0M
100M
200M
300M
400M
500M
600M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 12. ISL59921 NOISE SPECTRUM (10k TO 500MHz)
FIGURE 13. ISL59922 NOISE SPECTRUM (10k TO 500MHz)
FN6826.2
August 31, 2010
7
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
250
200
150
100
50
3.0
2.5
2.0
1.5
1.0
0.5
0
RISE
FALL
OUTPUT REFERRED
GAIN = 2
0
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
0M
100M
200M
300M
FREQUENCY (Hz)
400M
500M
600M
FIGURE 14. ISL59923 NOISE SPECTRUM (10k TO 500MHz)
FIGURE 15. ISL59920 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
2.0
3.0
2.5
FALL
1.8
1.6
1.4
FALL
2.0
1.2
RISE
1.0
0.8
0.6
0.4
0.2
0
1.5
RISE
1.0
0.5
0
0
4
8
12 16 20 24 28 32 36 40 44 48
DELAY (ns)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 16. ISL59921 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
FIGURE 17. ISL59922 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
2.5
0
V+ = +5.0V, V- = -5.0V
V
= 1.0V , SINE WAVE
FALL
2.0
-10
-20
-30
-40
-50
-60
-70
-80
OUT
= 150Ω
P-P
R
L
GAIN = 2
1.5
RISE
1.0
ND
2
HD
RD
0.5
0
3
HD
2M
6M
10M 14M 18M 22M 26M 30M 34M 38M
FREQUENCY (Hz)
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 18. ISL59923 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
FN6826.2
August 31, 2010
8
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
180
160
140
120
100
80
220
200
180
160
140
120
100
80
3 CHANNELS
3 CHANNELS
2 CHANNELS
1 CHANNEL
1 CHANNEL
2 CHANNELS
GAIN = 2
NO INPUT, NO LOAD
GAIN = 2
60
60
0
3
6
9
12 15 18 21 24 27 30 33 36 39 42 45 48
DELAY (ns)
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
FIGURE 20. ISL59920 POSITIVE SUPPLY CURRENT (V ) vs
SP
FIGURE 21. ISL59921 POSITIVE SUPPLY CURRENT (V ) vs
SP
DELAY TIME
DELAY TIME
220
200
150
140
3 CHANNELS
130
120
110
100
90
3 CHANNELS
180
160
140
120
100
80
2 CHANNELS
1 CHANNEL
80
2 CHANNELS
GAIN = 2
NO INPUT, NO LOAD
1 CHANNEL
GAIN = 2
NO INPUT, NO LOAD
70
60
60
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
FIGURE 22. ISL59922 POSITIVE SUPPLY CURRENT (V ) vs
SP
FIGURE 23. ISL59923 POSITIVE SUPPLY CURRENT (V ) vs
SP
DELAY TIME
DELAY TIME
200
-42.5
-43.0
180
DELAY = 62ns
-43.5
-44.0
-44.5
-44.0
-45.5
-46.0
-46.5
DELAY = 62ns
160
140
120
DELAY = 0ns
100
DELAY = 0ns
80
GAIN = 1 OR 2
60
GAIN = 1 OR 2
4.0
4.2
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8 6.0
-4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 -6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 24. ISL59920 I
+ vs V
SUPPLY
+
FIGURE 25. ISL59920 I
- vs V
SUPPLY
-
SUPPLY
SUPPLY
FN6826.2
August 31, 2010
9
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
240
GAIN = 2
220
DELAY = 46.5ns
DELAY = 46.5ns
200
180
160 GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
140
120
100
80
DELAY = 0ns
DELAY = 0ns
60
4.0 4.2
4.0 4.2
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8
6.0
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 26. ISL59921 I
+ vs V
SUPPLY
+
FIGURE 27. ISL59921 I
- vs V
SUPPLY
-
SUPPLY
SUPPLY
-45.0
220
200
180
160
GAIN = 2
DELAY = 31ns
-45.5
DELAY = 31ns
-46.0
-46.5
-47.0
-47.5
-48.0
-48.5
GAIN = 1 OR 2
140
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
120
100
80
-49.0
DELAY = 0ns
-49.5
-50.0
-50.5
DELAY = 0ns
60
4.0
4.0 4.2
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8
6.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 28. ISL59922 I
+ vs V
SUPPLY
+
FIGURE 29. ISL59922 I
- vs V
SUPPLY
-
SUPPLY
SUPPLY
150
140
130
120
110
100
90
-46.0
GAIN = 2
DELAY = 30ns
DELAY = 30ns
-46.5
-47.0
-47.5
-48.0
DELAY = 0ns
DELAY = 0ns
-48.5
-49.0
-49.5
GAIN = 1 OR 2
80
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
70
60
4.0 4.2
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8
6.0
4.0 4.2
4.4
4.6
4.8
5.0 5.2
5.4
5.6
5.8
6.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
ISL59923 I
+ vs V
+
SUPPLY
SUPPLY
FIGURE 30. ISL59923 I
- vs V
SUPPLY
-
SUPPLY
FN6826.2
August 31, 2010
10
ISL59920, ISL59921, ISL59922, ISL59923
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.54W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
1
19
17
18
16
CENABLE
7
R
2
IN
+
DELAY LINE
R
15
OUT
+
G
B
4
6
IN
+
+
DELAY LINE
DELAY LINE
G
B
13
11
OUT
OUT
+
+
IN
X2 20
9
SDATA
10
SCLOCK
CONTROL LOGIC
8
SENABLE
[BOTTOM PLATE]
C
3
5
12
14
FIGURE 32. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
TABLE 1.
Applications Information
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that provide skew compensation
between three high-speed signals. These devices
compensate for time skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable with differing electrical lengths (due to
different twist ratios) on each pair. Via their SPI interface,
these devices can be programmed to independently
compensate for the three different cable delays while
maintaining 80MHz bandwidth at their maximum setting.
There are four different variations of the ISL5992x (ISL5992x
will be used when talking about characteristics that are
common to all four devices).
NOMINAL DELAY
INCREMENT
(ns)
MAX DELAY
(ns)
PART NUMBER
ISL59920
62
46.5
31
2.0
1.5
1.0
2.0
ISL59921
ISL59922
ISL59923
30
FN6826.2
August 31, 2010
11
ISL59920, ISL59921, ISL59922, ISL59923
SENABLE
SCLOCK
t
t
SEN_CYCLE
SEN_SETUP
SDATA
0
A1
A0
b
D4
v
D3
w
D2
x
D1
D0*
z
*D0 is 0 when addressing the test register
a
y
FIGURE 33. SERIAL TIMING
TABLE 2. SERIAL BUS DATA (Continued)
Figure 32 shows the ISL5992x block diagram. The 3 analog
inputs are ground referenced single-ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing either 1, 1.5 or 2ns of delay. In addition to
adding delay, each filter block also introduces some low
pass filtering. As a result, the bandwidth of the signal path
decreases from the 0ns delay setting to the maximum delay
setting, as shown in Figures 2 through 9 of the “Typical
Performance Curves”.
ISL59920
DELAY
ISL59921
DELAY
ISL59922 ISL59923
DELAY
vwxyz
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
DELAY
8
6
4
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
7.5
9
5
10
6
12
10.5
12
7
14
8
16
13.5
15
9
18
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in delay compensation
with the lowest power and distortion.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
20
16.5
18
22
24
19.5
21
26
Serial Bus Operation
The ISL5992x is programmed via 8-bit words sent through
its serial interface. The first bit (MSB) of SDATA is latched on
the first falling clock edge after SENABLE goes low, as
shown in Figure 33. This bit should be a 0 under all
conditions. The next two bits determine the color register to
be written to: 01 = R, 02 = G, and 03 = B (00 is reserved for
the test register). The final five bits set the delay for the
specified color. After 8 bits are latched, any additional clocks
are treated as a new word (data is shifted directly to the final
registers as it is clocked in). This allows the user to write (for
example) the 24 bits of data necessary for R, G, and B as a
single 24-bit word. It is the user's responsibility to send
complete multiples of 8 clock cycles. The serial state
machine is reset on the falling edge of SENABLE, so any
data corruption that may have occurred due to too many or
too few clocks can be corrected with a new word with the
correct number of clocks. The initial value of all registers on
power-up is 0.
28
22.5
24
30
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
25.5
27
28.5
30
31.5
33
34.5
36
37.5
39
40.5
42
TABLE 2. SERIAL BUS DATA
43.5
45
ISL59920
DELAY
ISL59921
DELAY
ISL59922 ISL59923
vwxyz
00000
00001
00010
00011
DELAY
DELAY
0
2
4
6
0
0
1
2
3
0
2
4
6
46.5
1.5
3
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects
delay; ab = 00 writes to the test register to change the DAC slice
level.
4.5
FN6826.2
August 31, 2010
12
ISL59920, ISL59921, ISL59922, ISL59923
Offset Compensation
Offset Calibration with Sync-On-Video
To counter the effects of offset, the ISL5992x incorporates an
offset compensation circuit that reduces the offset to less than
±25mV. An offset correction cycle is triggered by the rising
edge of the SENABLE pin after writing a delay word to any of
the 3 channels. The offset calibration starts about 500ns after
the SENABLE rising edge to allow the ISL5992x time to settle
(electrically and thermally) to the new delay setting. It lasts
about 2.5µs, for a total offset correction time of 3.0µs. During
calibration, the ISL5992x’s inputs are internally shorted
together (however the characteristics of the ISL5992x’s
differential input pins stay the same), and the offset of the
output stage is adjusted until it has been minimized.
The offset correction mechanism temporarily disconnects
the input signals to perform the offset calibration. This
introduces several discontinuities in the video signal, as
shown in Figure 10 on page 7:
• 200-300mV spike when calibration is engaged
• Successive-approximation offset null
• 200-300mV spike when calibration is disengaged
• In addition, because an offset calibration is performed any
time the delay changes, the output video signal may be
moved forward or back in time by up to 62ns.
If the video signals going through the ISL5992x contain only
video (with no sync signals), this appears as a 2µs “sparkle”
on the screen - usually it is not even visible to the eye.
In addition to automatically triggering after a delay change
(or any register write), an additional offset calibration may be
initiated at any time, such as:
However if sync signals are embedded on the video, the
spikes may be misinterpreted as a sync signal, causing the
downstream circuitry to see an asynchronous sync pulse. In
some receiving systems (typically monitors), a single
asynchronous sync pulse can cause the system to think the
video signal has changed. Depending on the receiveing
monitor’s design, this can initiate a new video acquisition
cycle (for example, the monitor blanks the screen while it
measures the “new” HSYNC and VSYNC timing, selects the
right mode, and optimizes the image). This can cause the
monitor to go blank for up to several seconds after a single
delay change.
• When the die temperature changes. Applying power to the
ISL5992x will cause the die temperature to quickly increase
then slowly settle over 20 to 30ns. Because the ISL5992x
powers-down unused delay stages (to minimize power
consumption), the die temp will also change and settle after
a delay change. Initiating an offset 20ns (or longer,
depending on the thermal characteristics of the system)
after power-on or a delay change will minimize the offset in
normal operation thereafter.
• When the ambient temperature changes. If you are
monitoring the temperature, initiate a calibration every time
the temperature shifts by 5 to 10 degrees. If you are not
monitoring temperature, initiate a calibration periodically, as
expected by the environment the device is in.
Since this only happens at power-on and when the delays
are initially set, this is not a problem in normal use, but if the
monitor is blanking for several seconds every time the delay
is adjusted, it can cause calibration to take longer than
absolutely necessary. If this behavior is undesirable, it can
be eliminated as follows:
• After a CENABLE (Chip Enable) cycle. The CENABLE pin
may be taken low to put the ISL5992x in a low power
standby mode to conserve power when not needed. When
the CENABLE pin goes high to exit this low power mode,
the ISL5992x will recall the delay settings but it will not
recall the correct offset calibration settings, so to maintain
low offset, a write to the delay register is required after a
CENABLE cycle. Offset errors may be as large as
±200mV coming out of standby mode - recalibration is a
necessity. For best performance, initiate an additional
calibration again once the die temperature has settled (20
to 30ns after coming out of standby).
1. Synchronize the rising edge of SENABLE to the sync
pulse, so that the SENABLE goes high immediately after
the trailing edge of the sync pulse. SENABLE can be
taken low and the serial data written asynchronously at
any time - it is the rising edge of SENABLE that triggers
a calibration.
2. If the Sync Processor is part of the same design as
ISL5992x, ensure that the sync processor ignores the
first x microseconds after a valid sync, where x = 3µs + the
delay between the end of a sync and rising edge of
SENABLE. This will prevent the sync processor from
generating invalid sync signals due to the spikes.
• After a gain change (X2 pin changes state). The systematic
offset is different for a gain of x1 vs. a gain of x2, so an
offset calibration is recommended after a gain change.
However in a typical application the gain is permanently
fixed at x1 or x2, so this is not usually a concern.
3. If the Sync Processor is external to the design with the
ISL5992x (video with Sync-On-Green, for example), the
video signal should disconnected from the ISL59920 and
shorted to ground via an analog switch for the first x
microseconds after a valid sync, where x = 3µs + the
delay between the end of a sync and rising edge of
SENABLE. This will remove the calibration signals from
the video signal.
FN6826.2
August 31, 2010
13
ISL59920, ISL59921, ISL59922, ISL59923
These steps are only necessary if the sync signal is
embedded on the video and you want to avoid possible
INTERNAL DAC
SLICING LEVEL
4
monitor blanking during skew adjustment.
000wxyz0
COMPARATORS
A
Test Pins
RED
GREEN
BLUE
OUT
OUT
OUT
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inputs, as shown in
Figure 34:
TEST
R
G
B
B
TEST pulse = RED
(A) with respect to GREEN
(B)
R
OUT
OUT
OUT
OUT
A
B
TEST pulse = GREEN
G
with respect to BLUE
OUT
with respect to RED
OUT
TEST
TEST pulse = BLUE
B
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current
pulse is +50µA, and the output voltage goes up. When B
precedes A, the pulse is -50µA.
A
B
TEST
For the logic to work correctly, A and B must have a period of
overlap while they are high (a delay longer than the pulse
width cannot be measured).
A
B
Signals A and B are derived from the video input by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signals encoded on
top of the video or from a dedicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
OUTPUT
FIGURE 34. DELAY DETECTOR
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED
DAC RANGE [mV] DAC RANGE [mV]
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
wxyz
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
(GAIN 1)
-400
-350
-300
-250
-200
-150
-100
-50
(GAIN 2)
-200
-175
-150
-125
-100
-75
Internal DAC Voltage
The slice level of the internal DAC may be programmed by
writing a byte to the test register (00). Table 3 shows the
values that should be written to change the DAC slice level.
Please keep in mind when writing to the test register that the
LSB should always be zero.
Referred to the input, the DAC slice range for the ISL5992x
is cut in half for gain of 2 mode because the slicing occurs
after the x1/x2 stage output amplifier. (In the EL9115, the
slicing occurred before the amplifier so the range of the DAC
voltage was the same for either gain of 1 or gain of 2).
-50
-25
0
0
50
25
100
150
200
250
300
350
50
75
100
125
150
175
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
FN6826.2
August 31, 2010
14
ISL59920, ISL59921, ISL59922, ISL59923
Power Dissipation
As the delay setting increases, additional filter blocks turn on
and insert into the signal path. When the delay per channel
increments, V current increases by 0.9mA while V
SP SM
does not change significantly. Under the extreme settings,
the positive supply current reaches 141mA and the negative
supply current can be 41mA. Operating at ±5V power supply,
the worst-case ISL5992x power dissipation is:
(EQ. 1)
PD = 5 • 141mA + 5 • 41mA = 910mW
The minimum θ required for long term reliable operation of
JA
the ISL5992x is calculated using Equation 2:
(EQ. 2)
θ
= (T – T ) ⁄ PD = 55°C ⁄ W
J A
JA
Where:
T is the maximum junction temperature (+135°C)
J
T is the maximum ambient temperature (+85°C)
A
For a 20 Ld package on a well laid-out PCB with good
connectivity between the QFN’s pad and the PCB copper
area, 31°C/W θ thermal resistance can be achieved. This
JA
yields a much higher power dissipation of 3.54W using
Equation 2 (see Figure 31). To disperse the heat, the bottom
heat spreader must be soldered to the PCB. Heat flows
through the heat spreader to the circuit board copper then
spreads and convects to air. Thus, the PCB copper plane
becomes the heatsink (see TB389). This has proven to be a
very effective technique. A separate application note, which
details the 20 Ld QFN PCB design considerations, is
available.
FN6826.2
August 31, 2010
15
ISL59920, ISL59921, ISL59922, ISL59923
Quad Flat No-Lead Plastic Package (QFN)
L20.5x5C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
B
A
D
MILLIMETERS
SYMBOL
MIN
0.80
0.00
0.28
NOMINAL
0.90
MAX
1.00
0.05
0.32
NOTES
A
A1
b
-
1
2
3
PIN #1
I.D. MARK
0.02
-
E
0.30
-
c
0.20 REF
5.00 BASIC
3.70 REF
5.00 BASIC
3.70 REF
0.65 BASIC
0.40
-
(2X)
D
-
0.075 C
D2
E
8
-
E2
e
8
TOP VIEW
-
L
0.35
0.45
-
N
20
4
0.10 C
e
C
ND
NE
5 REF
6
5 REF
5
SEATING
PLANE
Rev. 0 6/06
0.08 C
N LEADS AND
NOTES:
SEE DETAIL “X”
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
EXPOSED PAD
SIDE VIEW
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
0.01 M C A B
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
b
PIN #1 I.D.
L
N LEADS
3
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
1
2
3
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
(E2)
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
5
NE
9. One of 10 packages in MDP0046
7
(D2)
BOTTOM VIEW
C
A
2
(c)
(L)
N LEADS
A1
DETAIL “X”
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6826.2
August 31, 2010
16
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明