ISL6125EVAL1_技术文档

ISL6123, ISL6124, ISL6125,

®

ISL6126, ISL6127, ISL6128, ISL6130

Data Sheet

February 5, 2007

FN9005.8

Power Sequencing Controllers

Features

The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,

ISL6128 and ISL6130 are integrated four channel

• Enables arbitrary turn-on and turn-off sequencing of up to

four power supplies (0.7V to 5V)

controlled-on/controlled-off power-supply sequencers with

supply monitoring, fault protection and a “sequence

completed” signal (RESET#). For larger systems, more than

four supplies can be sequenced by simply connecting a wire

between SYSRESET# pins of cascaded IC's. The ISL6125

uses four open-drain outputs to control the on/off sequencing

of four supplies, while the other sequencers use a patented,

micropower 7X charge pump to drive four external low-cost

NFET switch gates above the supply rail by 5.3V. These IC's

can be biased from any supply 5V down to 1.5V. Individual

product descriptions follow.

• Operates from 1.5V to 5V supply voltage

• Supplies V

DD

+5.3V of charge pumped gate drive

• Adjustable voltage slew rate for each rail

• Multiple sequencers can be daisy-chained to sequence an

infinite number of independent supplies

• Glitch immunity

• Under voltage lockout for each supply

• 1µA Sleep State (ISL6123, ISL6130)

• Active high (ISL6123, ISL6130) or low (ISL6124, ISL6125,

ISL6126, ISL6127, ISL6128) ENABLE# input

• Open drain version available (ISL6125)

The four channel ISL6123 (ENABLE input), ISL6124

(ENABLE# input) and ISL6125 ICs offer the designer 4 rail

control when it is required that all four rails are in minimal

compliance prior to turn on and that compliance must be

maintained during operation. The ISL6123 and ISL6130

have a low power standby mode when disabled, suitable for

battery powered applications.

• Voltage Determined Sequence (ISL6126, ISL6130)

• Pre-programmed Sequence available (ISL6127)

• Dual channel groupings (ISL6128)

• QFN package with Pb-free plus anneal option (RoHS

compliant)

Applications

The ISL6125 operates like the ISL6124 but instead of

charge pump driven gate drive outputs it has open drain

logic outputs for direct interface to other circuitry.

• Graphics cards

• FPGA/ASIC/microprocessor/PowerPC supply sequencing

• Network routers

In contrast to the majority, for both the ISL6126 and ISL6130

each of the four channels operates independently so that the

various GATEs will turn on once its individually associated

input voltage requirements are met.

• Telecommunications systems

Pinout

ISL6123, ISL6124, ISL6125,

The ISL6127 is a pre programmed A-B-C-D turn-on and

D-C-B-A turn-off sequenced IC. Once all inputs are in

compliance and ENABLE is asserted the sequencing starts

and each subsequent GATE will turn-on after the previous

one completes turning-on.

ISL6126, ISL6127, ISL6128, ISL6130

(24 LD QFN)

TOP VIEW

The ISL6128 has two groups of two channels each with its

independent I/O and is ideal for voltage sequencing into

redundant capability loads as all four inputs need to be

satisfied prior to turn on but a single group fault is ignored by

the other group.

24 23 22 21 20 19

ENABLE/

18 DLY_OFF_A

1

2

3

4

5

6

ENABLE#

17

16

15

GATE_A

UVLO_C

DLY_OFF_C

DLY_OFF_D

GATE_B

DLY_ON_C

DLY_ON_D

External resistors provide flexible voltage threshold

programming of monitored rail voltages. Delay and

sequencing are provided by external capacitors for both

ramp up and ramp down.

4mmx4mm

14 UVLO_D

GATE_C

13 DLY_OFF_B

Additional I/O is provided indicating and driving RESET state

in various configurations.

7

8

9

10 11 12

For volume applications, other programmable options and

features can be had. Contact the factory with your needs.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Ordering Information

TEMP.

PKG.

PART NUMBER*

ISL6123IR

PART MARKING

ISL6123IR

RANGE (°C)

PACKAGE

24 Ld 4x4 QFN

DWG. #

-40 to +85

L24.4x4

24 Ld 4x4 QFN

ISL6124IR

ISL6125IR

ISL6126IR

ISL6127IR

ISL6128IR

6123IRZ

6124IRZ

6125IRZ

6126IRZ

6127IRZ

6128IRZ

6130IRZ

-40 to +85

L24.4x4

ISL6125IR

ISL6126IR

ISL6127IR

ISL6128IR

ISL6123IRZA (Note)

ISL6124IRZA (Note)

ISL6125IRZA (Note)

ISL6126IRZA (Note)

ISL6127IRZA (Note)

ISL6128IRZA (Note)

ISL6130IRZA (Note)

ISL612XSEQEVAL1

ISL6125EVAL1

-40 to +85

24 Ld 4x4 QFN (Pb-free)

-40 to +85

ISL612X Evaluation Platform

ISL6125 Evaluation Platform

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which

are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

ISL6123 Block Diagram (1/4)

AIN

AOUT

BOUT

BIN

VDD+5V

Q-PUMP

BIAS

CIN

COUT

DOUT

VDD

LOCK OUT

DIN

1µA

DLY_ONX

V

DD

UVLO_A

UVLO_B

UVLO_C

UVLO_D

ENABLE

SYSRST#

RESET#

1.26V

-1µA

1µA

GROUND

DLY_OFFX

10ms

RISING DELAY

1.26V

FIGURE 1. TYPICAL ISL6123 APPLICATION

USAGE

GATEX

30µs

FILTER

UVLOX

RESET#

LOGIC

0.633V

150ms

RISING DELAY

EN

SYSRST

FN9005.8

February 5, 2007

2

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Pin Descriptions

PIN # PIN NAME

FUNCTION

Chip Bias

Bias Return

DESCRIPTION

23

10

1

VDD

GND

Bias IC from nominal 1.5V to 5V

IC ground

ENABLE_1/ Input to start on/off Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality

ENABLE#_1 sequencing.

is disabled for 10ms after UVLO is satisfied. ISL6123 and ISL6130 have ENABLE. ISL6124,

ISL6125, ISL6126 and ISL6127 have ENABLE#. Only ISL6128 has 2 ENABLE# inputs, 1 for

each 2 channel grouping. EN_1# for (A, B), and EN_2# for (C, D).

11

ENABLE#_2

24

9

RESET#

RESET# Output

RESET# provides a low signal 150ms after all GATEs are fully enhanced. This delay is for

stabilization of output voltages. RESET# will assert low upon UVLO not being satisfied or

ENABLE/ENABLE# being deasserted. The RESET outputs are open drain N channel FET and is

guaranteed to be in the correct state for VDD down to 1V and is filtered to ignore fast transients on

VDD and UVLO_X.

RESET#_2

RESET#_2 only exists on ISL6128 for (C, D) group I/O.

20

12

17

14

21

8

UVLO_A

UVLO_B

UVLO_C

UVLO_D

Under Voltage Lock These inputs provide for a programmable UV lockout referenced to an internal 0.633V reference

Out/Monitoring

Input

and are filtered to ignore short (<30µs) transients below programmed UVLO level.

DLY_ON_A Gate On Delay

Allows for programming the delay and sequence for Vout turn-on using a capacitor to ground. Each

cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current

source providing delay to the associated FETs GATE turn-on.

Timer Output

DLY_ON_B

These pins are NC on ISL6126, ISL6127 and ISL6130.

16

15

18

13

3

DLY_ON_C

DLY_ON_D

DLY_OFF_A Gate Off Delay

Allows for programming the delay and sequence for Vout turn-off through ENABLE/ENABLE# via a

capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference

voltage causing the corresponding gate to be pulled down turning-off the FET.

These pins are NC on ISL6127.

Timer Output

DLY_OFF_B

DLY_OFF_C

DLY_OFF_D

4

2

GATE_A

GATE_B

GATE_C

GATE_D

FET Gate Drive

Output

ISL6125 Open

Drain Outputs

Drives the external FETs with a 1µA current source to soft start ramp into the load.

On the ISL6125 only, these are open drain outputs that can be pulled up to a maximum of

VDD voltage.

5

6

7

22

SYSRST# System Reset I/O

As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low.

This input can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms

stabilization delay) from input signal on this pin being driven high to first GATE. As an output when

there is a UV condition, this pin pulls low. If common to other SYSRST# pins in a multiple IC

configuration, it will cause immediate and unconditional latch-off of all other GATEs on all other

ISL612X sequencers. This pin is a NC on ISL6126 and ISL6128 and ISL6130.

19

No Connect No Connect

No Connect

FN9005.8

February 5, 2007

3

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

ISL612X Variant Feature Matrix

NUMBEROF

NUMBER OF CHANNELS

UVLO

INPUTS

THAT

TURN-OFF

WHEN 1

UVLO

GATE DRIVE REQUIRED

OR OPEN CONDITIONS MONITORED

PRESET OR

ADJUSTABLE

SEQUENCE

NUMBER OF

UVLO AND

PAIRS OF I/O

PART

NAME EN/EN#

CMOS/

TTL

DRAIN

FOR INITIAL

START-UP

BY EACH

RESET#

OUTPUTS

FAULTS

FEATURES

ISL6123

EN

TTL

Gate Drive

4 UVLO

1 EN

4 UVLO

4 Gates

Time Adjustable 4 Monitors with Auto Restart,

On and Off

1 I/O

Low bias current

sleep

ISL6124

ISL6125

EN#

CMOS

CMO

Gate Drive

4 UVLO

1 EN

4 UVLO

4 Gates

Time Adjustable 4 Monitors with Auto Restart

On and Off 1 I/O

Open Drain

4 UVLO

1 EN

4 Open Drain Time Adjustable 4 Monitors with Auto Restart, Open

On and Off

1 I/O

Drain Sequenced

Outputs

ISL6126

EN#

CMOS

Gate Drive

1 UVLO

1 EN

4 UVLO

1 Gate

Voltage

Determined ON

Time

4 Monitors with Gates Independent

1 I/O On as UVLO Valid

Adjustable Off

ISL6127

ISL6128

ISL6130

EN#

EN

CMOS

TTL

Gate Drive

4 UVLO

1 EN

4 UVLO

2 UVLO

4 UVLO

4 Gates

2 Gates

1 Gates

Preset

4 Monitors with Auto Restart

1 I/O

4 UVLO

2 EN

Preset

2 Monitors Dual Redundant

with 2 I/O

Operation

1 UVLO

1 EN

Voltage

Determined ON

Time

4 Monitors with Gates Independent

1 I/O

On as UVLO Valid

Low bias current

sleep

Adjustable Off

FN9005.8

February 5, 2007

4

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Absolute Maximum Ratings

Thermal Information

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Thermal Resistance (Typical, Notes 1, 2)

4 x 4 QFN Package . . . . . . . . . . . . . . .

θ

(°C/W)

48

θ

JC

(°C/W)

9

DD

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +6V

JA

DD

ISL6125 LOGIC OUT. . . . . . . . . . . . . . . . . . . . . -0.3V to V

UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V

RESET#, DLY_ON, DLYOFF. . . . . . . . . . . . . . . -0.3V to V

+0.3V

DD

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(QFN - Leads Only)

Operating Conditions

V

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +1.5V to +5.5V

DD

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

A

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

3. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications

PARAMETER

V

= 1.5V to +5V, T = T = -40°C to +85°C, unless otherwise specified.

DD

A

J

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UVLO

Falling Undervoltage Lockout Threshold

Undervoltage Lockout Threshold Tempco

Undervoltage Lockout Hysteresis

Undervoltage Lockout Threshold Range

Undervoltage Lockout Delay

Transient Filter Duration

V

T = +25°C

619

633

40

10

7

647

mV

nV/°C

mV

UVLOvth

J

TC

T = -40°C to +85°C

J

UVLOvth

V

UVLOhys

RUVLOvth

TUVLOdel

TFIL

Max V

- Min V

UVLOvth

mV

UVLOvth

ENABLE satisfied

10

30

ms

V

, UVLO, ENABLE glitch filter

μs

DD

DELAY ON/OFF

Delay Charging Current

DLY_ichg

DLY_ichg_r

TC_DLY_ichg

DLY_Vth

V

= 0V

0.92

1

1.08

μA

DLY

Delay Charging Current Range

Delay Charging Current Temp. Coeff.

Delay Threshold Voltage

DLY_ichg(max) - DLY_ichg(min)

0.08

0.2

nA/°C

V

1.238

1.266

0.2

1.294

Delay Threshold Voltage Temp. Coeff.

ENABLE/ENABLE#, RESET# & SYSRST# I/O

ENABLE Threshold

TC_DLY_Vth

mV/°C

V

1.2

V

ENh

ENABLE# Threshold

0.5 V

DD

ENABLE/ENABLE# Hysteresis

ENABLE/ENABLE# Lockout Delay

ENABLE/ENABLE# Input Capacitance

RESET# Pull-up Voltage

V

Measured at V

= 1.5V

0.2

10

5

V

ENh - ENl

DD

TdelEN_LO

Cin_en

UVLO satisfied

ms

pF

V

Vpu_rst

V

DD

RESET# Pull-Down Current

I

V

= 1.5V, RST = 0.1V

= 3.3V, RST = 0.1V

= 5V, RST = 0.1V

5

mA

ms

V

RSTpd1

RSTpd3

RSTpd5

DD

13

17

RESET# Delay after GATE High

RESET# Output Low

T

GATE = V +5V

DD

160

RSTdel

V

Measured at V

= 5V with 5k

0.1

RSTl

DD

pull-up resistors

RESET Output Capacitance

Cout_rst

10

pF

FN9005.8

February 5, 2007

5

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Electrical Specifications

PARAMETER

V

= 1.5V to +5V, T = T = -40°C to +85°C, unless otherwise specified. (Continued)

DD

A

J

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

SYSRST# Pull-Up Voltage

SYSRST# Pull-Down Current

Vpu_srst

Ipu_1.5

Ipu_5

V

DD

5

V

= 1.5V

= 5V

μA

mV

pF

DD

100

150

10

SYSRST# Low Output Voltage

SYSRST# Output Capacitance

SYSRST# Low to GATE Turn-Off

GATE

Vol_srst

Cout_srst

= 1.5V, I = 100μA

OUT

T

GATE = 80% of V +5V

DD

40

ns

delSYS_G

GATE Turn-On Current

GATE Turn-Off Current

GATE Current Range

I

GATE = 0V

0.8

1.1

1.4

-0.8

0.35

μA

nA/°C

mA

V

GATEon

I

GATE = V , Disabled

DD

-1.4

-1.05

GATEoff_l

I

Within IC I

max-min

GATE

GATE_range

GATE Turn-On/Off Current Temp. Coeff.

GATE Pull-Down High Current

GATE High Voltage

TC_I

0.2

88

GATE

I

GATE = V , UVLO = 0V

DD

GATEoff_h

V

< 2V, T = +25°C

J

V

+4.9V

GATEh

DD

> 2V

V

+5V

+5.3V

0

V

DD

GATE Low Voltage

BIAS

V

Gate Low Voltage, V

= 1V

DD

0.1

0.5

V

GATEl

IC Supply Current

I

V

= 5V

0.20

mA

μA

VDD_5V

DD

I

= 3.3V

= 1.5V

0.14

0.10

VDD_3.3V

VDD_1.5V

ISL6123, ISL6130 Stand By IC Supply

Current

I

= 5V, ENABLE = 0V

1

VDD_sb

V

Power On Reset

V

_POR

DD

V

DD

will discharge to be ready when next needed. After the

entire turn on sequence has been completed and all

GATEs have reached the charge pumped voltage (VQP), a

160ms delay is started to ensure stability after which the

RESET# output will be released to go high. Subsequent to

turn-on, if any input falls below its UVLO point for longer

than the glitch filter period (~30μs) this is considered a

fault. RESET# and SYSRST# are pulled low and all GATEs

are simultaneously also pulled low. In this mode the GATEs

are pulled low with 88mA. Normal shutdown mode is

entered when no UVLO is violated and the ENABLE is

deasserted. When ENABLE is deasserted, RESET# is

asserted and pulled low. Next, all four shutdown ramp caps

on the DLY_OFF pins are charged with a 1μA source and

when any ramp-cap reaches DLY_Vth, a latch is set and a

current is sunk on the respective GATE pin to turn off its

external MOSFET. When the GATE voltage is

Descriptions and Operation

The ISL612X sequencer family consists of several four

channel voltage sequencing controllers in various

functional and personality configurations. All are designed

for use in multiple-voltage systems requiring power

sequencing of various supply voltages. Individual voltage

rails are gated on and off by external N-Channel MOSFETs,

the gates of which are driven by an internal charge pump to

V

_DD+5.3V (VQP) in a user programmed sequence.

With the four-channel ISL6123 the ENABLE must be

asserted high and all four voltages to be sequenced must

be above their respective user programmed Under Voltage

Lock Out (UVLO) levels before programmed output turn on

sequencing can begin. Sequencing and delay

determination is accomplished by the choice of external

cap values on the DLY_ON and DLY_OFF pins. Once all

four UVLO inputs and ENABLE are satisfied for 10ms, the

four DLY_ON caps are simultaneously charged with 1µA

current sources to the DLY_Vth level of 1.27V. As each

DLY_ON pin reaches the DLY_Vth level its associated

GATE will then turn-on with a 1µA source current to the

approximately 0.6V, the GATE is pulled down the rest of the

way at a higher current level. Each individual external FET

is thus turned off removing the voltages from the load in the

programmed sequence.

VQP voltage of V +5.3V. Thus all four GATEs will

DD

sequentially turn on. Once at DLY_Vth the DLY_ON pins

FN9005.8

February 5, 2007

6

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

The ISL6123 and ISL6124 have the same functionality

starts to charge its capacitor thus turning on all four GATEs.

Approximately 160ms after D GATE = VQP the RESET#

output is released to go high. Once any UVLO is unsatisfied,

only the related group’s RESET# and two GATEs are pulled

low. The related EN input has to be cycled for the faulted

group to be turned-on again. Normal shutdown is invoked by

either signaling both ENABLE# inputs high which will cause all

the two related GATEs to shutdown in reverse order from turn-

on. DLY_X caps adjust the delay between GATES during turn

on and off but not the order.

except for the ENABLE active polarity with the ISL6124

having an ENABLE# input. Additionally the ISL6123 and

ISL6130 also have an ultra low power sleep state when

ENABLE is low.

The ISL6125 has the same personality as the ISL6124 but

instead of charged pump driven GATE outputs it has open

drain outputs that can be pulled up to a maximum of V

.

DD

The ISL6126 and ISL6130 are different in that their

sequence on is not time determined but voltage

During bias up the RESET# output is guaranteed to be in the

determined. Its personality is that each of the four channels

operates independently so that once the IC is biased and

any one of the UVLO inputs is greater than the 0.63V

internal reference, and the enable input is also satisfied the

GATE for the associated UVLO input will turn-on. In turn,

the other UVLO inputs need to be satisfied for the

associated GATEs to turn-on. 150ms after all GATEs are

fully on (GATE voltage = VQP), the RESET# is released to

go high. The UVLO inputs can be driven by either a

previously turned on output rail offering a voltage

determined sequence or by logic signal inputs. Any

subsequent UVLO level < its programmed level will pull the

associated GATE and RESET# output low (if previously

released), but will not latch-off the other GATEs.

Predetermined turn-off is accomplished by deasserting

enable, this will cause RESET# to latch low and all four

GATE outputs to follow the programmed turn off sequence

similar to a ISL6124.

correct state with V

DD

lower than 1V.

The SYSRST# pin follows the V

DD

weak internal pull-up and is both an input and output

upon power up with a

connection providing two functions. As an input, if it is pulled

low all GATEs will be unconditionally shut off and RESET#

pulls low, see Figure 6. This input can also be used as a no

wait enabling input, if all inputs (ENABLE and UVLO) are

satisfied it does not wait through the ~10ms enable delay to

initiate DLY_ON cap charging when released to go high. As

an output it is useful when implementing multiple sequencers

in a design needing simultaneous shutdown as with a kill

switch across all sequencers. Once any UVLO is unsatisfied

longer than T

the related SYSRST# will pull low and pull all

FIL

other SYSRST# inputs low that are on a common connection

thus unconditionally shutting down all outputs across multiple

sequencers.

Except for ISL6128 after a fault, restart of the turn on

sequence is automatic once all requirements are met. This

allows for no interaction between the sequencer and a

controller IC if desired. The ENABLE & RESET# I/O do allow

for a higher level of feedback and control if desired. The

ISL6128 requires that the related ENABLE# be cycled for

restart of its associated group GATEs. If no capacitors are

connected between DLY_ON or DLY_OFF pins and ground

then all such related GATEs start to turn on immediately after

The ISL6127 is a four-channel sequencer pre-programmed

for A-B-C-D turn-on and D-C-B-A turn-off. After all four

UVLO and ENABLE# inputs are satisfied for ~10ms, the

sequencing starts and the next GATE in the sequence

starts to ramp up once the previous GATE has reached

~VQP-1V. 160ms after the last GATE is at VQP the

RESET# output will be deasserted. Once any UVLO is

unsatisfied, RESET# is pulled low, SYSRST# is pulled low

and all GATEs are simultaneously turned off. When

ENABLE# is signaled high the D GATE will start to pull low

and once below 0.6V the next GATE will then start to pull

low and so on until all GATEs are at 0V. Unloaded, this turn

off sequence will complete in <1ms. This variant offers a

lower cost and size implementation as the external delay

caps are not used. Since the delay caps are not used this

IC can not delay the start of subsequent GATEs thus

necessary stabilization or system house keeping need to

be considered.

the 10ms (T

) ENABLE stabilization time out has

UVLOdel

expired and the GATEs start to immediately turn off when

ENABLE is asserted.

If some of the rails are to be sequenced together, in order to

eliminate the effect of capacitor variance on the timing and to

reduce cost, a common capacitor can be connected to two or

more DLY_ON or DLY_OFF pins. In this case multiply the

capacitor value by the number of common DLY_X pins to

retain the desired timing.

Table 1 illustrates the nominal time delay from the start of

charging to the 1.27V reference for various capacitor values

on the DLY_X pins. This table does not include the 10ms of

enable lock out delay during a start up sequence but

represents the time from the end of the enable lock out delay

to the start of GATE transition. There is no enable lock out

delay for a sequence off, so this table illustrates the delay to

GATE transition from a disable signal.

The ISL6128 is a four-channel device that groups the four

channels into two groups of two channels each, as A, B

and C, D, each group having its own ENABLE# and

RESET# I/IO pins. This requires all four UVLO and both

ENABLE#s to be satisfied for sequencing to start. The A, B

group will first turn on 10ms after the second ENABLE# is

pulled low with A then B turning on followed by C then D.

Once the preceding GATE = VQP the next DLY_ON pin

FN9005.8

February 5, 2007

7

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Figure 2 illustrates the turn-on and Figure 3 illustrates the

TABLE 1.

nominal turnoff timing diagram of the ISL6123 and ISL6124

product.

NOMINAL DELAY TO SEQUENCING THRESHOLD

DLY PIN CAPACITANCE

TIME(s)

0.00006

0.00013

0.0013

0.013

0.13

The ISL6125 is similar to the ISL6124 except that instead of

charge pumped GATE outputs, there are sequenced open

Open

100pF

1000pF

0.01μF

0.1μF

1μF

drain outputs that can be pulled up to a maximum of V

.

DD

Note the delay and flexible sequencing possibilities. Multiple

series, parallel or adjustable capacitors can be used to easily

fine tune timing between that offered by standard value

capacitors.

1.3

10μF

13

NOTE: Nom. T

= Cap (μF) * 1.3MΩ.

DEL_SEQ

l

V

UVLOVth

<TFIL

UVLO_A

V

UVLOVth

UVLO_B

UVLO_C

V

UVLOVth

V

UVLOVth

T

UVLO_D

UVLOdel

ENABLE# (ISL6124)

V

EN

ENABLE (ISL6123)

DLY_Vth

DLYON_B

DLYON_D

DLY_Vth

DLYON_A

DLYON_C

V

QPUMP

GATE_B

GATE_D

GATE_C

GATE_A

V

-1V

QPUMP

T

RSTdel

RESET#

FIGURE 2. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM

FN9005.8

February 5, 2007

8

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

UVLO_X>VUVLOVth

ENABLE (ISL6123)

V

EN

ENABLE# (ISL6124)

DLYOFF_A

DLY_Vth

DLYOFF_B

DLYOFF_C

DLY_Vth

DLYOFF_D

GATE_C

GATE_D

GATE_A

GATE_B

RESET#

FIGURE 3. ISL6123, ISL6124 TURN-OFF TIMING DIAGRAM

Typical Performance Curves

1.04

1.03

634

633

632

V

= 5V

DD

1.02

631

630

629

628

627

626

1.01

1.00

V

= 1.5V

DD

V

= 1.5V

DD

0.99

0.98

0.97

DLY_OFF/ON

V

= +5V

DD

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

TEMPERATURE (°C)

FIGURE 4. UVLO THRESHOLD VOLTAGE

FIGURE 5. DLY CHARGE CURRENT

FN9005.8

February 5, 2007

9

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Typical Performance Curves (Continued)

GATE

5VOUT

3.3VOUT

SYSRST#

2V/DIV

1μs/DIV

FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF

The default configuration of the ISL612XSEQEVAL1

circuitries was built around the following design

assumptions:

Using the ISL612XSEQEVAL1 Platform

The ISL612XSEQEVAL1 platform is the primary evaluation

board for this family. The board has two complete, separate

and electrically identical circuits. See Figure 15 for its

schematic and photograph. Additionally, there is an ISL6125

specific eval platform, ISL6125EVAL1, due to its unique

open drain outputs for ease of evaluation. See Figure 16 for

its schematic and photograph.

1. Using the ISL6123IR or ISL6124IR

2. The four supplies being sequenced are 5V (IN_A), 3.3V

(IN_B), 2.5V (IN_C) and 1.5V (IN_D), the UVLO levels

are ~80% of nominal voltages. Resistors chosen such

that the total resistance of each divider is ~10k using

standard value resistors to approximate 80% of

nominal = 0.63V on UVLO input.

In the top right hand corner of the board is a SMD layout with

a ISL6123 illustrating the full functionality and small

implementation size for an application having the highest

component count.

Resistor choice is such that I x R2 = 0.633V at the desired

UV (undervoltage) level as the monitored voltage

decreases. Total resistance in the divider is a factor for

the designer to consider for accuracy of UV level and

efficiency vs electrical noise immunity trade-offs.

The majority of the board is given over to a socket and

discrete through-hole components circuit for ease of

evaluation flexibility through IC variant swapping and

modification of UVLO levels and sequencing order by

passive component substitution.

Vmonitored

Vmon/0.633mV = R1+R2/R2

when Vmon = desired UV level as

Vmon decreases.

R1

For example, a 5V supply with a

desired UV level at 4V would mean

R1+R2/R2 = 6.319. Ideally, any R1

and R2 combination that met this ratio

would work, but with only standard

value resistors available, small

deviations will occur.

The board is shipped with the ISL6123 installed in both

locations and with two each of the other released variant

types loose packed. As this sequencer family has a common

function pinout there are no major modifications to the board

necessary to evaluate the other ICs.

UVLO

R2

To the left, right and above the socket are four test point

strips (TP1, TP2, TP3, TP4). These give access to the

labeled IC I/O pins during evaluation. Remember that

significant current or capacitive loading of particular I/O pins

will affect functionality and performance.

3. The desired order turn-on sequence is first both 5V and

3.3V supplies together and then the 2.5V supply about

75ms later and lastly the 1.5V supply about 45ms later.

4. The desired turn-off sequence is first both 1.5V and 3.3V

supplies at the same time then the 2.5V supply about

50ms later and lastly the 5V supply about 72ms after that.

Attention to orientation and placement of variant ICs in the

socket must be paid to prevent IC damage or faulty

evaluation.

All scope shots are taken from ISL612XSEQEVAL1 board.

Figures 7 and 8 illustrate the desired turn-on and turn-off

sequences respectively. The sequencing order and delay

between voltages sequencing is set by external capacitance

values, so other than illustrated can be accomplished.

FN9005.8

February 5, 2007

10

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Figures 9 and 10 illustrate the timing relationships between the

Figure 13 shows the ISL6127 pre-programmed ABCD on

DCBA off order of sequencing with minimal non-adjustable

delay between each.

EN input, RESET#, DLY and GATE outputs and the VOUT

voltage for a single channel being turned on and off

respectively. RESET# is not shown in Figure 9 as it asserts

160ms after the last GATE goes high.

Figure 14 demonstrates the independence of the redundant

two rail sequencer. It shows that either one of the two groups

can be turned off and the ABCD order of restart with

capacitor programmable delay once both EN inputs are

pulled low.

All IC family variants share similar function for DLY_X capacitor

charging, GATE and RESET# operation. Figures 11 through 14

illustrate the principal feature and functional differences for

each of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.

Using the ISL6125EVAL1 Platform

Figure 11 features the ISL6125 open drain outputs being

sequenced on and off along with RESET# relationship which is

similar to all other family variants.

The ISL6125EVAL1 is the ISL6125 specific evaluation board

providing for easy evaluation of the ISL6125 with its unique

open drain outputs. The UVLO levels, sequence and delays

are programmed exactly like the other ISL612X ICs but the

ISL6125 has sequenced open drain outputs rather than

charge pumped driven GATE outputs. See Figure 16 for its

schematic and photograph.

Figure 12 illustrates the independent input feature of the

ISL6126 which allows once the EN# is low for each UVLO to be

individually satisfied and for its associated GATE to turn-on.

Only when the last variable VIN is satisfied as shown does the

RESET# release to signal all input voltages are valid.

Typical Performance Waveforms

5VOUT

RESET#

3.3VOUTPUT

3.3VOUT

ENABLE#

2.5VOUT

1.5VOUT

2.5VOUT

1.5VOUT

ENABLE#

1V/DIV

40ms/DIV

1V/DIV

20ms/DIV

FIGURE 8. ISL6124 SEQUENCED TURN-OFF

FIGURE 7. ISL6124 SEQUENCED TURN-ON

T

delENLO

GATE 2V/DIV

3.3VO 1V/DIV

DLY_Vth

RESET# 2V/DIV

EN 2V/DIV

DLY_ON 1V/DIV

DLY_OFF 1V/DIV

EN 2V/DIV

10ms/DIV

4ms/DIV

FIGURE 10. ISL6123 SINGLE CHANNEL TURN-OFF

FIGURE 9. ISL6123 SINGLE CHANNEL TURN-ON

FN9005.8

February 5, 2007

11

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Typical Performance Waveforms (Continued)

VIN_VAR

EN#

RESET#

STATIC EN/ALL OTHER VOUT

VOUT_VAR

LOGIC A -D

SEQUENCED

OUTPUTS

TRSTdel

RESET#

100ms/DIV

FIGURE 11. ISL6125 LOGIC OUTPUTS SEQUENCED ON AND

OFF AND RESET# RELATIONSHIP

FIGURE 12. ISL6126 UVLO INPUT/OUTPUT INDEPENDENCE

AND RESET# RELATIONSHIP

EN#_1 5V/DIV

A_VOUT

EN#_2 5V/DIV

B_VOUT

C_VOUT

D_VOUT

A_VOUT

B_VOUT

C_VOUT

D_VOUT

FIGURE 13. ISL6127 PREPROGRAMMED ABCD TURN-ON AND

DCBA TURN-OFF

FIGURE 14. ISL6128 GROUP INDEPENDENT TURN-OFF AND

DELAY ADJUSTABLE PRE PROGRAMMED TURN-ON

FN9005.8

February 5, 2007

12

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

IND = +1.5V

INC = +2.5V

INB = +3.3V

INA and VDD = +5V

C1

23

V

1μF

C2

1

DD

8

EN1

EN2

ENABLE1 DLY_ON_B

ENABLE2 DLY_ON_D

DLY_ON_C

C6

11

0.01μF

15

16

21

C3

0.1μF

C7

0.068μF

DLY_ON_A

R5

7.681k 4.99k 6.98k 8.45k

R7

R3

R1

0.01μF

S1

C4

3

12

14

17

20

UVLO_B

UVLO_D

UVLO_C

DLY_OFF_C

DLY_OFF_D

DLY_OFF_B

C8

0.047μF

4

C5

0.01μF

C9

13

18

0.01μF

UVLO_A

DLY_OFF_A

0.1μF

5 6 SI4922DY

ISL612XIR

2

4

R2

2.26k

R4

R6

3.01k

R8

GATE_A

Q3

3

4.99k

1.47k

5

6

GATE_B

GATE_C

7 8 SI4922DY

2

7

22

19

Q3

SYSRST#

NC

GATE_D

5

6

1

SI4922DY

Q4

R10

750

20

4

9

24

SI4922DY

Q4

RESET#2

RESET#1

3

R9

750

1

7 8

GND

10

2

1

RL5

10 RL7

5

RL6

5

RL8

2

FIGURE 15. EVAL BOARD CHANNEL 1 SCHEMATIC AND ISL612xSEQEVAL1 PHOTOGRAPH

FN9005.8

February 5, 2007

13

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

2.5V_(IND) 1.5V_(INC)

5.0V_(INA)

3.3V_(INB)

C1

23

1µF

0.01µF

VDD

C2

C3

C4

C5

1

8

ENABLE

DLY_ON_B

DLY_ON_D

DLY_ON_C

DLY_ON_A

ENABLE

0.022µF

0.068µF

15

16

21

OPEN

U1

0.047µF

C6

12

14

17

20

3

UVLO_B

UVLO_D

UVLO_C

UVLO_A

DLY_OFF_C

DLY_OFF_D

DLY_OFF_B

DLY_OFF_A

OPEN

0.01µF

0.1µF

C7

C8

C9

4

13

18

A

2

5

6

7

R8

10k

GATE_A

GATE_B

GATE_C

GATE_D

ISL612X

SEQ_A

SEQ_B

SEQ_C

SEQ_D

R9

R10

R13

10k

22

SYSRST

9

11

25

NC

R7

750

24

RESET

D1

EP

GND

19

10

RESET

AGND

A

FIGURE 16. ISL6125EVAL1 SCHEMATIC AND PHOTOGRAPH

FN9005.8

February 5, 2007

14

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

TABLE 2. ISL612XSEQEVAL1 BOARD CHANNEL 1 COMPONENT LISTING

COMPONENT

DESIGNATOR

COMPONENT FUNCTION

ISL612X, 4 Supply Sequencer Socket

Voltage Rail Switches

COMPONENT DESCRIPTION

S1

Intersil, ISL612X4 Supply Sequencer Socket

Q3, Q4

SI4922DY or equivalent, Dual 8A, 30V, 0.018Ω, N-Channel

MOSFET

R7

R8

R1

R2

R5

R6

R3

R4

R9

R10

C7

C9

C2

C5

C3

C4

C6

C8

C1

D1

D2

RL8

RL7

RL6

RL5

5V to UVLO_A Resistor for Divider String

UVLO_A to GND Resistor for Divider String

3.3V to UVLO_B Resistor for Divider String

UVLO_B to GND Resistor for Divider String

2.5V to UVLO_C Resistor for Divider String

UVLO_C to GND Resistor for Divider String

1.5V to UVLO_D Resistor for Divider String

UVLO_D to GND Resistor for Divider String

RESET#1 LED Current Limiting Resistor

RESET#2 LED Current Limiting Resistor

5V turn-on Delay Cap. (13ms)

5V turn-off Delay Cap. (130ms)

3.3V turn-on Delay Cap. (13ms)

3.3V turn-off Delay Cap. (3ms)

2.5V turn-on Delay Cap. (88ms)

2.5V turn-off Delay Cap. (61ms)

1.5V turn-on Delay Cap. (130ms)

1.5V turn-off Delay Cap. (13ms)

Decoupling Capacitor

8.45kΩ 1%, 0402

1.47kΩ 1%, 0402

7.68kΩ 1%, 0402

2.26kΩ 1%, 0402

6.98kΩ 1%, 0402

3.01kΩ 1%, 0402

4.99kΩ 1%, 0402

750Ω 10%, 0805

0.01µF 10%, 6.3V, 0402

0.1µF 10%, 6.3V, 0402

0.01µF 10%, 6.3V, 0402

0.068µF 10%, 6.3V, 0402

0.047µF 10%, 6.3V, 0402

0.1µF 10%, 6.3V, 0402

0.01µF 10%, 6.3V, 0402

0.1µF, 0805

RESET#1 Indicating LED

0805, SMD LEDs Red

10Ω 20%, 3W Carbon

5Ω 20%, 3W Carbon

2Ω 20%, 3W Carbon

RESET#2 Indicating LED

5V Load Resistor

3.3V Load Resistor

2.5V Load Resistor

1.5V Load Resistor

FN9005.8

February 5, 2007

15

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

TABLE 3. ISL6125EVAL1 COMPONENT LISTING

COMPONENT

DESIGNATOR

COMPONENT FUNCTION

ISL6125, Four Supply Sequencer

COMPONENT DESCRIPTION

U1

Intersil, ISL6125, Four Supply Sequencer with Open Drain

Outputs

R6

R12

R1

R11

R2

R3

R4

R5

R9

C5

C9

C2

C8

C3

C7

C4

C6

C1

D1

R8

R9

R10

R13

5V to UVLO_A Resistor for Divider String

UVLO_A to GND Resistor for Divider String

3.3V to UVLO_B Resistor for Divider String

UVLO_B to GND Resistor for Divider String

2.5V to UVLO_D Resistor for Divider String

UVLO_D to GND Resistor for Divider String

1.5V to UVLO_C Resistor for Divider String

UVLO_D to GND Resistor for Divider String

RESET LED Current Limiting Resistor

5V turn-on Delay Cap. A

8.45kΩ 1%, 0402

1.47kΩ 1%, 0402

7.68kΩ 1%, 0402

2.26kΩ 1%, 0402

6.98kΩ 1%, 0402

3.01kΩ 1%, 0402

4.99kΩ 1%, 0402

750Ω 10%, 0805

DNP, 0402

5V turn-off Delay Cap. A (135ms)

3.3V turn-on Delay Cap.B (13.7ms)

3.3V turn-off Delay Cap. B (13.7ms)

2.5V turn-on Delay Cap.D (28ms)

2.5V turn-off Delay Cap. D

0.1µF 10%, 6.3V, 0402

0.01µF 10%, 6.3V, 0402

0.022µF 10%, 6.3V, 0402

DNP, 0402

1.5V turn-on Delay Cap. C (98ms)

1.5V turn-off Delay Cap. C (59ms)

Decoupling Capacitor

0.068µF 10%, 6.3V, 0402

0.047µF 10%, 6.3V, 0402

0.1µF, 0805

RESET#1 Indicating LED

0805, SMD LED

10kΩ, 0402

SEQ_OUTPUT_A Pull-Up Resistor

SEQ_OUTPUT_B Pull-Up Resistor

SEQ_OUTPUT_C Pull-Up Resistor

SEQ_OUTPUT_D Pull-Up Resistor

10kΩ, 0402

Three configurations are described and illustrated here.

Application Implementations

In applications where the integrity of critical voltages must be

assured prior to sequencing, additional monitoring of the

critical supplies is needed. If the compliance of the voltage is

critical for either undervoltage and/or overvoltage, the

ISL613X family of supervisors can be employed to provide

this additional assurance across multiple sequencers. See

document FN9115 for supervisor data sheet. Figure 17 is a

block diagram of this voltage compliant, high assurance, low

risk configuration showing the ISL613X supervisor and a mix

of FET switched outputs and logic output sequencers

(ISL6124 and ISL6125 ICs).

Multiple Sequencer Implementations

In order to control the sequencing of more than 4 voltages,

several of the ISL6123, ISL6124, ISL6125 or ISL6127

devices can be variously configured together to accomplish

this. There may be concerns of a particular implementation

that would make a particular configuration preferable over

another. The fundamental questions to answer to determine

which configuration is best suited for your applications are:

1. What level of voltage assurance is needed prior to

sequencing on and can the voltage supplies be grouped

into high and low criticality?

2. Is there a critical maximum time window all supplies must

be present at load or is there a first and a second group

preference possibly with some work done in between the

two groups of voltages being present?

FN9005.8

February 5, 2007

16

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

ISL613Xs

OE

MONITORING

ON ALL RAILS

LOW = RESET

VMON

PGOOD

UVLO

SYSRST#

ISL6124

# N

G

A

T

SYSRST#

UVLO

ISL6124

# N

en

RESET#

G

E

UVLO

A

T

E

en

ENABLE#

RESET#

ENABLE#

SYSRST#

RESET#

ENABLE#

SYSRST#

ISL6125

# N+1

L

O

G

I

RESET#’

POWER

SUPPLY

RESET#

UVLO

ISL6125

# N+1

L

O

G

I

C

POWER

SUPPLY

RESET#

UVLO

C

FIGURE 18. MULTIPLE ISL612X USING LOGIC GATES FOR

VOLTAGE PRESENCE DETECT

FIGURE 17. ISL612X AND ISL613X VOLTAGE COMPLIANT

SEQUENCING BLOCK DIAGRAM

prevent the turn-on sequence from completing if there is one

unsatisfied UVLO input in a group. Using this configuration

If the mere presence of some voltage potential is adequate

prior to sequencing on, then a small number of standard

logic AND gates can be used to accomplish this. The block

diagram in Figure 18 illustrates this voltage presence

configuration.

involves waiting through the T

and T

(total of

UVLOdel

RSTdel

~160ms) for each sequencer IC in the chain for the final

RESET# to release. Once ENABLE on the first sequencer is

deasserted all the RESET# outputs will quickly pull low and

thus allow the sequenced turn-off of this configuration to

ripple through several banks as quickly as the user

In either case, the sequencing is straight forward across

multiple sequencers as all DLY_ON capacitors will

simultaneously start charging ~10ms after the common

ENABLE input signal is delivered. This allows the choice of

capacitors to be related to each other no different than using

a single sequencer. When the common enabling signal is

deasserted these configurations will then execute the

turn-off sequence across all sequencers as programmed by

the DLY_OFF capacitor values.

programmed sequence as chosen by the DLY_OFF

capacitors allow. Once again with common bussed

SYSRTS# pins, simultaneous shut down of all GATEs and

LOGIC down upon an unsatisfied UVLO input is assured

once all FETs or LOGIC output are on. If a GATE drive

option IC is used to drive both FETs and logic signals then

care to ensure the charged pump GATE does not over drive

and damage the logic input must be taken. A simple resistor

divider can be used to lower the GATE voltage to a suitable

voltage for the logic input as shown in Figure 19.

In both cases, with all the SYSRST# pins bussed together,

once the on sequence is complete, simultaneous shutdown

upon any UVLO input failure is assured as SYSRST# output

will momentarily pull low turning off all GATE and LOGIC

outputs.

There may be applications that require or allow groups of

supplies being brought up in sequence and supplies within

each group to be sequenced. Figure 19 illustrates such a

configuration that allows the first group of supplies to turn-on

before the second group starts. This arrangement does not

necessarily preclude adding the assurance of all supplies

prior to turn-on sequencing as previously shown but it will

FN9005.8

February 5, 2007

17

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

OE

LOW = RESET

SYSRST#

ISL6124

# N

G

UVLO

A

T

ENABLE

E

ENABLE#

RESET#

TO LOGIC

INPUT

ENABLE#

SYSRST#

FIGURE 20. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING

ISL6125

# N+1

L

O

G

I

POWER

SUPPLY

RESET#

UVLO

C

RESET#

FIGURE 19. MULTIPLE ISL612X SERIAL CONFIGURATION

Voltage Tracking

In some applications the various voltages may have to track

each other as they ramp up and down, whereas others may

just need sequencing. In these cases tracking can be

accomplished and has been demonstrated over a wide

range of load current (1A to 10A) and load capacitance

(10µF to 3300µF) with the ISL612X family. Figure 20 and

Figure 21 illustrate output voltage ramping tracking

performance, note that differences are less than 0.5V. With

the relevant GATE pins tied together in a star pattern, so that

the resistance between any two GATE pins is equivalent (1k

to 10k) results in a sharing of the GATE ramping voltage and

with the same or similar enough FETs this behavior is

observed.

FIGURE 21. OUTPUT VOLTAGE HIGH TO LOW TRACKING

It is suggested that this circuit implementation be prototyped

and evaluated for the particular expected loads prior to

committing to manufacturing build.

FN9005.8

February 5, 2007

18

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Negative Voltage Sequencing

+V

The ISL612X family can use the charged pump GATE output

to drive FETs that would control and sequence negative

voltages down to a nominal -5V with minimal additional

external circuitry. Figure 22 shows turn-on of 5V bipolar

supplies together, then the +2.5V and turn-off of both

positive supplies being turned off together after the -5V.

Figure 23 shows the minimal additional external circuitry to

accomplish this. The 5V zener diode is used to level shift the

GATE drive down 5V to prevent premature turn-on when

GATE = 0V. Once GATE drive voltage > Vz, then FET

Vgs > 5V, ensuring full turn-on once GATE gets to

+BIAS

R5

R1

R2

R3

(10k)

(1k)

ISL6131

OR

ISL6536A

VMON

Q1 Si1300DL

OR EQUIV.

R4

PGOOD

(15K)

TO UVLO OF

-BIAS

ISL612X FOR

-V CONTROL AND

SEQUENCING

R6

-V

R1 and R2 define -V UVLO level

R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up

R4 and R5 provide Q1 gate bias between 0V and +V

to 0V (resistor values suitable for -V = -5V and +V = +3.3V)

VDD+5.3V. Turn-on and turn-off ramp rate can be adjusted

with FET gate series resistor value. Sequencing of the -V rail

is accomplished as normal via the DLY_X capacitor value

although adjustments in prototyping should be factored in to

fine tune for actual circuit requirements.

FIGURE 24. HGH ACCURACY -V LOCK OUT

+V

R1

Figures 24 and 25 illustrate a high accuracy -V detection

circuit using the ISL6131 and a low cost low accuracy -V

detect circuit and respectively.

TO UVLO OF ISL612X FOR CONTROL

AND SEQUENCING OF -V

R2

Chose R1 and R2 values to drive UVLO

high when -V is sufficiently present

-V

FIGURE 25. LOW ACCURACY -V PRESENCE DETECTION

Application Considerations

Timing Error Sources

In any system there are variance contributors, for the ISL612X

family the timing errors are mainly contributed by three sources.

Capacitor Timing Mismatch Error

Obviously, the absolute capacitor value is an error source,

thus lower percentage tolerance capacitors help to reduce

this error source. Figure 26 illustrates a difference of 0.57ms

between two DLY_X outputs ramping to DLY_X threshold

voltage, these 5% capacitors were from a common source.

In applications where two or more GATEs or LOGIC outputs

must have concurrent transitions, it is recommended that a

common GATE drive be used to eliminate this timing error.

FIGURE 22. ±VOLTAGE SEQUENCING

-Vout

-Vin

R1

D1

ISL612X GATE

Additional 2 components

necessary for -V control

and sequencing.

D1 necessary to prevent premature turn-on. R1 is used to hold

FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to

adjust -V ramp rates. Choose a R1 value between 4MΩ and 10MΩ

initially and fine tune resistor value for the particular need.

FIGURE 23. -VOLTAGE FET DRIVE CIRCUIT

FIGURE 26. CAPACITOR TIMING MISMATCH

FN9005.8

February 5, 2007

19

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

DLY_X Threshold Voltage and Charging Current

Mismatch

The two other error sources come from the IC itself and are

the differences in the DLY_X threshold voltage, (DLY_Vth)

when the GATE charging latch is set and the DLY_X

charging current, (DLY_ichg) across the four individual I/Os.

Both of these parameters are bounded by specification and

Figure 27 illustrates that with a common capacitor the typical

error contributed by these factors is insignificant as both

DLY_X traces overlay each other.

FIGURE 27. DLY_VTH AND DLY_ICHG TIMING MISMATCH

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9005.8

February 5, 2007

20

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130

Package Outline Drawing

L24.4x4

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

4X

2.5

4.00

A

20X

0.50

PIN #1 CORNER

(C 0 . 25)

B

19

24

PIN 1

INDEX AREA

1

18

2 . 10 ± 0 . 15

13

0.15

(4X)

12

24X 0 . 4 ± 0 . 1

7

0.10 M C

A B

TOP VIEW

+ 0 . 07

24X 0 . 23

4

- 0 . 05

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

0 . 90 ± 0 . 1

C

BASE PLANE

( 3 . 8 TYP )

SEATING PLANE

0.08

SIDE VIEW

C

(

2 . 10 )

( 20X 0 . 5 )

5

C

0 . 2 REF

( 24X 0 . 25 )

0 . 00 MIN.

0 . 05 MAX.

( 24X 0 . 6 )

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9005.8

February 5, 2007

21


型号：	ISL6125EVAL1
厂家：	Intersil
描述：	Power Sequencing Controllers 电源排序控制器控制器
文件：	总21页 (文件大小：493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6125EVAL1 [INTERSIL]

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