ISL6126IRZA [RENESAS]
4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24;
| 型号： | ISL6126IRZA |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC24, 4 X 4 MM, ROHS COMPLIANT, PLASTIC, QFN-24 |
| 文件： | 总23页 (文件大小：1057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128,
ISL6130
FN9005
Rev 1.00
September 26, 2012
The Intersil ISL6123, ISL6124, ISL6125, ISL6126, ISL6127,
Features
ISL6128 and ISL6130 are integrated 4-channel
controlled-on/controlled-off power-supply sequencers with
supply monitoring, fault protection and a “sequence completed”
signal (RESET). For larger systems, more than four supplies can
be sequenced by simply connecting a wire between the
SYSRESET pins of cascaded ICs. The ISL6125 uses four active
open-drain outputs to control the on/off sequencing of four
supplies. The other sequencers use a patented, micropower 7x
charge pump to drive four external low-cost NFET switch gates
above the supply rail by 5.3V. These ICs can be biased from 5V
down to 1.5V by any supply.
• Enables Arbitrary Turn-on and Turn-off Sequencing of Up to Four
Power Supplies (0.7V to 5V)
• Operates From 1.5V to 5V Supply Voltage
• Supplies V +5.3V of Charge Pumped Gate Drive
DD
• Adjustable Voltage Slew Rate for Each Rail
• Multiple Sequencers Can be Daisy-Chained to Sequence an
Infinite Number of Independent Supplies
• Glitch Immunity
• Undervoltage Lockout for Each Supply
• 1µA Sleep State (ISL6123, ISL6130)
The 4-channel ISL6123 (ENABLE input), ISL6124 (ENABLE
input) and ISL6125 offer the designer 4-rail control when all
four rails must be in minimal compliance before turn-on and
during operation. The ISL6123 and ISL6130 have a low-power
standby mode when disabled, which is suitable for
battery-powered applications.
• Active High (ISL6123, ISL6130) ENABLE or Low (ISL6124,
ISL6125, ISL6126, ISL6127, ISL6128) ENABLE Input
• Active Open Drain Version Available (ISL6125)
• Voltage-determined Sequence (ISL6126, ISL6130)
• Pre-programmed Sequence Available (ISL6127)
• Dual Channel Groupings (ISL6128)
• QFN Package
The ISL6125 operates like the ISL6124, but instead of
charge-pump-driven gate drive outputs, it has open-drain logic
outputs for direct interface to other circuitry.
In contrast, for the ISL6126 and ISL6130, each of the four
channels operates independently. Each GATE turns on once its
individually associated input voltage requirements are met.
• Pb-free (RoHS-compliant)
Applications
• Graphics Cards
The ISL6127 is a pre-programmed A-B-C-D turn-on and D-C-B-A
turn-off sequenced IC. Once all inputs are in compliance and
ENABLE is asserted, sequencing begins. Each subsequent GATE
turns on after the previous one turns on.
• FPGA/ASIC/Microprocessor/PowerPC Supply Sequencing
• Network Routers
• Telecommunications Systems
The ISL6128 has two groups of two channels, each with its
independent I/O. It is ideal for voltage sequencing into
redundant capability loads. All four inputs must be satisfied
before turn-on, but a single group fault is ignored by the other
group.
V1
V1OUT
V2
V3
V4
V2OUT
V3OUT
V4OUT
External resistors provide flexible voltage threshold
programming of monitored rail voltages. Delay and
sequencing are provided by external capacitors for ramp-up
and ramp-down.
Additional I/O is provided for indicating and driving the RESET
state in various configurations.
V
DD
ENABLE
SYSRST
RESET
UVLO_A
UVLO_B
UVLO_C
UVLO_D
For volume applications, other programmable options and
features are available. Contact Intersil sales support with your
needs.
GROUND
FIGURE 1. TYPICAL ISL6123 APPLICATION
FN9005 Rev 1.00
Page 1 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Ordering Information
PART NUMBER
PACKAGE
(Pb-free)
(Notes 1, 2, 3)
PART MARKING
61 23IRZ
TEMP. RANGE (°C)
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PKG. DWG. #
L24.4x4
ISL6123IRZA
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
ISL6124IRZA
ISL6125IRZA
ISL6126IRZA
ISL6127IRZA
ISL6128IRZA
ISL6130IRZA
ISL6123EVAL1Z
ISL6125EVAL1Z
NOTES:
61 24IRZ
L24.4x4
L24.4x4
L24.4x4
L24.4x4
L24.4x4
L24.4x4
61 25IRZ
61 26IRZ
61 27IRZ
61 28IRZ
61 30IRZ
ISL6123 Evaluation Platform
ISL6125 Evaluation Platform
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130. For
more information on MSL please see Tech Brief TB363.
VDD+5V
Q-PUMP
BIAS
VDD
P1
P2
V1OUT
V2OUT
LOCK OUT
S1
en
S2
en
1µA
S3
en
V3OUT
V4OUT
1µA
P3
S4
en
DLY_ONX
V
DD
1.26V
-1µA
1µA
UVLO_A
UVLO_B
UVLO_C
UVLO_D
SYSRST
RESET
ISL6125
ENABLE
DLY_OFFX
GROUND
10ms
RISING DELAY
1.26V
GATEX
30µs
FILTER
UVLOX
FIGURE 2. ISL6125 APPLICATION
RESET
LOGIC
0.633V
150ms
RISING DELAY
EN
SYSRST
FIGURE 3. ISL6123 BLOCK DIAGRAM (1/4)
FN9005 Rev 1.00
Page 2 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Configurations
ISL6123, ISL6124, ISL6125
(24 LD QFN)
ISL6127
(24 LD QFN)
TOP VIEW
TOP VIEW
24 23 22 21 20 19
24 23 22 21 20 19
ENABLE_1/
ENABLE_1
ENABLE_1/
18 DLY_OFF_A
18 NC
1
2
3
4
5
6
1
2
3
4
5
6
ENABLE_1
GATE_A
17
16
15
14
17
16
15
14
GATE_A
*OUTPUT_A
UVLO_C
UVLO_C
NC
DLY_OFF_C
DLY_OFF_D
DLY_ON_C
DLY_ON_D
UVLO_D
NC
NC
EPAD
(GND)
EPAD
(GND)
NC
GATE_B
*OUTPUT_B
GATE_B
GATE_C
UVLO_D
GATE_C
13 DLY_OFF_B
13 NC
*OUTPUT_C
7
8
9
10 11 12
7
8
9
10 11 12
*OUTPUT_A, OUTPUT_B, OUTPUT_C, OUTPUT_D ARE UNIQUE TO
ISL6125
ISL6126, ISL6130
(24 LD QFN)
ISL6128
(24 LD QFN)
TOP VIEW
TOP VIEW
24 23 22 21 20 19
ENABLE_1/
24 23 22 21 20 19
18 DLY_OFF_A
17
1
2
3
4
5
6
ENABLE_1
GATE_A
18 DLY_OFF_A
1
2
3
4
5
6
ENABLE_1
GATE_A
UVLO_C
16 NC
15
17
16
15
UVLO_C
DLY_OFF_C
DLY_OFF_D
GATE_B
DLY_OFF_C
DLY_OFF_D
GATE_B
DLY_ON_C
DLY_ON_D
EPAD
(GND)
EPAD
(GND)
NC
14 UVLO_D
14 UVLO_D
GATE_C
13 DLY_OFF_B
GATE_C
13 DLY_OFF_B
7
8
9
10 11 12
7
8
9
10 11 12
FN9005 Rev 1.00
Page 3 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Pin Descriptions
PIN NUMBER
PIN
ISL6123, ISL6124, ISL6126,
NAME
ISL6125
ISL6130 ISL6127 ISL6128
DESCRIPTION
Chip Bias. Bias IC from nominal 1.5V to 5V.
Bias Return. IC ground.
V
23
10
1
23
10
1
23
10
1
23
10
1
DD
GND
ENABLE_1/
ENABLE_1
Input to start on/off sequencing. Input to initiate start of programmed
sequencing of supplies on or off. Enable functionality disabled for 10ms after
UVLO is satisfied. ISL6123 and ISL6130 have ENABLE, and ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE. Only ISL6128 has two ENABLE
inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and
ENABLE_2 is for (C, D).
ENABLE_2/
ENABLE_2
NC
NC
NC
11
RESET
24
NC
24
NC
24
NC
24
9
RESET Output. RESET provides low signal 150ms after all GATEs are fully
enhanced. Delay is for stabilization of output voltages. RESET asserts low
upon UVLO not being satisfied or ENABLE/ENABLE being deasserted. RESET
outputs are open-drain, N-channel FET and are guaranteed to be in correct
state for VDD down to 1V and are filtered to ignore fast transients on VDD and
UVLO_X.
RESET_2
RESET_2 only exists on ISL6128 for (C, D) group I/O.
UVLO_A
UVLO_B
20
20
12
17
14
20
12
17
14
20
12
17
14
21
8
Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout
referenced to an internal 0.633V reference. Filtered to ignore short (<30µs)
transients below programmed UVLO level.
12
UVLO_C
17
UVLO_D
14
DLY_ON_A
DLY_ON_B
DLY_ON_C
DLY_ON_D
DLY_OFF_A
DLY_OFF_B
DLY_OFF_C
DLY_OFF_D
GATE_A
21
Gate On Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-on using a capacitor to ground. Each capacitor charged with 1µA
10ms after turn-on initiated by ENABLE/ENABLE. Internal current source
provides delay to associated FET GATE turn-on.
8
16
16
15
18
13
3
15
18
18
13
3
Gate Off Delay Timer Output. Allows programming of delay and sequence for
VOUT turn-off through ENABLE/ENABLE via a capacitor to ground. Each
capacitor charged with 1µA internal current source to an internal reference
voltage, causing corresponding gate to be pulled down, thus turning off FET.
13
3
4
4
4
2
2
2
5
6
7
2
FET Gate Drive Output. Drives external FETs with 1µA current source to soft-
start ramp into load.
GATE_B
5
5
5
GATE_C
6
6
6
GATE_D
7
7
7
OUTPUT_A
OUTPUT_B
OUTPUT_C
OUTPUT_D
SYSRST
2 (ISL6125)
5 (ISL6125)
6 (ISL6125)
7 (ISL6125)
22
On ISL6125 only, these are ACTIVE open drain outputs that can be pulled up
to a maximum of VDD voltage.
22
System Reset I/O. As an input, allows for immediate and unconditional latch-off
of all GATE outputs when driven low. This input can also be used to initiate
programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from input
signal on this pin being driven high to first GATE. As an output, when there is a UV
condition, this pin pulls low. If common to other SYSRST pins in a multiple IC
configuration, it causes immediate and unconditional latch-off of all other GATEs
on all other ISL612X sequencers.
GND
NC
EPAD
9, 19
EPAD
EPAD
EPAD
Ground. Die Substrate. Can be left floating.
No Connect
8, 9, 11, 3, 4, 8, 9,
15, 16, 11, 13,
19, 22
19, 21, 22 15,16,18,
19, 21
FN9005 Rev 1.00
Page 4 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL612X and ISL6130 Variant Feature Matrix
NUMBER OF
NUMBER OF
GATE DRIVE
OR OPEN
DRAIN
REQUIRED
CONDITIONS
FOR INITIAL
START-UP
UVLO INPUTS CHANNELSTHAT
MONITORED TURNOFFWHEN
PRESET OR
ADJUSTABLE
SEQUENCE
NUMBER OF
UVLO AND
PAIRS OF I/O
PART
NAME
CMOS/
TTL
BY EACH
RESET
ONE UVLO
FAULTS
EN/EN
EN
OUTPUTS
FEATURES
ISL6123
TTL
Gate Drive
4 UVLO
1 EN
4 UVLO
4 Gates
Time Adjustable
On and Off
4 Monitors Auto Restart,
with 1 I/O Low Bias Current
Sleep
ISL6124
ISL6125
EN
EN
CMOS
CMO
Gate Drive
4 UVLO
1 EN
4 UVLO
4 UVLO
4 Gates
Time Adjustable
On and Off
4 Monitors Auto Restart
with 1 I/O
Open Drain
4 UVLO
1 EN
4 Open Drain
Time Adjustable
On and Off
4 Monitors Auto Restart, Open
with 1 I/O Drain Sequenced
Outputs
ISL6126
EN
CMOS
Gate Drive
1 UVLO
1 EN
4 UVLO
1 Gate
Voltage
Determined ON
Time Adjustable
Off
4 Monitors Gates Independent
with 1 I/O On as UVLO Valid
ISL6127
ISL6128
ISL6130
EN
EN
EN
CMOS
CMOS
TTL
Gate Drive
Gate Drive
Gate Drive
4 UVLO
1 EN
4 UVLO
2 UVLO
4 UVLO
4 Gates
2 Gates
1 Gate
Preset
4 Monitors Auto Restart
with 1 I/O
4 UVLO
2 EN
Preset
2 Monitors Dual Redundant
with 2 I/O Operation
1 UVLO
1 EN
Voltage
Determined ON
Time Adjustable
Off
4 Monitors Gates Independent
with 1 I/O On as UVLO Valid
Low Bias Current
Sleep
FN9005 Rev 1.00
Page 5 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Absolute Maximum Ratings (Note 6)
Thermal Information
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V
Thermal Resistance (Typical)
24 Ld 4x4 QFN Package (Notes 4, 5) . . . . .
(°C/W)
46
JC
(°C/W)
8
DD
JA
GATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +6V
DD
ISL6125 LOGIC OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
DD
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
UVLO, ENABLE, ENABLE, SYSRST . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
DD
RESET, DLY_ON, DLYOFF . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V + 0.3V
DD
Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.5V to +5.5V
DD
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 for details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
V
= 1.5V to +5V, T = T = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
DD A J
operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
UVLO
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
Falling Undervoltage Lockout Threshold
Undervoltage Lockout Threshold Tempco
Undervoltage Lockout Hysteresis
Undervoltage Lockout Threshold Range
Undervoltage Lockout Delay
Transient Filter Duration
V
T = +25°C
619
633
40
10
7
647
mV
µV/°C
mV
UVLOvth
J
TC
UVLOvth
V
UVLOhys
RUVLOvth
TUVLOdel
Max V
- Min V
UVLOvth
mV
UVLOvth
ENABLE satisfied
10
30
ms
t
V
, UVLO, ENABLE glitch filter
µs
FIL
DD
DELAY ON/OFF
Delay Charging Current
DLY_ichg
DLY_ichg_r
TC_DLY_ichg
V
= 0V
0.92
1
1.08
µA
µA
DLY
Delay Charging Current Range
DLY_ichg(max) - DLY_ichg(min)
0.08
0.2
Delay Charging Current Temperature
Coefficient
nA/°C
Delay Threshold Voltage
DLY_Vth
1.238
1.266
0.2
1.294
V
Delay Threshold Voltage Temperature
Coefficient
TC_DLY_Vth
mV/°C
ENABLE/ENABLE, RESET AND SYSRST I/O
ENABLE Threshold
V
V
1.2
V
V
ENh
ENh
ENABLE Threshold
0.5 V
DD
ENABLE/ENABLE Hysteresis
ENABLE/ENABLE Lockout Delay
ENABLE/ENABLE Input Capacitance
RESET Pull-up Voltage
V
V
Measured at V = 1.5V
DD
0.2
10
5
V
ENh - ENl
t
UVLO satisfied
ms
pF
V
delEN_LO
Cin_en
Vpu_rst
V
DD
RESET Pull-Down Current
I
5
mA
mA
mA
V
V
V
= 1.5V, RST = 0.1V
= 3.3V, RST = 0.1V
= 5V, RST = 0.1V
RSTpd1
DD
DD
DD
I
13
17
RSTpd3
I
RSTpd5
FN9005 Rev 1.00
Page 6 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Electrical Specifications
V
= 1.5V to +5V, T = T = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
A J
DD
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
RESET Delay after GATE High
RESET Output Low
SYMBOL
TEST CONDITIONS
(Note 7)
TYP
160
(Note 7)
UNIT
ms
V
T
GATE = V +5V
DD
RSTdel
V
0.1
Measured at V = 5V with 5k
DD
RSTl
pull-up resistors
RESET Output Capacitance
SYSRST Pull-Up Voltage
SYSRST Pull-Down Current
C
10
pF
V
OUT_RST
Vpu_srst
Ipu_1.5
Ipu_5
V
DD
V
V
V
= 1.5V
= 5V
5
µA
µA
mV
pF
ns
DD
DD
DD
100
150
10
SYSRST Low Output Voltage
SYSRST Output Capacitance
SYSRST Low to GATE Turn-Off
GATE
Vol_srst
Cout_srst
= 1.5V, I
= 100µA
OUT
t
GATE = 80% of V + 5V
DD
40
delSYS_G
GATE Turn-On Current
GATE Turn-Off Current
GATE Current Range
I
GATE = 0V
0.8
1.1
1.4
-0.8
0.35
µA
µA
GATEon
I
GATE = V , Disabled
DD
-1.4
-1.05
GATEoff_l
I
Within IC I
max-min
GATE
µA
GATE_range
GATE Turn-On/Off Current Temperature
Coefficient
TC_I
0.2
88
nA/°C
GATE
GATE Pull-Down High Current
GATE High Voltage
I
GATE = V , UVLO = 0V
DD
mA
V
GATEoff_h
V
V
V
< 2V, T = +25°C
J
V
V
+ 4.9V
GATEh
GATEh
DD
DD
DD
V
> 2V
V
+ 5V
+ 5.3V
0
V
DD
DD
GATE Low Voltage
V
Gate Low Voltage, V = 1V
DD
0.1
V
GATEl
ISL6125 OPEN DRAIN
Open Drain On Resistance
R
V
V
V
= 5V, EN = V
DD
25
32
40
DSON_5V
DSON_3.3V
DSON_2.5V
DD
DD
DD
R
R
= 3.3V, EN = V
= 2.5V, EN = V
DD
DD
BIAS
IC Supply Current
I
V
V
V
V
= 5V
0.20
0.14
0.10
0.5
mA
mA
mA
µA
V
VDD_5V
DD
DD
DD
DD
I
= 3.3V
= 1.5V
VDD_3.3V
VDD_1.5V
I
ISL6123, ISL6130 Stand By IC Supply Current
I
= 5V, ENABLE = 0V
1
1
VDD_sb
V _POR
DD
V
Power-on Reset
DD
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
are driven by an internal charge pump to V + 5.3V (VQP) in
DD
a user-programmed sequence.
Descriptions and Operation
The ISL612X sequencer family consists of several 4-channel
voltage sequencing controllers in various functional and
personality configurations. All are designed for use in
multiple-voltage systems requiring power sequencing of
various supply voltages. Individual voltage rails are gated on
and off by external N-Channel MOSFETs, the gates of which
With the 4-channel ISL6123, ENABLE must be asserted high,
and all four voltages to be sequenced must be above their
respective user-programmed undervoltage lockout (UVLO)
levels before programmed output turn-on sequencing can
begin. Sequencing order and delay are determined by the
choice of external capacitor values on the DLY_ON and
FN9005 Rev 1.00
Page 7 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_OFF pins. Once all four UVLO inputs and ENABLE are
satisfied for 10ms (t , the four DLY_ON capacitors
outputs to follow the programmed turn-off sequence,
similarly to the ISL6124.
delEN_LO)
are simultaneously charged with 1µA current sources to the
DLY_Vth level of 1.27V. As each DLY_ON pin reaches the
DLY_Vth level, its associated GATE turns on, with a 1µA
The ISL6127 is a 4-channel sequencer pre-programmed for
A-B-C-D turn-on and D-C-B-A turn-off. After all four UVLO and
ENABLE inputs are satisfied for ~10ms, the sequencing
starts. The next GATE in the sequence starts to ramp up once
the previous GATE has reached ~VQP-1V. After a period of
source current to the charge pump voltage (VQP) of V
+
DD
5.3V. Thus, all four GATEs sequentially turn on in the user
defined order. Once at DLY_Vth, the DLY_ON pins discharge
so they are ready when next needed.
160ms (T
) after the last GATE is at VQP, the RESET
RSTdel
output is deasserted. If any UVLO is unsatisfied, RESET is
pulled low, SYSRST is pulled low, and all GATEs are
simultaneously turned off. When ENABLE is signaled high,
the D GATE starts to pull low. Once below 0.6V, the next GATE
starts to pull low, and so on, until all GATEs are at 0V.
Unloaded, this turn-off sequence completes in <1ms.
After the entire turn-on sequence has been completed and all
GATEs have reached the charge pumped voltage (VQP), a
160ms delay (T
) is started to ensure stability, after
RSTdel
which the RESET output is released to go high.
After turn-on, if any input falls below its UVLO point for longer
than the glitch filter period (~30µs), it is considered a fault.
RESET and SYSRST are pulled low, and all GATEs are
simultaneously also pulled low. In this mode, the GATEs are
pulled low with 88mA.
This variant offers a lower cost and size implementation
because the external delay capacitors are not used. Because
the delay capacitors are not used, this IC cannot delay the
start of subsequent GATEs. Thus, necessary stabilization or
system housekeeping need to be considered.
Normal shutdown mode is entered when no UVLO is violated
and ENABLE is deasserted. When ENABLE is deasserted,
RESET is immediately asserted and pulled low. Next, all four
shutdown ramp capacitors on the DLY_OFF pins are charged
with a 1µA source. When any ramp-capacitor reaches
DLY_Vth, a latch is set, and a current is sunk on the
respective GATE pin to turn off its external MOSFET. When the
GATE voltage is approximately 0.6V, the GATE is pulled down
the rest of the way at a higher current level. Each individual
external FET is thus turned off, which removes the voltages
from the load in the user programmed sequence.
The ISL6128 is a 4-channel device that groups the four
channels into two groups of two channels each. Each group
of A, B and C, D, has its own ENABLE and RESET I/O pins. All
four UVLO and both ENABLEs must be satisfied for
sequencing to start. The A, B group turns on first, 10ms after
the second ENABLE is pulled low, with A then B turning on,
followed by C then D.
Once the preceding GATE = VQP, the next DLY_ON pin starts to
charge its capacitor; thus, all four GATEs turn on. Approximately
160ms after D GATE = VQP, the RESET output is released to go
high. Once any UVLO is unsatisfied, only the related group’s
RESET and two GATEs are pulled low. The related EN input must
be cycled for the faulted group to be turned on again.
The ISL6123 and ISL6124 have the same functionality,
except for the ENABLE active polarity; the ISL6124 has an
ENABLE input. Additionally, the ISL6123 and ISL6130 also
have an ultra low-power sleep state when ENABLE is low.
Normal shutdown is invoked by signaling both ENABLE inputs
high, which causes the two related GATEs to shut down in
reverse order from turn-on. DLY_X capacitors adjust the delay
between GATES during turn-on and turn-off, but not the order.
The ISL6125 has the same personality as the ISL6124, but
instead of charged-pump-driven GATE outputs, it has
open-drain outputs that can be pulled up to a maximum of
V
.
DD
During bias up, the RESET output is guaranteed to be in the
The ISL6126 and ISL6130 are different in that their on
sequence is not time determined but voltage determined.
Each of the four channels operate independently. Once the IC
is biased and any one of the UVLO inputs is greater than the
0.63V internal reference, and the ENABLE input is also
satisfied, the associated GATE for the satisfied UVLO input
turns on.
correct state, with V lower than 1V.
DD
Upon power-up, the SYSRST pin follows V with a weak
DD
internal pull-up. It is both an input and an output connection and
can provide two functions. As an input, if it is pulled low, all
GATEs are unconditionally shut off, and RESET pulls low
(Figure 8). This input can also be used as a no-wait enabling
input. If all inputs (ENABLE and UVLO) are satisfied, it does not
wait through the ~10ms enable delay to initiate DLY_ON
capacitor charging when released to go high. As an output, it is
useful when implementing multiple sequencers in a design
needing simultaneous shutdown, as with a kill switch across all
sequencers. Once any UVLO is unsatisfied longer than tFIL, the
related SYSRST pulls low. It also pulls low all other SYSRST
inputs that are on a common connection. By doing so, it
unconditionally shuts down all outputs across multiple
sequencers.
In turn, the other UVLO inputs must be satisfied for the
associated GATEs to turn on. After a period of 160ms
(T
) once all GATEs are fully on (GATE voltage = VQP),
RSTdel
RESET is released to go high.
The UVLO inputs can be driven by either a previously
turned-on output rail offering a voltage-determined sequence
or by logic signal inputs. Any subsequent UVLO level that is
less than its programmed level pulls the associated GATE and
RESET output low (if previously released) but does not
latch-off the other GATEs.
Except for the ISL6128 after a fault, restart of the turn-on
sequence is automatic, once all requirements are met. This
allows for no interaction between the sequencer and a controller
IC, if desired. The ENABLE and RESET I/O do allow for a higher
Predetermined turn-off is accomplished by deasserting
ENABLE. This causes RESET to latch low and all four GATE
FN9005 Rev 1.00
Page 8 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
level of feedback and control, if desired. The ISL6128 requires
that the related ENABLE be cycled for restart of its associated
group GATEs. If no capacitors are connected between DLY_ON or
DLY_OFF pins and ground, then all such related GATEs start to
turn on immediately after the 10ms (TUVLOdel) ENABLE
stabilization timeout has expired. The GATEs start to turn off
immediately when ENABLE is asserted.
TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD
DLY PIN CAPACITANCE
TIME(s)
0.00006
0.00013
0.0013
0.013
0.13
Open
100pF
1000pF
0.01µF
0.1µF
1µF
If some of the rails are sequenced together to reduce cost and
eliminate the effect of capacitor variance on the timing, a
common capacitor can be connected to two or more DLY_ON or
DLY_OFF pins. In this case, multiply the capacitor value by the
number of common DLY_X pins to obtain the desired timing.
1.3
10µF
13
Table 1 shows the nominal time delay on the DLY_X pins for
various capacitor values, from the start of charging to the 1.27V
reference. This table does not include the 10ms of ENABLE
lockout delay during a start-up sequence, but it does represent
the time from the end of the ENABLE lockout delay to the start
of GATE transition. There is no ENABLE lockout delay for a
sequence-off, so this table illustrates the delay to GATE
transition from a disable signal.
NOTE: Nom. T
= Capacitor (µF)*1.3M.
DEL_SEQ
Figure 4 shows the turn-on and Figure 5 shows the nominal
turn-off timing diagram of the ISL6123 and ISL6124.
The ISL6125 is similar to the ISL6124 except that, instead of
charge pumped GATE outputs, there are sequenced open-drain
outputs that can be pulled up to a maximum of V
.
DD
Delay and flexible sequencing possibilities include multiple series,
parallel, or adjustable capacitors that can be used to easily
fine-tune timing over that offered by standard value capacitors.
V
UVLOVth
<t
FIL
UVLO_A
UVLO_B
UVLO_C
V
UVLOVth
V
UVLOVth
V
UVLOVth
t
UVLO_D
UVLOdel
ENABLE (ISL6124)
V
EN
ENABLE (ISL6123)
DLY_Vth
DLYON_B
DLYON_D
DLY_Vth
DLY_Vth
DLYON_A
DLYON_C
DLY_Vth
V
V
V
V
QPUMP
QPUMP
QPUMP
QPUMP
GATE_B
GATE_D
GATE_C
GATE_A
V
-1V
QPUMP
t
RSTdel
RESET
FIGURE 4. ISL6123, ISL6124 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM
FN9005 Rev 1.00
September 26, 2012
Page 9 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
l
UVLO_X>VUVLOVth
ENABLE (ISL6123)
V
EN
ENABLE (ISL6124)
DLYOFF_A
DLY_Vth
DLY_Vth
DLY_Vth
DLYOFF_B
DLYOFF_C
DLY_Vth
DLYOFF_D
GATE_C
GATE_D
GATE_A
GATE_B
RESET
FIGURE 5. ISL6123, ISL6124 TURN-OFF TIMING DIAGRAM
Typical Performance Curves
1.04
1.03
634
633
632
631
630
629
628
627
626
V
= 5V
DD
1.02
1.01
1.00
V
= 1.5V
DD
V
= 1.5V
DD
0.99
0.98
0.97
DLY_OFF/ON
V
= +5V
DD
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 6. UVLO THRESHOLD VOLTAGE
FIGURE 7. DLY CHARGE CURRENT
FN9005 Rev 1.00
Page 10 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Curves(Continued)
GATE
5VOUT
3.3VOUT
SYSRST
1µs/DIV
2V/DIV
FIGURE 8. SYSRST LOW TO OUTPUT LATCH-OFF
All scope shots are taken from the ISL6123EVAL1Z board.
Using the ISL6123EVAL1Z
Platform
The ISL6123EVAL1Z platform layout illustrates the small
implementation size for a typical 4-rail sequencing application.
The platform allows evaluation of the ISL6123, ISL6124,
ISL6126, ISL6127, ISL6128 and ISL6130. See Figure 17 for
schematic and photograph of evaluation platform and Table 2
for the component listing.
Figures 9 and 10 illustrate the desired turn-on and turn-off
sequences, respectively. The sequencing order and delay
between voltages sequencing is set by external capacitance
values; sequences other than those illustrated can be
accomplished.
Figures 11 and 12 illustrate the timing relationships between the
EN input; the RESET, DLY and GATE outputs; and the V
voltage
OUT
for a single channel being turned on and off, respectively. RESET
is not shown in Figure 11 as it asserts 160ms after the last GATE
goes high.
Significant current loading of the GATE or capacitive loading of
the DLY_ON and OFF pins will affect functionality and
performance.
All IC family variants share a similar function for DLY_X capacitor
charging and GATE and RESET operation. Figures 13 through 16
illustrate the principal feature and functional differences for each
of the ISL6125, ISL6126, ISL6127 and ISL6128 variants.
The default configuration of the ISL6123EVAL1Z circuit is built
around the following design assumptions:
1. Using the ISL6123IR.
Figure 13 shows the ISL6125 open-drain outputs being
sequenced on and off, along with the RESET relationship, which is
similar to all other family variants.
2. The four supplies being sequenced are 5V (IN_A), 3.3V
(IN_B), 2.5V (IN_D) and 1.5V (IN_C). The UVLO levels are
~80% of nominal voltages. Resistors are chosen such that
the total resistance of each divider is ~10k. Using standard
value resistors to approximate 80% of nominal voltage
supply = 0.63V on UVLO input.
Figure 14 illustrates the independent input feature of the
ISL6126 which, once EN is low, allows for each UVLO to be
individually satisfied and for its associated GATE to turn on. Only
when the last variable V is satisfied, as shown, does RESET
IN
3. The desired order turn-on sequence is 5V first, then 3.3V
about 12ms later, then the 2.5V supply about 19ms later,
and lastly, the 1.5V supply about 40ms later.
release, to signal all input voltages are valid.
Figure 15 shows the ISL6127 pre-programmed ABCD turn-on
and DCBA turn-off order of sequencing, with minimal
non-adjustable delay between each.
4. The desired turn-off sequence is first both 1.5V and 3.3V
supplies at the same time, then the 2.5V supply about
50ms later, and lastly, the 5V supply about 72ms after that.
Figure 16 demonstrates the independence of the ISL6128, the
redundant 2-rail sequencer. It shows that either one of the two
groups can be turned off, and the ABCD order of restart with
capacitor programmable delay, once both EN inputs are pulled
low.
LED off indicates sequence has completed and RESET has
released and pulled high.
The board is shipped with the ISL6123 installed and with each
of the other released variant types loose packed. As this
sequencer family has a common function pinout for most
variants, no major modifications to the board are necessary to
evaluate the other ICs. See Figure 18 for the ISL6125-specific
evaluation board and schematic.
FN9005 Rev 1.00
Page 11 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
your needs). The UVLO levels, sequence and delays are
Using the ISL6125EVAL1Z
Platform
The ISL6125EVAL1Z is the ISL6125-specific evaluation board
that allows evaluation of the ISL6125 and the ISL6130 with
their open-drain outputs (contact Intersil sales support with
programmed exactly like the other ISL612X ICs except that the
ISL6125 and ISL6130 have sequenced, open-drain outputs
rather than charge-pump-driven GATE outputs. See Figure 18
for the ISL6125EVAL1Z schematic and photograph and
Table 3 for the component listing.
Typical Performance Waveforms
5VOUT
5VOUT
RESET
3.3VOUT
3.3VOUT
ENABLE
2.5VOUT
1.5VOUT
2.5VOUT
1.5VOUT
ENABLE
1V/DIV
20ms/DIV
1V/DIV
40ms/DIV
FIGURE 9. ISL6124 SEQUENCED TURN-ON
FIGURE 10. ISL6124 SEQUENCED TURN-OFF
T
delENLO
GATE 2V/DIV
GATE 2V/DIV
3.3VO 1V/DIV
3.3VO 1V/DIV
RESET 2V/DIV
DLY_Vth
DLY_Vth
EN 2V/DIV
DLY_ON 1V/DIV
DLY_OFF 1V/DIV
EN 2V/DIV
10ms/DIV
4ms/DIV
FIGURE 11. ISL6123 SINGLE CHANNEL TURN-ON
FIGURE 12. ISL6123 SINGLE CHANNEL TURN-OFF
FN9005 Rev 1.00
September 26, 2012
Page 12 of 23
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Typical Performance Waveforms(Continued)
VIN_VAR
EN
RESET
STATIC EN/ALL OTHER VOUT
VOUT_VAR
LOGIC A -D
SEQUENCED
OUTPUTS
TRSTdel
RESET
100ms/DIV
100ms/DIV
FIGURE 13. ISL6125 LOGIC OUTPUTS SEQUENCED ON AND OFF
AND RESET RELATIONSHIP
FIGURE 14. ISL6126 UVLO INPUT/OUTPUT INDEPENDENCE AND
RESET RELATIONSHIP
A_VOUT
EN_1 5V/DIV
EN_2 5V/DIV
B_VOUT
C_VOUT
A_VOUT
B_VOUT
D_VOUT
C_VOUT
D_VOUT
FIGURE 15. ISL6127 PRE-PROGRAMMED ABCD TURN-ON AND
DCBA TURN-OFF
FIGURE 16. ISL6128 GROUP INDEPENDENT TURN-OFF AND DELAY
ADJUSTABLE PRE-PROGRAMMED TURN-ON
FN9005 Rev 1.00
Page 13 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V
3.3V
1.5V
+5V
C1
23
V
1µF
C2
1
DD
8
EN1
EN2
EN_1
EN_2
DLY_ON_B
DLY_ON_C
DLY_ON_D
C4
11
0.01µF
C3
16
15
21
0.1µF
C5
0.068µF
DLY_ON_A
R4
7.68k 6.98k 4.99k 8.45k
R6
R2
R1
0.01µF
C6
S1
C7
4
12
14
17
20
UVLO_B DLY_OFF_D
UVLO_D DLY_OFF_C
UVLO_C DLY_OFF_B
0.047µF
C8
3
0.01µF
C9
13
18
0.01µF
UVLO_A DLY_OFF_A
0.1µF
7 8
ISL6123IR
GATE_A
2
2
R12
2.26k
R3
3.01k
R5
4.99k
R11
1.47k
Q1
5
6
GATE_B
GATE_C
1
5 6
4
7
22
Q1
SYSRST
SYSRST
GATE_D
7 8
3
D2 DNP
R10
2
Q2
9
24
RESET2
RESET1
NC
EP
19
25
DNP
1
R9
750
5 6
GND
4
D1
RST2
Q2
10
3
RST
R14
10 R10 10 R13
10
R9
10
Z
FIGURE 17. ISL6123EVAL1Z SCHEMATIC AND PHOTOGRAPH
FN9005 Rev 1.00
Page 14 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
2.5V_(IND) 1.5V_(INC)
3.3V_(INB)
5.0V_(INA)
C1
23
1µF
0.01µF
V
C2
C3
C4
C5
1
DD
8
ENABLE
DLY_ON_B
ENABLE
0.022µF
0.068µF
15
16
21
DLY_ON_D
DLY_ON_C
DLY_ON_A
OPEN
U1
0.047µF
C6
12
14
17
20
3
UVLO_B
UVLO_D
UVLO_C
UVLO_A
DLY_OFF_C
DLY_OFF_D
DLY_OFF_B
DLY_OFF_A
OPEN
0.01µF
0.1µF
C7
C8
C9
4
13
18
A
2
5
6
7
R8
10k
OUT_A
OUT_B
OUT_C
OUT_D
ISL6125
SEQ_A
SEQ_B
SEQ_C
SEQ_D
R9
R10
R13
10k
10k
10k
22
SYSRST
SYSRST
9
11
25
NC
NC
R7
750
24
RESET
D1
NC
19
GND
10
EP
RESET
AGND
A
FIGURE 18. ISL6125EVAL1Z SCHEMATIC AND PHOTOGRAPH
FN9005 Rev 1.00
Page 15 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 2. ISL6123EVAL1Z BOARD COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
COMPONENT DESCRIPTION
Intersil, ISL6123, Four Supply Sequencer
FDS6990S or equivalent, Dual N-Channel MOSFET
8.45k 1%, 0402
U1
Q1, Q2
R6
ISL6123
Voltage Rail Switches
5V to UVLO_A Resistor for Divider String
UVLO_A to GND Resistor for Divider String
3.3V to UVLO_B Resistor for Divider String
UVLO_B to GND Resistor for Divider String
2.5V to UVLO_D Resistor for Divider String
UVLO_D to GND Resistor for Divider String
1.5V to UVLO_C Resistor for Divider String
UVLO_D to GND Resistor for Divider String
RESET LED Current Limiting Resistor
5V turn-on Delay Capacitor A (~10ms)
5V turn-off Delay Capacitor A (~140ms)
3.3V turn-on Delay Capacitor B (~13ms)
3.3V turn-off Delay Capacitor B (~13ms)
2.5V turn-on Delay Capacitor D (~25ms)
2.5V turn-off Delay Capacitor D (0ms)
1.5V turn-on Delay Capacitor C (~100ms)
1.5V turn-off Delay Capacitor C (~60ms)
Decoupling Capacitor
R11
R1
1.47k 1%, 0402
7.68k 1%, 0402
R12
R2
2.26k 1%, 0402
6.98k 1%, 0402
R3
3.01k 1%, 0402
R4
4.99k 1%, 0402
R5
4.99k 1%, 0402
R9
750 10%, 0402
C5
DNP, 0402
C9
0.1µF 10%, 6.3V, 0402
0.01µF 10%, 6.3V, 0402
0.01µF 10%, 6.3V, 0402
0.022µF 10%, 6.3V, 0402
DNP, 0402
C2
C8
C3
C7
C4
0.068µF 10%, 6.3V, 0402
0.047µF 10%, 6.3V, 0402
1µF, 0402
C6
C1
D1
RESET Indicating LED
0805, SMD LEDs Red
DNP
D2
RESET Indicating LED
R9
5V Load Resistor
10W 20%, 3W
R10
R13
R14
3.3V Load Resistor
10 20%, 3W
2.5V Load Resistor
10 20%, 3W
1.5V Load Resistor
10 20%, 3W
Test Points Labeled as to Function
FN9005 Rev 1.00
Page 16 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
TABLE 3. ISL6125EVAL1Z COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
COMPONENT DESCRIPTION
Intersil, ISL6125, Four Supply Sequencer with Open Drain Outputs
8.45k 1%, 0402
U1
ISL6125, Four Supply Sequencer
R6
5V to UVLO_A Resistor for Divider String
UVLO_A to GND Resistor for Divider String
3.3V to UVLO_B Resistor for Divider String
UVLO_B to GND Resistor for Divider String
2.5V to UVLO_D Resistor for Divider String
UVLO_D to GND Resistor for Divider String
1.5V to UVLO_C Resistor for Divider String
UVLO_D to GND Resistor for Divider String
RESET LED Current Limiting Resistor
5V turn-on Delay Capacitor A
R12
R1
1.47k 1%, 0402
7.68k 1%, 0402
R11
R2
2.26k 1%, 0402
6.98k 1%, 0402
R3
3.01k 1%, 0402
R4
4.99k 1%, 0402
R5
4.99k 1%, 0402
R9
750 10%, 0805
C5
DNP, 0402
C9
5V turn-off Delay Capacitor A (135ms)
3.3V turn-on Delay Capacitor B (13.7ms)
3.3V turn-off Delay Capacitor B (13.7ms)
2.5V turn-on Delay Capacitor D (28ms)
2.5V turn-off Delay Capacitor D
0.1µF 10%, 6.3V, 0402
0.01µF 10%, 6.3V, 0402
0.01µF 10%, 6.3V, 0402
0.022µF 10%, 6.3V, 0402
DNP, 0402
C2
C8
C3
C7
C4
1.5V turn-on Delay Capacitor C (98ms)
1.5V turn-off Delay Capacitor C (59ms)
Decoupling Capacitor
0.068µF 10%, 6.3V, 0402
0.047µF 10%, 6.3V, 0402
0.1µF, 0805
C6
C1
D1
RESET1 Indicating LED
0805, SMD LED
R8
SEQ_OUTPUT_A Pull-Up Resistor
10k, 0402
R9
SEQ_OUTPUT_B Pull-Up Resistor
10k, 0402
R10
R13
SEQ_OUTPUT_C Pull-Up Resistor
10k, 0402
SEQ_OUTPUT_D Pull-Up Resistor
10k, 0402
Three configurations are described and illustrated here.
Application Implementations
Multiple Sequencer Implementations
The ISL6123, ISL6124, ISL6125 and ISL6127 devices can be
configured to control sequencing of more than four voltages. A
particular configuration may be preferable to another, depending
on concerns. The fundamental questions to determine which
configuration is best suited for your applications are:
In applications for which the integrity of critical voltages must be
assured prior to sequencing, additional monitoring of the critical
supplies is needed. If voltage compliance is critical for either
undervoltage or overvoltage, voltage supervisors can be used to
provide this additional assurance across multiple sequencers.
Figure 19 is a block diagram of a voltage-compliant,
high-assurance, low-risk configuration showing the ISL6131 or
ISL6132 supervisor and a mix of FET switched outputs and logic
output sequencers (ISL6124 and ISL6125 ICs).
1. What level of voltage assurance is needed prior to sequencing
on, and can the voltage supplies be grouped into high and low
criticality?
2. Is there a critical maximum time window in which all supplies
must be present at load, or is there a first and a second group
preference, possibly with some work done in between the two
groups of voltages being present?
FN9005 Rev 1.00
Page 17 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL6131 or ISL6132
OE
OE
MONITORING
ON ALL RAILS
LOW = RESET
LOW = RESET
VMON
PGOOD
UVLO
SYSRST
ISL6124
# N
G
A
T
SYSRST
ISL6124
UVLO
en
# N
RESET
G
E
UVLO
A
T
E
en
ENABLE
RESET
ENABLE
ENABLE
SYSRST
RESET
ENABLE
SYSRST
ISL6125
# N+1
L
O
G
I
RESET
POWER
SUPPLY
RESET
UVLO
ISL6125
# N+1
L
O
G
I
C
POWER
SUPPLY
RESET
UVLO
C
FIGURE 20. MULTIPLE ISL612X USING LOGIC GATES FOR
VOLTAGE PRESENCE DETECT
FIGURE 19. ISL612X AND ISL613X VOLTAGE COMPLIANT
SEQUENCING BLOCK DIAGRAM
allows the sequenced turn-off of this configuration to ripple
through several banks as quickly as the user-programmed (by
DLY_OFF) sequence capacitors allow.
If the mere presence of some voltage potential is adequate prior
to sequencing on, then a small number of standard logic and
gates can be used to accomplish this. The block diagram in
Figure 20 illustrates this voltage presence configuration.
Again, with common bused SYSRTS pins, simultaneous
shutdown of all GATEs and LOGIC down upon an unsatisfied UVLO
input is assured, once all FETs or LOGIC outputs are on. If a GATE
drive option IC is used to drive both FETs and logic signals, then
care must be taken to ensure the charged pump GATE does not
overdrive and damage the logic input. A simple resistor divider
can be used to lower the GATE to a suitable voltage for the logic
input, as shown in Figure 21.
In either case, the sequencing is straightforward across multiple
sequencers, as all DLY_ON capacitors simultaneously start
charging ~10ms after the common ENABLE input signal is
delivered. This allows the choice of capacitors to be related to
each other and is no different than using a single sequencer.
When the common enabling signal is de-asserted, these
configurations execute the turn-off sequence across all
sequencers as programmed by the DLY_OFF capacitor values.
In both cases, with all the SYSRST pins bused together, once the
turn-on sequence is complete, simultaneous shutdown upon any
UVLO input failure is assured. SYSRST output momentarily pulls
low and turns off all GATE and LOGIC outputs.
Some applications may require or allow groups of supplies to be
brought up in sequence and for supplies within each group to be
sequenced. Figure 21 shows a configuration that allows the first
group of supplies to turn on before the go second group starts.
This arrangement does not necessarily preclude adding the
assurance of all supplies prior to turn-on sequencing, as
previously shown. It does prevent the turn-on sequence from
completing, if there is one unsatisfied UVLO input in a group.
This configuration involves waiting through the T
and
(total of ~160ms) for each sequencer IC in the chain
UVLOdel
T
RSTdel
before the final RESET releases. Once ENABLE on the first
sequencer is de-asserted, all RESET outputs quickly pull low. This
FN9005 Rev 1.00
Page 18 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
OE
LOW = RESET
SYSRST
ISL6124
# N
G
UVLO
A
T
ENABLE
E
ENABLE
RESET
TO LOGIC
INPUT
ENABLE
SYSRST
FIGURE 22. OUTPUT VOLTAGE ON LOW TO HIGH TRACKING
ISL6125
# N+1
L
O
G
I
POWER
SUPPLY
RESET
UVLO
C
RESET
RESET
FIGURE 21. MULTIPLE ISL612X SERIAL CONFIGURATION
Voltage Tracking
In some applications, voltages may have to track each other as
they ramp up and down, whereas others may just need
sequencing. In these cases, tracking can be accomplished and
has been demonstrated over a wide range of load currents (1A to
10A) and load capacitances (10µF to 3300µF) with the ISL612X
family. Figure 22 and Figure 23 illustrate output voltage ramping
tracking performance. Note that differences are less than 0.5V.
With the relevant GATE pins tied together in a star pattern, so
that resistance between any two GATE pins is equivalent
(1k to 10k), GATE ramping voltage is shared. With the same or
similar enough FETs, this behavior is also observed.
FIGURE 23. OUTPUT VOLTAGE ON HIGH TO LOW TRACKING
It is suggested that this circuit implementation be prototyped
and evaluated for the particular expected loads prior to
committing to manufacturing build.
FN9005 Rev 1.00
Page 19 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
+V
The ISL612X family can use the charged pump GATE output to
drive FETs that would control and sequence negative voltages
down to a nominal -5V with minimal additional external circuitry.
Figure 24 shows simultaneous turn-on of the 5V bipolar supplies,
and then simultaneous turn-off of the +2.5V and both positive
supplies after the -5V. Figure 25 shows the minimal additional
external circuitry to accomplish this. The 5V zener diode is used
to level-shift the GATE drive down by 5V to prevent premature
turn-on when GATE = 0V. Once GATE drive voltage > Vz, then FET
+BIAS
R5
R1
R3
(10k)
(1k)
ISL6131
OR
ISL6536A
VMON
Q1 Si1300DL
OR EQUIV.
R4
PGOOD
R2
(15K)
TO UVLO OF
ISL612X FOR
-V CONTROL AND
SEQUENCING
-BIAS
R6
-V
R1 and R2 define -V UVLO level.
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up.
R4 and R5 provide Q1 gate bias between 0V and +V
Vgs > 5V, ensuring full turn-on once GATE gets to V + 5.3V.
DD
Turn-on and turn-off ramp rates can be adjusted with the FET
gate series resistor value. The -V rail is sequenced normally via
the DLY_X capacitor value, although adjustments in prototyping
should be factored in to fine-tune for actual circuit requirements.
to 0V (resistor values suitable for -V = -5V and +V = +3.3V).
FIGURE 26. HIGH ACCURACY -V LOCK OUT
Figures 26 and 27 illustrate a high-accuracy -V detection circuit
using the ISL6131 and a low-cost, low-accuracy -V detection
circuit, respectively.
+V
R1
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
R2
Choose R1 and R2 values to drive UVLO
high when -V is sufficiently present.
-V
FIGURE 27. LOW ACCURACY -V PRESENCE DETECTION
Application Considerations
Timing Error Sources
In any system there are variance contributors. For the ISL612x
family, timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source; thus,
lower-percentage tolerance capacitors help to reduce this error
source. Figure 28 illustrates a difference of 0.57ms between two
DLY_X outputs ramping to DLY_X threshold voltage. These 5%
capacitors were from a common source. In applications where
two or more GATEs or LOGIC outputs must have concurrent
transitions, it is recommended that a common GATE drive be
used to eliminate this timing error.
FIGURE 24. ±VOLTAGE SEQUENCING
-V
-V
OUT
IN
R1
D1
ISL612X GATE
ADDITIONAL 2 COMPONENTS
NECESSARY FOR -V CONTROL
AND SEQUENCING.
D1 necessary to prevent premature turn-on. R1 is used to hold
FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to
adjust -V ramp rates. Choose an R1 value between 4MW and 10MW
initially, and fine-tune resistor value for the particular need.
FIGURE 25. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 28. CAPACITOR TIMING MISMATCH
FN9005 Rev 1.00
Page 20 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
DLY_X Threshold Voltage and Charging
Current Mismatch
The two other error sources come from the IC itself and are found
across the four DLY_X outputs. These errors are the DLY_X
threshold voltage (DLY_Vth) variance when the GATE_X charging
and discharging current latches are set, and the DLY_X charging
current (DLY_ichg) variances to determine the time to next
sequencing event. Both of these parameters are bounded by
specification. Figure 29 shows that, with a common capacitor,
the typical error contributed by these factors is insignificant,
since both DLY_X traces overlay each other.
FIGURE 29. DLY_VTH AND DLY_ICHG TIMING MISMATCH
© Copyright Intersil Americas LLC 2003-2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9005 Rev 1.00
Page 21 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
CHANGE
6/13/2012
FN9005.12
Added ISL6125 specific information throughout the document for clarification / differentiation.
- Page 1, Figure 1: “Improved Typical Application Diagram”
- Page 2, Figure 2“Improved ISL6125 Application Diagram”
- Page 3, Pin Configuration diagram ISL6123, ISL6124, ISL6125 table, added "OUTPUT_A, OUTPUT_B,
OUTPUT_C and OUTPUT_D,” to diagram.
-Page 4, Pin Descriptions table added OUTPUT_A, OUTPUT_B, OUTPUT_C and OUTPUT_D
5/24/2011
FN9005.11
- On Page 1, Features: added “ENABLE” to Active High information for ISL6123 and ISL6130.
- On Page 2, Ordering Information table: updated evaluation board; changed ISL612XSEQEVAL1Z to
ISL6123EVAL1Z. Removed obsolete parts: ISL6123IR, ISL6124IR, ISL6125IR, ISL6126IR, ISL6127IR,
ISL6128IR.
- On Page 4, Pin Descriptions: changed Description for ENABLE/ENABLE pins from “ISL6123, ISL6124,
ISL6125, ISL6126, ISL6127 and ISL6130 have ENABLE.” to “ISL6123 and ISL6130 have ENABLE, and ISL6124,
ISL6125, ISL6126 and ISL6127 have ENABLE.”
- On Page 6, Thermal Information: changed theta-ja from 48 to 46; changed theta-jc from 9 to 8.
- On Page 6, Electrical Specifications: added "ISL6125 Open Drain" specs for "Open Drain On Resistance”.
- On Page 11: changed heading “Using the ISL612XSEQEVAL1Z Platform” to “Using the ISL6123EVAL1Z
Platform” and edited this section to reflect attributes of revised evaluation board.
- On Page 14: replaced Figure 16, "EVAL BOARD CHANNEL 1 SCHEMATIC AND ISL612XSEQEVAL1Z
PHOTOGRAPH” with "ISL6123EVAL1Z SCHEMATIC AND PHOTOGRAPH”
- On Page 16: replaced Table 2, "ISL612XSEQEVAL1Z BOARD CHANNEL 1 COMPONENT LISTING” with
"ISL6123EVAL1Z BOARD COMPONENT LISTING”
10/15/2008
2/27/2008
FN9005.10
FN9005.9
Corrected pinout information in table and diagram.
- Updated evaluation boards discussion to indicate Pb-free versions throughout document.
- Clarified pinouts and pin description tables.
- Added Pb-free reflow link to Thermal Information.
2/5/2007
10/12/2006
3/9/2006
FN9005.8
FN9005.7
FN9005.6
FN9005.5
Added ISL6130 to datasheet.
Made corrections and clarifications to discussions of evaluation board.
Clarified block diagram and applications text.
12/2/2005
- Clarified text of SYSRST functional description.
- Added bias and several SYSRST# and RST# typical parameters numbers.
- Cleared up tracking scope shot mismatch.
6/10/2005
8/18/2004
1/14/2004
10/3/2003
7/15/2003
FN9005.4
FN9005.3
FN9005.2
FN9005.1
FN9005.0
Improved ESD to 2.5kV.
Added Pb-free options.
Minor edits
Minor edits
New document
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL6123, ISL6124, ISL6125,
ISL6126, ISL6127, ISL6128, ISL6130.
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff.
FITs are available from our website at: http://rel.intersil.com/reports/search.php
FN9005 Rev 1.00
Page 22 of 23
September 26, 2012
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Package Outline Drawing
L24.4x4
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 10 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 10 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN9005 Rev 1.00
Page 23 of 23
September 26, 2012
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明