ISL6141IBZA_技术文档

ISL6141, ISL6151

®

Data Sheet

July 2004

FN9079.1

Negative Voltage Hot Plug Controller

Features

The ISL6141 is an 8-pin, negative voltage hot plug controller

that allows a board to be safely inserted and removed from a

live backplane. Inrush current is limited to a programmable

value by controlling the gate voltage of an external N-

channel pass transistor. The pass transistor is turned off if

the input voltage is less than the Under-Voltage threshold, or

greater than the Over-Voltage threshold. The IntelliTrip^TM

electronic circuit breaker and programmable current limit

features protect the system against short circuits. When the

Over-Current threshold is exceeded, the output current is

limited for 600µs before the circuit breaker shuts down the

FET. If the fault disappears before the 600µs time-out,

normal operation resumes. In addition, the IntelliTrip^TM

electronic circuit breaker has a fast Hard Fault shutdown with

a threshold set at 4 times the current limit value. When

activated, the GATE is immediately turned off and then

slowly turned back on for a single retry (soft-start). The

active low PWRGD signal can be used to directly enable a

power module (with a low enable input). The ISL6151 is the

same device but has an active high PWRGD output.

• Operates from -20V to -80V (-100V Absolute Max Rating)

• Programmable Inrush Current

• Programmable Over-Voltage Protection

• Programmable Under-Voltage Protection

- 135mV of hysteresis

- Equals ~4.6V of hysteresis at the power supply

• UVLO (Under-Voltage Lock-Out) ~ 16.5V

• Programmable Current Limit with 600µs time-out

• IntelliTrip^TMelectronic circuit breaker distinguishes

between Over-Current and Hard Fault conditions

- Fast shutdown for Hard Faults with a single retry (fault

current > 4X current limit value).

• Pin Compatible with ISL6140/50.

• Power Good Control Output

- Monitors both the DRAIN (voltage drop across the FET)

and the GATE voltage; once both are OK, the Power

Good output is latched in the active state.

- PWRGD active high: ISL6151 (H version)

- PWRGD active low: ISL6141 (L version)

Typical Application (RL, CL are the Load)

GND

• Pb-free available

R4

Applications

V

DD

UV

OV

• VoIP (Voice over Internet Protocol) Servers

• Telecom systems at -48V

PWRGD

R5

R6

ISL6141

SENSE GATE

C1

V

DRAIN

C2

EE

• Negative Power Supply Control

• +24V Wireless Base Station Power

(LOAD)

CL

R3

R2

RL

Related Literature

-48V IN

• ISL6140/41 EVAL1 Board Set, Document # AN9967

• ISL6142/52 EVAL1 Board Set, Document # AN1000

• ISL6140/50 Hot Plug Controller, Document # FN9039

• ISL6116 Hot Plug Controller, Document # FN4778

NOTE: See www.intersil.com/hotplug for more information.

R1

Q1

-48V OUT

R1 = 0.02Ω (1%)

R2 = 10Ω (5%)

C1 = 150nF (25V)

C2 = 3.3nF (100V)

R3 = 18kΩ (5%)

R4 = 549kΩ (1%)

R5 = 6.49kΩ (1%)

R6 = 10kΩ (1%)

Q1 = IRF530 (100V, 17A, 0.11Ω)

CL = 100µF (100V)

Pinout

RL = equivalent load

ISL6141 OR ISL6151 (8 LEAD SOIC)

8

7

6

5

1

2

3

4

V

PWRGD/PWRGD

DD

TOP VIEW

OV

DRAIN

GATE

UV

V

SENSE

EE

ISL6141 has active low (L version) PWRGD output pin

ISL6151 has active high (H version) PWRGD output pin

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

Intellitrip™ is a trademark of Intersil Americas Inc.

ISL6141, ISL6151

Ordering Information (Continued)

Ordering Information

PKG.

DWG. #

PKG.

DWG. #

o

PART NO.

TEMP. RANGE ( C) PACKAGE

-40 to 85

PART NO.

ISL6141CB

TEMP. RANGE ( C) PACKAGE

ISL6151IBZA

(See Note)

8 Lead SOIC M8.15

(Pb-free)

0 to 70

8 Lead SOIC M8.15

ISL6141CBZA

(See Note)

*Add “-T” suffix to part number for tape and reel packaging.

(Pb-free)

ISL6151CB

0 to 70

8 Lead SOIC M8.15

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

ISL6151CBZA

(See Note)

8 Lead SOIC M8.15

(Pb-free)

ISL6141IB

-40 to 85

8 Lead SOIC M8.15

ISL6141IBZA

(See Note)

8 Lead SOIC M8.15

(Pb-free)

ISL6151IB

-40 to 85

8 Lead SOIC M8.15

GND

V

DD

-

UVLO

1.265V

R4

R5

+

REGULATOR,

REFERENCES

-

V

EE

UV

OV

-

13V

UV

OV

1.255V

+

-

V

EE

+

-

1.255V

LOGIC

+

-

TIMING

V

EE

GATE DRIVE

-

R6

HARD

FAULT

210mV

+

-

V

EE

GATE

-

11.1V

+

-

CURRENT

LIMIT

-

PWRGD

50mV

OUTPUT

+

REGULATOR

(ISL6141)

V

EE

DRIVE

-

+

PWRGD

(ISL6151)

-

LATCH

LOGIC

1.3V

+

V

+

EE

-

V

EE

600µs

TIMER

PWRGD

GATE

R3

DRAIN

SENSE

V

EE

LOAD

CL

C2

R2

RL

C1

-48V OUT

-48V IN

R1

Q1

FIGURE 1. BLOCK DIAGRAM

2

ISL6141, ISL6151

external FET. The built in 25mV hysteresis will keep the

GATE off until the OV pin drops below 1.230V, which is the

nominal high to low threshold. A typical application will use

Pin Descriptions

PWRGD (ISL6141; L Version) Pin 1

This digital output is an open-drain pull-down device. During

start-up the DRAIN and GATE voltages are monitored with

two separate comparators. The first comparator looks at the

an external resistor divider from V

level as desired. A three-resistor divider can be used to set

both OV and UV trip points.

to V to set the OV

DD

EE

DRAIN pin voltage compared to the internal V

(V

PG

the external FET and sense resistor. When the DRAIN to V

voltage drop is less than 1.3V, the first of two conditions

required for the power to be considered good are met. In

addition, the GATE voltage monitored by the second

comparator must be within approximately 2.5V of its normal

operating voltage (13.6V). When both criteria are met the

PWRGD output will transition from high to low, enabling a

power module in some applications. The output is latched in

the low state until any of the signals that shut off the GATE

occur (Over-Voltage, Under-Voltage, Under-Voltage Lock-Out,

Over-Current Time-Out, or powering down). Any of these

conditions will re-set the latch and the PWRGD output will

transition from low to high indicating power is no longer good.

In this case the output pull-down device shuts off, and the pin

becomes high impedance. Typically an external pull-up of

some kind is used to pull the pin high (many brick regulators

have a pull-up function built in).

reference

is nominal 1.3V); this measures the voltage drop across

PG

UV (Under-Voltage) Pin 3 - This analog input compares the

voltage on the pin to an internal comparator with a built in

hysteresis of 135mV. When the UV input goes below the

nominal reference (high to low transition) voltage of 1.120V,

the GATE pin is immediately pulled low to shut off the

external FET. Since the comparator has a built in 135mV

hysteresis the GATE will remain off until the UV pin rises

above a 1.255V low to high threshold. A typical application

EE

will use an external resistor divider from V

to V to set

DD

EE

the UV level as desired. A three-resistor divider can be used

to set both OV and UV trip points.

The UV pin is also used to reset the Over-Current latch. The

pin must be cycled below 1.120V (nominal) and then above

1.255V (nominal) to clear the latch and initiate a normal

power-up sequence.

V

Pin 4 - This is the most negative supply voltage, such

EE

as in a -48V system. Most of the other signals are referenced

relative to this pin, even though it may be far away from what

is considered a GND reference.

PWRGD (ISL6151; H Version) Pin 1 - This digital

output is used to provide an active high signal to enable an

external module. The Power Good comparators are the

same as described above, but the active state of the output

is reversed (reference Figure 33).

SENSE Pin 5 - This analog input monitors the voltage drop

across the external sense resistor (between SENSE and

V

) to determine if the current exceeds the programmed

EE

Over-Current trip point, equal to 50mV / Rsense. If the load

current exceeds the Over-Current threshold, the circuit will

regulate the current to maintain the nominal voltage drop

(50mV) across the sensing resistor R1 (Rsense). If current is

limited for more than 600µs, the Over-Current shutdown

(also called electronic circuit breaker) will quickly turn off the

FET and latch the GATE pin off.

If the latch is reset (GATE turns off), the internal DMOS

device (Q3) is turned off, and Q2 (NPN) turns on to clamp

the output one diode drop above the DRAIN voltage to

produce a logic low.

Once the latch is set (both DRAIN and GATE are normal), the

DMOS device (Q3) turns on and sinks current to V through

EE

a 6.2KΩ resistor. The base of Q2 is clamped to V to turn it

A Hard Fault comparator is employed to detect and respond

quickly to severe short circuits. The threshold of this

EE

off. If the external pull-up current is high enough (>1mA, for

example), the voltage drop across the resistor will be large

enough to produce a logic high output (in this example, 1mA *

6.2kΩ = 6.2V) and enable the external module.

comparator is set approximately four times higher (210mV)

than the Over-Current trip point. When its threshold is

exceeded the GATE is immediately (10µs typical) shut off,

the timer is reset, and a single retry (soft start) is attempted

before latching the GATE off (assuming the fault remains).

During the retry, if the fault disappears prior to the Over-

Current Time-Out period (600µs) the FET will remain on as

normal. If the GATE is latched off, the user must either toggle

the UV pin below then above its threshold, or reduce the

Note that for all H versions, although this is a digital pin

functionally, the logic high level is determined by the external

pull-up device, and the power supply to which it is

connected; the IC will not clamp it below the V

voltage.

DD

Therefore, if the external device does not have its own

clamp, or if it would be damaged by a high voltage, an

external clamp might be necessary.

supply voltage below the V

above it. This will clear the latch and initiate a normal power-

up sequence.

UVLO trip point and then

DD

OV (Over-Voltage) Pin 2 - This analog input compares the

voltage on the pin to an internal voltage reference of 1.255V

(nominal). When the input goes above the reference (low to

high transition) an Over-Voltage condition is detected and

the GATE pin is immediately pulled low to shut off the

3

ISL6141, ISL6151

GATE Pin 6 - This analog output drives the gate of the

external FET used as a pass transistor. The GATE pin is high

(FET is on) when the following conditions are met:

• UVLO is above its trip point (~16.5V)

• Voltage on the UV pin is above its trip point (1.255V)

• Voltage on the OV pin is below its trip point (1.255V)

• No Over-Current conditions are present.

If any of the 4 conditions are violated, the GATE pin will be

pulled low to shut off or regulate current through the FET.

The GATE is latched off only when the 600µs Over-Current

Time-Out period is exceeded.

The GATE is driven high by a weak (-50µA nominal) pull-up

current source, in order to slowly turn on the FET. It is driven

low by a 70mA nominal pull-down device for three of the

above shut-off conditions. A larger (350mA nominal) pull-

down current shuts off the FET very quickly in the event of a

hard fault where the sense pin voltage exceeds

approximately 210mV.

DRAIN Pin 7 - This is the analog input to one of two

comparators that control the PWRGD (ISL6141) or PWRGD

(ISL6151) outputs. It compares the voltage of the external

FET DRAIN to a 1.3V internal reference (V ). The DRAIN

PG

voltage is criticized only until the PWRGD or PWRGD

outputs are latched into their active low or high states. The

latch is reset when any of the conditions that turn off the

GATE occur (UVLO, OV, UV, OC Time-Out). Note that the

comparator does NOT itself turn off the GATE.

V

Pin 8 - This is the most positive power supply pin. It can

DD

range from the Under-Voltage Lock-Out threshold (16.5V) to

+80V (Relative to V ).

EE

4

ISL6141, ISL6151

.

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage (V

to V ). . . . . . . . . . . . . . . . . . . . -0.3V to 100V

EE

Thermal Resistance (Typical, Note 1)

θ

( C/W)

DD

JA

DRAIN, PWRGD, PWRGD Voltage . . . . . . . . . . . . . . .-0.3V to 100V

UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V

SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V

ESD Rating

8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

90

o

Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V

Operating Conditions

o

Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40 C to 85 C

Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0 C to 70 C

Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. PWRGD is referenced to DRAIN; V = 0V.

-V

PWRGD DRAIN

Electrical Specifications

V

= +48V, V = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

EE

DD

Commercial (0 C to 70 C) or Industrial (-40 C to 85 C). Typical specs are at 25 C.

o

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

Units

DC PARAMETERS

V

DD

Supply Operating Range

Supply Current

V

20

-

80

V

DD

I

UV = 3V; OV = V ; SENSE = V ; V

=

2.4

4.5

mA

DD

EE

EE DD

80V

UVLO High

V

Low to High transition

High to Low transition

15

13

16.7

14.8

1.9

19

17

V

UVLOH

DD

UVLO Low

V

UVLOL

UVLO hysteresis

GATE PIN

GATE Pin Pull-Up Current

GATE Pin Pull-Down Current

I

GATE Drive on, V

V

GATE = EE

-30

-50

70

-60

15

µA

mA

V

PU

I

GATE Drive off, UV or OV false

PD1

PD2

PD3

I

GATE Drive off, Over-Current Time-Out

70

GATE Drive off; Hard Fault (Vsense > 210mV)

350

13.6

2.5

External GATE Drive (V

= 20V, 80V)

∆ V

(V

V

, 20V <=V

DD

<=80V

12

40

DD

GATE

GATE - EE)

GATE High Threshold (PWRGD/PWRGD

active)

V

∆V - V

V

GH

GATE

SENSE PIN

Current Limit Trip Voltage

Hard Fault Trip Voltage

SENSE Pin Current

UV PIN

V

= (V

- V

)

50

60

mV

µA

CL

SENSE

EE

V

= (V

- V

)

210

-1.3

HFT

HFTV

SENSE

= 50mV

EE

I

-4.0

SENSE

UV Pin High Threshold Voltage

UV Pin Low Threshold Voltage

UV Pin Hysteresis

V

UV Low to High Transition

UV High to Low Transition

1.240

1.105

1.255

1.120

135

1.270

1.145

V

UVH

V

UVL

V

mV

UVHY

5

ISL6141, ISL6151

Electrical Specifications

V

= +48V, V = +0V Unless Otherwise Specified. All tests are over the full temperature range; either

EE

DD

o

Commercial (0 C to 70 C) or Industrial (-40 C to 85 C). Typical specs are at 25 C. (Continued)

PARAMETER

UV Pin Input Current

OV pin

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

Units

I

V

= V

EE

-0.05

-0.5

µA

INUV

UV

OV Pin High Threshold Voltage

OV Pin Low Threshold Voltage

OV Pin Hysteresis

V

OV Low to High Transition

OV High to Low Transition

1.235

1.215

1.255

1.230

25

1.275

1.255

V

OVH

V

OVL

V

mV

µA

OVHY

INOV

OV Pin Input Current

DRAIN Pin

I

V

= V

-0.05

-0.5

OV

EE

Power Good Threshold (PWRGD/PWRGD

active)

V

- V

0.80

1.30

38

2.00

60

V

PG

DRAIN

EE

DRAIN Input Bias Current

I

= 48V

µA

DRAIN

ISL6141 (PWRGD Pin: L Version)

PWRGD Output Low Voltage

V

(V

- V

< V

I

PG; OUT

= 1mA

= 5mA

-

0.30

1.50

0.05

1.0

3.0

10

V

OL1

OL5

DRAIN

EE)

I

PG; OUT

Output Leakage

I

V

= 48V, V

= 80V

PWRGD

µA

OH

ISL6151 (PWRGD Pin: H Version)

PWRGD Output Low Voltage (PWRGD-DRAIN)

PWRGD Output Impedance

AC Timing

V

= 5V, I

= 1mA

PG

-

0.85

6.2

1.0

9.0

V

OL

DRAIN

OUT

< V

R

(V

- V

EE)

3.5

kΩ

OUT

DRAIN

OV High to GATE Low

t

Figures 2A, 3A

Figures 2A, 3B

Figures 2A, 6

Figures 2B, 8

0.6

1.0

0.6

1.0

1.3

4.5

3.0

12.0

3.0

12.0

3

µs

PHLOV

PLHOV

OV Low to GATE High

UV Low to GATE Low

t

0.90

5.0

PHLUV

PLHUV

UV High to GATE High

SENSE High to GATE Low

Current Limit to GATE Low (O.C. Time-out)

t

0.35

600

10

PHLSENSE

t

PHLCB

Hard Fault to GATE Low (200mV comparator)

Typical GATE shutdown based on application

ckt. Guaranteed by design.

t

Figures 7, 23, 27 (zero Ω short to V

)

DD

PHLHF

ISL6141 (L Version)

DRAIN Low to PWRGD Low

GATE High to PWRGD Low

ISL6151 (H Version)

t

Figures 2A, 4A (note 2)

Figures 2A, 5A (note 2)

3.0

1.0

5.0

3.0

µs

PHLDL

t

PHLGH

DRAIN Low to (PWRGD-DRAIN) High

GATE High to (PWRGD-DRAIN) High

t

Figures 2A, 4B (note 2)

Figures 2A, 5B (note 2)

3.0

0.4

5.0

3.0

µs

PLHDL

t

PLHGH

6

ISL6141, ISL6151

Test Circuit and Timing Diagrams

5V

R = 5K

5V

+

48V

-

R = 5K

+

48V

-

V

PWRGD

OV

DD

8

7

6

5

1

2

3

4

V

PWRGD

OV

DD

DRAIN

8

7

6

5

1

2

3

4

V

DRAIN

GATE

DRAIN

OV

ISL6141

ISL6151

DRAIN

GATE

ISL6141

ISL6151

9.0KΩ

UV

V

OV

UV

V

EE

SENSE

V

EE

SENSE

V

0.9KΩ

UV

V

UV

0.1KΩ

V

SENSE

.

FIGURE 2A. TYPICAL TEST CIRCUIT

FIGURE 2B. TEST CIRCUIT FOR 600µs TIME-OUT

OV Pin

1.255V

2V

1.120V

1.255V

1.230V

UV Pin

GATE

0V

t

PLHUV

t

PHLUV

t

PHLOV

PLHOV

13.6V

1V

GATE

0V

FIGURE 3B. UV TO GATE TIMING

FIGURE 3A. OV TO GATE TIMING

FIGURE 3. OV AND UV TO GATE TIMING

DRAIN

1.3V

V

PG

V

PG

V

EE

V

t

EE

t

PHLDL

PWRGD

1.0V

PWRGD

FIGURE 4A. DRAIN TO PWRGD TIMING (ISL6141)

FIGURE 4B. DRAIN TO PWRGD TIMING (ISL6151)

FIGURE 4. DRAIN TO PWRGD/PWRGD TIMING

∆V

- V

= 0V

GATE

∆V

- V = 0V

GATE

V

2.5V

GH

V

2.5V

GH

GATE

t

PLHGH

GATE

t

PHLGH

PWRGD

1.0V

= 0V

PWRGD

1.0V

V

- V

DRAIN

PWRGD

FIGURE 5A. GATE TO PWRGD (ISL6141)

FIGURE 5. GATE TO PWRGD/PWRGD TIMING

FIGURE 5B. GATE TO PWRGD (ISL6151)

7

ISL6141, ISL6151

Test Circuit and Timing Diagrams (Continued)

50mV

210mV

SENSE

GATE

SENSE

0V

13.6V

GATE

t

PHLSENSE

t

PHLHF

V

~4V (depends on FET threshold)

EE

FIGURE 6. SENSE TO GATE TIMING

FIGURE 7. SENSE TO GATE (Hard Fault) TIMING

UV

t

PHLCB

GATE

1.0V

FIGURE 8. CURRENT LIMIT TO GATE TIMING

Typical Performance Curves

4.5

4

3.5

3

2.5

2

1.5

1

2.3

2.25

2.2

2.15

2.1

2.05

2

0.5

0

1.95

10 20 30 40 50 60 70 80 90 100

Supply Voltage (VDD)

-40

-20

0

20

40

60

80

100

Temperature (C)

o

FIGURE 9. SUPPLY CURRENT VS. SUPPLY VOLTAGE (25 C)

FIGURE 10. SUPPLY CURRENT VS. TEMPERATURE, V = 48V

DD

8

ISL6141, ISL6151

Typical Performance Curves (Continued)

16

14

12

10

8

2.45

2.4

2.35

2.3

2.25

2.2

6

4

2

0

2.15

2.1

10

20

30

40

50

60

70

80 100

-40

-20

0

20

40

60

80

100

Supply Voltage (VDD)

Temperature (C)

o

FIGURE 11. SUPPLY CURRENT VS TEMPERATURE, V

= 80V

FIGURE 12. GATE VOLTAGE VS SUPPLY VOLTAGE (25 C)

DD

14

13.9

13.8

13.7

13.6

13.5

13.4

14

13.9

13.8

13.7

13.6

13.5

13.4

13.3

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (C)

FIGURE 13. GATE VOLTAGE VS TEMPERATURE, V

= 48V

FIGURE 14. GATE VOLTAGE VS TEMPERATURE, V

= 80V

DD

14

13.9

13.8

13.7

13.6

13.5

13.4

50

49

48

47

46

45

44

43

42

41

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (C)

FIGURE 15. GATE VOLTAGE VS TEMPERATURE, V

= 20V

FIGURE 16. GATE PULL-UP CURRENT VS TEMPERATURE

DD

9

ISL6141, ISL6151

Typical Performance Curves (Continued)

450

400

350

300

250

200

150

100

50

90

80

70

60

50

40

30

20

10

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (C)

FIGURE 17. GATE PULL-DOWN CURRENT

(UV/OV/TIME-OUT) VS TEMPERATURE

FIGURE 18. HARD FAULT GATE PULL-DOWN CURRENT

(200mV COMPARATOR) VS TEMPERATURE

(1 ma)

54

52

50

48

46

44

42

40

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

5mA

1mA

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (C)

FIGURE 19. OVER-CURRENT TRIP VOLTAGE VS

TEMPERATURE

FIGURE 20. PWRGD (ISL6141) V

VS TEMPERATURE

OL

2

6.8

6.7

6.6

6.5

6.4

6.3

6.2

6.1

1.5

1

0.5

0

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

Temperature (C)

FIGURE 21. PWRGD (ISL6151) IMPEDANCE VS

TEMPERATURE

FIGURE 22. DRAIN to PWRGD / PWRGD TRIP VOLTAGE (V

VS TEMPERATURE

)

PG

10

ISL6141, ISL6151

Applications Information

GND

R4

V

DD

UV

OV

R5

R6

ISL6141

SENSE GATE

C1

PWRGD

DRAIN

V

EE

(LOAD)

CL

R3

C2

R2

RL

-48V IN

R1

Q1

-48V OUT

FIGURE 23. TYPICAL APPLICATION WITH MINIMUM COMPONENTS

input power supply is divided down such that when the

Typical Values for a representative system; which

assumes:

voltage on the OV pin is below its threshold and the UV pin is

above its threshold their comparators will be in the proper

state signaling the supply is within its desired range, allowing

the GATE to turn on. The equations below define the

comparator thresholds for an increasing (in magnitude)

supply voltage.

• 43V to 71V supply range; 48 nominal; UV = 43V;

OV = 71V

• 1Amp of typical current draw; 2.5 Amp Over-Current

• 100µF of load capacitance (CL); equivalent RL of 48Ω

(R = V/I = 48V/1A)

〈 R + R + R 〉

4

5

6

(EQ. 1)

----------------------------------------

V

=

× 1.255

UV

(R + R )

R1: 0.02Ω (1%)

5

6

R2: 10Ω (5%)

〈 R + R + R 〉

4

5

6

(EQ. 2)

----------------------------------------

V

=

× 1.255

OV

(R )

6

R3: 18kΩ (5%)

The values of R4 = 549K, R5 = 6.49K, and R6 = 10K shown

in figure 23 set the Under-Voltage turn-on threshold to 43V,

and the Over-Voltage turn off threshold to 71V. The Under-

Voltage (UV) comparator has a hysteresis of 135mV (4.6V of

hysteresis on the supply) which correlates to a 38.4V turn off

voltage. The Over-Voltage comparator has a 25mV

hysteresis which translates to a turn on voltage (supply

decreasing) of approximately 69.6V.

R4: 549kΩ (1%)

R5: 6.49kΩ (1%)

R6: 10kΩ (1%)

C1: 150nF (25V)

C2: 3.3nF (100V)

Q1: IRF530 (100V, 17A, 0.11Ω)

Q1 - is the FET that connects the input supply voltage to the

output load, when properly enabled. It needs to be selected

based on several criteria:

Quick Guide to Choosing Component

Values

• Maximum voltage expected on the input supply (including

transients) as well as transients on the output side.

(See fig 23 for reference)

This section will describe the minimum components needed

for a typical application, and will show how to select

component values. (Note that “typical” values may only be

good for this application; the user may have to select

alternate component values to optimize performance for

other applications). Each block will then have more detailed

explanation of how the device works, and alternatives.

• Maximum current and power dissipation expected during

normal operation, usually at a level just below the current

limit threshold.

• Power dissipation and/or safe-operating-area

considerations during current limiting and single retry

events.

• Other considerations include the GATE voltage threshold

R4, R5, R6 - together set the Under-Voltage (UV) and Over-

Voltage (OV) trip points. When the power supply ramps up

and down, these trip points (and their hysteresis) will

determine when the GATE is allowed to turn on and off (UV

and OV do not control the PWRGD / PWRGD output). The

which affects the r

(which in turn, affects the

DS(ON)

voltage drop across the FET during normal operation),

and the maximum GATE voltage allowed (the ICs GATE

output is clamped to ~14V).

11

ISL6141, ISL6151

R1 - Is the Over-Current sense resistor. If the input current is

case of a regulator, there may be capacitors on the output of

that circuit as well; these need to be added into the

capacitance calculation during inrush (unless the regulator is

delayed from operation by the PWRGD signal).

high enough, such that the voltage drop across R1 exceeds

the SENSE comparator trip point (50mV nominal), the GATE

pin will be pulled lower (to ~4V) and current will be regulated

to 50mV/Rsense for approximately 600µs. The Over-Current

threshold is defined in Equation 3 below. If the 600µs time-

out period is exceeded the Over-Current latch will be set and

the FET will be turned off to protect the load from excessive

current. A typical value for R1 is 0.02Ω, which sets an Over-

RL - is the equivalent resistive value of the load and

determines the normal operation current delivered through

the FET. It also affects some dynamic conditions (such as

the discharge time of the load capacitors during a power-

down). A typical value might be 48Ω (I = V/R = 48/48 = 1A).

Current trip point of; I

= V/R = 0.05/0.02 = 2.5 Amps. To

OC

select the appropriate value for R1, the user must first

determine at what level of current it should trip, take into

account worst case variations for the trip point (50mV

±10mV = ±20%), and the tolerances of the resistor (typically

1% or 5%). Note that the Over-Current threshold should be

set above the inrush current level plus the expected load

current to avoid activating the current limit and time-out

circuitry during start-up. If the power good output is used to

enable an external module, the desired inrush current only

needs to be considered. One rule of thumb is to set the

Over-Current threshold 2-3 times higher than the normal

operating current.

R2, C1, R3, C2 - are related to the GATE driver, as it

controls the inrush current.

R2 prevents high frequency oscillations; 10Ω is a typical

value. R2 = 10Ω.

R3 and C2 act as a feedback network to control the inrush

current as shown in equation 4 below, where CL is the load

capacitance (including module input capacitance), and I is

PU

the GATE pin charging current, nominally 50µA.

C

L

C

2

------

(EQ. 4)

I

= I

×

PU

inrush

50mv

I

= -------------------

OC

(EQ. 3)

R

sense

Begin by choosing a value of acceptable inrush current for

the system, and then solve for C2.

Physical layout of R1 SENSE resistor is critical to avoid

the possibility of false over current events. Since it is in the

main input-to-output path, the traces should be wide enough

to support both the normal current, and up to the over-

current trip point. Ideally trace routing between the R1

C1 and R3 prevent Q1 from turning on momentarily when

power is first applied. Without them, C2 would pull the gate

of Q1 up to a voltage roughly equal to V *C2/Cgs(Q1)

EE

(where Cgs is the FET gate-source capacitance) before the

ISL6141/2 could power up and actively pull the gate low.

Place C1 in parallel with the gate capacitance of Q1; isolate

them from C2 by R3.

resistor and the ISL6141/51 (pin 4 (V ) and pin 5 (SENSE)

EE

is direct and as short as possible with zero current in the

sense lines. (See Figure 24).

C1= [(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the

FET’s minimum gate threshold, Vinmax is the maximum

operating input voltage, and Cgd is the FET gate-drain

capacitance.

CORRECT

INCORRECT

R3 - its value is not critical, a typical value of 18kΩ is

recommended but values down to 1KΩ can be used. Lower

values of R3 will add delay to the gate turn-on for hot

insertion and the single retry event following a hard fault.

To SENSE

and V

EE

Note that although this IC was designed for -48V systems, it

can also be used as a low-side switch for positive 48V

systems; the operation and components are usually similar.

One possible difference is the kind of level shifting that may

be needed to interface logic signals to the UV input (to reset

the latch) or PWRGD output. For example, many of the IC

functions are referenced to the IC substrate, connected to

CURRENT

SENSE RESISTOR

FIGURE 24. SENSE RESISTOR LAYOUT GUIDELINES

CL - is the sum of all load capacitances, including the load’s

input capacitance itself. Its value is usually determined by

the needs of the load circuitry, and not the hot plug (although

there can be interaction). For example, if the load is a

regulator, then the capacitance may be chosen based on the

input requirements of that circuit (holding regulation under

current spikes or loading, filtering noise, etc.) The value

chosen will affect the peak inrush current. Note that in the

the V pin. But this pin may be considered -48V or GND,

depending upon the polarity of the system. And input or

output logic (running at 5V or 3.3V or even lower) might be

EE

externally referenced to either V

of GND.

or V of the IC, instead

EE

DD

12

ISL6141, ISL6151

Inrush Current Control

Electronic Circuit Breaker/Current Limit

The primary function of the ISL6141 hot plug controller is to

control the inrush current. When a board is plugged into a

live backplane, the input capacitors of the board’s power

supply circuit can produce large current transients as they

charge up. This can cause glitches on the system power

supply (which can affect other boards!), as well as possibly

cause some permanent damage to the power supply.

The ISL6141/51 features programmable current limiting with a

fixed 600µs time-out period to protect against excessive

supply or fault currents. The IntelliTrip^TMelectronic circuit

breaker is capable of detecting both hard faults, and less

severe Over-Current conditions.

The Over-Current trip point is determined by R1 (Eq. #3) also

referred to as Rsense. When the voltage across this resistor

exceeds 50mV, the current limit regulator will turn on, and the

GATE will be pulled lower (to ~4V) to regulate current through

the FET at 50mV/Rsense. If the fault persists and current

limiting exceeds the 600µs time-out period, the FET will be

The key to allowing boards to be inserted into a live

backplane is to turn on the power to the board in a controlled

manner, usually by limiting the current allowed to flow

through a FET switch, until the input capacitors are fully

charged. At that point, the FET is fully on, for the smallest

voltage drop across it. Figure 25 below illustrates the typical

inrush current response resulting from a hot insertion for the

following conditions:

turned off by discharging the GATE pin to V . This will

EE

enable the Over-Current latch and the PWRGD/PWRGD

output will transition to the inactive state to indicate power is

no longer good. To clear the latch and initiate a normal power-

up sequence, the user must either power down the system

(below the UVLO voltage), or toggle the UV pin below and

above its threshold (usually with an external transistor). Figure

26 below shows the Over-Current shut down and current

limiting response for a 10Ω short to ground on the output. With

• V = -48V, Rsense = 0.02Ω (2.5A current limit)

EE

• C1 = 150nF, C2 = 3.3nF, R3 = 18kΩ

• I

= 50µA (100µF/3.3nF) = 1.5A

• C = 100uF, R = 150Ω (48V/150Ω = 320mA)

Inrush

L

FIGURE 26. CURRENT LIMITING AND TIMEOUT

FIGURE 25. INRUSH CURRENT LIMITING FOR A HOT

INSERTION

a 10Ω short and a -48V supply, the initial fault current is

approximately 4.8A, producing a voltage drop across the

0.02Ω sense resistor of 95mV, roughly two times the Over-

Current threshold of 50mV. This enables the 600µs timer and

the GATE is quickly pulled low to limit the current to 2.5A

(50mV/Rsense). The fault condition persists for the duration of

the time-out period and the GATE is latched off in about

670µs. There is a short filter (3µs nominal) on the comparator,

so current transients shorter than this will be ignored. Longer

transients will initiate the GATE pull down, current limiting, and

the timer. If the fault current goes away before the time-out

period expires the device will exit the current limiting mode

and resume normal operation.

After the contact bounce subsides the UVLO and UV criteria

are quickly met and the GATE begins to ramp up. As the

GATE reaches approximately 4V with respect to the source,

the FET begins to turn on allowing current to charge the load

capacitor. As the drain to source voltage begins to drop, the

feedback network of C2 and R3 hold the GATE constant, in

this case limiting the current to approximately 1.3A. When

the DRAIN voltage completes its ramp down the load current

remains constant at 320mA as the GATE voltage increases

to its final value.

13

ISL6141, ISL6151

In addition to the above current limit and 600µs time-out,

comparator with a nominal reference of 1.255V. A resistor

divider between the V (gnd) and V is typically used to

there is a Hard Fault comparator to respond to short circuits

with an immediate GATE shutdown (typically 10µs) and a

single retry. The trip point of this comparator is set ~4 times

(210mV) higher than the Over-Current threshold of 50mV. If

the Hard Fault comparator trip point is exceeded, a hard pull

down current (350mA) is enabled to quickly pull down the

GATE and momentarily turn off the FET. The fast shutdown

resets the 600µs timer and is followed by a soft start, single

retry event. If the fault is still present after the GATE is slowly

turned on, the current-limit regulator will trip (sense pin

voltage > 50mV), turn on the timer, and limit the current to

50mV/Rsense for 600µs before latching the GATE pin low.

Note: Since the 600µs timer starts when the SENSE pin

exceeds the 50mV threshold, then depending on the speed of

the current transient exceeding 200mV, it’s possible that the

current limit time-out and shutdown can occur before the Hard

Fault comparator trips (and thus no retry). Figure 27 illustrates

the Hard Fault response with a zero ohm short circuit at the

output.

DD

EE

set the trip points on the UV and OV pins. If the voltage on

the UV pin is above its threshold and the voltage on the OV

pin is below its threshold, the supply is within its operating

range and the GATE will be allowed to turn on, or remain on.

If the UV pin voltage drops below its high to low threshold, or

the OV pin voltage increases above its low to high threshold,

the GATE pin will be pulled low, turning off the FET until the

supply is back within tolerance.

The OV and UV inputs are high impedance, so the value of

the external resistor divider is not critical with respect to input

current. Therefore, the next consideration is total current; the

resistors will always draw current, equal to the supply

voltage divided by the total resistance of the divider

(R4+R5+R6) so the values should be chosen high enough to

get an acceptable current. However, to the extent that the

noise on the power supply can be transmitted to the pins, the

resistor values might be chosen to be lower. A filter capacitor

from UV to V or OV to V is a possibility, if certain

EE EE

transients need to be filtered. (Note that even some

transients which will momentarily shut off the GATE might

recover fast enough such that the GATE or the output current

does not even see the interruption).

Finally, take into account whether the resistor values are

readily available, or need to be custom ordered. Tolerances

of 1% are recommended for accuracy. Note that for a typical

48V system (with a 43V to 72V range), the 43V or 72V is

being divided down to 1.255V, a significant scaling factor. For

UV, the ratio is roughly 35 times; every 3mV change on the

UV pin represents roughly 0.1V change of power supply

voltage. Conversely, an error of 3mV (due to the resistors, for

example) results in an error of 0.1V for the supply trip point.

The OV ratio is around 60. So the accuracy of the resistors

comes into play.

The hysteresis of the comparators is also multiplied by the

scale factor of 35 for the UV pin (35 * 135mV = 4.7V of

hysteresis at the power supply) and 60 for the OV pin (60 *

25mV = 1.5V of hysteresis at the power supply).

FIGURE 27. HARD FAULT SHUTDOWN AND RETRY

As in the Over-Current response discussed previously the

supply is set at -48V and the current limit is set at 2.5A. After

the initial gate shutdown (10µs) a soft start is initiated with

the short circuit still present. As the GATE slowly turns on the

current ramps up and exceeds the Over-Current threshold

(50mV) enabling the timer and current limiting. The fault

remains for the duration of the time-out period and the GATE

pin is quickly pulled low and latched off requiring a UVLO or

UV reset to resume normal operation (assuming the fault

has gone away).

With the three resistors, the UV equation is based on the

simple resistor divider:

1.255 = V

* (R5 + R6)/(R4 + R5 + R6) or

= 1.255 (R4 + R5 + R6)/(R5 + R6)

UV

V

UV

Similarly, for OV:

1.255 = V * (R6)/(R4 + R5 + R6) or

OV

= 1.255 (R4 + R5 + R6)/(R6)

V

OV

Note that there are two equations, but 3 unknowns. Because

of the scale factor, R4 has to be much bigger than the other

two; chose its value first, to set the current (for example, 50V /

500kΩ draws 100µA), and then the other two will be in the

10kΩ range. Solve the two equations for two unknowns. Note

that some iteration may be necessary to select values that

Applications: OV and UV

The UV and OV pins can be used to detect Over-Voltage and

Under-Voltage conditions on the input supply and quickly

shut down the external FET. Each pin is tied to an internal

14

ISL6141, ISL6151

meet the requirement, and are also readily available standard

values.

The three resistor divider (R4, R5, R6) is the recommended

approach for most cases. But if acceptable values can’t be

found, then consider 2 separate resistor dividers (one for

each pin, both from V

to V ). This also allows the user to

DD

EE

adjust or trim either trip point independently. Some

applications employ a short pin ground on the connector tied

to R4 to ensure the hot plug device is fully powered up

before the UV and OV pins (tied to the short pin ground) are

biased. This ensures proper control of the GATE is

maintained during power up. This is not a requirement for the

ISL6141/51 however the circuit will perform properly if a

short pin scheme is implemented (reference Figure 34).

Supply ramping

As previously mentioned the UV and OV pins can be used to

detect under and Over-Voltage conditions on the input

supply. Figures 28 and 29 illustrate the GATE shutdown

response and the UV/OV hysteresis as a typical power

supply is ramped from 0 to 80V, and then from 80V to 0V.

FIGURE 29. SUPPLY RAMP-DOWN

Applications: PWRGD/PWRGD

The PWRGD/PWRGD outputs are typically used to directly

enable a power module, such as a DC/DC converter. The

PWRGD (ISL6141) is used for modules with active low

enable (L version), and PWRGD (ISL6151) for those with

active high enable (H version). The modules usually have a

pull-up device built-in, as well as an internal clamp. If not, an

external pull-up resistor may be needed. If the pin is not

used, it can be left open.

For both versions at initial start-up, when the DRAIN to V

EE

voltage differential is less than 1.3V and the GATE voltage is

within 2.5V (V ) of its normal operating voltage (13.6V),

GH

power is considered good and the PWRGD/PWRGD pins

will go active. At this point the output is latched and the

DRAIN is no longer criticized. The latch is reset by any of the

signals that shut off the GATE (Over-Voltage, Under-Voltage;

Under-Voltage-Lock-Out; Over-Current Time-Out or

powering down). In this case the PWRGD/PWRGD output

will go inactive, indicating power is no longer good.

ISL6141 (L version; Figure 30): Under normal conditions

FIGURE 28. SUPPLY RAMP-UP

(DRAIN voltage - V < V , and ∆V

- V

< V )

EE PG GATE

GATE

GH

the Q2 DMOS will turn on, pulling PWRGD low, enabling the

module.

As the supply ramps up, the UV threshold is reached at

43.6V and the FET begins to turn on. Within 40ms the GATE

is fully on and the device is operating normally. As the supply

continues to ramp up the Over-Voltage threshold is

exceeded at approximately 70.5V and the GATE is quickly

shut down as expected. In figure 29 the GATE voltage

begins in the off state as the supply voltage is above the OV

set point. As the supply voltage decreases the GATE turns

on at about 69V (roughly a 1.5 volt hysteresis). Some 800ms

later (a characteristic of the supply used) the UV high to low

threshold is met at approximately 38.5 volts (about 5.0V of

hysteresis) and the GATE is shut off.

VDD

VIN+ VOUT+

∆ V

(SECTION OF) ISL6141

GATE

PWRGD

(L VERSION)

V

GH

ON/OFF

-

ACTIVE LOW

ENABLE

Q2

+

CL

GATE

+

LOGIC

+

LATCH

V

MODULE

PG

+

-

+

-

V

EE

DRAIN

VOUT-

VIN-

V

EE

FIGURE 30. ACTIVE LOW ENABLE MODULE

15

ISL6141, ISL6151

When any of the 4 conditions occur that turn off the GATE

(OV, UV, UVLO, Over-Current Time-Out) the PWRGD latch

is reset and the Q2 DMOS device will shut off (high

pin. This should be able to pull low against the module pull-

up current, and disable the module.

VDD

impedance). The pin will quickly be pulled high by the

external module (or an optional pull-up resistor or equivalent)

which in turn will disable it. If a pull-up resistor is used, it can

be connected to any supply voltage that doesn’t exceed the

IC pin maximum ratings on the high end, but is high enough

to give acceptable logic levels to whatever signal it is driving.

An external clamp may be used to limit the voltage range.

VIN+ VOUT+

∆

V

PWRGD

(SECTION OF) ISL6151

(H VERSION)

GATE

V

GH

RPG

-

ON/OFF

6.2K

GATE

+

ACTIVE HIGH

ENABLE

LOGIC

CL

Q2

+

V

PG

LATCH

MODULE

+

-

Q3

V

+

-

V

DD

V

EE

DRAIN

VIN- VOUT-

∆ V

(SECTION OF) ISL6141

GATE

PWRGD

R12

(L VERSION)

FIGURE 33. ACTIVE HIGH ENABLE MODULE

V

GH

PWRGD

-

GATE

+

Q2

OPTO

LOGIC

+

LATCH

Applications: GATE pin

V

PG

To help protect the external FET, the output of the GATE pin

is internally clamped; up to an 80V supply and will not be any

higher than 15V. Under normal operation when the supply

voltage is above 20V, the GATE voltage will be regulated to a

+

-

+

-

V

EE

V

EE

DRAIN

nominal 13.6V above V

.

FIGURE 31. ACTIVE LOW ENABLE OPTO-ISOLATOR

EE

Applications: “Brick” Regulators

The PWRGD can also drive an opto-coupler (such as a

4N25), as shown in Figure 31 or LED (Figure 32). In both

cases, they are on (active) when power is good. Resistors

R12 or R13 are chosen, based on the supply voltage, and

the amount of current needed by the loads.

One of the typical loads used are DC/DC regulators, some

commonly known as “brick” regulators, (partly due to their

shape, and because it can be considered a “building block”

of a system). For a given input voltage range, there are

usually whole families of different output voltages and

current ranges. There are also various standardized sizes

and pinouts, starting with the original “full” brick, and since

getting smaller (half-bricks and quarter-bricks are now

common).

V

DD

∆ V

(SECTION OF) ISL6141

GATE

PWRGD

(L VERSION)

R13

V

GH

-

GATE

+

Q2

LOGIC

+

LATCH

LED (GREEN)

Other common features may include: all components (except

some filter capacitors) are self-contained in a molded plastic

package; external pins for connections; and often an

ENABLE input pin to turn it on or off. A hot plug IC, such as

the ISL6141 is often used to gate power to a brick, as well as

turn it on.

V

PG

+

-

+

-

V

EE

V

EE

DRAIN

FIGURE 32. ACTIVE LOW ENABLE WITH LED

Many bricks have both logic polarities available (Enable Hi or

Lo input); select the ISL6141 (L version) and ISL6151 (H

version) to match. There is little difference between them,

although the L version output is usually simpler to interface.

ISL6151 (H version; Figure 33): Under normal conditions

(DRAIN voltage - V < V , and ∆V

- V

< V ),

EE PG GATE

GATE

GH

the Q3 DMOS will be on, shorting the bottom of the internal

resistor to V , and turning Q2 off. If the pull-up current from

EE

the external module is high enough, the voltage drop across

the 6.2kΩ resistor will look like a logic high (relative to

DRAIN). Note that the module is only referenced to DRAIN,

The Enable input often has a pull-up resistor or current

source, or equivalent built in; care must be taken in the

ISL6151 (H version) output that the given current will create

a high enough input voltage (remember that current through

the RPG 6.2kΩ resistor generates the high voltage level; see

Figure 33).

not V (but under normal conditions, the FET is on, and the

EE

DRAIN and V are almost the same voltage).

EE

When any of the 4 conditions occur that turn off the GATE,

the Q3 DMOS turns off, and the resistor and Q2 clamp the

PWRGD pin to one diode drop (~0.7V) above the DRAIN

The input capacitance of the brick is chosen to match its

system requirements, such as filtering noise, and

maintaining regulation under varying loads. Note that this

input capacitance appears as the load capacitance of the

ISL6141/51.

16

ISL6141, ISL6151

The brick’s output capacitance is also determined by the

When placed from V

to V on the board, it will clamp the

EE

DD

system, including load regulation considerations. However, it

can affect the ISL6141/51, depending upon how it is

enabled. For example, if the PWRGD signal is not used to

enable the brick, the following could occur. Sometime during

the inrush current time, as the main power supply starts

charging the brick input capacitors, the brick itself will start

working, and start charging its output capacitors and load;

that current has to be added to the inrush current. In some

cases, the sum could exceed the Over-Current shutdown,

which would shut down the whole system! Therefore,

whenever practical, it is advantageous to use the PWRGD

output to keep the brick off at least until the input caps are

charged up, and then start-up the brick to charge its output

caps.

voltage.

If transients on the input power supply occur when the

supply is near either the OV or UV trip points, the GATE

could turn on or off momentarily. One possible solution is to

add a filter cap C4 to the V

R10. A large value of R10 is better for the filtering, but be

pin, through isolation resistor

DD

aware of the voltage drop across it. For example, a 1kΩ

resistor, with 2.4mA of I

would have 2.4V across it and

DD

dissipate 2.4mW. Since the UV and OV comparators are

referenced with respect to the V supply, they should not

be affected. But the GATE clamp voltage could be offset by

the voltage across the extra resistor.

EE

The switch SW1 is shown as a simple push button. It can be

replaced by an active switch, such as an NPN or NFET; the

principle is the same; pull the UV node below its trip point,

and then release it (toggle low). To connect an NFET, for

example, the DRAIN goes to UV; the source to V , and the

GATE is the input; if it goes high (relative to V ), it turns the

EE

Typical brick regulators include models such as Lucent

JW050A1-E or Vicor VI-J30-CY. These are nominal -48V

input, and 5V outputs, with some isolation between the input

and output.

EE

NFET on, and UV is pulled low. Just make sure the NFET

resistance is low compared to the resistor divider, so that it

has no problem pulling down against it.

Applications: Optional Components

In addition to the typical application, and the variations

already mentioned, there are a few other possible

components that might be used in specific cases. See Figure

34 for some possibilities.

R8 is a pull-up resistor for PWRGD, if there is no other

component acting as a pull-up device. The value of R8 is

determined by how much current is needed when the pin is

If the input power supply exceeds the 100V absolute

maximum rating, even for a short transient, that could cause

permanent damage to the IC, as well as other components

on the board. If this cannot be guaranteed, a voltage

suppressor (such as the SMAT70A, D1) is recommended.

pulled low (also affected by the V

voltage); and it should

DD

be pulled low enough for a good logic low level. An LED can

also be placed in series with R8, if desired. In that case, the

criteria is the LED brightness versus current.

GND

R10*

R4

GND

R8*

(SHORT PIN)

V

DD

UV

OV

ISL6141 (L)

G

R5

R6

PWRGD

DRAIN

SW1*

V

SENSE

GATE

EE

NFET*

(INSTEAD

OF SW1)

D1*

CL*

C4*

R3

C2

C1

R2

-V IN

R1

Q1

-V OUT

FIGURE 34. ISL6141/51 OPTIONAL COMPONENTS (SHOWN WITH *)

17

ISL6141, ISL6151

Note that with the placement shown, most of the signal lines

are short, and there should not be minimal interaction

between them.

Applications: Layout Considerations

For the minimum application, there are only 6 resistors, 2

capacitors, one IC and one FET. A sample layout is shown in

Figure 35. It assumes the IC is 8-SOIC; the FET is in a

D2PAK (or similar SMD-220 package).

Although decoupling capacitors across the IC supply pins

are often recommended in general, this application may not

need one, nor even tolerate one. For one thing, a decoupling

cap would add to (or be swamped out by) any other input

capacitance; it also needs to be charged up when power is

applied. But more importantly, there are no high speed (or

any) input signals to the IC that need to be conditioned. If still

desired, consider the isolation resistor R10, as shown in

Figure 34.

Although GND planes are common with multi-level PCBs, for

a -48V system, the -48V rails (both input and output) act

more like a GND than the top 0V rail (mainly because the IC

signals are mostly referenced to the lower rail). So if

separate planes for each voltage are not an option, consider

prioritizing the bottom rails first.

GND

C2

R3

R2

C1

VDD 8

D 7

1 PG

2 OV

3 UV

4 VEE

R6

G

DRAIN

U1

FET

G 6

R5

R4

S 5

S

R1

-48V OUT

-48V IN

GND

R4

V

DD

UV

OV

PWRGD

R5

R6

ISL6141

SENSE GATE

C1

V

DRAIN

EE

(LOAD)

R3

C2

CL

R2

RL

-48V IN

R1

Q1

-48V OUT

FIGURE 35. ISL6141/51 SAMPLE LAYOUT (NOT TO SCALE)

NOTES:

1. Layout scale is approximate; routing lines are just for illustration

purposes; they do not necessarily conform to normal PCB

design rules. High current buses are wider, shown with parallel

lines.

BOM (Bill Of Materials)

R1 = 0.02Ω (5%)

R2 = 10Ω (5%)

R3 = 18kΩ (5%)

2. Approximate size of the above layout is 1.6 x 0.6 inches; almost

half of the area is just the FET (D2PAK or similar SMD-220

package).

R4 = 549kΩ (1%)

R5 = 6.49kΩ (1%)

R6 = 10kΩ (1%)

3. R1 sense resistor is size 2512; all other R’s and C’s shown are

0805; they can all potentially use smaller footprints, if desired.

C1 = 150nF (25V)

C2 = 3.3nF (100V)

Q1 = IRF530 (100V, 17A, 0.11Ω)

4. The RL and CL are not shown on the layout.

5. R4 uses a via to connect to GND on the bottom of the board; all

other routing can be on top level. (It’s even possible to eliminate

the via, for an all top-level route).

6. PWRGD signal is not used here.

18

ISL6141, ISL6151

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

N

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

-

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

o

h x 45

D

3

4

-C-

α

µ

0.050 BSC

1.27 BSC

-

e

A1

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

C

B

0.10(0.004)

5

0.25(0.010) M

C A M B S

L

6

N

α

8

7

NOTES:

o

0

8

0

8

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

19


型号：	ISL6141IBZA
厂家：	Intersil
描述：	Negative Voltage Hot Plug Controller 负电压热插拔控制器控制器
文件：	总19页 (文件大小：426K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6141IBZA [INTERSIL]

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