ISL6173DRZA [INTERSIL]
Dual Low Voltage Hot Swap Controller; 双路低电压热插拔控制器
| 型号： | ISL6173DRZA |
| 厂家： | 
Intersil |
| 描述： | Dual Low Voltage Hot Swap Controller |
| 文件： | 总20页 (文件大小：450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL6173
®
Data Sheet
February 15, 2005
FN9186.2
Dual Low Voltage Hot Swap Controller
Features
This IC targets dual voltage hot swap applications across the
+2.5V to +3.3V (nominal) bias supply voltage range with a
second lower voltage rail down to less than 1V. It features a
charge pump for driving external N-Channel MOSFETs,
regulated current protection and duration, output undervoltage
monitoring and reporting, optional latch-off or retry response,
and adjustable soft-start.
• Fast Current Regulation amplifier quickly responds to
overcurrent fault conditions
• Less than 1µs response Time to Dead Short
• Programmable Current Regulation Level and Duration
• Two Levels of Overcurrent Detection Provide Fast
Response to Varying Fault Conditions
• Overcurrent Circuit Breaker and Fault Isolation functions
• Adjustable Current Regulation Threshold as low as 20mV
The current regulation level (CR) for each rail is set by two
external resistors and each CR duration is set by an external
capacitor on the TIM pin. After the CR duration has expired
the IC then quickly pulls down the associated GATE(s)
output turning off its external FET(s). The ISL6173 offers a
latched output or indefinite auto retry mode of operation.
• Selectable Latch-off or Auto Retry Response to Fault
conditions
• Adjustable voltage ramp-up for In-rush Protection During
Turn-On
Ordering Information
• Rail Independent Control, Monitoring and Reporting I/O
• Dual Supply Hot Swap Power Distribution Control to <1V
• Charge Pump Allows the use of N-Channel MOSFETs
• QFN Package:
TEMP.
PKG.
PART NUMBER RANGE (°C)
PACKAGE
DWG. #
ISL6173DRZA *
ISL6173DRZA-T*
0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
0 to +85 28 Ld 5x5 QFN (Pb-free) L28.5x5
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
ISL6173EVAL3 Evaluation Platform
- Near Chip Scale Package footprint, which improves
*Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PCB efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
Applications
• Power Supply Sequencing, Distribution and Control
Pinout
ISL6173 (28 LEAD QFN)
• Hot Swap/Electronic Breaker Circuits
TOP VIEW
Rsns1
V1(in)
V1(out)
28
27
26
25
24
23
22
SNS1
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
VS1 SNS1 GT1 VO1
EN1 EN2
UV1
PG1
FLT1
RTR/LTCH
BIAS
CPQ+
19
SS2
18 GT2
17
SS1
CPQ-
CPVDD
OCREF
SS2
ISL6173
GT1
FLT2
PG2
FLT1
PG1
CT1
FLT2
PGND
GND
16 PG2
15 CT2
UV2
CT1 CT2 VS2
SNS2 GT2 VO2
8
9
10
11
12
13
14
V2(OUT)
V2(in)
Rsns2
FIGURE 1. TYPICAL APPLICATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004-2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL6173
Block Diagram
Io
LOAD
Vin
Vo
Rsns
Q
Iset Rset
Current
Limit
10V
24µA
Amplifier
Soft Start
Amplifier
-
CPVDD
10µA
-
+
42µA
SS1
+
3K
Css
-
+
WOC
FLT1
Comparator
OC Timer
&
1.178V
+
Logic
Iref
OCREF
Rref
CPVDD
10µA
-
OC
Iref
4
Current
Mirror
Comparator
PG1
CT1
BIAS
10K
+
-
Ct
EN1
1.178V
633mV
Timeout
Rs1
Rs2
Comparator
BIAS
10K
-
UV1
RTR/LTCH
BIAS
UV
+
Comparator
CPQ+
Cp
10V(out)
X2
X2
Charge
Pump
Charge
Pump
CPQ-
CPVDD
Cv
633mV
POR and
Bandgap
1.178V
ISL6173
FIGURE 2. ISL6173 - INTERNAL BLOCK-DIAGRAM OF THE IC - CHANNEL ONE ONLY
FN9186.2
February 15, 2005
2
ISL6173
Pinout
28 LEAD QFN
TOP VIEW
28
27
26
25
24
23
22
SNS1
VO1
SS1
1
2
3
4
5
6
7
21 SNS2
20 VO2
19
SS2
18 GT2
17
GT1
FLT1
PG1
CT1
FLT2
16 PG2
15 CT2
8
9
10
11
12
13
14
Pin Descriptions
PIN
NAME
FUNCTION
DESCRIPTION
1
SNS1
Current Sense Input
This pin is connected to the current sense resistor and control MOSFET Drain node. It provides
current sense signal to the internal comparator and amplifier in conjunction with VS1 pin.
2
3
VO1
SS1
Output Voltage 1
This pin is connected to the control MOSFET switch source, which connects to a load. Internally, this
voltage is used for SS control.
Soft-Start Duration Set A capacitor from this pin to ground sets the output soft-start ramp slope. This capacitor is charged by
Input
the internal 10µA current source setting the soft-start ramp. The output voltage ramp tracks the SS
ramp by controlled enhancement of FET gate. Once ramp-up is completed, the capacitor continues
to charge to the CPVDD voltage rail. If common capacitor is used (by tying SS1, SS2 together and
the capacitor to GND from the connection) then both the outputs track each other as they ramp up.
4
5
6
7
GT1
FLT1
PG1
CT1
Gate Drive Output
Fault Output
Direct connection to the gate of the external N-Channel MOSFET. At turn-on the Gate will charge to
4 X Vbias or 10V(max) from the 24µA source.
This is an open drain output. It asserts (pulls low) once the current regulation duration (determined
by the CTx timeout cap) has expired. This output is valid for Vbias>1V.
Power Good Output
Timer Capacitor
This is an active low, open drain output. When asserted (logic zero), it indicates that the voltage on
UV1 pin is more than 643mV (633mV + 10mV hysteresis). This output is valid at VBIAS >1V.
A capacitor from this pin to ground controls the current regulation duration from the onset of current
regulation to channel shutdown (current limit time-out). Once the voltage on CTx cap reaches
V
the GATE output is pulled down and the FLT is asserted.
CT_Vth
The duration of current limit time-out = (C
*1.178)/10µA
TIM
When the OC comparator trips AND the RTR/LTCH pin is pulled low, the IC’s faulty channel remains
shut down for 64 cycles (each cycle length is equal to the current limit time-out duration).
8
RTR/
LTCH
Retry Or Latch Input
This input dictates the IC behavior (for either channel) under OC condition. If it is pulled high (or left
floating), the IC will shut down upon OC time-out. If it is pulled low, the IC will go into retry mode after
an interval determined by the capacitor on CTx pin. The faulting channel will remain shut down for
64 cycles and will try to come out of it on the 65th cycle. Each cycle length is determined by the
formula shown in CT pin description.
9
GND
Chip Gnd
This pin is also internally shorted to the metal tab at the bottom of the IC.
Charge pump ground. Both GND and PGND must be tied together externally.
10
PGND
FN9186.2
3
February 15, 2005
ISL6173
Pin Descriptions (Continued)
PIN
NAME
FUNCTION
DESCRIPTION
11
CPQ-
ChargePumpCapacitor Flying cap lowside.
Low Side
12
BIAS
Chip Bias Voltage
Provides IC Bias. Should be 2V to 4V for IC to function normally. This pin can be powered from a
supply voltage that is not being controlled. It is preferable to use 3.3V even if the channels being
controlled are 2.5V or lower because more gate drive voltage will be available to the MOSFETs.
13
14
CPQ+
ChargePumpCapacitor Flying cap highside. Use of 0.1µF for 2.5V bias and 0.022µF for 3.3V bias is recommended.
High Side
CPVDD Charge Pump Output
This is the voltage used for some internal pullups and bias. Use of 0.47µF (minimum) is
recommended.
15
16
17
18
19
CT2
PG2
FLT2
GT2
SS2
Timer Capacitor
Power Good Output
Fault Output
Same function as pin 7
Same function as pin 6
Same as pin 5
Gate Drive Output
Same as pin 4
Soft-Start Duration Set Same as pin 3
Input
20
21
22
VO2
SNS2
VS2
Output Voltage 2
Same as pin 2
Same as pin 1
Current Sense Input
Current Sense
Reference
Voltage input for one of the two voltages. Provides a 20µA current source for the ISET series resistor
which sets the voltage to which the sense resistor IR drop is compared.
23
UV2
EN2
Undervoltage Monitor
Input
This pin is one of the two inputs to the undervoltage comparator. The other input is the 633mV
reference. It is meant to sense the output voltage through a resistor divider. If the output voltage
drops so that the voltage on the UV pin goes below 633mV, PG2 is deasserted.
24
25
Enable
This is an active low input. When asserted (pulled low), the SS and gate drive are released and the
output voltage gets enabled. When deasserted (pulled high or left floating), the reverse happens.
OCREF Ref. Current Adj.
Allows adjustment of the reference current through R
and the internal current regulation set
SET
resistor, thus setting the thresholds for CR, OC and WOC.
26
27
EN1
UV1
Enable Input
Same as pin 24
Same as pin 23
Undervoltage Monitor
Input
28
VS1
Current Sense
Reference
Same as pin 22
FN9186.2
February 15, 2005
4
ISL6173
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Notes 1, 4)
5x5 QFN Package . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
For recommended soldering conditions, see Tech Brief TB389.
(QFN - Leads Only)
VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
GTx, CPQ+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +12V
ENx, RTR/LTCH, SNSx, PGx, FLTx, VSx, CTx, UVx,
θ
(°C/W)
42
θ
(°C/W)
JA
JC
12.5
SSx, CPQ-, CPVDD. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5VDC
Output Current . . . . . . . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .1750V
Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .125V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . .1750V
Operating Conditions
VBIAS/VIN1 Supply Voltage Range. . . . . . . . . . . .+2.25V to +3.63V
Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
A
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. All voltages are relative to GND, unless otherwise specified.
3. 1V (min) on the BIAS pin required for FLT to be valid.
4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= 2.5V to +3.3V, T = T = 0°C - 85°C, Unless Otherwise Specified.
DD
A
J
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
25
MAX
UNIT
CURRENT REGULATION CONTROL
Current Regulation Threshold Voltage
Current Regulation Accuracy
Current Regulation Threshold Voltage
Current Regulation Accuracy
CT Threshold Voltage
V
RISET = 1.25K 1%, I
= 20µA
20
-20
30
+20
55
mV
%
CRVTH_1
SET
SET
SET
SET
V
R
RISET = 1.25K 1%, I
RISET = 2.50K 1%, I
RISET = 2.50K 1%, I
= 20µA
= 20µA
= 20µA
CRVTH_1
V
45
50
mV
%
CRVTH_2
V
R
-10
+10
1.202
CRVTH_2
V
1.128
1.178
10
V
CT_Vth
CT Charging Current
I
µA
CT
GATE DRIVE
GATE Response Time from WOC (Open)
pd_woc_open
GATE open
100mV of overdrive on the WOC
comparator
3
ns
GATE Response Time from WOC (Loaded)
pd_woc_load
pd_cr_load
GATE = 1nF
100
5
ns
µs
GATE Response Time in Current Regulation
mode (Loaded)
GATE = 1nF
120% Load Current
GATE Turn-On Current
IGATE
GATE = 2V
21
24
27
µA
V
V
= 2V
VS
= 2.1V
SNS
GATE Voltage
V
Bias = 2.5V (see graph on page 7)
7.5
9.0
V
V
GATE
2.1 < Bias < 2.5
(see graph on page 7)
8
9
BIAS
Supply Current
I
V
= 3.3V
17
mA
V
BIAS
BIAS
POR Rising Threshold
POR Falling Threshold
POR Threshold Hysteresis
VIN_POR_L2H
VIN_POR_H2L
VIN_POR_HYS
2.12
2.10
V
5
mV
FN9186.2
5
February 15, 2005
ISL6173
Electrical Specifications
V
= 2.5V to +3.3V, T = T = 0°C - 85°C, Unless Otherwise Specified. (Continued)
DD
A
J
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I/O
Undervoltage Comparator Falling Threshold
Undervoltage Comparator Hysteresis
EN Rising Threshold
V
620
7
635
16
650
25
mV
mV
V
UV_VTHF
V
UV_HYST
PWR_Vth_R
PWR_Vth_F
PWR_HYST
V
V
V
= 2.5V
= 2.5V
= 2.5V
1.55
0.97
600
1.95
1.10
850
2.19
1.30
1100
0.4
BIAS
BIAS
BIAS
EN Falling Threshold
EN Hysteresis
V
mV
V
PG Pull-Down Voltage
FLT Pull-Down Voltage (Note 3)
Soft-Start Charging Current
CHARGE PUMP
I
I
= 8mA
0.047
0.047
VOL_PG
PG
= 8mA
0.4
V
VOL_FLT
IQ_SS
FLT
VSS = 1V
10
µA
CPVDD
V_CPVDD
V_CPVDD
V
V
= 3.3V
= 3.3V
4.9
5.2
5.0
5.5
V
V
BIAS
BIAS
CPVDD
T = 25°C
External User Load = 6mA
FN9186.2
6
February 15, 2005
ISL6173
Typical Performance Curves (at 25°C unless otherwise specified)
2.045
2.04
2.035
2.03
2.025
2.02
2.015
2.01
2.005
2
12
10
8
6
4
2
C
= 22nF, C
2.9
= 0.47µF
3.7
PQ
PVDD
3.2
0
-10
0
25
40
60
85
1.0
1.4
1.7
2.0
2.3
V_BIAS(V)
TEMPERATURE (°C)
FIGURE 3. I_BIAS vs V_BIAS
FIGURE 4. POR RISING THRESHOLD vs TEMPERATURE
10
9
8
7
6
10
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
C
= 22nF, C
PVDD
= 0.47µF
C
= 0.1µF, C = 0.47µF
PVDD
PQ
PQ
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9 4
V_BIAS (v)
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.5 3.7 3.8 3.9
V_BIAS (V)
4
FIGURE 5. V
GATE
vs V_BIAS
FIGURE 6. V
vs V_BIAS
GATE
24.6
24.4
24.2
24
0.19
0.18
0.17
0.16
0.15
0.14
0.13
0.12
0.11
0.1
23.8
23.6
23.4
I
= 8mA
85
PG
-10
0
25
40
60
85
-10
0
25
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. GATE DRIVE vs TEMPERATURE
FIGURE 8. PG_VOL vs TEMPERATURE
FN9186.2
February 15, 2005
7
ISL6173
Typical Performance Curves (at 25°C unless otherwise specified) (Continued)
10000
3
2.5
1000
2
100
1.5
1
10
0.5
1
0
100
0
0.1
0.47
1
2
4
8.7
14
22
150
200
250
300
C
(nF)
OC (% OF LIMIT)
G
FIGURE 9. WOC RESPONSE vs LOAD CAPACITANCE
FIGURE 10. RESPONSE TIME vs I *R
SNS
O
2.008
2.006
2.004
2.002
2
1.998
1.996
-10
0
25
40
60
85
TEMPERATURE (°C)
FIGURE 11. POR FALLING vs TEMPERATURE
FN9186.2
8
February 15, 2005
ISL6173
Each of these modes is described in detail as follows:
Detailed Description of Operation
ISL6173 targets dual voltage hot-swap applications with a
bias of 2.1V to 3.6VDC and the voltages being controlled
down to 0.7VDC. The IC’s main function is to limit and
regulate the inrush current into the loads. This is achieved by
enhancing an external MOSFET in a controlled manner. In
order to fully enhance the MOSFET, the IC must provide
adequate gate to source voltage, which is typically 5V or
greater. Hence, the final steady-state voltage on Gate (GT)
pin must be 5V above the load voltage. Two internal charge-
pumps allow this to happen.
1. Current Limit or Current Regulation (CR) Mode: - When
the load current reaches the current regulation threshold, the
current amplifier loop closes and the circuit behaves like a
current source. The Current Limit Amplifier is a folded
cascode type with source follower output capable of pulling
down the gate very fast in response to fast overload
transients. The current regulation threshold is set by setting a
reference current, I
, through R by selecting an
SET
SET
appropriate resistor between OCREF and GND, which sets
I
. The relationship between I
and I
is I
=
REF REF
SET
REF
4*I = Vocref/Rocref = 1.178/Rocref. I
, where I
SET
REF
REF
would typically be set at 80µA.
VIN
VO
Q
Selecting appropriate values for R
and R
such that
(EQ. 1)
SET
SNS
when I = I
,
O
CR
Io*R
= I
*R
SNS
SET SET
VIN
10V
Vin
Vo
-
+
0
CPVDD
24µA
+
Rsns
Q
SOFT-
START
Rset
Iset
CPVDD
10µA
CURRENT REGULATION
MODE:
-
AMPLIFIER
0
SS1
-
Iset*Rset = Io*Rsns
42µA
+
+
-
CURRENT
LIMIT
10V
ISL6173
AMPLIFIER
24µA
FIGURE 12. SOFT-START OPERATION
-
Controlled Soft-Start
+
3K
The output voltages are monitored through the Vo pins and
slew up at a rate determined by the capacitors on the Soft-
start (SS) pin, as illustrated in Figure 12. 24µA of gate
charge current is available. The soft-start amplifier controls
the output voltage by robbing some of the gate charge
current thus slowing down the MOSFET enhancement.
When the load voltage reaches its set level, as sensed by its
respective UV pin through an external resistor divider, the
Power Good (PG) output goes active.
Iref
4
FIGURE 13. CURRENT REGULATION OPERATION
The operating mode is shown in Figure 13. When the circuit
enters this mode, the OC comparator detects it and sets off
the timer. CT begins to charge from an internal 10µA current
source. The amount of time it takes for this cap to charge to
1.178V sets up the current regulation duration. Upon
Current Monitoring and Protection
The IC monitors the load current (Io) by sensing the voltage-
drop across the low value current sense resistor (R
which is connected in series with the MOSFET as shown in
the diagram on page 2, through Sense (SNS) and voltage
),
SNS
expiration of this time-out period, the MOSFET gate is pulled
down quickly by the current limit amplifier, unless the load
current level had already dropped back to a level below the
current regulation threshold level prior to that. In that case, the
current regulation mode is no longer active, the MOSFET is
set (VS) pins. The latter is through a resistor, R
shown. Two levels of overcurrent detection are available to
protect against all possible fault scenarios. These levels are:
, as
SET
1. Current Limit or Current Regulation (CR)
2. Way Overcurrent (WOC)
allowed to fully enhance and the IC discharges the C Cap. If
T
RTR/LTCH pin is left open or pulled to BIAS, the output
remains latched off after the expiration of the time-out period
determined by C . If RTR/LTCH pin is pulled to GND, the IC
T
FN9186.2
February 15, 2005
9
ISL6173
automatically retries to turn on the MOSFET after a wait
on this pin reaches 1.178V, the CR duration expires. Fault
(FLT) pin goes active (pulls low), signaling the load of a fault
condition and the gate (GT) pin gets pulled low.
period, during which C is charged and discharged 64 times
T
and the retry attempt takes place on the 65th time. This wait
period allows the MOSFET junction to cool down.
Retry vs Latched Fault Operational Modes:
2. Way Overcurrent (WOC) Mode - This mode is designed
to handle very fast, very low impedance shorts on the load
side, which can result in very high di/dt. Typically, the current
limit set for this mode is 300% of the current regulation limit.
This mode uses a very fast comparator, which directly looks
RTR/LTCH pin dictates the IC behavior after the gate (GT)
pin pulls down following OC timeout expiration. If the
RTR/LTCH pin is left floating, the gate pin will remain latched
off. It can only be released by de-asserting and reasserting
the enable (EN) input. If RTR/LTCH pin is pulled to GND,
then the Retry mode will be activated. In this mode the IC will
automatically attempt to turn-on the MOSFET after a delay,
determined by the capacitor on CT pin. In the Retry mode,
the internal logic charges and discharges the CT cap 64
times during “wait” period. On the 65th time, the FLT output
clears during retry attempt. If the overcurrent condition
persists after the soft-start, the CT pin will again start
charging and the process repeats.
at the voltage drop across R
and pulls the gate very
SNS
quickly to GND (as shown in Figure 14) and immediately
releases it. If the WOC is still present, the IC enters current
regulation mode and the rest of the current regulation
behavior follows as described earlier in undercurrent
regulation mode.
Io
Vo
Vin
-
+
Q
+
Rsns
Bias and Charge Pump Voltages:
Iset Rset
-
The BIAS pin feeds the chip bias voltage directly to the first
of the two internal charge pumps, which are cascaded. The
output of the first charge pump, in addition to feeding the
second charge pump, is accessible on the CPVDD pin. The
voltage on the CPVDD pin is approximately 5V. It also
provides power to the POR and band-gap circuitry as shown
in the block diagram. A capacitor connected externally
across CPQ+ and CPQ- pins of the IC is the “flying” cap for
the charge-pump.
GATE
PULLDOWN
CURRENT
ISL6173
WOC
COMPARATOR
3K
-
The second charge-pump is used exclusively to drive the
gates of the MOSFETs through the 24µA current sources,
one for each channel. The output of this charge pump is
approximately 10V as shown in the block diagram.
+
25Ω
Tracking
FIGURE 14. WOC OPERATION
Additionally, as shown in the block diagram, there is also an
“OC comparator”, which also looks at the Rsense voltage
drop. When this drop exceeds the Current Limit set point, it
triggers the timeout circuit, which starts ticking and CTx is
allowed to charge. If the current limit condition remains in
effect until after the time-out period expires (CTx voltage
exceeding 1.178V), the gate of the MOSFET is pulled down,
the SSx capacitor is discharged, FLT is asserted and a new
SS sequence is allowed to begin after ENx recycle or by
keeping the RTR/LTCH pin pulled low.
The voltage on OCREF pin is the same as the internal band-
gap reference voltage, which is 1.178V (nominal). A resistor
to GND from this pin sets the reference current (and hence
the reference voltage) for the current limit amplifier and
OC/WOC comparators. The current regulation (CR) duration
is set by the capacitor on CT pin to GND. Once the voltage
CH1: V 1, CH2: V 2, T = 2ms/DIV, C = 0.066µF
SS
O
O
FIGURE 15. TRACKING MODE WAVEFORMS
FN9186.2
February 15, 2005
10
ISL6173
The two channels can be forced to track each other by
simply tying their SS pins together and using a common SS
capacitor. In addition, their EN pins also must be tied
together. Typical Start-up waveforms in this mode are shown
in Figure 15. If one channel goes down for any reason, the
other one will too. One important thing to note here is that
only the overcurrent latch-off mode will work. Auto-retry
feature WILL NOT work. Retry must be controlled manually
through EN.
same rate as the SS cap voltage. This is tightly controlled
by the soft-start amplifier shown in the block diagram.
5. SS cap begins to charge but the corresponding CTx cap
is held discharged.
6. Fault (FLT) remains deasserted (stays high) and the
output voltage continues to rise.
7. If the load current on the output exceeds the set current
limit for greater than the OC timeout period, FLT gets
asserted and the channel shutdown occurs.
8. If the voltage on UV pin exceeds 633mV threshold as a
result of rising Vo, the Power Good (PG) output goes
active.
9. At the end of the SS interval, the SS cap voltage reaches
CPVDD and remains charged as long as EN remains
asserted or there is no other fault condition present that
would attempt to pull down the gate.
Typical Hot-plug Power Up Sequence
1. When power is applied to the IC on the BIAS pin, the first
charge pump immediately powers up.
2. If the BIAS voltage is 2.1V or higher, the IC comes out of
POR. Both SS and CT caps remain discharged and the
gate (GT) voltage remains low.
3. ENx pin, when pulled low (below it’s specified threshold),
State Diagram
enables the respective channel.
This is shown in Figure 16. It provides a quick overview of
the IC operation and can also be used as a troubleshooting
road map.
4. SSx cap begins to charge up through the internal 10µA
current source, the gate (GT) voltage begins to rise and
the corresponding output voltage begins to rise at the
FN9186.2
11
February 15, 2005
ISL6173
IC Operation State Diagram
No
Pow er
Apply Pow er
Bias>1V
PG
&
FLT
Outputs
Valid
Bias>2V
EN De-as serted
FLT
Cleared
EN A s s erted
Gate
Pulldow n
Count 64
Puls es
&
Io>ICR
Soft Start
(Tss)
Io>>ICR
(WOC)
Reset
Current
Limit
Mode
Output
Voltage
Available
Io>ICR
RTR/LTCH = L
Reset &
Latch
Off
Run
OC Timer
(Toc)
State
RTR/LTCH = H
FLT
Io>=Icr
AND
Vuv<633mV Vuv>645mV
Asserted
t>Toc
PG
Asserted
FIGURE 16.
FN9186.2
12
February 15, 2005
ISL6173
Current Set Resistor (R
Applications Information
Selection of External Components
The typical application circuit of Figure 2 has been used for
this section, which provides guidelines to select the external
component values.
SET)
This resistor directly sets the threshold for the current
regulation amplifier and indirectly sets the same for the OC
and WOC comparators in conjunction with R
. Once
SNS
R
has been selected, use Equation 1 (on page 9) to
SNS
calculate R
. Use 20µA for I
in a typical application.
SET SET
MOSFET (Q1)
Reference Current Set Resistor (R
)
REF
This resistor sets up the current in the internal current
source, I /4, shown in Figure 2 for the comparators. The
This component should be selected on the basis of its
r
specification at the expected Vgs (gate to source
DS(ON)
REF
voltage at the OCREF pin is the same as the internal
voltage) and the effective input gate capacitance (Ciss). One
needs to ensure that the combined voltage drop across the
bandgap reference. The current (I
resistor is simply:
) flowing through this
REF
Rsense and r
at the desired maximum current
DS(ON)
(including transients) will still keep the output voltage above
the minimum required level. Power dissipation in the device
under short circuit condition should also be an important
consideration especially in auto-retry mode (RTR/LTCH pin
pulled low). Using ISL6173 in latched off mode results in
lower power dissipation in the MOSFET.
I
= 1.178/R
REF
REF
, should be set at 80µA to force 20µA in the
This current, I
REF
internal current source as shown in Figure 2, because of the
4:1 current mirror. This equates to the resistor value of
14.7K.
Ciss of the MOSFET influences the overcurrent response
time. It is recommended that a MOSFET with Ciss of less
than 10nF be chosen. Ciss will also have an impact on the
SS cap value selection as seen later.
Selection of Rs1 and Rs2
These resistors set the UV detect point. The UV comparator
detects the undervoltage condition when it sees the voltage
at UV pin drop below 0.633V. The resistor divider values
should be selected accordingly.
Current Sense Resistor (R
)
SNS
The voltage drop across this resistor, which represents the
load current (Io), is compared against the set threshold of
the current regulation amplifier. The value of this resistor is
determined by how much combined voltage drop is tolerable
between the source and the load. It is recommended that at
least 20mV drop be allowed across this resistor at max load
current. This resistor is expected to carry maximum full load
Charge Pump Capacitor Selection (C and C )
P
V
C
is the “flying cap” and C is the smoothing cap of the
V
P
charge pump, which operates at 450kHz set internally. The
output resistance of the charge pump, which affects the
regulation, is dependent on the C value and its ESR,
P
charge-pump switch resistance, and the frequency and ESR
of the smoothing cap, C .
V
current indefinitely. Hence, the power rating of this resistor
2
must be greater than I
*R .
SNS
It is recommended that C be kept within 0.022µF
P
O(MAX)
(minimum) to 0.1µF (maximum) range. Only ceramic
capacitors are recommended. Use 0.1µF cap if CPVDD
output is expected to power an external circuit, in which case
the current draw from CPVDD must be kept below 10mA.
This resistor is typically a low value resistor and hence the
voltage signal appearing across it is also small. In order to
maintain high current sense accuracy, current sense trace
routing is critical. It is recommended that either a four wire
resistor or the following routing method be used:
C
should at least be 0.47µF (ceramic only). Higher values
V
may be used if low ripple performance is desired.
LOAD CURRENT CARRYING
TRACES
Time-out Capacitor Selection (C )
T
This capacitor controls the current regulation time-out
period. As shown in Figure 2, when the voltage across this
capacitor exceeds 1.178V, the time-out comparator detects it
and pulls down the gate voltage thus shutting down the
channel. An internal 10µA current source charges this
capacitor. Hence, the value of this capacitor is determined by
the following equation:
CURRENT
SENSE
R
SNS
TRACES
C = (10µA * T )/1.178
OUT
T
Where,
FIGURE 17. RECOMMENDED CURRENT SENSE RESISTOR
PCB LAYOUT
T
= Desired time-out period.
OUT
FN9186.2
13
February 15, 2005
ISL6173
The outputs are brought out to banana sockets to allow
Soft-Start Capacitor Selection (C
)
SS
external loading if desired.
The rate of change of voltage (dv/dt) on this capacitor, which
is determined by the internal 10µA current source, is the
same as that on the output load capacitance. Hence, the
value of this capacitor directly controls the inrush current
amplitude during hot swap operation.
J1 and J3 are wire jumpers. A user can replace them with
wire loops to attach a scope current probe. However, doing
so may reduce the di/dt enough to prevent WOC comparator
from tripping. The internal current regulation amplifier is fast
enough to respond to very fast di/dt. Hence, it is advisable to
use the on board dynamic load circuitry, as will be described,
if a user wants to check the WOC performance.
C
= C *(10µA/I )
INRUSH
SS
Where,
O
C
= Load Capacitance
O
The dynamic load circuitry, shown in Figure 21, is included
on the board on both channels to ensure minimum
inductance in the current flow path. Two sets of load are
available per output:
I
I
= Desired Inrush Current
INRUSH
is the sum of the dc steady-state load current and
INRUSH
the load capacitance charging current. If the dc steady-state
load remains disabled until after the soft-start period expires
(PGx could be used as a load enable signal, for example),
then only the capacitor charging current should be used as
1) CR Load: This load is set at 1Ω (approximately 3.3A for
3.3V output), which is higher than the 2.2A of CR limit but
less than WOC limit (6.6A) set on the board.
I
. The Css value should always be more than (1/2.4)
INRUSH
2) WOC Load: This load is set at 340mΩ, which is roughly
10A for 3.3V supply. This is higher than 6.6A WOC limit set
on the board.
of that of Ciss of the MOSFET to ensure proper soft-start
operation. This is because the Ciss is charged from 24µA
current source whereas the Css gets charged from a 10µA
current source (please refer to Figure 12). In order to make
sure both Vss and Vo track during the soft-start, this
condition is necessary.
A function/pulse generator is required to activate the
dynamic load circuitry. The function/pulse generator should
have adjustable pulse-width (3ms), single pulse (manual
trigger) and 5V pulse amplitude capability. Agilent model
No: 33220A or equivalent is a good choice. The function
generator needs to be connected through a co-ax cable to
J11 or J12 for channel 1 or channel 2 respectively. WOC or
CR load can be activated by turning SW4 or SW5 (channel
1) and SW6 or SW7 (channel 2) ON followed by applying the
pulse generator to turn on an appropriate load.
ISL6173 Evaluation Platform
The ISL6173EVAL1 is the primary evaluation board for this
IC. The board is a standalone evaluation platform and it only
needs input bias and test voltages. The schematic for this
board is shown in Figures 20 and 21. The component
placement diagram is shown in Figure 22.
The load circuit consists of a MOSFET driver (EL7202),
MOSFET (IRF7821) and surface mount load resistors. The
MOSFET drivers, U2 and U3, respond to a pulse from the
generator to turn on the MOSFET for the duration of the
pulse, which should be set less than the timeout period
described in “Time-out Capacitor Selection”. On this board
the timeout capacitor value is 0.15µF, which corresponds to
a timeout period of 17.67ms.
The evaluation board has been designed with a typical
application and accessibility to all the features in mind to
enable a user to understand and verify these features of the
IC. The circuit is designed for 2A for each input rail but it can
easily be scaled up or down by adjusting some component
values. LED indicators are provided to indicate Fault and
Power Good status. Switches are there to perform Enable
function for each channel, to select auto-retry or latchoff
mode and to check WOC and CR modes.
One way to tell if the WOC mode is active would be by
looking at the Gate waveform of the control MOSFET (M1 or
M2). The WOC comparator when tripped, pulls down the
Gate hard. The following waveform shows WOC operation:
There are two input voltages, one for each channel plus
there is “+5V” input. The latter is to test the pull-up capability
of FLT and PG outputs to +5V and also to power the LEDs
and the dynamic load circuitry. ISL6173 does not require 5V.
Pins SS1 and SS2 of the IC are available on header J2 as
test points so that they can be tied together to achieve
tracking between Vo1 and Vo2. Both the Enable (EN)
switches (SW1 and SW2) must be turned ON to check this
function.
Each channel is preloaded with capacitive load. Extra load
can be externally applied as required.
FN9186.2
14
February 15, 2005
ISL6173
FIGURE 18. WOC OPERATION
Channel 1 is Vgate, Channel 2 is the pulse generator output
and Channel 3 is Vout. Note how Vgate gets immediately
pulled down to zero volts up on load application.
In CR mode, however, Vgate always remains above zero
volts because WOC comparator never trips. This can be
seen on the following scope shot:
FIGURE 19. CURRENT REGULATION OPERATION
It is also important to note that in WOC mode, although
Vgate gets pulled down to zero initially, the gate is quickly
released and slowly rises until the CR amplifier takes control.
FN9186.2
15
February 15, 2005
ISL6173
Bill of Materials for ISL6173 Eval 1 Board
ITEM QTY
REFERENCE
PART
PKG
Leaded
MFG P/N
MANUFACTURER
Nichicon
Nichicon
Any
1
2
2
2
2
2
2
2
1
1
2
1
1
2
2
2
1
2
2
6
C1, C18
C2, C17
C3, C4
C5, C6
C9, C10
C11, C12
C13
220µF
47µF
UPM1E221MPH6 or eq
UPM1E470MEH or eq
Leaded
0805
0805
0805
0805
0805
1206
0805
7343
0805
SMA
1206
1206
3
0.1µF
4
1000pF
0.033µF
0.15µF
0.47µF
2.2µF
Any
5
Any
6
Any
7
Any
8
C14
Any
9
C19, C20
C21
0.01µF
10µF
Any
10
11
12
13
14
15
16
17
18
Any
C22
0.022µF
Any
D1, D6
D3, D4
D2, D5
J2
MBR130P
LED GRN
LED RED
2 Pin Header
Jumper
MBR130P
PG1101W
BR1101W
ON Semi
Stanley
Stanley
Any
J1, J3
J11, J12
Any
BNC Jack
IRF7821
M1, M2, M3, M4, M5, M6
SO8
IRF7821
International
Rectifier
19
10
RS1, RS2, R10, R12, R30, R31
R55, R56, R57, R58
R1, R27, R49, R50, R51, R52
R2, R3, R25, R26
R8
1K
0805
Any
20
21
22
23
24
25
26
27
28
29
30
6
4
0.01
390
3.57K
2.55K
14.7K
0
2512
0805
0805
0805
0805
0805
0805
0805
0805
2512
2512
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
Any
1
1
R9
1
R11
3
R14, R15, R20
R16, R17, R18, R19
R29, R32
4
10K
1.1K
10
2
4
R33, R34, R35, R36
R37, R38, R42, R43, R44, R45
R39, R40, R41, R46, R47, R48
R61, R62, R63, R64
R53, R54
6
1
10
5
31
32
34
35
38
2
2
1
2
7
100
1206
Any
R59, R60
49.9
0805
Any
U1
ISL6173
EL7202/SO
Toggle Switch
QFN28 5x5
SO8
ISL6172
Intersil
Intersil
C & K
U2, U3
SW5, SW6, SW7, SW8, SW9,
SW10, SW11
GT11MCKE
FN9186.2
16
February 15, 2005
Schematic, ISL6173 Eval1
M1
IRF7821
J4
J8
TP2
Vi_1
VO1
R1
0.01
3.3V
Vi_1
VO1
TP1
C2
R53
100
C1
47µF
5V
D1
MBR130P
220µF
R29
TP6
TP5
5V
1.1K
J1
RS2
1K
C5
1000pF
R10
1K
CON2
C20
NO STUFF
0.01µF
R2
R3
R14
0
C4
390
390
C21
0.1µF
C19
5V
C3
RS1
1K
10µF
R8
5V
J5
0.01µF
0.1µF
3.57K
TP11
SW3
D2
R20
2
VO1
SNS1 GT1
EN1 EN2
RTR/LTCH
BIAS
VS1
SW1
TP4
SW2
0
FLT1
D3
R17
R16
10K
R30
1K
8
TP7
10K
LED55B/TO
LED55B/TO
27
6
5
UV1
TP12
12
13
11
PG1
FLT1
SS1
C22
CPQ+
CPQ-
U1
ISL6173
0.022µF
GND_OUT
J9
C10
3
OPEN = Disable
CLOSE = Enable
C14
0.033µF
R19
10K
R18
10K
2.2µF
TP3
25
29
16
17
19
23
OCREF
GND1
PG2
TP13
R11
TP17 TP18
14.7K
14
CPVDD
PGND
OPEN = Latch
CLOSE = Retry
GND_IN
J6
C13
FLT2
SS2
UV2
0.47µF
C9
10
9
0.033µF
TP14
R31
1K
GND
CT1
20
VO2
SNS2 GT2
TP9
CT2 VS2
D4
D5
TP8
FLT2
PG2
R32
C11
1.1K
LED55B/TO
LED55B/TO
C12
0.15µF
0.15µF
R15
0
TP16
J2
CON2
TP10
C6
R12 R9
R25
390
R26
390
1000pF
1K 2.55K
NO STUFF
5V
CON2
J3
C18
220µF
Vi_2
J7
TP15
J10
C17
R27
0.01
VO2
47µF
Vi_2
VO2
2.5V
R54
100
D6
MBR130P
M2
IRF7821
FIGURE 20.
Schematic, ISL6173 Eval1 (Continued)
VO1
TP27
1
TP28
1
R64 R63
R38
1
R37
1
R42
1
5
5
R40 R39
R41
5
5
5
TP29
1
TP30
1
TP31
5
6
7
8
5
6
7
8
M3
IRF7821
SW5
M4
IRF7821
4
2
SW4
R33
10
J11
4
1
2
3
R34
10
TP26
1
R59
49.9
4
1
2
3
TP25
1
R55
1K
R49
01
R56
1K
R50
01
U2
5V
1
2
3
4
8
7
6
5
NC1 NC8
IN2 OUTA
GND
V+
IN2_ OUTB
EL7202/SO
VO2
TP19
TP24
1
1
R62 R61 R47 R46 R48
SW7
R44
1
R43
1
R45
1
5
5
5
5
5
TP20
TP23
1
1
TP32
5
6
7
SW6
5
6
7
8
M5
IRF7821
8
M6
IRF7821
4
2
R35
10
J12
4
1
2
3
R36
R60
49.9
4
1
2
3
10
R57
1K
TP22
TP21
1
1
1
1
R58
1K
1
1
R52
01
R51
01
U3
5V
1
2
3
4
8
7
6
5
NC1 NC8
IN2 OUTA
GND
V+
IN2_ OUTB
EL7202/SO
FIGURE 21.
ISL6173 Eval 1 - Component Layout
FIGURE 22.
ISL6173
Quad Flat No-Lead Plas tic Package (QFN)
L28.5x5
Micro Lead Frame Plas tic Package (MLFP)
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)
2X
0.15
C A
MILLIMETERS
D
A
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
9
D/2
A
A1
A2
A3
b
0.80
0.90
-
D1
-
-
0.02
-
D1/2
2X
0.65
9
N
0.15 C
B
6
0.20 REF
9
INDEX
AREA
1
2
3
E1/2
E/2
9
0.18
2.95
2.95
0.25
0.30
3.25
3.25
5,8
D
5.00 BSC
-
E1
E
B
D1
D2
E
4.75 BSC
9
2X
3.10
7,8
0.15 C
B
5.00 BSC
-
2X
TOP VIEW
E1
E2
e
4.75 BSC
9
0.15 C A
3.10
7,8
0
A2
4X
A
/ /
0.10 C
0.08 C
0.50 BSC
-
C
k
0.20
0.50
-
0.60
28
7
-
-
L
0.75
8
SEATING PLANE
A1
A3
SIDE VIEW
9
N
2
5
Nd
Ne
P
3
NX b
0.10 M C A B
4X P
7
3
D2
D2
8
7
-
-
-
0.60
12
9
NX k
(DATUM B)
θ
-
9
2
N
Rev. 1 11/04
4X P
1
NOTES:
(DATUM A)
2
3
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
(Ne-1)Xe
REF.
E2
6
INDEX
AREA
7
8
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
E2/2
NX L
8
N
e
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
9
(Nd-1)Xe
REF.
CORNER
OPTION 4X
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
BOTTOM VIEW
A1
NX b
5
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
C
L
SECTION "C-C"
C
L
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
L
L
10
10
L1
L1
e
e
C
C
TERMINAL TIP
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9186.2
20
February 15, 2005
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