ISL6208CIRZ [INTERSIL]
High Voltage Synchronous Rectified Buck MOSFET Drivers;型号: | ISL6208CIRZ |
厂家: | Intersil |
描述: | High Voltage Synchronous Rectified Buck MOSFET Drivers |
文件: | 总11页 (文件大小:338K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High Voltage Synchronous Rectified Buck MOSFET
Drivers
ISL6208C
Features
The ISL6208C is a high frequency, dual MOSFET driver,
optimized to drive two N-Channel power MOSFETs in a
synchronous-rectified buck converter topology. It is especially
suited for mobile computing applications that require high
efficiency and excellent thermal performance. The driver,
combined with an Intersil multiphase Buck PWM controller,
forms a complete single-stage core-voltage regulator solution
for advanced mobile microprocessors.
• Dual MOSFET drives for synchronous rectified bridge
• Adaptive shoot-through protection
• 0.5Ω on-resistance and 4A sink current capability
• Supports high switching frequency up to 2MHz
- Fast output rise and fall time
- Low propagation delay
• Three-State PWM input for power stage shutdown
• Internal bootstrap Schottky diode
The ISL6208C features 4A typical sinking current for the lower
gate driver. This current is capable of holding the lower
MOSFET gate off during the rising edge of the phase node. This
prevents shoot-through power loss caused by the high dv/dt of
phase voltages. The operating voltage matches the 30V
breakdown voltage of the MOSFETs commonly used in mobile
computer power supplies.
• Low bias supply current (5V, 80µA)
• Diode emulation for enhanced light load efficiency and
pre-biased start-up applications
• VCC POR (Power-On-Reset) feature integrated
• Low three-state shutdown holdoff time (typical 160ns)
• Pin-to-pin compatible with ISL6207
The ISL6208C also features a three-state PWM input that,
working together with Intersil’s multiphase PWM controllers,
will prevent negative voltage output during CPU shutdown. This
feature eliminates a protective Schottky diode usually seen in
microprocessor power systems.
• DFN package
• Pb-Free (RoHS compliant)
MOSFET gates can be efficiently switched up to 2MHz using
the ISL6208C. Each driver is capable of driving a 3000pF load
with propagation delays of 8ns and transition times under
10ns. Bootstrapping is implemented with an internal Schottky
diode. This reduces system cost and complexity, while allowing
the use of higher performance MOSFETs. Adaptive
Applications
• Core voltage supplies for Intel™ and AMD™ mobile
microprocessors
• High frequency low profile DC/DC converters
• High current low output voltage DC/DC converters
• High input voltage DC/DC converters
shoot-through protection is integrated to prevent both
MOSFETs from conducting simultaneously.
A diode emulation feature is integrated in the ISL6208C to
enhance converter efficiency at light load conditions. This
feature also allows for monotonic start-up into pre-biased
outputs. When diode emulation is enabled, the driver will allow
discontinuous conduction mode by detecting when the
inductor current reaches zero and subsequently turning off the
low-side MOSFET gate.
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
• Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for MLFP Packages”
• Technical Brief TB447 “Guidelines for Preventing
Boot-to-Phase Stress on Half-Bridge MOSFET Driver ICs”
November 29, 2012
FN8395.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL6208C
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
(Notes 1, 2, 3)
ISL6208CHRZ
ISL6208CIRZ
NOTES:
8CH
8CI
-10 to +100
-40 to +100
8 Ld 2x2 DFN
8 Ld 2x2 DFN
L8.2x2D
L8.2x2D
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6208C. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL6208C
(8 LD 2x2 DFN)
TOP VIEW
UGATE
8
PHASE
1
2
3
4
BOOT
PWM
7
FCCM
VCC
6
5
LGATE
GND
Pin Description
PIN
SYMBOL
UGATE
BOOT
DESCRIPTION
1
The UGATE pin is the upper gate drive output. Connect to gate of the high-side power N-Channel MOSFET.
2
BOOT is the floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin
and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See “Internal
Bootstrap Diode” on page 9 for guidance in choosing the appropriate capacitor value.
3
PWM
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation. See
“Three-State PWM Input” on page 9 for further details. Connect this pin to the PWM output of the controller.
4
5
6
7
GND
LGATE
VCC
GND is the ground pin for the IC.
LGATE is the lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Connect the VCC pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND.
FCCM
The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. Otherwise,
continuous conduction mode is forced. See “Diode Emulation” on page 9 for more detail.
8
PHASE
Connect the PHASE pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a
return path for the upper gate driver.
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ISL6208C
Block Diagram
VCC
BOOT
FCCM
UGATE
PHASE
SHOOT-
THROUGH
PROTECTION
CONTROL
LOGIC
VCC
PWM
LGATE
GND
10kΩ
THERMAL PAD
FIGURE 1. BLOCK DIAGRAM
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ISL6208C
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Application with 2-Phase Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Diode Emulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Three-State PWM Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Adaptive Shoot-Through Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reducing Phase Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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ISL6208C
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
Thermal Resistance (Typical)
8 Ld 2x2 DFN Package (Notes 5, 6). . . . . .
θ
(°C/W)
89
θ
(°C/W)
24
JA
JC
Input Voltage (V
, V ) . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V
FCCM PWM
BOOT Voltage (V
BOOT To PHASE Voltage (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 33V
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
BOOT-GND
). . . . . . . . . . . . . . . . -0.3V to 7V (DC)
BOOT-PHASE
-0.3V to 9V (<10ns)
PHASE Voltage (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V
GND - 8V (<20ns Pulse Width, 10µJ)
Recommended Operating Conditions
Ambient Temperature Range
UGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . V
- 0.3V (DC) to V
PHASE
- 5V (<20ns Pulse Width, 10µJ) to V
BOOT
BOOT
V
PHASE
LGATE Voltage. . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V (DC) to VCC + 0.3V
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Hi-Temp Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . . +125°C
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
GND - 2.5V (<20ns Pulse Width, 5µJ) to VCC + 0.3V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. The Phase Voltage is capable of withstanding -7V when the BOOT pin is at GND.
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +100°C (Industrial), -10°C to +100°C (Hi-Temp Commercial).
MIN
MAX
PARAMETER
SUPPLY CURRENT
SYMBOL
TEST CONDITIONS
(Note 7) TYP (Note 7) UNITS
V
CC
Bias Supply Current
POR
I
PWM pin floating, V
FCCM
= 5V
-
80
-
µA
VCC
V
Rising
Falling
-
2.40
-
3.40
2.90
500
3.90
V
V
CC
CC
V
-
-
Hysteresis
mV
BOOTSTRAP DIODE
Forward Voltage
PWM INPUT
V
V
= 5V, forward bias current = 2mA
0.50
0.55
0.65
V
F
VCC
Input Current
I
V
V
V
V
V
= 5V
= 0V
-
250
-250
1.00
3.8
-
µA
µA
V
PWM
PWM
-
-
PWM
PWM Three-State Rising Threshold
PWM Three-State Falling Threshold
Three-State Shutdown Hold-off Time
FCCM INPUT
= 5V
0.70
3.5
100
1.30
4.1
250
VCC
VCC
VCC
= 5V
V
t
= 5V, temperature = +25°C
175
ns
TSSHD
FCCM LOW Threshold
FCCM HIGH Threshold
SWITCHING TIME
0.50
-
-
-
V
V
-
2.0
UGATE Rise Time
t
V
V
V
V
= 5V, 3nF load
= 5V, 3nF load
= 5V, 3nF load
= 5V, 3nF load
-
-
-
-
8.0
8.0
8.0
4.0
-
-
-
-
ns
ns
ns
ns
RU
VCC
VCC
VCC
VCC
LGATE Rise Time
t
RL
UGATE Fall Time
t
FU
LGATE Fall Time
t
FL
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ISL6208C
Electrical Specifications Recommended operating conditions, unless otherwise noted. Boldface limits apply over the operating
temperature range, -40°C to +100°C (Industrial), -10°C to +100°C (Hi-Temp Commercial). (Continued)
MIN
MAX
PARAMETER
UGATE Turn-Off Propagation Delay
LGATE Turn-Off Propagation Delay
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
UG/LG Three-State Propagation Delay
Minimum LG ON-TIME in DCM
OUTPUT
SYMBOL
TEST CONDITIONS
= 5V, outputs unloaded
(Note 7) TYP (Note 7) UNITS
t
V
V
V
V
V
-
18
25
-
ns
ns
ns
ns
ns
ns
PDLU
VCC
VCC
VCC
VCC
VCC
t
= 5V, outputs unloaded
= 5V, outputs unloaded
= 5V, outputs unloaded
= 5V, outputs unloaded
-
10
10
-
-
30
30
-
PDLL
t
20
PDHU
t
20
PDHL
t
35
PTS
t
-
400
-
LGMIN
Upper Drive Source Resistance
Upper Driver Source Current
Upper Drive Sink Resistance
Upper Driver Sink Current
Lower Drive Source Resistance
Lower Driver Source Current
Lower Drive Sink Resistance
Lower Driver Sink Current
NOTE:
R
500mA source current
= 2.5V
-
-
-
-
-
-
-
-
1
2.5
Ω
A
Ω
A
Ω
A
Ω
A
U
I
V
2.00
1
-
U
UGATE-PHASE
500mA sink current
= 2.5V
R
2.5
U
I
V
2.00
1
-
2.5
-
U
UGATE-PHASE
500mA source current
= 2.5V
R
L
I
V
2.00
0.5
4.00
L
LGATE
500mA sink current
V = 2.5V
LGATE
R
1.0
-
L
I
L
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Typical Application with 2-Phase Converter
+5V
+5V
V
BAT
VCC
+V
CORE
BOOT
UGATE
+5V
FB
COMP
FCCM
VCC
VSEN
PWM
PHASE
LGATE
DRIVE
ISL6208C
PWM1
PWM2
PGOOD
THERMAL
PAD
FCCM
MAIN
CONTROL
ISEN1
VID
ISEN2
+5V
V
VCC
BAT
BOOT
FS
DACOUT
FCCM
PWM
UGATE
PHASE
GND
DRIVE
ISL6208C
LGATE
THERMAL
PAD
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ISL6208C
Timing Diagram
2.5V
t
PWM
PDHU
t
t
PDLU
TSSHD
t
t
RU
RU
t
t
FU
FU
t
PTS
1V
UGATE
LGATE
t
PTS
1V
t
RL
t
FL
t
TSSHD
t
PDHL
t
PDLL
t
FL
PHASE
Functional Pin Description
Connect the PHASE pin to the source of the upper MOSFET and
the drain of the lower MOSFET. This pin provides a return path for
the upper gate driver.
UGATE
The UGATE pin is the upper gate drive output. Connect to gate of
the high-side power N-Channel MOSFET.
Theory of Operation
BOOT
Designed for speed, the ISL6208C dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one externally
provided PWM signal.
BOOT is the floating bootstrap supply pin for the upper gate drive.
Connect the bootstrap capacitor between this pin and the PHASE
pin. The bootstrap capacitor provides the charge to turn on the
upper MOSFET. See “Internal Bootstrap Diode” on page 9 for
guidance in choosing the appropriate capacitor value.
A rising edge on PWM initiates the turn-off of the lower MOSFET
(see “Timing Diagram”). After a short propagation delay [t
],
PDLL
the lower gate begins to fall. Typical fall times [t ] are provided
FL
PWM
in the “Electrical Specifications” on page 5. Adaptive
shoot-through circuitry monitors the LGATE voltage. When LGATE
has fallen below 1V, UGATE is allowed to turn ON. This prevents
both the lower and upper MOSFETs from conducting
simultaneously, or shoot-through.
The PWM signal is the control input for the driver. The PWM signal
can enter three distinct states during operation. See “Three-State
PWM Input” on page 9 for further details. Connect this pin to the
PWM output of the controller.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
GND
propagation delay (t
) is encountered before the upper gate
GND is the ground pin for the IC.
PDLU
begins to fall (t ). The upper MOSFET gate-to-source voltage is
FU
LGATE
monitored, and the lower gate is allowed to rise after the upper
MOSFET gate-to-source voltage drops below 1V. The lower gate
then rises (t ), turning on the lower MOSFET.
LGATE is the lower gate drive output. Connect to gate of the
low-side power N-Channel MOSFET.
RL
This driver is optimized for converters with large step-down
compared to the upper MOSFET because the lower MOSFET
conducts for a much longer time in a switching period. The lower
gate driver is therefore sized much larger to meet this application
requirement.
VCC
Connect the VCC pin to a +5V bias supply. Place a high quality
bypass capacitor from this pin to GND.
FCCM
The 0.5Ω ON-resistance and 4A sink current capability enables
the lower gate driver to absorb the current injected to the lower
gate through the drain-to-gate capacitor of the lower MOSFET and
prevents a shoot-through caused by the high dv/dt of the phase
node.
The FCCM pin enables or disables Diode Emulation. When FCCM
is LOW, diode emulation is allowed. Otherwise, continuous
conduction mode is forced. See “Diode Emulation” on page 9 for
more detail.
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ISL6208C
Typical Performance Waveforms
FIGURE 2. LOAD TRANSIENT (0A TO 30A, 3-PHASE)
FIGURE 3. LOAD TRANSIENT (30A TO 0A, 3-PHASE)
FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD
FIGURE 7. PRE-BIASED START-UP IN DCM MODE
FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD
FIGURE 6. PRE-BIASED START-UP IN CCM MODE
FN8395.0
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ISL6208C
larger standard value capacitance is 0.15µF. A good quality
ceramic capacitor is recommended.
Diode Emulation
Diode emulation allows for higher converter efficiency under light
load situations. With diode emulation active, the ISL6208C will
detect the zero current crossing of the output inductor and turn
off LGATE. This ensures that discontinuous conduction mode
(DCM) is achieved. Diode emulation is asynchronous to the PWM
signal. Therefore, the ISL6208C will respond to the FCCM input
immediately after it changes state. Refer to“Typical Performance
Waveforms” on page 8. Note: Intersil does not recommend Diode
2.0
1.8
1.6
1.4
1.2
1.0
0.8
Emulation use with r
current sensing topologies. The turn-
DS(ON)
OFF of the low-side MOSFET can cause gross current
measurement inaccuracies.
Q
= 100nC
0.6
0.4
0.2
0.0
GATE
Three-State PWM Input
20nC
A unique feature of the ISL6208C and other Intersil drivers is the
addition of a shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set holdoff
time, the output drivers are disabled and both MOSFET gates are
pulled and held low. The shutdown state is removed when the PWM
signal moves outside the shutdown window. Otherwise, the PWM
rising and falling thresholds outlined in the “Electrical
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ΔV (V)
BOOT_CAP
FIGURE 8. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Power Dissipation
Specifications” table on page 5 determine when the lower and
upper gates are enabled.
Package power dissipation is mainly a function of the switching
frequency and total gate charge of the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation is approximately 800mW. When designing the driver
into an application, it is recommended that the following
calculation be performed to ensure safe operation at the desired
frequency for the selected MOSFETs. The power dissipated by the
driver is approximated, as shown in Equation 2:
Adaptive Shoot-Through
Protection
Both drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is monitored
until it reaches a 1V threshold, at which time the UGATE is released
to rise. Adaptive shoot-through circuitry monitors the upper MOSFET
gate-to-source voltage during UGATE turn-off. Once the upper
MOSFET gate-to-source voltage has dropped below a threshold of
1V, the LGATE is allowed to rise.
P = f (1.5V
Q
+ V Q ) + I
V
VCC
(EQ. 2)
sw
U
L
U
L
CC
where f is the switching frequency of the PWM signal. V and
sw
V represent the upper and lower gate rail voltage. Q and Q is
U
L
U
L
the upper and lower gate charge determined by MOSFET
selection and any external capacitance added to the gate pins.
The lV product is the quiescent power of the driver and is
V
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode. Simply
adding an external capacitor across the BOOT and PHASE pins
completes the bootstrap circuit.
CC CC
typically negligible.
1000
Q
= 50nC
Q
Q
=100nC
= 200nC
U
U
L
Q
Q
= 50nC
= 50nC
U
L
Q
= 100nC
900
800
700
600
500
400
300
200
100
0
L
The bootstrap capacitor must have a maximum voltage rating
above the maximum battery voltage plus 5V. The bootstrap
capacitor can be chosen from Equation 1:
Q
= 20nC
=50nC
U
L
Q
GATE
Q
(EQ. 1)
-----------------------
C
≥
BOOT
ΔV
BOOT
where Q
GATE
charge the gate of the upper MOSFET. The ΔV
is the amount of gate charge required to fully
term is
BOOT
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate charge,
Q
, of 25nC at 5V and also assume the droop in the drive
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (kHz)
GATE
voltage over a PWM cycle is 200mV. One will find that a
bootstrap capacitance of at least 0.125µF is required. The next
FIGURE 9. POWER DISSIPATION vs FREQUENCY
FN8395.0
November 29, 2012
9
ISL6208C
for VCC and GND is also recommended. Decoupling loops
should be short.
Layout Considerations
Reducing Phase Ring
• All power traces (UGATE, PHASE, LGATE, GND, VCC) should be
short and wide, and avoid using vias. If vias must be used, two
or more vias per layer transition is recommended.
The parasitic inductances of the PCB and power devices (both
upper and lower FETs) could cause increased PHASE ringing,
which may lead to voltages that exceed the absolute maximum
rating of the devices. When PHASE rings below ground, the
negative voltage could add charge to the bootstrap capacitor
through the internal bootstrap diode. Under worst-case
conditions, the added charge could overstress the BOOT and/or
PHASE pins. To prevent this from happening, the user should
perform a careful layout inspection to reduce trace inductances,
• Keep the SOURCE of the upper FET as close as thermally
possible to the DRAIN of the lower FET.
• Keep the connection in between the SOURCE of lower FET and
power ground wide and short.
• Input capacitors should be placed as close to the DRAIN of the
upper FET and the SOURCE of the lower FET as thermally
possible.
2
and select low lead inductance MOSFETs and drivers. D PAK and
DPAK packaged MOSFETs have high parasitic lead inductances,
as opposed to SOIC-8. If higher inductance MOSFETs must be
used, a Schottky diode is recommended across the lower
MOSFET to clamp negative PHASE ring.
Note: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal pad of
the DFN to the power ground with multiple vias is recommended.
This heat spreading allows the part to achieve its full thermal
potential.
A good layout would help reduce the ringing on the phase and
gate nodes significantly:
• Avoid using vias for decoupling components where possible,
especially in the BOOT-to-PHASE path. Little or no use of vias
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8395.0
CHANGE
November 29, 2012
Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL6208C
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN8395.0
November 29, 2012
10
ISL6208C
Package Outline Drawing
L8.2x2D
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE (DFN) WITH EXPOSED PAD
Rev 0, 3/11
2.00
6
A
PIN #1
6
B
INDEX AREA
PIN 1
INDEX AREA
8
1
6x 0.50
1.55±0.10
(4X)
0.15
0.22
0.10M C AB
( 8x0.30 )
4
TOP VIEW
0.90±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0 . 2 REF
0.10
C
C
0.90±0.10
BASE PLANE
0 . 00 MIN.
0 . 05 MAX.
SEATING PLANE
0.08
C
SIDE VIEW
DETAIL "X"
( 8x0.20 )
( 8x0.30 )
PACKAGE
OUTLINE
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
( 6x0.50 )
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
1.55
2.00
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
( 8x0.22 )
5.
6.
0.90
2.00
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
TYPICAL RECOMMENDED LAND PATTERN
FN8395.0
November 29, 2012
11
相关型号:
ISL6208CRZ
High Voltage Synchronous Rectified Buck MOSFET Drivers; QFN8, SOIC8; Temp Range: See Datasheet
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ISL6208CRZ-T
High Voltage Synchronous Rectified Buck MOSFET Drivers; QFN8, SOIC8; Temp Range: See Datasheet
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