ISL6310EVAL1_技术文档

ISL6310

®

Data Sheet

October 19, 2005

FN9209.2

Two-Phase Buck PWM Controller with

High Current Integrated MOSFET Drivers

Features

• Integrated Multi-Phase Power Conversion

- 1 or 2 Phase Operation

The ISL6310 is a two-phase PWM control IC with integrated

MOSFET drivers. It provides a precision voltage regulation

system for multiple applications including, but not limited to,

high current low voltage point-of-load converters, embedded

applications and other general purpose low voltage medium

to high current applications. The integration of power

MOSFET drivers into the controller IC marks a departure

from the separate PWM controller and driver configuration of

previous multi-phase product families. By reducing the

number of external parts, this integration allows for a cost

and space saving power management solution.

• Precision Output Voltage Regulation

- Differential Remote Voltage Sensing

- ±0.8% System Accuracy Over Temperature

(for REF=0.6V and 0.9V)

- ±0.5% System Accuracy Over Temperature

(for REF=1.2V and 1.5V)

- Usable for output voltages not exceeding 2.3V

- Adjustable Reference-Voltage Offset

• Precision Channel Current Sharing

- Uses Loss-Less r

Current Sampling

DS(ON)

Output voltage can be programmed using the on-chip DAC

or an external precision reference. A two bit code programs

the DAC reference to one of 4 possible values (0.6V, 0.9V,

1.2V and 1.5V). A unity gain, differential amplifier is provided

for remote voltage sensing, compensating for any potential

difference between remote and local grounds. The output

voltage can also be offset through the use of single external

resistor. An optional droop function is also implemented and

can be disabled for applications having less stringent output

voltage variation requirements or experiencing less severe

step loads.

• Optional Load Line (Droop) Programming

- Uses Loss-Less Inductor DCR Current Sampling

• Variable Gate-Drive Bias - 5V to 12V

• Internal or External Reference Voltage Setting

- On-Chip Adjustable Fixed DAC Reference voltage with

2-bit Logic Input Selects from Four Fixed Reference

Voltages (0.6V, 0.9V, 1.2V, 1.5V)

- Reference can be Changed Dynamically

- Can use an External Voltage Reference

• Overcurrent Protection

• Multi-tiered Overvoltage Protection

- OVP Pin to Drive Optional Crowbar Device

A unique feature of the ISL6310 is the combined use of both

DCR and r

current sensing. Load line voltage

DS(ON)

positioning and overcurrent protection are accomplished

through continuous inductor DCR current sensing, while

• Selectable Operation Frequency up to 1.5MHz per phase

• Digital Soft-Start

• Capable of Start-up in a Pre-Biased Load

• Pb-Free Plus Anneal Available (RoHS Compliant)

r

current sensing is used for accurate channel-current

DS(ON)

balance. Using both methods of current sampling utilizes the

best advantages of each technique.

Protection features of this controller IC include a set of

sophisticated overvoltage and overcurrent protection.

Overvoltage results in the converter turning the lower

MOSFETs ON to clamp the rising output voltage and protect

the load. An OVP output is also provided to drive an optional

crowbar device. The overcurrent protection level is set

through a single external resistor. Other protection features

include protection against an open circuit on the remote

sensing inputs. Combined, these features provide advanced

protection for the output load.

Applications

• High Current DDR/Chipset core voltage regulators

• High Current, Low voltage DC/DC converters

• High Current, Low voltage FPGA/ASIC DC/DC converters

Ordering Information

PART NUMBER*

ISL6310CRZ (Note)

ISL6310IRZ (Note)

ISL6310EVAL1

PART MARKING

ISL6310CRZ

TEMPERATURE (°C)

0 to 70

PACKAGE

32 Ld 5x5 QFN (Pb-free)

PKG. DWG. #

L32.5x5

ISL6310IRZ

-40 to 85

Evaluation Platform

* Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6310

Pinout

ISL6310 (QFN)

TOP VIEW

32 31 30 29 28 27 26 25

REF

OFST

VCC

1

2

3

4

5

6

7

8

24 BOOT1

23

22

PHASE1

OVP

COMP

FB

21 REF1

33

GND

20

19

18

ENLL

VDIFF

RGND

VSEN

PHASE2

BOOT2

17 UGATE2

9

10 11 12 13 14 15 16

FN9209.2

2

October 19, 2005

ISL6310

Block Diagram

ENLL

OCSET

PGOOD

ICOMP DROOP

OVP

ISEN AMP

100µA

OC

0.66V

ISUM

IREF

VCC

POWER-ON

RESET

PVCC

BOOT1

UGATE1

RGND

VSEN

+1V

SOFT-START

AND

FAULT LOGIC

x1

SHOOT-

THROUGH

PROTECTION

GATE

x1

PHASE1

LGATE1

FS

CONTROL

LOGIC

VDIFF

UVP

OVP

0.2V

CLOCK AND

SAWTOOTH

GENERATOR

BOOT2

UGATE2

PWM1

∑

SHOOT-

THROUGH

PROTECTION

GATE

CONTROL

LOGIC

+150mV

x 0.82

PHASE2

LGATE2

REF1

REF0

DAC

PWM2

∑

PHASE 2

DETECT

DAC

2PH

CHANNEL

CURRENT

BALANCE

1

N

REF

FB

E/A

COMP

OFST

∑

OFFSET

CHANNEL

CURRENT

SENSE

ISEN1

ISEN2

GND

FN9209.2

October 19, 2005

3

ISL6310

Typical Application - ISL6310

+12V

FB

COMP

PVCC

BOOT1

VDIFF

VSEN

RGND

UGATE1

PHASE1

ISEN1

+5V

2PH

VCC

LGATE1

OFST

FS

DAC

REF

ISL6310

LOAD

REF1

REF0

+12V

OVP

PGOOD

BOOT2

+12V

GND

UGATE2

PHASE2

ISEN2

ENLL

IREF

DROOP

OCSET

LGATE2

ICOMP

ISUM

FN9209.2

October 19, 2005

4

ISL6310

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

Supply Voltage, PVCC. . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +15V

Thermal Resistance

θ

(°C/W)

35

θ

(°C/W)

5

JA

JC

QFN Package (Notes 1, 2) . . . . . . . . . .

Absolute Boot Voltage, V

. . . . . . . .GND - 0.3V to GND + 36V

BOOT

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

Phase Voltage, V

PHASE

. . . . . . . . GND - 0.3V to 15V (PVCC = 12)

GND - 8V (<400ns, 20µJ) to 24V (<200ns, V

= 12V)

+ 0.3V

BOOT-PHASE

Upper Gate Voltage, V

. . . . V

- 0.3V to V

PHASE

UGATE

BOOT

V

- 3.5V (<100ns Pulse Width, 2µJ) to V

PHASE

Lower Gate Voltage, V

. . . . . . . . GND - 0.3V to PVCC + 0.3V

LGATE

GND - 5V (<100ns Pulse Width, 2µJ) to PVCC+ 0.3V

Input, Output, or I/O Voltage . . . . . . . . . GND - 0.3V to VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . Class I JEDEC STD

Recommended Operating Conditions

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

PVCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .+5V to 12V ±5%

Ambient Temperature (ISL6310CR, ISL6310CRZ) . . . . 0°C to 70°C

Ambient Temperature (ISL6310IR, ISL6310IRZ) . . . .-40°C to 85°C

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified.

PARAMETER

BIAS SUPPLY AND INTERNAL OSCILLATOR

Input Bias Supply Current

TEST CONDITIONS

MIN

TYP

MAX UNITS

I

; ENLL = high

-

15

20

mA

VCC

Gate Drive Bias Current

; ENLL = high, all gate outputs open,

1.5

3.0

PVCC

Fsw = 250kHz

VCC Rising

VCC POR (Power-On Reset) Threshold

PVCC POR (Power-On Reset) Threshold

4.25

3.75

4.25

3.75

-

4.38

3.88

4.38

3.88

1.50

66.6

4.50

4.00

4.50

4.00

-

V

%

VCC Falling

PVCC Rising

PVCC Falling

Oscillator Ramp Amplitude (Note 3)

Maximum Duty Cycle (Note 3)

CONTROL THRESHOLDS

V

PP

-

ENLL Rising Threshold

-

0.66

100

-

V

mV

V

ENLL Hysteresis

COMP Shutdown Threshold

COMP Falling

0.25

0.35

0.5

REFERENCE AND DAC

System Accuracy (DAC = 0.6V, 0.9V)

System Accuracy (DAC = 1.2V, 1.50V)

DAC Input Low Voltage (REF0, REF1)

DAC Input High Voltage (REF0, REF1)

External Reference (Note 3)

DROOP connected to IREF

-0.8

-0.5

-

0.8

0.5

0.4

-

%

V

-

0.8

0.6

47.5

V

-

1.75

52.5

V

OFS Sink Current Accuracy (Negative Offset)

OFS Source Current Accuracy (Positive Offset)

R

= 30kΩ from OFS to VCC

= 10kΩ from OFS to GND

50.0

µA

OFS

FN9209.2

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October 19, 2005

ISL6310

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Specified. (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNITS

ERROR AMPLIFIER

DC Gain (Note 3)

R

C

= 10K to ground

-

96

20

-

dB

MHz

V/µs

V

L

Gain-Bandwidth Product (Note 3)

Slew Rate (Note 3)

= 100pF, R = 10K to ground

L

-

= 100pF, Load = ±400µA

-

3.90

-

8

Maximum Output Voltage

Minimum Output Voltage

REMOTE SENSE DIFFERENTIAL AMPLIFIER

Input bias current (VSEN)

Bandwidth (Note 3)

Load = 1mA

Load = -1mA

4.20

0.85

-

1.0

V

(VSEN = 1.5V)

49

-

55

20

8

60

-

µA

MHz

V/µs

Slew Rate (Note 3)

-

OVERCURRENT PROTECTION

OCSET trip current

93

-5

100

0

107

5

µA

OCSET Accuracy

OC Comparator offset (OCSET and ISUM

Difference)

mV

ICOMP Offset

ISEN Amplifier offset

-5

0

5

mV

PROTECTION

Undervoltage Threshold

Undervoltage Hysteresis

Overvoltage Threshold while IC Disabled

Overvoltage Threshold

VSEN falling

VSEN Rising

80

-

82

3

84

-

%DAC

V

1.62

1.67

1.72

VSEN Rising

DAC +

125mV

DAC +

150mV

DAC +

175mV

V

Overvoltage Hysteresis

VSEN Falling

-

50

-

mV

V

Open Sense-Line Protection Threshold

IREF Rising and Falling

VDIFF VDIFF + VDIFF

+ 0.9V

1V

+ 1.1V

OVP Output High Drive Voltage

SWITCHING TIME

I

= 15mA, VCC = 5V

2.2

3.4

-

V

OVP

UGATE Rise Time (Note 3)

t

V

= 12V, 3nF Load, 10% to 90%

= 12V, 3nF Load, 90% to 10%

-

26

18

12

10

-

ns

RUGATE; PVCC

LGATE Rise Time (Note 3)

V

RLGATE; PVCC

UGATE Fall Time (Note 3)

V

FUGATE; PVCC

LGATE Fall Time (Note 3)

V

FLGATE; PVCC

UGATE Turn-On Non-overlap (Note 3)

LGATE Turn-On Non-overlap (Note 3)

GATE DRIVE RESISTANCE (Note 3)

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

OVER TEMPERATURE SHUTDOWN

Thermal Shutdown Setpoint (Note 3)

Thermal Recovery Setpoint (Note 3)

NOTE:

; V

= 12V, 3nF Load, Adaptive

PDHUGATE PVCC

; V

PDHLGATE PVCC

V

= 12V, 150mA Source Current

1.25

0.9

2.0

1.6

3.0

Ω

PVCC

= 12V, 150mA Sink Current

= 12V, 150mA Source Current

= 12V, 150mA Sink Current

0.85

0.60

1.4

2.2

0.94

1.35

-

160

100

-

°C

3. Parameter magnitude guaranteed by design. Not 100% tested.

FN9209.2

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October 19, 2005

ISL6310

Timing Diagram

t

PDHUGATE

t

FUGATE

RUGATE

UGATE

LGATE

t

RLGATE

FLGATE

t

PDHLGATE

Simplified Power System Diagram

+12V

IN

+5V

IN

Q1

CHANNEL1

2

REF0,REF1

DAC

Q2

ENLL

OVP

V

OUT

PGOOD

Q3

Q4

ISL6310

CHANNEL2

operation. Pulled high, the pin enables the controller for

operation.

Functional Pin Description

VCC (Pin 3)

Bias supply for the IC’s small-signal circuitry. Connect this

pin to a +5V supply and locally decouple using a quality

1.0µF ceramic capacitor.

FS (Pin 29)

A resistor, placed from FS to ground, will set the switching

frequency. Refer to Equation 33 and Figure 24 for proper

resistor calculation.

PVCC (Pin 15)

Power supply pin for the MOSFET drive. This pin can be

connected to any voltage from +5V to +12V, depending on

the desired MOSFET gate drive level.

2PH (Pin 31)

This pin is used to choose between single or two phase

operation. Tying this pin to VCC allows for 2-phase operation.

Tying the 2PH pin to GND causes the controller to operate in

a single phase mode.

GND (Pin 33)

Bias and reference ground for the IC.

REF0 and REF1 (Pins 30, 21)

ENLL (Pin 20)

This pin is a threshold sensitive (approximately 0.66V) enable

input for the controller. Held low, this pin disables controller

These pins make up the 2-bit input that selects the fixed DAC

reference voltage. These pins respond to TTL logic

thresholds. The ISL6310 decodes these inputs to establish

FN9209.2

7

October 19, 2005

ISL6310

one of four fixed reference voltages; see “Table 1” for

correspondence between REF0 and REF1 inputs and

reference voltage settings.

REF (Pin 1)

The REF input pin is the positive input of the error amplifier.

This pin can be connected to the DAC pin using a resistor

(1-5kΩ) when the internal DAC voltage is used as the

reference voltage. When an external voltage reference is used,

it must be connected directly to the REF pin, while the DAC pin

is left unconnected. The output voltage will be regulated to the

voltage at the REF pin unless this voltage is greater than the

voltage at the DAC pin. If an external reference is used at this

pin, its magnitude cannot exceed 1.75V.

These pins are internally pulled high, to approximately 1.2V,

by 40µA (typically) internal current sources; the internal pull-

up current decreases to 0 as the REF0 and REF1 voltages

approach the internal pull-up voltage. Both REF0 and REF1

pins are compatible with external pull-up voltages not

exceeding the IC’s bias voltage (VCC).

VSEN and RGND (Pins 8, 7)

VSEN and RGND are inputs to the precision differential

remote-sense amplifier and should be connected to the sense

pins of the remote load.

A capacitor is used between the REF pin and ground to

smooth the DAC voltage during soft-start.

OFST (Pin 2)

The OFST pin provides a means to program a DC current for

generating an offset voltage across the resistor between FB

and VDIFF. The offset current is generated via an external

resistor and precision internal voltage references. The polarity

of the offset is selected by connecting the resistor to GND or

VCC. For no offset, the OFST pin should be left unconnected.

ICOMP, ISUM, and IREF (Pins 10, 12, 13)

ISUM, IREF, and ICOMP are the DCR current sense

amplifier’s negative input, positive input, and output

respectively. For accurate DCR current sensing, connect a

resistor from each channel’s phase node to ISUM and

connect IREF to the summing point of the output inductors,

roughly VOUT. A parallel R-C feedback circuit connected

between ISUM and ICOMP will then create a voltage from

IREF to ICOMP proportional to the voltage drop across the

inductor DCR. This voltage is referred to as the droop voltage

and is added to the differential remote-sense amplifier’s

output

OCSET (Pin 9)

This is the overcurrent set pin. Placing a resistor from OCSET

to ICOMP, allows a 100µA current to flow out of this pin,

producing a voltage reference. Internal circuitry compares the

voltage at OCSET to the voltage at ISUM, and if ISUM ever

exceeds OCSET, the overcurrent protection activates.

An optional 0.001-0.01µF ceramic capacitor can be placed

from the IREF pin to the ISUM pin to help reduce common

mode noise that might be introduced by the layout.

ISEN1, ISEN2 (Pins 26, 16)

These pins are used for balancing the channel currents by

sensing the current through each channel’s lower MOSFET

when it is conducting. Connect a resistor between the ISEN1

and ISEN2 pins and their respective phase node. This

resistor sets a current proportional to the current in the lower

MOSFET during its conduction interval.

DROOP (Pin 11)

This pin enables or disables droop. Tie this pin to the ICOMP

pin to enable droop. To disable droop, tie this pin to the IREF

pin.

UGATE1 and UGATE2 (Pins 25, 17)

VDIFF (Pin 6)

Connect these pins to the upper MOSFETs’ gates. These

pins are used to control the upper MOSFETs and are

monitored for shoot-through prevention purposes. Maximum

individual channel duty cycle is limited to 66%.

VDIFF is the output of the differential remote-sense amplifier.

The voltage on this pin is equal to the difference between

VSEN and RGND added to the difference between IREF and

ICOMP. VDIFF therefore represents the VOUT voltage plus

the droop voltage.

BOOT1 and BOOT2 (Pins 24,18)

These pins provide the bias voltage for the upper MOSFETs’

drives. Connect these pins to appropriately-chosen external

bootstrap capacitors. Internal bootstrap diodes connected to

the PVCC pins provide the necessary bootstrap charge.

FB and COMP (Pins 5, 4)

The internal error amplifier’s inverting input and output

respectively. FB is connected to VDIFF through an external

R or R-C network depending on the desired type of

compensation (Type II or III). COMP is tied back to FB

through an external R-C network to compensate the

regulator.

PHASE1 and PHASE2 (Pins 23, 19)

Connect these pins to the sources of the upper MOSFETs.

These pins are the return path for the upper MOSFETs’

drives.

DAC (Pin 32)

The DAC pin is the direct output of the internal DAC. This pin

is connected to REF pin using 1-5kΩ resistor, This pin can be

left open if an external reference is used.

LGATE1 and LGATE2 (Pins 27, 14)

These pins are used to control the lower MOSFETs and are

monitored for shoot-through prevention purposes. Connect

these pins to the lower MOSFETs’ gates. Do not use

FN9209.2

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October 19, 2005

ISL6310

external series gate resistors as this might lead to shoot-

through.

PGOOD (Pin 28)

I

+ I

L2

L1

PGOOD is used as an indication of the end of soft-start. It is

an open-drain logic output that is low impedance until the soft-

start is completed and V is equal to the VID setting. Once in

out

I

L2

normal operation PGOOD indicates whether the output

voltage is within specified overvoltage and undervoltage limits.

If the output voltage exceeds these limits or a reset event

occurs (such as an overcurrent event), PGOOD becomes

high impedance again. The potential at this pin should not

exceed that of the potential at VCC pin by more than a typical

forward diode drop at any time

PWM2

I

L1

PWM1

OVP (Pin 22)

Overvoltage protection pin. This pin pulls to VCC when an

overvoltage condition is detected. Connect this pin to the

gate of an SCR or MOSFET tied across V and ground to

prevent damage to a load device.

FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS

FOR 2-PHASE CONVERTER

IN

To understand the reduction of ripple current amplitude in the

multi-phase circuit, examine the equation representing an

individual channel peak-to-peak inductor current.

Operation

Multi-Phase Power Conversion

(V – V

) ⋅ V

IN

OUT

(EQ. 1)

I

= ---------------------------------------------------------

PP

L ⋅ F

⋅ V

SW IN

Modern low voltage DC/DC converter load current profiles

have changed to the point that the advantages of multi-

phase power conversion are impossible to ignore. The

technical challenges associated with producing a single-

phase converter that is both cost-effective and thermally

viable have forced a change to the cost-saving approach of

multi-phase. The ISL6310 controller helps simplify

implementation by integrating vital functions and requiring

minimal external components. The block diagram on page 2

provides a top level view of multi-phase power conversion

using the ISL6310 controller.

In Equation 1, V and V

IN

are the input and output

voltages respectively, L is the single-channel inductor value,

and F is the switching frequency.

OUT

SW

The output capacitors conduct the ripple component of the

inductor current. In the case of multi-phase converters, the

capacitor current is the sum of the ripple currents from each

of the individual channels. Compare Equation 1 to the

expression for the peak-to-peak current after the summation

of N symmetrically phase-shifted inductor currents in

Equation 2. Peak-to-peak ripple current decreases by an

amount proportional to the number of channels. Output

voltage ripple is a function of capacitance, capacitor

equivalent series resistance (ESR), and inductor ripple

current. Reducing the inductor ripple current allows the

designer to use fewer or less costly output capacitors.

Interleaving

The switching of each channel in an ISL6310-based

converter is timed to be symmetrically out of phase with the

other channel. As a result, the two-phase converter has a

combined ripple frequency twice the frequency of one of its

phases. In addition, the peak-to-peak amplitude of the

combined inductor currents is proportionately reduced

(Equations 1 and 2).

(V – N ⋅ V

) ⋅ V

OUT

IN

OUT

(EQ. 2)

I

= -------------------------------------------------------------------

C, PP

L ⋅ F

⋅ V

SW

IN

Another benefit of interleaving is to reduce input ripple

current. Input capacitance is determined in part by the

maximum input ripple current. Multi-phase topologies can

improve overall system cost and size by lowering input ripple

current and allowing the designer to reduce the cost of input

capacitance. The example in Figure 2 illustrates input

currents from a two-phase converter combining to reduce

the total input ripple current.

Increased ripple frequency and lower ripple amplitude

generally translate to lower per-channel inductance and

lower total output capacitance for a given set of performance

specifications. Figure 1 illustrates the additive effect on

output ripple frequency. The two channel currents (I and

L1

I

), combine to form the AC ripple current and the DC load

L2

current. The ripple component has two times the ripple

frequency of each individual channel current.

FN9209.2

9

October 19, 2005

ISL6310

change in state of the PWM signal and turns off the

C

CURRENT

IN

synchronous MOSFET and turns on the upper MOSFET.

The PWM signal will remain high until the pulse termination

signal marks the beginning of the next cycle by triggering the

PWM signal low.

Single phase operation can be selected by connecting 2PH

to GND.

Q1 D-S CURRENT

Channel Current Balance

One important benefit of multi-phase operation is the thermal

advantage gained by distributing the dissipated heat over

multiple devices and greater area. By doing this the designer

avoids the complexity of driving parallel MOSFETs and the

expense of using expensive heat sinks and exotic magnetic

materials.

Q2 D-S CURRENT

FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-

CAPACITOR RMS CURRENT FOR 2-PHASE

CONVERTER

In order to realize the thermal advantage, it is important that

each channel in a multi-phase converter be controlled to

carry about the same amount of current at any load level. To

achieve this, the currents through each channel must be

Figures 25 and 26 in the section entitled Input Capacitor

Selection can be used to determine the input-capacitor RMS

current based on load current, duty cycle, and the number of

channels. They are provided as aids in determining the

optimal input capacitor solution.

sampled every switching cycle. The sampled currents, I ,

n

from each active channel are summed together and divided

by the number of active channels. The resulting cycle

average current, I

, provides a measure of the total load-

AVG

PWM Operation

current demand on the converter during each switching

cycle. Channel current balance is achieved by comparing

the sampled current of each channel to the cycle average

current, and making the proper adjustment to each channel

pulse width based on the error. Intersil’s patented current

balance method is illustrated in Figure 3, with error

The timing of each converter leg is set by the number of

active channels. The default channel setting for the ISL6310

is two. One switching cycle is defined as the time between

the internal PWM1 pulse termination signals. The pulse

termination signal is the internally generated clock signal

that triggers the falling edge of PWM1. The cycle time of the

pulse termination signal is the inverse of the switching

frequency set by the resistor between the FS pin and

ground. Each cycle begins when the clock signal commands

PWM1 to go low. The PWM1 transition signals the internal

channel 1 MOSFET driver to turn off the channel 1 upper

MOSFET and turn on the channel 1 synchronous MOSFET.

In the default channel configuration, the PWM2 pulse

terminates 1/2 of a cycle after the PWM1 pulse.

correction for channel 1 represented. In the figure, the cycle

average current, I

, is compared with the channel 1

AVG

sample, I , to create an error signal I

.

1

ER

The filtered error signal modifies the pulse width

commanded by V to correct any unbalance and force

COMP

I

toward zero. The same method for error signal

ER

correction is applied to each active channel.

+

PWM1

V

COMP

TO GATE

CONTROL

LOGIC

+

-

One switching cycle for the ISL6310 is defined as the time

between consecutive PWM pulse terminations (turn-off of

the upper MOSFET on a channel). Each cycle begins when

a switching clock signal commands the upper MOSFET to

go off. The other channel’s upper MOSFET conduction is

terminated 1/2 of a cycle later.

SAWTOOTH SIGNAL

FILTER f(s)

I

ER

+

I

2

I

AVG

Σ

÷ N

-

Once a PWM pulse transitions low, it is held low for a

minimum of 1/3 cycle. This forced off time is required to

ensure an accurate current sample. Current sensing is

described in the next section. After the forced off time

expires, the PWM output is enabled. The PWM output state

is driven by the position of the error amplifier output signal,

I

1

NOTE: Channel 2 is optional.

FIGURE 3. CHANNEL 1 PWM FUNCTION AND CURRENT-

BALANCE ADJUSTMENT

V

, minus the current correction signal relative to the

COMP

Current Sampling

In order to realize proper current balance, the currents in

each channel must be sampled every switching cycle. This

sampling occurs during the forced off-time, following a PWM

sawtooth ramp as illustrated in Figure 3. When the modified

V

voltage crosses the sawtooth ramp, the PWM output

COMP

transitions high. The internal MOSFET driver detects the

FN9209.2

10

October 19, 2005

ISL6310

transition low. During this time the current sense amplifier

uses the ISEN inputs to reproduce a signal proportional to

The ISL6310 senses the channel load current by sampling

the voltage across the lower MOSFET r , as shown in

Figure 5. A ground-referenced operational amplifier, internal

to the ISL6310, is connected to the PHASE node through a

DS(ON)

the inductor current, I . This sensed current, I

, is simply

L

SEN

a scaled version of the inductor current. The sample window

opens exactly 1/6 of the switching period, t , after the

resistor, R

. The voltage across R

is equivalent to

of the lower MOSFET

SW

ISEN

the voltage drop across the r

ISEN

PWM transitions low. The sample window then stays open

the rest of the switching cycle until PWM transitions high

again, as illustrated in Figure 4.

DS(ON)

while it is conducting. The resulting current into the ISEN pin

is proportional to the channel current, I . The ISEN current is

L

sampled and held as described in the Current Sampling

The sampled current, at the end of the t

, is

SAMPLE

section. From Figure 5, the following equation for I is

n

proportional to the inductor current and is held until the next

switching period sample. The sampled current is used only

for channel current balance.

derived where I is the channel current.

L

r

DS(ON)

----------------------

I

= I

⋅

(EQ. 3)

n

L

R

ISEN

Output Voltage Setting

I

L

The ISL6310 uses a digital to analog converter (DAC) to

generate a reference voltage based on the logic signals at

the REF0 and REF1 pins. The DAC decodes the 2-bit logic

signals into one of the discrete voltages shown in Table 1.

Each REF0 and REF1 pins are pulled up to an internal 1.2V

voltage by weak current sources (40µA current, decreasing

to 0 as the voltage at the REF0, REF1 pins varies from 0 to

the internal 1.2V pull-up voltage). External pull-up resistors

or active-high output stages can augment the pull-up current

sources, up to a voltage of 5V. The DAC pin must be

PWM

SWITCHING PERIOD

I

SEN

SAMPLING PERIOD

connected to REF pin through a 1-5kΩ resistor and a filter

capacitor (0.022µF) is connected between REF and GND.

NEW SAMPLE

CURRENT

OLD SAMPLE

CURRENT

The ISL6310 accommodates the use of external voltage

reference connected to REF pin if a different output voltage

is required. The DAC voltage must be set at least as high as

external reference. The error amp internal noninverting input

is the lower of REF or (DAC +300mV).

TIME

FIGURE 4. SAMPLE AND HOLD TIMING

The ISL6310 supports MOSFET r

current sensing to

sample each channel’s current for channel current balance.

DS(ON)

The internal circuitry, shown in Figure 5 represents channel

n of an N-channel converter. This circuitry is repeated for

each channel in the converter, but may not be active

depending on the status of the 2PH pin, as described in the

PWM Operation section.

A third method for setting the output voltage is to use a

resistor divider (R , R ) from the output terminal (V

)

P1 S1

to VSEN pin to set the output voltage level as shown in

OUT

Figure 6. This method is good for generating voltages up to

2.3V (with the REF voltage set to 1.5V).

For this case, the output voltage can be obtained as follows:

V

IN

(R + R

)

S1

P1

−

+

(EQ. 4)

r

V

= V

⋅ ---------------------------------

V

– V

OFS DROOP

CHANNEL N

DS(ON)

= I x-------------------------

OUT

REF

I

R

SEN

P1

UPPER MOSFET

L

R

ISEN

I

n

It is recommended to choose resistor values of less than

I

L

500Ω for R and R resistors in order to get better output

SAMPLE

&

HOLD

S1

P1

voltage DC accuracy.

ISEN(n)

-

R

TABLE 1. ISL6310 DAC VOLTAGE SELECTION TABLE

ISEN

-

+

REF1

REF0

DAC

I x r

+

L

DS(ON)

0

1

0

1

0

1

0.600V

0.900V

1.200V

1.500V

CHANNEL N

LOWER MOSFET

ISL6310 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

FIGURE 5. ISL6310 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY FOR CURRENT BALANCE

FN9209.2

October 19, 2005

11

ISL6310

The output of the error amplifier, V

, is compared to the

COMP

Voltage Regulation

sawtooth waveform to generate the PWM signals. The PWM

signals control the timing of the Internal MOSFET drivers

and regulate the converter output so that the voltage at FB is

equal to the voltage at REF. This will regulate the output

voltage to be equal to Equation 5. The internal and external

circuitry that controls voltage regulation is illustrated in

Figure 6.

In order to regulate the output voltage to a specified level, the

ISL6310 uses the integrating compensation network shown in

Figure 6. This compensation network insures that the steady

state error in the output voltage is limited only to the error in

the reference voltage (output of the DAC or the external

voltage reference) and offset errors in the OFS current

source, remote sense and error amplifiers. Intersil specifies

the guaranteed tolerance of the ISL6310 to include the

combined tolerances of each of these elements, except when

an external reference or voltage divider is used, then the

tolerances of these components has to be taken into account.

(EQ. 5)

V

= V

± V

– V

OFS DROOP

OUT

REF

Load-Line (Droop) Regulation

In some high current applications, a requirement on a

precisely controlled output impedance is imposed. This

dependence of output voltage on load current is often

termed “droop” or “load line” regulation.

EXTERNAL CIRCUIT

ISL6310 INTERNAL CIRCUIT

R

C

2

1

COMP

DAC

VID DAC

The Droop is an optional feature in the ISL6310. It can be

enabled by connecting ICOMP pin to DROOP pin as shown

in Figure 6. To disable it, connect the DROOP pin to IREF

pin.

REF

+

-

C

REF

FB

V

COMP

As shown in Figure 6, a voltage, V

, proportional to the

, feeds into the

DROOP

+

R

ERROR AMPLIFIER

V

1

total current in all active channels, I

OUT

OFS

+

I

OFS

-

differential remote-sense amplifier. The resulting voltage at

the output of the remote-sense amplifier is the sum of the

output voltage and the droop voltage. As Equation 5 shows,

feeding this voltage into the compensation network causes

the regulator to adjust the output voltage so that it’s equal to

the reference voltage minus the droop voltage.

VDIFF

VSEN

R

S1

+

R

P1

V

OUT

-

RGND

The droop voltage, V

current through the output inductors. This is accomplished

by using a continuous DCR current sensing method.

, is created by sensing the

DROOP

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

DROOP

-

V

DROOP

Inductor windings have a characteristic distributed

resistance or DCR (Direct Current Resistance). For

simplicity, the inductor DCR is considered as a separate

lumped quantity, as shown in Figure 7. The channel current,

IREF

+

ICOMP

ISENSE

C

SUM

AMP

-

I , flowing through the inductor, passes through the DCR.

L

ISUM

Equation 6 shows the s-domain equivalent voltage, V ,

L

across the inductor.

(EQ. 6)

FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE

REGULATION WITH OFFSET ADJUSTMENT

V (s) = I ⋅ (s ⋅ L + DCR)

L

The inductor DCR is important because the voltage dropped

across it is proportional to the channel current. By using a

simple R-C network and a current sense amplifier, as shown

in Figure 7, the voltage drop across all of the inductors DCRs

can be extracted. The output of the current sense amplifier,

The ISL6310 incorporates an internal differential remote

sense amplifier in the feedback path. The amplifier removes

the voltage error encountered when measuring the output

voltage relative to the controller ground reference point,

resulting in a more accurate means of sensing output voltage.

Connect the load’s output sense pins to the non-inverting

input, VSEN, and inverting input, RGND, of the remote sense

V

, can be shown to be proportional to the channel

DROOP

currents I and I , shown in Equation 7.

L1

L2

(EQ. 7)

amplifier. The droop voltage, V

, also feeds into the

s ⋅ L

DROOP







------------- + 1

R



DCR

COMP

remote sense amplifier. The remote sense output, V

therefore equal to the sum of the output voltage, V

, is

DIFF

OUT

------------------------------------------------------------------------- -----------------------

V

(s) =

⋅

⋅ (I + I ) ⋅ DCR

DROOP

L1 L2

(s ⋅ R

⋅ C

+ 1)

R

, and

COMP

S

the droop voltage. V

is connected to the inverting input of

DIFF

the error amplifier through an external resistor.

FN9209.2

12

October 19, 2005

ISL6310

If the R-C network components are selected such that the

R-C time constant matches the inductor L/DCR time

Once the desired output offset voltage has been determined,

use the following formulas to set R

:

OFS

to GND):

constant, then V

is equal to the sum of the voltage

DROOP

For Positive Offset (connect R

OFS

drops across the individual DCRs, multiplied by a gain. As

0.5 ⋅ R

Equation 8 shows, V

total output current, I

is therefore proportional to the

1

DROOP

OUT

(EQ. 9)

R

= --------------------------

OFS

V

.

OFFSET

R

COMP

(EQ. 8)

--------------------

V

=

⋅ I

⋅ DCR

OUT

For Negative Offset (connect R to VCC):

OFS

DROOP

R

S

1.5 ⋅ R

1

R

= --------------------------

(EQ. 10)

OFS

V

-

OFFSET

V (s)

L

I

OUT

L

DCR

VDIFF

PHASE1

V

INDUCTOR

OUT

I

L1

+

OFS

-

R

C

S

OUT

V

R

1

L

VREF

DCR

E/A

PHASE2

ISUM

INDUCTOR

L2

FB

I

R

OFS

S

R

COMP

C

COMP

ICOMP

-

1.5V

DROOP

+

-

V

DROOP

0.5V

C

OFS

SUM

(Optional)

ISL6310

R

OFS

+

IREF

GND

VCC

GND

ISL6310

FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

FIGURE 7. DCR SENSING CONFIGURATION

By simply adjusting the value of R , the load line can be set

S

to any level, giving the converter the right amount of droop at

all load currents. It may also be necessary to compensate for

any changes in DCR due to temperature. These changes

cause the load line to be skewed, and cause the R-C time

constant to not match the L/DCR time constant. If this

becomes a problem a simple negative temperature

VDIFF

-

V

R

OFS

+

1

VREF

E/A

FB

coefficient resistor network can be used in the place of

I

OFS

R

to compensate for the rise in DCR due to

COMP

temperature.

Output Voltage Offset Programming

The ISL6310 allows the designer to accurately adjust the

VCC

offset voltage by connecting a resistor, R

, from the OFS

OFS

pin to VCC or GND. When R

is connected between OFS

OFS

and VCC, the voltage across it is regulated to 1.5V. This

causes a proportional current (I ) to flow into the OFS pin

-

R

OFS

1.5V

+

-

OFS

is connected to ground, the

0.5V

OFS

and out of the FB pin. If R

OFS

ISL6310

voltage across it is regulated to 0.5V, and I

FB pin and out of the OFS pin. The offset current flowing

through the resistor between VDIFF and FB will generate the

desired offset voltage which is equal to the product (I

R ). These functions are shown in Figures 8 and 9.

flows into the

OFS

GND

VCC

FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE

PROGRAMMING

x

OFS

1

FN9209.2

13

October 19, 2005

ISL6310

Advanced Adaptive Zero Shoot-Through Deadtime

1.6

1.4

1.2

1.

Control (Patent Pending)

The integrated drivers incorporate a unique adaptive deadtime

control technique to minimize deadtime, resulting in high

efficiency from the reduced freewheeling time of the lower

MOSFET body-diode conduction, and to prevent the upper and

lower MOSFETs from conducting simultaneously. This is

accomplished by ensuring either rising gate turns on its

MOSFET with minimum and sufficient delay after the other has

turned off.

0.8

0.6

0.4

Q

= 100nC

GATE

During turn-off of the lower MOSFET, the PHASE voltage is

monitored until it reaches a -0.3V/+0.8V trip point for a

forward/reverse current, at which time the UGATE is released

50nC

0.2

0.0

20nC

to rise. An auto-zero comparator is used to correct the r

DS(ON)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

∆V (V)

drop in the phase voltage preventing false detection of the

BOOT_CAP

-0.3V phase level during r

conduction period. In the

DS(ON)

FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

case of zero current, the UGATE is released after 35ns delay of

the LGATE dropping below 0.5V. During the phase detection,

the disturbance of LGATE falling transition on the PHASE node

is blanked out to prevent falsely tripping. Once the PHASE is

high, the advanced adaptive shoot-through circuitry monitors

the PHASE and UGATE voltages during a PWM falling edge

and the subsequent UGATE turn-off. If either the UGATE falls

to less than 1.75V above the PHASE or the PHASE falls to less

than +0.8V, the LGATE is released to turn on.

Gate Drive Voltage Versatility

The ISL6310 provides the user flexibility in choosing the

gate drive voltage for efficiency optimization. The controller

ties the upper and lower drive rails together. Simply applying

a voltage from 5V up to 12V on PVCC sets both gate drive

rail voltages simultaneously.

Internal Bootstrap Device

Initialization

The two integrated drivers feature an internal bootstrap

schottky diode. Simply adding an external capacitor across

the BOOT and PHASE pins completes the bootstrap circuit.

The bootstrap function is also designed to prevent the

bootstrap capacitor from overcharging due to the large

negative swing at the PHASE node. This reduces voltage

stress on the boot to phase pins.

Prior to initialization, proper conditions must exist on the

ENLL, VCC, PVCC and the REF0 and REF1 pins. When the

conditions are met, the controller begins soft-start. Once the

output voltage is within the proper window of operation, the

controller asserts PGOOD.

Enable and Disable

While in shutdown mode, the PWM outputs are held in a

high-impedance state to assure the drivers remain off. The

following input conditions must be met before the ISL6310 is

released from shutdown mode.

The bootstrap capacitor must have a maximum voltage

rating above PVCC + 5V and its capacitance value can be

chosen from the following equation:

Q

GATE

-------------------------------------

C

≥

1. The bias voltage applied at VCC must reach the internal

power-on reset (POR) rising threshold. Once this

threshold is reached, proper operation of all aspects of

the ISL6310 is guaranteed. Hysteresis between the rising

and falling thresholds assure that once enabled, the

ISL6310 will not inadvertently turn off unless the bias

voltage drops substantially (see Electrical

BOOT_CAP

∆V

BOOT_CAP

(EQ. 11)

Q

⋅ PVCC

G1

V

----------------------------------

Q

=

⋅ N

Q1

GATE

GS1

where Q is the amount of gate charge per upper MOSFET

G1

Specifications).

at V

gate-source voltage and N is the number of

Q1

GS1

control MOSFETs. The ∆V

term is defined as the

BOOT_CAP

allowable droop in the rail of the upper gate drive. Figure 10

shows the boot capacitor ripple voltage as a function of boot

capacitor value and total upper MOSFET gate charge.

FN9209.2

14

October 19, 2005

ISL6310

For example, a regulator with 450kHz switching frequency

ISL6310 INTERNAL CIRCUIT

EXTERNAL CIRCUIT

VCC

having REF voltage set to 1.2V has T equal to 3.55ms.

SS

A 100mV offset exists on the remote-sense amplifier at the

beginning of soft-start and ramps to zero during the first 640

cycles of soft-start (704 cycles following enable). This

prevents the large inrush current that would otherwise occur

should the output voltage start out with a slight negative

bias.

PVCC

+12V

POR

CIRCUIT

ENABLE

10.7kΩ

COMPARATOR

During the first 640 cycles of soft-start (704 cycles following

enable) the DAC voltage increments the reference in 25mV

steps. The remainder of soft-start sees the DAC ramping

with 12.5mV steps.

ENLL

+

-

1.40kΩ

0.66V

The ISL6310 also has the ability to start up into a pre-

charged output as shown in Figure 12, without causing any

unnecessary disturbance. The FB pin is monitored during

soft-start, and should it be higher than the equivalent internal

ramping reference voltage, the output drives hold both

MOSFETs off. Once the internal ramping reference exceeds

the FB pin potential, the output drives are enabled, allowing

the output to ramp from the pre-charged level to the final

level dictated by the reference setting. Should the output be

pre-charged to a level exceeding the reference setting, the

output drives are enabled at the end of the soft-start period,

leading to an abrupt correction in the output voltage down to

the “reference set” level.

SOFT-START

AND

FAULT LOGIC

FIGURE 11. POWER SEQUENCING USING THRESHOLD-

SENSITIVE ENABLE (ENLL) FUNCTION

2. The voltage on ENLL must be above 0.66V. The EN input

allows for power sequencing between the controller bias

voltage and another voltage rail. The enable comparator

holds the ISL6310 in shutdown until the voltage at ENLL

rises above 0.66V. The enable comparator has 100mV of

hysteresis to prevent bounce.

3. The driver bias voltage applied at the PVCC pins must

reach the internal power-on reset (POR) rising threshold.

In order for the ISL6310 to begin operation, PVCC is the

only pin that is required to have a voltage applied that

exceeds POR. Hysteresis between the rising and falling

thresholds assure that once enabled, the ISL6310 will not

inadvertently turn off unless the PVCC bias voltage drops

substantially (see Electrical Specifications).

OUTPUT PRECHARGED

ABOVE DAC LEVEL

OUTPUT PRECHARGED

BELOW DAC LEVEL

V

(0.5V/DIV)

GND>

When each of these conditions is true, the controller

immediately begins the soft-start sequence.

OUT

Soft-Start

ENLL (5V/DIV)

During soft-start, the DAC voltage ramps linearly from zero

to the programmed level. The PWM signals remain in the

high-impedance state until the controller detects that the

ramping DAC level has reached the output-voltage level.

This protects the system against the large, negative inductor

currents that would otherwise occur when starting with a pre-

existing charge on the output as the controller attempted to

regulate to zero volts at the beginning of the soft-start cycle.

T1 T2

T3

FIGURE 12. SOFT-START WAVEFORMS FOR ISL6310-BASED

MULTI-PHASE CONVERTER

Fault Monitoring and Protection

The ISL6310 actively monitors output voltage and current to

detect fault conditions. Fault monitors trigger protective

measures to prevent damage to the sensitive load. One

common power good indicator is provided for linking to

external system monitors. The schematic in Figure 13

outlines the interaction between the fault monitors and the

power good signal.

The Output soft-start time, T , begins with a delay period

SS

equal to 64 switching cycles after the ENLL has exceeded its

POR level, followed by a linear ramp with a rate determined

by the switching period, 1/F

.

SW

64 + DAC ⋅ 1280

(EQ. 12)

T

= -------------------------------------------

SS

F

SW

FN9209.2

15

October 19, 2005

ISL6310

successful soft-start, the overvoltage trip level is only REF

plus 150mV. OVP releases 50mV below its trip point if it was

“REF plus 150mV” that tripped it, and releases 100mV below

*Connect DROOP to IREF

to disable the Droop feature

R

OCSET

DROOP*

ICOMP

OCSET

100µA

V

-

OCSET

+

its trip point if it was the fixed voltage, V

, that tripped it.

OVP

IREF

ISUM

Actions are taken by the ISL6310 to protect the load when an

overvoltage condition occurs, until the output voltage falls

back within set limits.

+

ISEN

-

V

DROOP

+

At the inception of an overvoltage event, all LGATE signals

are commanded high, and the PGOOD signal is driven low.

This causes the controller to turn on the lower MOSFETs

and pull the output voltage below a level that might cause

damage to the load. The LGATE outputs remain high until

VDIFF falls to within the overvoltage limits explained above.

The ISL6310 will continue to protect the load in this fashion

as long as the overvoltage condition recurs.

OC

+

-

VDIFF

+1V

DAC + 150mV

Once an overvoltage condition ends the ISL6310 continues

normal operation and PGOOD returns high.

SOFT-START, FAULT

AND CONTROL LOGIC

V

OVP

Pre-POR Overvoltage Protection

Prior to PVCC and VCC exceeding their POR levels, the

ISL6310 is designed to protect the load from any overvoltage

events that may occur. This is accomplished by means of an

internal 10kΩ resistor tied from PHASE to LGATE, which

turns on the lower MOSFET to control the output voltage

until the overvoltage event ceases or the input power supply

cuts off. For complete protection, the low side MOSFET

should have a gate threshold well below the maximum

voltage rating of the load/microprocessor.

-

OV

UV

VSEN

RGND

+

PGOOD

x1

-

+

0.82 x DAC

ISL6310 INTERNAL CIRCUITRY

In the event that during normal operation the PVCC or VCC

voltage falls back below the POR threshold, the pre-POR

overvoltage protection circuitry reactivates to protect from

any more pre-POR overvoltage events

FIGURE 13. POWER GOOD AND PROTECTION CIRCUITRY

Power Good Signal

The power good pin (PGOOD) is an open-drain logic output

that transitions high when the converter is operating after

soft-start. PGOOD pulls low during shutdown and releases

high after a successful soft-start. PGOOD transitions low

when an undervoltage, overvoltage, or overcurrent condition

is detected or when the controller is disabled by a reset from

ENLL or POR. If after an undervoltage or overvoltage event

occurs the output returns to within under and overvoltage

limits, PGOOD will return high.

Open Sense Line Protection

In the case that either of the remote sense lines, VSEN or

GND, become open, the ISL6310 is designed to detect this

and shut down the controller. This event is detected by

monitoring the voltage on the IREF pin, which is a local

version of V

sensed at the outputs of the inductors.

OUT

If VSEN or RGND become opened, VDIFF falls, causing the

duty cycle to increase and the output voltage on IREF to

increase. If the voltage on IREF exceeds “VDIFF+1V”, the

controller will shut down. Once the voltage on IREF falls

below “VDIFF+1V”, the ISL6310 will restart at the beginning

of soft-start.

Undervoltage Detection

The undervoltage threshold is set at 82% of the REF

voltage. When the output voltage (VSEN-RGND) is below

the undervoltage threshold, PGOOD gets pulled low. No

other action is taken by the controller. PGOOD will return

high if the output voltage rises above 85% of the REF

voltage.

Overcurrent Protection

The ISL6310 detects overcurrent events by comparing the

droop voltage, V

, to the OCSET voltage, V , as

DROOP OCSET

Overvoltage Protection

shown in Figure 13. The droop voltage, set by the external

current sensing circuitry, is proportional to the output current

as shown in Equation 8. A constant 100µA flows through

The ISL6310 constantly monitors the difference between the

VSEN and RGND voltages to detect if an overvoltage event

occurs. During soft-start, while the DAC/REF is ramping up,

the overvoltage trip level is the higher of REF plus 150mV or a

R

, creating the OCSET voltage. When the droop

OCSET

voltage exceeds the OCSET voltage, the overcurrent

protection circuitry activates. Since the droop voltage is

fixed voltage, V

. The fixed voltage, V

, is 1.67V. Upon

OVP

FN9209.2

October 19, 2005

16

ISL6310

proportional to the output current, the overcurrent trip level,

the maximum amount of load current. Generally speaking,

I

, can be set by selecting the proper value for R

,

the most economical solutions are those in which each

phase handles between 25 and 30A. All surface-mount

designs will tend toward the lower end of this current range.

If through-hole MOSFETs and inductors can be used, higher

per-phase currents are possible. In cases where board

space is the limiting constraint, current can be pushed as

high as 40A per phase, but these designs require heat sinks

and forced air to cool the MOSFETs, inductors and heat-

dissipating surfaces.

MAX

as shown in Equation 13.

OCSET

I

⋅ R

100µA ⋅ R

⋅ DCR

COMP

MAX

(EQ. 13)

R

= ---------------------------------------------------------

OCSET

S

Once the output current exceeds the overcurrent trip level,

will exceed V , and a comparator will trigger

V

DROOP

OCSET

the converter to begin overcurrent protection procedures. At

the beginning of overcurrent shutdown, the controller turns

off both upper and lower MOSFETs. The system remains in

this state for a period of 4096 switching cycles. If the

controller is still enabled at the end of this wait period, it will

attempt a soft-start (as shown in Figure 14). If the fault

remains, the trip-retry cycles will continue indefinitely until

either the controller is disabled or the fault is cleared. Note

that the energy delivered during trip-retry cycling is much

less than during full-load operation, so there is no thermal

hazard.

MOSFETs

The choice of MOSFETs depends on the current each

MOSFET will be required to conduct, the switching frequency,

the capability of the MOSFETs to dissipate heat, and the

availability and nature of heat sinking and air flow.

Lower MOSFET Power Calculation

The calculation for the approximate power loss in the lower

MOSFET can be simplified, since virtually all of the loss in

the lower MOSFET is due to current conducted through the

channel resistance (r

). In Equation 14, I is the

DS(ON)

M

maximum continuous output current, I is the peak-to-peak

PP

inductor current (see Equation 1), and d is the duty cycle

OUTPUT CURRENT

(V

/V ).

OUT IN

2

I

⋅ (1 – d)

12













I

·

L, PP

(EQ. 14)

M

P

= r

⋅

⋅ (1 – d) + ------------------------------------

-----

N

LOW, 1

DS(ON)

0A

An additional term can be added to the lower-MOSFET loss

equation to account for additional loss accrued during the

dead time when inductor current is flowing through the

lower-MOSFET body diode. This term is dependent on the

OUTPUT VOLTAGE

diode forward voltage at I , V

, the switching

frequency, F , and the length of dead times, t and t , at

M

D(ON)

0V

SW

d1

d2

the beginning and the end of the lower-MOSFET conduction

interval respectively.

FIGURE 14. OVERCURRENT BEHAVIOR IN HICCUP MODE

I

N

I

N

I

M

PP

M

PP















General Design Guide

P

= V

⋅ F

⋅

----- + -------- ⋅ t + ----- –

⋅ t

d2



--------

2

LOW, 2

D(ON)

SW

d1

2

This design guide is intended to provide a high-level

explanation of the steps necessary to create a multi-phase

power converter. It is assumed that the reader is familiar with

many of the basic skills and techniques referenced below. In

addition to this guide, Intersil provides complete reference

designs that include schematics, bills of materials, and example

board layouts for many applications.

(EQ. 15)

The total maximum power dissipated in each lower MOSFET

is approximated by the summation of P and P

.

LOW,2

LOW,1

Upper MOSFET Power Calculation

In addition to r

losses, a large portion of the upper-

DS(ON)

Power Stages

MOSFET losses are due to currents conducted across the

input voltage (V ) during switching. Since a substantially

The first step in designing a multi-phase converter is to

determine the number of phases. This determination

depends heavily on the cost analysis which in turn depends

on system constraints that differ from one design to the next.

Principally, the designer will be concerned with whether

components can be mounted on both sides of the circuit

board, whether through-hole components are permitted, the

total board space available for power-supply circuitry, and

IN

higher portion of the upper-MOSFET losses are dependent

on switching frequency, the power calculation is more

complex. Upper MOSFET losses can be divided into

separate components involving the upper-MOSFET

switching times, the lower-MOSFET body-diode reverse-

recovery charge, Q , and the upper MOSFET r

rr

DS(ON)

conduction loss.

FN9209.2

October 19, 2005

17

ISL6310

When the upper MOSFET turns off, the lower MOSFET does

When designing the ISL6310 into an application, it is

recommended that the following calculation is used to

ensure safe operation at the desired frequency for the

selected MOSFETs. The total gate drive power losses,

not conduct any portion of the inductor current until the

voltage at the phase node falls below ground. Once the

lower MOSFET begins conducting, the current in the upper

MOSFET falls to zero as the current in the lower MOSFET

ramps up to assume the full inductor current. In Equation 16,

P

, due to the gate charge of MOSFETs and the

Qg_TOT

integrated driver’s internal circuitry and their corresponding

average driver current can be estimated with Equations 20

and 21, respectively.

the required time for this commutation is t and the

1

UP,1

approximated associated power loss is P

.

P

= P

+ P

+ I ⋅ VCC

Qg_Q2 Q

(EQ. 20)

t



I

N

I



Qg_TOT

Qg_Q1

1

M

PP



⋅





(EQ. 16)

P

≈ V

⋅

⋅ F

SW

 ---- 

----- + --------

UP,1

IN



2





3

--

P

=

⋅ Q

⋅ PVCC ⋅ F

⋅ N

Q1

Qg_Q1

Qg_Q2

G1

SW

PHASE

2

At turn on, the upper MOSFET begins to conduct and this

transition occurs over a time t . In Equation 17, the

approximate power loss is P

= Q

⋅ PVCC ⋅ F

⋅ N

G2

SW

Q2

PHASE

2

UP,2

.

(EQ. 21)

3





t

I

N













--

=

I

⋅ Q

⋅ N

+ Q

⋅ N



⋅ F

+ I

SW Q

2

M





PP

⋅

DR

G1

G2

Q2

PHASE

(EQ. 17)



Q1

2

P

≈ V

⋅

⋅ F

----

2

----- – --------

UP,2

IN

SW



2

In Equations 20 and 21, P

is the total upper gate drive

is the total lower gate drive power

Qg_Q1

A third component involves the lower MOSFET reverse-

power loss and P

Qg_Q2

recovery charge, Q . Since the inductor current has fully

rr

loss; the gate charge (Q and Q ) is defined at the

G1 G2

commutated to the upper MOSFET before the lower-

particular gate to source drive voltage PVCC in the

corresponding MOSFET data sheet; I is the driver total

MOSFET body diode can recover all of Q , it is conducted

rr

Q

through the upper MOSFET across VIN. The power

quiescent current with no load at both drive outputs; N and

Q1

dissipated as a result is P

.

UP,3

N

are the number of upper and lower MOSFETs per phase,

Q2

(EQ. 18)

P

= V ⋅ Q ⋅ F

IN rr SW

UP,3

respectively; N

is the number of active phases. The

PHASE

I

VCC product is the quiescent power of the controller

Q*

Finally, the resistive part of the upper MOSFET is given in

Equation 19 as P

without capacitive load and is typically 75mW at 300kHz.

.

UP,4

The total gate drive power losses are dissipated among the

resistive components along the transition path and in the

bootstrap diode. The portion of the total power dissipated in

the controller itself is the power dissipated in the upper drive

2

---------

12









I

N

PP

M

(EQ. 19)

P

≈ r

⋅

⋅ d +



-----

UP,4

DS(ON)



path resistance, P

DR_LOW

, the lower drive path resistance,

. The rest of

DR_UP

The total power dissipated by the upper MOSFET at full load

can now be approximated as the summation of the results

from Equations 16, 17, 18 and 19. Since the power

equations depend on MOSFET parameters, choosing the

correct MOSFETs can be an iterative process involving

repetitive solutions to the loss equations for different

MOSFETs and different switching frequencies.

P

, and in the boot strap diode, P

BOOT

the power will be dissipated by the external gate resistors

(R and R ) and the internal gate resistors (R and

G1 G2 GI1

R

) of the MOSFETs. Figures 15 and 16 show the typical

GI2

upper and lower gate drives turn-on transition path. The total

power dissipation in the controller itself, P , can be roughly

DR

estimated as:

Package Power Dissipation

P

= P

+ P

+ (I • VCC)

BOOT Q

DR

DR_UP

Qg_Q1

DR_LOW

When choosing MOSFETs it is important to consider the

amount of power being dissipated in the integrated drivers

located in the controller. Since there are a total of two drivers

in the controller package, the total power dissipated by both

drivers must be less than the maximum allowable power

dissipation for the QFN package.

(EQ. 22)

P

= ---------------------

BOOT

3

P



R

+ R



Qg_Q1

HI1

LO1

---------------------

P

=

-------------------------------------- + ---------------------------------------- ⋅







DR_UP

3

R

+ R

R



HI1

EXT1

LO1 EXT1

Calculating the power dissipation in the drivers for a desired

application is critical to ensure safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of 125°C. The maximum allowable IC power

dissipation for the 5x5 QFN package is approximately 4W at

room temperature. See Layout Considerations paragraph for

thermal transfer improvement suggestions.

P

R

LO2









Qg_Q2

---------------------

HI2

P

-------------------------------------- + --------------------------------------- ⋅



DR_LOW

2

R

+ R

R

+ R

EXT2



HI2

EXT2

LO2

R

N

R

N

GI1

GI2

R

= R

+ -------------

R

= R

+ -------------

EXT1

G1

EXT2

G2

Q1

Q2

FN9209.2

October 19, 2005

18

ISL6310

In certain circumstances, it may be necessary to adjust the

PVCC

BOOT

value of one or more ISEN resistors. When the components of

one or more channels are inhibited from effectively dissipating

their heat so that the affected channels run hotter than

D

C

GD

R

HI1

G

desired, choose new, smaller values of R

for the affected

UGATE

ISEN

C

DS

phases (see the section entitled Channel Current Balance).

Choose R in proportion to the desired decrease in

R

LO1

R

GI1

C

G1

ISEN,2

GS

Q1

temperature rise in order to cause proportionally less current

to flow in the hotter phase.

S

PHASE

∆T

2

(EQ. 24)

----------

R

= R

⋅

ISEN,2

ISEN

FIGURE 15. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

1

In Equation 24, make sure that ∆T is the desired temperature

PVCC

2

rise above the ambient temperature, and ∆T is the measured

1

D

temperature rise above the ambient temperature. While a

single adjustment according to Equation 24 is usually

C

GD

R

HI2

G

sufficient, it may occasionally be necessary to adjust R

two or more times to achieve optimal thermal balance

between all channels.

ISEN

LGATE

C

DS

R

LO2

R

GI2

C

G2

GS

Q2

Load Line Regulation Component Selection (DCR

Current Sensing)

S

For accurate load line regulation, the ISL6310 senses the

total output current by detecting the voltage across the

output inductor DCR of each channel (As described in the

Load Line Regulation section). As Figure 18 illustrates, an

R-C network is required to accurately sense the inductor

DCR voltage and convert this information into a “droop”

voltage, which is proportional to the total output current.

FIGURE 16. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Current Balancing Component Selection

The ISL6310 senses the channel load current by sampling

the voltage across the lower MOSFET r

, as shown in

DS(ON)

Figure 17. The ISEN pins are denoted ISEN1, and ISEN2.

The resistors connected between these pins and the

respective phase nodes determine the gains in the channel

current balance loop.

Choosing the components for this current sense network is a

two step process. First, R

and C

must be

COMP

COMP COMP

chosen so that the time constant of this R

-C

network matches the time constant of the inductor L/DCR.

V

IN

Then the resistor R must be chosen to set the current

S

CHANNEL N

UPPER MOSFET

sense network gain, obtaining the desired full load droop

voltage. Follow the steps below to choose the component

values for this R-C network.

I

L

1. Choose an arbitrary value for C

. The recommended

COMP

ISEN(n)

value is 0.01µF.

R

2. Plug the inductor L and DCR component values, and the

ISEN

values for C

chosen in steps 1, into Equation 25 to

COMP

-

calculate the value for R

.

COMP

ISL6310

I x r

L

DS(ON)

L

+

(EQ. 25)

---------------------------------------

=

R

COMP

CHANNEL N

LOWER MOSFET

DCR ⋅ C

COMP

3. Use the new value for R

COMP

obtained from Equation 25,

FIGURE 17. ISL6310 INTERNAL AND EXTERNAL CURRENT-

SENSING CIRCUITRY

as well as the desired full load current, I , full load droop

FL

voltage, V

, and inductor DCR in Equation 26 to

DROOP

Select values for these resistors based on the room

calculate the value for R .

S

I

temperature r

of the lower MOSFETs; the full-load

DS(ON)

FL

(EQ. 26)

------------------------

R

=

⋅ R

⋅ DCR

COMP

S

operating current, I ; and the number of phases, N using

FL

V

DROOP

Equation 23.

r

I

FL

DS(ON)

⋅

(EQ. 23)

----------------------- -------

R

=

ISEN

–

N

6

50 ⋅ 10

FN9209.2

19

October 19, 2005

ISL6310

-

V (s)

L

I

OUT

L

DCR

PHASE1

PHASE2

V

INDUCTOR

L1

OUT

∆V

2

I

∆V

1

R

C

S

OUT

L

V

OUT

DCR

INDUCTOR

L2

R

S

I

TRAN

∆I

ISUM

R

C

COMP

-

FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR

ICOMP

Compensation

DROOP

V

DROOP

The two opposing goals of compensating the voltage

regulator are stability and speed. Depending on whether the

regulator employs the optional load-line regulation as

described in Load-Line Regulation, there are two distinct

methods for achieving these goals.

+

IREF

ISL6310

Compensating the Load-Line Regulated Converter

FIGURE 18. DCR SENSING CONFIGURATION

The load-line regulated converter behaves in a similar

manner to a peak current mode controller because the two

poles at the output filter L-C resonant frequency split with the

introduction of current information into the control loop. The

final location of these poles is determined by the system

function, the gain of the current signal, and the value of the

Due to errors in the inductance or DCR it may be necessary

to adjust the value of R to match the time constants

COMP

correctly. The effects of time constant mismatch can be seen

in the form of droop overshoot or undershoot during the

initial load transient spike, as shown in Figure 19. Follow the

steps below to ensure the R-C and inductor L/DCR time

constants are matched accurately.

compensation components, R and C .

2

1

C

(OPTIONAL)

2

1. Capture a transient event with the oscilloscope set to

about L/DCR/2 (sec/div). For example, with L = 1µH and

DCR = 1mΩ, set the oscilloscope to 500µs/div.

C

1

R

2

COMP

FB

2. Record ∆V and ∆V as shown in Figure 19.

1

2

3. Select a new value, R

, for the time constant

COMP,2

resistor based on the original value, R

following equation.

, using the

COMP,1

ISL6310

R

1

∆V

1

(EQ. 27)

----------

R

= R

⋅

VDIFF

COMP, 2

COMP, 1

2

4. Replace R

with the new value and check to see that

COMP

the error is corrected. Repeat the procedure if necessary.

FIGURE 20. COMPENSATION CONFIGURATION FOR

LOAD-LINE REGULATED ISL6310 CIRCUIT

After choosing a new value for R

, it will most likely be

COMP

necessary to adjust the value of R to obtain the desired full

S

Since the system poles and zero are affected by the values

of the components that are meant to compensate them, the

solution to the system equation becomes fairly complicated.

Fortunately, there is a simple approximation that comes very

close to an optimal solution. Treating the system as though it

were a voltage-mode regulator, by compensating the L-C

poles and the ESR zero of the voltage mode approximation,

load droop voltage. Use Equation 26 to obtain the new value

for R .

S

FN9209.2

20

October 19, 2005

ISL6310

yields a solution that is always stable with very close to ideal

transient performance.

The optional capacitor C , is sometimes needed to bypass

2

noise away from the PWM comparator (see Figure 20). Keep

a position available for C , and be prepared to install a high

2

The feedback resistor, R₁, has already been chosen as

frequency capacitor of between 22pF and 150pF in case any

leading edge jitter problem is noted.

outlined in Load-Line Regulation Resistor. Select a target

bandwidth for the compensated system, F . The target

0

Compensating the Converter operating without

Load-Line Regulation

The ISL6310 multi-phase converter operating without load

line regulation behaves in a similar manner to a voltage-

mode controller. This section highlights the design

consideration for a voltage-mode controller requiring external

compensation. To address a broad range of applications, a

type-3 feedback network is recommended (see Figure 21).

bandwidth must be large enough to assure adequate

transient performance, but smaller than 1/3 of the per-

channel switching frequency. The values of the

compensation components depend on the relationships of f

0

to the L-C pole frequency and the ESR zero frequency. For

each of the following three, there is a separate set of

equations for the compensation components.

1

--------------------------- > F

Case 1:

Case 2:

Case 3:

0

2π ⋅ L ⋅ C

C

2

2π ⋅ F ⋅ V

⋅

L ⋅ C

0

OSC

-----------------------------------------------------------

R

C

= R

⋅

2

1

0.66 ⋅ V

IN

C

R

1

2

COMP

FB

0.66 ⋅ V

IN

= ------------------------------------------------

2π ⋅ V

⋅ R ⋅ f

OSC

1

0

C

3

R

1

ISL6310

---------------------------

≤ F < ---------------------------------

R

0

3

VDIFF

2π ⋅ C ⋅ ESR

2π ⋅ L ⋅ C

2

V

⋅ (2π) ⋅ F ⋅ L ⋅ C

0

OSC

---------------------------------------------------------------

R

C

= R

⋅

(EQ. 28)

2

1

0.66 ⋅ V

IN

FIGURE 21. COMPENSATION CONFIGURATION FOR

NON-LOAD-LINE REGULATED ISL6310 CIRCUIT

0.66 ⋅ V

IN

= -------------------------------------------------------------------------------

(2π) ⋅ F ⋅ V

2

⋅ R

1

⋅

L ⋅ C

0

OSC

Figure 22 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, applicable, with a

small number of adjustments, to the multi-phase ISL6310

1

F

> ---------------------------------

0

2π ⋅ C ⋅ ESR

circuit. The output voltage (V

) is regulated to the

OUT

2π ⋅ F ⋅ V

⋅ L

OSC

0

reference voltage, VREF, level. The error amplifier output

(COMP pin voltage) is compared with the oscillator (OSC)

modified saw-tooth wave to provide a pulse-width modulated

-----------------------------------------------

R

C

= R

⋅

2

1

0.66 ⋅ V ⋅ ESR

IN

0.66 ⋅ V ⋅ ESR ⋅

C

IN

= --------------------------------------------------------------

2π ⋅ V ⋅ R ⋅ F

wave with an amplitude of V at the PHASE node. The

IN

⋅

L

OSC

1

0

PWM wave is smoothed by the output filter (L and C). The

output filter capacitor bank’s equivalent series resistance is

represented by the series resistor ESR.

In Equations 28, L is the per-channel filter inductance

divided by the number of active channels; C is the sum total

of all output capacitors; ESR is the equivalent series

The modulator transfer function is the small-signal transfer

function of V

/V

. This function is dominated by a

V /V , and shaped by the

OUT COMP

resistance of the bulk output filter capacitance; and V

is

OSC

DC gain, given by d

MAX IN OSC

the peak-to-peak sawtooth signal amplitude as described in

output filter, with a double pole break frequency at F and a

zero at F . For the purpose of this analysis, L and DCR

CE

LC

the Electrical Specifications.

Once selected, the compensation values in Equations 28

assure a stable converter with reasonable transient

performance. In most cases, transient performance can be

represent the individual channel inductance and its DCR

divided by 2 (equivalent parallel value of the two output

inductors), while C and ESR represents the total output

capacitance and its equivalent series resistance.

improved by making adjustments to R . Slowly increase the

2

value of R while observing the transient performance on an

2

1

F

= ---------------------------

F

= ---------------------------------

oscilloscope until no further improvement is noted. Normally,

LC

CE

2π ⋅ C ⋅ ESR

2π ⋅ L ⋅ C

C will not need adjustment. Keep the value of C from

1

Equations 28 unless some performance issue is noted.

FN9209.2

21

October 19, 2005

ISL6310

2. Calculate C such that F is placed at a fraction of the F

,

1

Z1 LC

C

2

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

LC

desired number). The higher the quality factor of the output

filter and/or the higher the ratio F /F , the lower the F

CE LC

Z1

C

R

3

R

frequency (to maximize phase boost at F ).

LC

C

2

1

COMP

1

C

= ----------------------------------------------

-

1

2π ⋅ R ⋅ 0.5 ⋅ F

2

LC

R

FB

1

+

E/A

3. Calculate C such that F is placed at F .

P1 CE

2

C

VREF

1

C

= -------------------------------------------------------

2

2π ⋅ R ⋅ C ⋅ F – 1

2

1

CE

VDIFF

4. Calculate R such that F is placed at F . Calculate C

3

Z2

LC

3

-

RGND

VSEN

such that F is placed below F

(typically, 0.5 to 1.0

P2

SW

+

times F ). F

SW SW

represents the per-channel switching

frequency. Change the numerical factor to reflect desired

placement of this pole. Placement of F lower in frequency

P2

V

OSCILLATOR

helps reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at the

COMP pin and minimizing resultant duty cycle jitter.

OUT

V

IN

V

OSC

PWM

CIRCUIT

R

1

R

= ---------------------

3

F

L

SW

DCR

C

------------ – 1

UGATE

PHASE

LC

HALF-BRIDGE

DRIVE

1

C

= ------------------------------------------------

3

2π ⋅ R ⋅ 0.7 ⋅ F

3

SW

ESR

It is recommended that a mathematical model is used to plot

the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

LGATE

ISL6310

EXTERNAL CIRCUIT

frequency response of the modulator (G

), feedback

MOD

FIGURE 22. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

compensation (G ) and closed-loop response (G ):

FB

CL

d

⋅ V

1 + s(f) ⋅ ESR ⋅ C

MAX

V

IN

⋅

The compensation network consists of the error amplifier

(internal to the ISL6310) and the external R -R , C -C

----------------------------- -----------------------------------------------------------------------------------------------------------

G

(f) =

MOD

2

OSC

1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C

1

3

1

3

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

1 + s(f) ⋅ R ⋅ C

2

1

----------------------------------------------------

G

⋅

FB

s(f) ⋅ R ⋅ (C + C )

1

2

frequency (F ; typically 0.1 to 0.3 of F ) and adequate

0

SW

1 + s(f) ⋅ (R + R ) ⋅ C

3

phase margin (better than 45 degrees). Phase margin is the

difference between the closed loop phase at F and 180°.

1

3

-------------------------------------------------------------------------------------------------------------------------

C

⋅ C

2

0dB

The equations that follow relate the compensation network’s













1

--------------------

(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R

⋅



3

2

C

+ C



1

2

poles, zeros and gain to the components (R , R , R , C , C ,

1

2

3

1

2

G

(f) = G

(f) ⋅ G (f)

MOD FB

where, s(f) = 2π ⋅ f ⋅ j

and C ) in Figures 20 and 21. Use the following guidelines for

3

CL

locating the poles and zeros of the compensation network:

COMPENSATION BREAK FREQUENCY EQUATIONS

1. Select a value for R (1kΩ to 5kΩ, typically). Calculate

1

value for R for desired converter bandwidth (F ). If

1

2

0

F

= --------------------------------------------

F

= ------------------------------

P1

Z1

C

⋅ C

2

setting the output voltage to be equal to the reference set

voltage as shown in Figure 22, the design procedure can

be followed as presented. However, when setting the

output voltage via a resistor divider placed at the input of

the differential amplifier (as shown in Figure 6), in order

to compensate for the attenuation introduced by the

2π ⋅ R ⋅ C

1

--------------------

⋅

2π ⋅ R

2

C

+ C

1

2

1

3

F

= -------------------------------------------------

F

= ------------------------------

Z2

P2

2π ⋅ (R + R ) ⋅ C

2π ⋅ R ⋅ C

3

1

3

Figure 23 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

error amplifier gain bounds the compensation gain. Check the

resistor divider, the obtained R value needs be

2

multiplied by a factor of (R +R )/R . The remainder

P1 S1 P1

of the calculations remain unchanged, as long as the

compensated R value is used.

2

V

⋅ R ⋅ F

OSC

1 0

R

= ---------------------------------------------

2

d

⋅ V ⋅ F

MAX

IN LC

compensation gain at F against the capabilities of the error

P2

FN9209.2

October 19, 2005

22

ISL6310

amplifier. The closed loop gain, G , is constructed on the

CL

initially deviate by an amount approximated by the voltage

log-log graph of Figure 23 by adding the modulator gain,

drop across the ESL. As the load current increases, the

voltage drop across the ESR increases linearly until the load

current reaches its final value. The capacitors selected must

have sufficiently low ESL and ESR so that the total output-

voltage deviation is less than the allowable maximum.

Neglecting the contribution of inductor current and regulator

response, the output voltage initially deviates by an amount

G

(in dB), to the feedback compensation gain, G (in

MOD

FB

dB). This is equivalent to multiplying the modulator transfer

function and the compensation transfer function and then

plotting the resulting gain.

MODULATOR GAIN

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

F

Z1 Z2

P1

P2

di

(EQ. 29)

----

∆V ≈ (ESL) ⋅ + (ESR) ⋅ ∆I

dt

The filter capacitor must have sufficiently low ESL and ESR

so that ∆V < ∆V

.

MAX

R2

-------





Most capacitor solutions rely on a mixture of high frequency

capacitors with relatively low capacitance in combination

with bulk capacitors having high capacitance but limited

high-frequency performance. Minimizing the ESL of the

high-frequency capacitors allows them to support the output

voltage as the current increases. Minimizing the ESR of the

bulk capacitors allows them to supply the increased current

with less output voltage deviation.

20log

d

⋅ V





R1

MAX

V

IN

20log---------------------------------

0

OSC

G

FB

G

CL

G

MOD

FREQUENCY

LOG

F

0

LC

CE

FIGURE 23. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

The ESR of the bulk capacitors also creates the majority of

the output-voltage ripple. As the bulk capacitors sink and

source the inductor ac ripple current (see Interleaving and

Equation 2), a voltage develops across the bulk capacitor

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin. The mathematical model

presented makes a number of approximations and is

generally not accurate at frequencies approaching or

exceeding half the switching frequency. When designing

compensation networks, select target crossover frequencies

in the range of 10% to 30% of the per-channel switching

ESR equal to I

(ESR). Thus, once the output capacitors

C,PP

are selected, the maximum allowable ripple voltage,

V

, determines the lower limit on the inductance.

PP(MAX)





⋅

V

– N ⋅ V

V

OUT



IN

OUT



(EQ. 30)

L

(ESR)

≥

-------------------------------------------------------------------

F

⋅ V ⋅ V

SW

IN

PP(MAX)

frequency, F

.

SW

Since the capacitors are supplying a decreasing portion of

the load current while the regulator recovers from the

transient, the capacitor voltage becomes slightly depleted.

The output inductors must be capable of assuming the entire

load current before the output voltage decreases more than

Output Filter Design

The output inductors and the output capacitor bank together

to form a low-pass filter responsible for smoothing the

pulsating voltage at the phase nodes. The output filter also

must provide the transient energy until the regulator can

respond. Because it has a low bandwidth compared to the

switching frequency, the output filter limits the system

transient response. The output capacitors must supply or

sink load current while the current in the output inductors

increases or decreases to meet the demand.

∆V

. This places an upper limit on inductance.

MAX

Equation 31 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater

output-voltage deviation than the leading edge. Equation 32

addresses the leading edge. Normally, the trailing edge

dictates the selection of L because duty cycles are usually

less than 50%. Nevertheless, both inequalities should be

evaluated, and L should be selected based on the lower of

the two results. In each equation, L is the per-channel

inductance, C is the total output capacitance, and N is the

number of active channels.

In high-speed converters, the output capacitor bank is usually

the most costly (and often the largest) part of the circuit.

Output filter design begins with minimizing the cost of this part

of the circuit. The critical load parameters in choosing the

output capacitors are the maximum size of the load step, ∆I,

the load-current slew rate, di/dt, and the maximum allowable

output-voltage deviation under transient loading, ∆V

Capacitors are characterized according to their capacitance,

ESR, and ESL (equivalent series inductance).

2 ⋅ N ⋅ C ⋅ V

O

(EQ. 31)

---------------------------------

2

L ≤

⋅ ∆V

– (∆I ⋅ ESR)

MAX

.

(

)

∆I

MAX

(

)

1.25 ⋅ N ⋅ C

(EQ. 32)







---------------------------------

2

L ≤

⋅ ∆V

– (∆I ⋅ ESR) ⋅ V – V

MAX

IN

O



(

)

∆I

At the beginning of the load transient, the output capacitors

supply all of the transient current. The output voltage will

FN9209.2

23

October 19, 2005

ISL6310

falling edge voltage spikes. The spikes result from the high

Switching Frequency

current slew rate produced by the upper MOSFET turn on and

off. Place them as close as possible to each upper MOSFET

drain to minimize board parasitics and maximize suppression.

There are a number of variables to consider when choosing

the switching frequency, as there are considerable effects on

the upper MOSFET loss calculation. These effects are

outlined in MOSFETs, and they establish the upper limit for

the switching frequency. The lower limit is established by the

requirement for fast transient response and small output-

voltage ripple as outlined in Output Filter Design. Choose the

lowest switching frequency that allows the regulator to meet

the transient-response requirements.

0.3

0.2

0.1

Switching frequency is determined by the selection of the

frequency-setting resistor, R . Figure 24 and Equation 33

FS

are provided to assist in selecting the correct value for R

.

FS

[

]

)

10.61 – 1.035 ⋅ log(F

(EQ. 33)

I

= 0

= 0.5 I

= 0.75 I

SW

L,PP

R

= 10

FS

O

0

0.2

0.4

0.6

IN/

0.8

1.0

DUTY CYCLE (V

V

)

O

200

100

50

FIGURE 25. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR 2-PHASE CONVERTER

0.6

0.4

0.2

20

10

100K

500K

1M

2M

200K

SWITCHING FREQUENCY (Hz)

FIGURE 24. R vs SWITCHING FREQUENCY

FS

I

= 0

= 0.5 I

= 0.75 I

L,PP

O

Input Capacitor Selection

The input capacitors are responsible for sourcing the AC

component of the input current flowing into the upper

MOSFETs. Their RMS current capacity must be sufficient to

handle the ac component of the current drawn by the upper

MOSFETs which is related to duty cycle and the number of

active phases.

0

0.2

0.4

0.6

IN

0.8

1.0

DUTY CYCLE (V /V

)

O

FIGURE 26. NORMALIZED INPUT-CAPACITOR RMS

CURRENT FOR SINGLE-PHASE CONVERTER

For a Two-phase design, use Figure 25 to determine the

input-capacitor RMS current requirement set by the duty

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

cycle, maximum sustained output current (I ), and the ratio

O

of the peak-to-peak inductor current (I

) to I . Select a

L,PP

O

bulk capacitor with a ripple current rating which will minimize

the total number of input capacitors required to support the

RMS current calculated. The voltage rating of the capacitors

should also be at least 1.25 times greater than the maximum

input voltage. Figure 26 provides the same input RMS

current information for single-phase designs. Use the same

approach for selecting the bulk capacitor type and number.

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turnoff

transition of the upper PWM MOSFET. Prior to turnoff, the

upper MOSFET was carrying channel current. During the

turnoff, current stops flowing in the upper MOSFET and is

picked up by the lower MOSFET. Any inductance in the

Low ESL, high-frequency ceramic capacitors are needed in

addition to the input bulk capacitors to suppress leading and

FN9209.2

24

October 19, 2005

ISL6310

switched current path generates a large voltage spike during

The critical small components include the bypass capacitors

for VCC and PVCC. Locate the bypass capacitors, CBP,

close to the device. It is especially important to locate the

components associated with the feedback circuit close to

their respective controller pins, since they belong to a high-

impedance circuit loop, sensitive to EMI pick-up. It is also

important to place current sense components close to their

respective pins on the ISL6310, including the RISEN

resistors, RS, RCOMP, CCOMP. For proper current sharing

route two separate symmetrical as possible traces from the

corresponding phase node for each RISEN.

the switching interval. Careful component selection, tight

layout of the critical components, and short, wide circuit

traces minimize the magnitude of voltage spikes.

There are two sets of critical components in a DC/DC

converter using a ISL6310 controller. The power-

components are the most critical because they switch large

amounts of energy. Next are small signal components that

connect to sensitive nodes or supply critical bypassing

current and signal coupling.

It is important to have a symmetrical layout, preferably with

the controller equidistantly located from the two power trains it

controls. Equally important are the gate drive lines (UGATE,

LGATE, PHASE): since they drive the power train MOSFETs

using short, high current pulses, it is important to size them as

large and as short as possible to reduce their overall

impedance and inductance. Extra care should be given to the

LGATE traces in particular since keeping the impedance and

inductance of these traces helps to significantly reduce the

possibility of shoot-through. Equidistant placement of the

controller to the two power trains also helps keeping these

traces equally short (equal impedances, resulting in similar

driving of both sets of MOSFETs).

A multi-layer printed circuit board is recommended. Figure 27

shows the connections of the critical components for the

converter. Note that capacitors C

xxIN

and C could each

xxOUT

represent numerous physical capacitors. Dedicate one solid

layer, usually the one underneath the component side of the

board, for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. Keep the metal runs from

the PHASE terminal to inductor L

OUT

short. The power plane

should support the input power and output power nodes. Use

copper filled polygons on the top and bottom circuit layers for

the phase nodes. Use the remaining printed circuit layers for

small signal wiring. The wiring traces from the IC to the

MOSFETs’ gates and sources should be sized to carry at least

one ampere of current (0.02” to 0.05”).

The power components should be placed first. Locate the input

capacitors close to the power switches. Minimize the length of

the connections between the input capacitors, C , and the

IN

power switches. Locate the output inductors and output

capacitors between the MOSFETs and the load. Locate the

high-frequency decoupling capacitors (ceramic) as close as

practicable to the decoupling target, making use of the shortest

connection paths to any internal planes, such as vias to GND

immediately next, or even onto the capacitor solder pad.

FN9209.2

25

October 19, 2005

ISL6310

LOCATE CLOSE TO IC

(MINIMIZE CONNECTION PATH)

KEY

R

1

HEAVY TRACE ON CIRCUIT PLANE LAYER

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

C

2

+12V

R

C

2

1

C

HF01

FB

COMP

VDIFF

PVCC

BOOT1

C

BIN1

C

HF1

LOCATE NEAR SWITCHING TRANSISTORS;

(MINIMIZE CONNECTION PATH)

C

BOOT1

VSEN

RGND

UGATE1

PHASE1

ISEN1

+5V

L

OUT1

2PH

VCC

R

ISEN1

C

HF0

LGATE1

R

OFST

FS

R

FS

DAC

REF

ISL6310

R

REF

C

(C

)

HFOUT

BOUT

C

REF

LOAD

REF1

REF0

+12V

to PVCC

OVP

PGOOD

C

BIN2

LOCATE NEAR LOAD;

(MINIMIZE CONNECTION PATH)

C

HF2

BOOT2

+12V

GND

C

BOOT2

UGATE2

PHASE2

ISEN2

L

ENLL

IREF

OUT2

R

ISEN2

DROOP

OCSET ICOMP

LGATE2

ISUM

R

C

S

COMP

R

OCSET

R

S

COMP

C

SUM

FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

FN9209.2

26

October 19, 2005

ISL6310

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L32.5x5

32LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.18

2.95

0.23

0.30

3.25

5, 8

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

3.10

7, 8

5.00 BSC

-

E1

E2

e

4.75 BSC

9

3.10

7, 8

0.50 BSC

-

k

0.25

0.30

-

L

0.40

0.50

0.15

8

L1

N

-

32

8

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9209.2

27

October 19, 2005


型号：	ISL6310EVAL1
厂家：	Intersil
描述：	Two-Phase Buck PWM Controller with High Current Intergrated MOSFET Driver 两相降压PWM控制器，具有高电流综合型MOSFET驱动器驱动器控制器
文件：	总27页 (文件大小：707K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6310EVAL1 [INTERSIL]

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