ISL6353IRTZ_技术文档

Multiphase PWM Regulator for VR12 DDR Memory

Systems

ISL6353

Features

The ISL6353 is a three-phase PWM buck regulator controller for

VR12 DDR memory applications. The multi-phase implementation

results in better system performance, superior thermal

• VR12 Serial Communications Bus

• Precision Voltage Regulation

- 5mV Steps with VID Fast/Slow Slew Rates

• Supports Two Current Sensing Methods

- Lossless Inductor DCR Current Sensing

- Precision Resistor Current Sensing

management, lower component cost and smaller PCB area.

The ISL6353 has two integrated power MOSFET drivers for

implementing a cost effective and space saving power

management solution.

• Programmable 1, 2 or 3-Phase Operation

• Adaptive Body Diode Conduction Time Reduction

• Superior Noise Immunity and Transient Response

• Pin Programmable Output Voltage and Power State Mode

The PWM modulator of the ISL6353 is based on Intersil’s Robust

Ripple Regulator™ (R ) technology. Compared with the traditional

multi-phase buck regulator, the R modulator commands variable

PWM switching frequency during load transients, achieving faster

transient response. R also naturally goes into pulse frequency

modulation operation in light load conditions to achieve higher light

load efficiency.

3

• Output Current Monitor and Thermal Monitor

• Differential Remote Voltage Sensing

• High Efficiency Across Entire Load Range

• Programmable Switching Frequency

The ISL6353 is designed to be completely compliant with VR12

specifications. The ISL6353 has a serial VID (SVID) bus

communicating with the CPU. The output can be programmed for

1-, 2- or 3-phase interleaved operation. The output voltage and

power state can also be controlled independent of the serial VID

bus.

• Resistor Programmable VBOOT, Power State Operation, SVID

Address Setting, I

MAX

• Excellent Dynamic Current Balance Between Phases

• OCP/WOC, OVP, OT Alert, PGOOD

The ISL6353 has several other key features. It supports DCR

current sensing with a single NTC thermistor for DCR

temperature compensation or accurate resistor current sensing.

It also has remote voltage sense, adjustable switching frequency,

current monitor, OC/OV protection and power-good. Temperature

monitor and thermal alert is available too.

• Small Footprint 40 Ld 5x5 TQFN Package

• Pb-Free (RoHS Compliant)

Applications

• DDR Memory

95

1.5V PS0

COMP

200mV/DIV

1.5V PS1 2ph CCM

94

93

92

91

90

89

88

87

86

85

1.5V PS2 1ph DE

1.35VPS0

VDDQ = 1.5V

50mV/DIV

PHASE1/2/3

5V/DIV

1.35V PS1 2ph CCM

1.35VPS2 1ph DE

26A STEP LOAD

1V/DIV

0

10

20

30

40

50

60

70

80

20µs/DIV

LOAD (A)

FIGURE 2. ISL6353EVAL1Z EFFICIENCY vs LOAD

FIGURE 1. FAST TRANSIENT RESPONSE

FN6897.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

September 15, 2011

ISL6353

Simplified Application Circuit Using Inductor DCR Current Sensing

VIN

+5V_DUAL

VIN (5VSB/12V DUAL)

ADDR

PROG2

BOOT1

PROG1

NTC

UG1

PH1

RNTC

°C

PH1

VO1

SDA

ALERT#

SCLK

LG1

{

µP

GND

+12V

VW

COMP

FB

BOOT2

UG2

PH2

VDDQ

PH2

VO2

ISL6353

LG2

VCCSENSE

VSSSENSE

VSEN

RTN

FB2

GND

+5V

+12V

BOOT

UGATE

VCTRL

VCC

PHASE

ISL6596

ISEN1

ISEN2

ISEN3

GND

DRIVER

PWM

LGATE

PWM3

PH3

VO3

VSET1

VSET2

PSI

VSUMN

VO1

ISUMN

VO2

VO3

°C

ISUMP

IMON

September 15, 2011

FN6897.0

2

ISL6353

Block Diagram

VR_ON

PSI

VREADY

PROG

POWER-ON RESET

(POR)

VDD

A/D

T_MONITOR

IMON

SDA

ALERT#

SCLK

DIGITAL

INTERFACE

ISEN1

ISEN2

ISEN3

VSET1

VSET2

DAC

D/A

IBAL

PHASE CURRENT

BALANCE

ADDR

IMAX

VBOOT

TMAX

PROG1

PROG2

PROG

DROOP

VIN

# OF PHASES FOR PS1

SET (A/D)

BOOT2

T_MONITOR

DRIVER

UG2

PH2

NTC

TEMP MONITOR

VR_HOT#

VW

DAC

+

DRIVER

LG2

RTN

FB2

?

+

GND

E/A

R³

PWM3

MODULATOR

-

FB

BOOT1

UG1

COMP

DRIVER

PH1

DROOP

VDDP

CURRENT

SENSE

ISUMP

ISUMN

+

-

LG1

DRIVER

OC AND WOC

PROTECTION

GND

IMON

PGOOD

OV PROTECTION

VSEN

OVP

September 15, 2011

FN6897.0

3

ISL6353

Pin Configuration

ISL6353

(40 LD TQFN)

TOP VIEW

40 39 38 37 36 35 34 33 32 31

SDA

1

2

3

4

5

6

7

8

9

30 LG2

ALERT#

SCLK

29 VDDP

28 PWM3

27

26

25

24

23

22

VR_ON

PGOOD

IMON

LG1

GND

(BOTTOM PAD)

PH1

VR_HOT#

NTC

UG1

BOOT1

PROG1

VW

COMP 10

21 VIN

11 12 13 14 15 16 17 18 19 20

Pin Descriptions

PIN NUMBER

SYMBOL

DESCRIPTION

1, 2, 3

SDA, ALERT#, SCLK Serial communication bus signals connected between the CPU and the voltage regulator.

4

5

VR_ON

PGOOD

Voltage regulator enable input. A high level logic signal on this pin enables the VR.

Open-drain output to indicate the regulator is ready to supply regulated voltage. Use an appropriate external pull-up

resistor.

6

IMON

Output current monitor pin. IMON sources a current proportional to the regulator output current. A resistor

connected from this pin to ground will set a voltage that is proportional to the load current. This voltage is sampled

with an internal ADC to produce a digital IMON signal that can be read through the serial communications bus.

7

8

9

VR_HOT#

NTC

Thermal overload output indicator.

Thermistor input to the VR_HOT# circuit.

VW

Window voltage set pin used to set the switching frequency. A resistor from this pin to COMP programs the

switching frequency (18kΩ gives approximately 300kHz).

10

11

12

COMP

FB

This pin is the output of the error amplifier.

This pin is the inverting input of the error amplifier.

FB2

This pin switches in an RC network from VOUT to FB in PS1 and PS2 modes to help improve transient performance

and phase margin when dropping phases in low power states. There is a switch between the FB2 pin and the FB

pin. The switch is off in the PS0 state and on in the PS1 and PS2 states. If this function is not needed, the pin can

be left open.

13

14

ISEN3

ISEN2

Individual current sensing input for Phase 3. Leave this pin open when ISL6353 is configured in 2-phase mode.

Individual current sensing input for Phase 2. When ISEN2 is pulled to 5V VDD, the controller will disable Phase 2,

and the controller will run in 1-phase mode.

15

16

ISEN1

VSEN

Individual current sensing input for Phase 1.

Output voltage sense pin. Connect to the output voltage (typically VDDQ) at the desired remote voltage sensing

location.

September 15, 2011

FN6897.0

4

ISL6353

Pin Descriptions(Continued)

PIN NUMBER

SYMBOL

DESCRIPTION

17

18, 19

20

RTN

Output voltage sense return pin. Connect to the ground at desired remote sensing location.

ISUMN and ISUMP Inverting and non-inverting input of the transconductance amplifier for current monitoring and OCP.

VDD

VIN

5V bias power.

21

Input supply voltage, used for input supply feed-forward compensation.

22

PROG1

BOOT1

The program pin for the voltage regulator I

setting. Refer to Table 6.

MAX

23

Connect an MLCC capacitor across the BOOT1 and the PH1 pins. The boot capacitor is charged through an internal

switch connected from the VDDP pin to the BOOT1 pin.

24

25

26

27

28

29

30

31

32

33

34

35

36

UG1

PH1

Output of the Phase 1 high-side MOSFET gate driver. Connect the UG1 pin to the gate of the Phase 1 high-side

MOSFET.

Current return path for the Phase 1 high-side MOSFET gate driver. Connect the PH1 pin to the node consisting of

the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 1.

GND

This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the

controller or to the exposed pad on the back of the IC using a low impedance path.

LG1

Output of the Phase 1 low-side MOSFET gate driver. Connect the LG1 pin to the gate of the Phase 1 low-side

MOSFET.

PWM3

VDDP

LG2

PWM output for Phase 3. When PWM3 is pulled to 5V VDD, the controller will disable Phase 3 and allow other

phases to operate.

Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF using an

MLCC capacitor to the ground plane close to the IC.

Output of the Phase 2 low-side MOSFET gate driver. Connect the LG2 pin to the gate of the Phase 2 low-side

MOSFET.

GND

This is an electrical ground connection for the IC. Connect this pin to the ground plane of the PCB right next to the

controller or to the exposed pad on the back of the IC using a low impedance path.

PH2

Current return path for the Phase 2 high-side MOSFET gate driver. Connect the PH2 pin to the node consisting of

the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of Phase 2.

UG2

Output of the Phase 2 high-side MOSFET gate driver. Connect the UG2 pin to the gate of the Phase 2 high-side

MOSFET.

BOOT2

PROG2

PSI

Connect an MLCC capacitor across the BOOT2 and the PH2 pins. The boot capacitor is charged through an internal

switch connected from the VDDP pin to the BOOT2 pin.

The program pin for the voltage regulator V

for PS1 mode.

voltage, droop enable/disable and the number of active phases

BOOT

This pin can be used to set the power state of the controller with external logic signals. By connecting this pin to

ground, the controller will refer only to the power state indicated by the serial communication bus register. If the

pin is connected to a high impedance, the controller will enter the PS1 state. If the pin is connected to a logic high,

the controller will enter the PS2 state.

37

38

VSET2

VSET1

This pin is a logic input that can be used in conjunction with VSET1 to program the output voltage of the regulator

with external logic signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to

the VID setting indicated by the serial communication bus register.

This pin is a logic input that can be used in conjunction with VSET2 to program the output voltage of the regulator

with external signals. Refer to Table 9. By connecting VSET1 and VSET2 to ground, the controller will refer to the

VID setting indicated by the serial communication bus register.

39

40

-

OVP

An inverter output, latched high for an overvoltage event. It is reset by POR.

This pin sets the address offset register, range from 0 to 13 (0h to Dh).

ADDR

GND (Bottom Pad) Electrical ground of the IC. Unless otherwise stated, all signals are referenced to the GND pin. Connect this ground

pad to the ground plane through a low impedance path. Recommend use of at least 5 vias to connect to ground

planes in PCB internal layers.

September 15, 2011

5

FN6897.0

ISL6353

Ordering Information

PART NUMBER

PART

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

(Notes 1, 2, 3)

MARKING

ISL6353CRTZ

ISL6353 CRTZ

0 to +70

40 Ld 5x5 TQFN

L40.5x5

ISL6353IRTZ

ISL6353EVAL1Z

NOTES:

ISL6353 IRTZ

-40 to +85

Evaluation Board

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6353. For more information on MSL please see techbrief TB363.

September 15, 2011

6

FN6897.0

ISL6353

Table of Contents

Simplified Application Circuit Using Inductor DCR Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Gate Driver Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Multiphase R3 Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Diode Emulation and Period Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Voltage Regulation and Differential Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

VID Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

VID OFFSET Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Inductor DCR Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Resistor Current-Sensing Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Current Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Phase Current Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

CCM Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Phase Count Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Dynamic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

FB2 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Adaptive Body Diode Conduction Time Reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

System Parameter Programming PROG1/2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SVID ADDRESS Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

External Control of VOUT and Power State VSET1/2, PSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Supported Serial VID Data And Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

September 15, 2011

7

FN6897.0

ISL6353

Absolute Maximum Ratings

Thermal Information

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

Input Supply Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V

Boot Voltage (BOOT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V

Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)

Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)

UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . PHASE - 0.3V (DC) to BOOT

. . . . . . . . . . . . . . . . . . . . . . .PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT

LGATE Voltage (LGATE). . . . . . . . . . . . . . . . . . . . . . -0.3V (DC) to VDD + 0.3V

. . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V

All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD +0.3V)

Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V

ESD Rating

Thermal Resistance (Typical)

40 Ld TQFN Package (Notes 4, 5) . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

_JA(°C/W)

32

θ

_JC(°C/W)

3

Recommended Operating Conditions

Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%

Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 25V

Ambient Temperature

ISL6353CRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

ISL6353IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Junction Temperature

ISL6353CRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +125°C

ISL6353IRTZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . 2000V

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V

Charged Device Model (Tested per JESD22-C101A) . . . . . . . . . . . 750V

Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C for ISL6353CRTZ and T = -40°C to +85°C for ISL6353IRTZ,

DD

A

f

= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range.

SW

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6) TYP (Note 6) UNITS

INPUT POWER SUPPLY

+5V Supply Current

I

VR_ON = 1V

VR_ON = 0V

4

4.6

1

mA

µA

V

VDD

Input Supply Current

I

1

VIN

Power-On-Reset Threshold

POR

V

rising

4.35

4.15

4.00

3.50

4.5

r

f

r

f

DD

falling

4.00

2.8

V

VIN pin rising

VIN pin falling

4.35

+0.5

V

SYSTEM AND REFERENCES

System Accuracy

CRTZ

%Error (V

No load; closed loop, active mode range

) VID = 0.75V to 1.50V,

-0.5

%

CC_CORE

VID = 0.5V to 0.7375V

VID = 0.3V to 0.4875V

-8

8

mV

%

-15

-0.8

15

0.8

IRTZ

No load; closed loop, active mode range

) VID = 0.75V to 1.50V,

%Error (V

CC_CORE

VID = 0.5V to 0.7375V

VID = 0.3V to 0.4875V

-10

-18

10

18

mV

V

Maximum Output Voltage + Offset

Minimum Output Voltage

V

VID = FFh

OFFSET = 7Fh

1.520+

0.635 =

2.155

CC_CORE(max)

V

VID = 01h

0.25

V

CC_CORE(min)

OFFSET = 00h

September 15, 2011

FN6897.0

8

ISL6353

Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C for ISL6353CRTZ and T = -40°C to +85°C for ISL6353IRTZ,

DD

A

f

= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range. (Continued)

SW

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 6) TYP (Note 6) UNITS

CHANNEL FREQUENCY

Nominal Channel Frequency

Adjustment Range

f

R

= 18kΩ, 3-channel operation, V = 1V

COMP

280

200

300

320

500

kHz

SW(nom)

FSET

AMPLIFIERS

Current-Sense Amplifier Input Offset

Error Amp DC Gain

I

= 0A

-0.1

+0.1

mV

dB

FB

A

119

17

v0

GBW

Error Amp Gain-Bandwidth Product

ISEN1/2/3

C = 20pF

MHz

L

Input Bias Current

20

0.26

7

nA

POWER GOOD AND PROTECTION MONITORS

PGOOD Low Voltage

V

I

= 4mA

PGOOD

0.4

1

V

OL

PGOOD Leakage Current

ALERT# Pull-Down Resistance

ALERT# Leakage Current

VR_HOT# Pull-Down Resistance

VR_HOT# Leakage Current

GATE DRIVER

I

PGOOD = 3.3V

-1

µA

Ω

OH

13

1

µA

Ω

7

13

1

µA

UGATE Pull-Up Resistance

UGATE Source Current

UGATE Sink Resistance

UGATE Sink Current

R

200mA Source Current

UGATE - PHASE = 2.5V

1.0

2.0

1.0

2.0

1.0

2.0

0.5

4.0

23

1.5

0.9

Ω

A

UGPU

I

UGSRC

R

250mA Sink Current

Ω

A

UGPD

I

UGATE - PHASE = 2.5V

UGSNK

LGATE Pull-Up Resistance

LGATE Source Current

R

250mA Source Current

LGATE - GND = 2.5V

Ω

A

LGPU

I

LGSRC

LGATE Sink Resistance

LGATE Sink Current

R

250mA Sink Current

Ω

A

LGPD

I

LGATE - GND = 2.5V

LGSNK

UGATE to LGATE Deadtime

LGATE to UGATE Deadtime

PROTECTION FUNCTIONS

Pre-Charge Overvoltage Threshold

Overvoltage Threshold

OVP Pin Sink Current

t

UGATE falling to LGATE rising, no load

LGATE falling to UGATE rising, no load

ns

UGFLGR

LGFUGR

28

OV

VSEN rising above setpoint for >1ms

2.29

145

20

2.35

175

V

P

200

mV

mA

µA

H

I

V

= VDD - 1V

OVP

Overcurrent Threshold

CRTZ

IRTZ

CRTZ

IRTZ

CRTZ

IRTZ

CRTZ

IRTZ

3/2/1-Phase Config, PS0

56.5

54.5

38.3

37

60

40

20

30

64.5

43.2

22.25

33

3-Phase Config, PS1 - Drop to 2-Phase

3-Phase Config, PS1/2 - Drop to 1-Phase

2-Phase Config, PS1/2 - Drop to 1-Phase

19

18.5

28

27

33

September 15, 2011

FN6897.0

9

ISL6353

Electrical Specifications Operating Conditions: V = 5V, T = 0°C to +70°C for ISL6353CRTZ and T = -40°C to +85°C for ISL6353IRTZ,

DD

A

f

= 300kHz, unless otherwise noted. Boldface limits apply over the operating temperature range. (Continued)

SW

MIN

MAX

PARAMETER

SYMBOL

CRTZ

IRTZ

TEST CONDITIONS

3/2/1-Phase Config, PS0

(Note 6) TYP (Note 6) UNITS

Way Overcurrent Threshold

76.8

74

88

60

32

46

20

100

68

µA

mV

3/2/1-Phase Config, PS0

CRTZ

IRTZ

3-Phase Config, PS1 - Drop to 2-Phase

3-Phase Config, PS1/2 - Drop to 1-Phase

2-Phase Config, PS1/2 - Drop to 1-Phase

One ISEN above another ISEN for >1.2ms

52

50

68

CRTZ

IRTZ

28

35.8

52

27

CRTZ

IRTZ

40

39.5

52

Current Imbalance Threshold

PWM

PWM3 Output Low

PWM3 Output High

PWM3 Tri-State Leakage

THERMAL MONITOR

NTC Source Current

V

Sinking 5mA

Sourcing 5mA

PWM3 = 2.5V

1.0

V

OL_MAX

V

3.5

OH_MIN

2

µA

CRTZ

IRTZ

NTC = 1.3V

Falling

58

56

60

62

µA

V

60

VR_HOT# Trip Voltage

VR_HOT# Reset Voltage

ALERT# Trip Voltage

ALERT# Reset Voltage

CURRENT MONITOR

IMON Output Current

0.895

0.91

0.95

0.93

0.97

Rising

0.965

0.985

V

Falling

0.915

V

Rising

V

I

ISUM- pin current = 50µA

ISUM- pin current = 2µA

Rising

12.3

400

12.45

500

12.6

600

µA

nA

V

IMON

IccMAX Alert Trip Voltage

IccMAX Alert Reset Voltage

INPUTS

V

1.2

1.225

IMONMAX

Falling

1.05

1.14

V

VR_ON Input Low

V

0.3

V

IL_MAX

VR_ON Input High

V

0.8

-1

IH_MIN

VR_ON

VR_ON Leakage Current

I

VR_ON = 0V

0

µA

V

VR_ON = 1V, 300kΩ Typical Pull-Down

3.3

VSET1/2 Input Low

VSET1/2 Input High

PSI Sink/Source Current

PSI Pin State

VSET

1.5

IL_MAX

3.1

12

V

IH_MIN

PSI Voltage

16

20

0.51

3.91

5

µA

V

PS0, V = 5V

DD

0

PS1, V = 5V

DD

1.06

4.47

2.12

V

PS2, V = 5V

DD

V

PSI High-Z Voltage

SCLK, SDA

2.37

2.60

V

SCLK, SDA Leakage

VR_ON = 0V, SCLK & SDA = 0V & 1V

VR_ON = 1V, SCLK & SDA = 1V

VR_ON = 1V, SDA = 0V

-1

-5

1

µA

20

40

VR_ON = 1V, SCLK = 0V

NOTE:

6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

September 15, 2011

FN6897.0

10

ISL6353

Gate Driver Timing Diagram

PWM

t

LGFUGR

t

FU

t

RU

1V

UGATE

LGATE

1V

t

RL

t

FL

t

UGFLGR

Theory of Operation

Multiphase R Modulator

VW

3

HYSTERETIC

WINDOW

V_crm

COMP

MASTER CLOCK CIRCUIT

VW

MASTER

CLOCK

Clock1

Clock2

Clock3

COMP

Vcrm

MASTER

CLOCK

Phase

Sequencer

MASTER

CLOCK

gmVo

Crm

CLOCK1

PWM1

SLAVE CIRCUIT 1

L1

I_L1

Phase1

Clock1

PWM1

Vo

S

R

VW

Q

CLOCK2

PWM2

Co

Vcrs1

gm

Crs1

Crs2

Crs3

CLOCK3

PWM3

SLAVE CIRCUIT 2

L2

I_L2

Phase2

PWM2

Clock2

S

R

VW

Q

VW

Vcrs2

gm

V_crs2

V_crs3

V_crs1

SLAVE CIRCUIT 3

L3

I_L3

Phase3

PWM3

Clock3

S

R

VW

Q

3

FIGURE 4. R MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

Vcrs3

gm

3

FIGURE 3. R MODULATOR CIRCUIT

September 15, 2011

FN6897.0

11

ISL6353

voltage V hits VW, the slave circuit turns off the PWM pulse,

Crs

VW

and the current source discharges C .

rs

Since the ISL6353 individual phase modulators use a

large-amplitude and noise-free synthesized signal, V , to

crs

COMP

determine the pulse width, phase jitter is lower than conventional

hysteretic mode and fixed PWM mode controllers. Unlike

conventional hysteretic mode converters, the ISL6353 has an

error amplifier that allows the controller to maintain 0.5% output

voltage accuracy.

Vcrm

Master

Clock

Clock1

PWM1

Figure 5 shows the principle of operation during a load step-up

response. The COMP voltage rises after the load step up,

Clock2

PWM2

generating master clock pulses more quickly, so PWM pulses

turn on earlier, increasing the effective switching frequency. This

allows for higher control loop bandwidth than conventional fixed

frequency PWM controllers. The VW voltage rises as the COMP

voltage rises, making the PWM pulses wider as well. During load

step-down response, COMP voltage falls. It takes the master

clock circuit longer to generate the next clock signal, so the PWM

pulse is held off until needed. The VW voltage falls as the COMP

voltage falls, reducing the current PWM pulse width. This kind of

behavior gives the ISL6353 excellent load transient response.

Clock3

PWM3

VW

Vcrs1

Vcrs3

Vcrs2

The fact that all the phases share the same VW window voltage

also ensures excellent dynamic current balance among phases.

3

FIGURE 5. R MODULATOR OPERATION DURING A LOAD

STEP-UP RESPONSE

Diode Emulation and Period Stretching

The ISL6353 is a multiphase regulator controller implementing

the Intel VR12™ protocol primarily intended for use in DDR

memory regulator applications. It can be programmed for 1-, 2- or

P H A S E

3

3-phase operation. It uses Intersil’s patented R (Robust Ripple

3

Regulator™) modulator. The R modulator combines the best

U G A TE

LG A TE

features of fixed frequency PWM and hysteretic PWM while

eliminating many of their respective shortcomings. Figure 3

3

conceptually shows the ISL6353 multiphase R modulator circuit,

and Figure 4 shows the principle of operation.

A current source flows from the VW pin to the COMP pin, creating

a voltage window set by the resistor between the two pins. This

voltage window is called the VW window in the following

discussion.

IL

FIGURE 6. DIODE EMULATION OPERATION

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator discharges

ISL6353 can operate in diode emulation (DE) mode to improve

light load efficiency. In DE mode, the low-side MOSFET conducts

when the current is flowing from source to drain and does not

allow reverse current, thus emulating a diode. As Figure 6 shows,

when LGATE is on, the low-side MOSFET carries current, creating

negative voltage on the phase node due to the voltage drop across

the ON-resistance. The ISL6353 monitors the current by

monitoring the phase node voltage. It turns off LGATE when the

phase node voltage reaches zero to prevent the inductor current

from reversing direction and creating unnecessary power loss.

the ripple capacitor C with a current source equal to g V , where

rm

m o

g

is a gain factor. The C voltage V

is a sawtooth waveform

m

rm crm

traversing between the VW and COMP voltages. It resets to VW

when it hits COMP, and generates a one-shot master clock signal. A

phase sequencer distributes the master clock signal to the slave

circuits. If the ISL6353 is in 3-phase mode, the master clock signal

will be distributed to the three phases, and the Clock1~3 signals will

be 120° out-of-phase. If the ISL6353 is in 2-phase mode, the

master clock signal will be distributed to Phases 1 and 2, and the

Clock1 and Clock2 signals will be 180° out-of-phase. If the ISL6353

is in 1-phase mode, the master clock signal will be distributed to

Phase 1 only and is the Clock1 signal.

If the load current is light enough, as Figure 6 shows, the inductor

current will reach and stay at zero before the next phase node

pulse, and the regulator is in discontinuous conduction mode

(DCM). If the load current is heavy enough, the inductor current

will never reach 0A, and the regulator is in CCM although the

controller is in DE mode.

Each slave circuit has its own ripple capacitor C , whose voltage

rs

mimics the inductor ripple current. A g amplifier converts the

m

inductor voltage into a current source to charge and discharge

C . The slave circuit turns on its PWM pulse upon receiving the

rs

clock signal, and the current source charges C . When C

rs

September 15, 2011

FN6897.0

12

ISL6353

CCM/DCM BOUNDARY

VW

VDD

VR_ON

V_crs

2.5mV/µs

VBOOT

1.3ms

DAC

i_L

LIGHT DCM

VW

PGOOD

V_crs

READY FOR SVID COMMAND

FIGURE 8. SOFT-START WAVEFORMS

i_L

Voltage Regulation and Differential Sensing

DEEP DCM

VW

After the start sequence, the ISL6353 regulates the output voltage

to the value set by the SetVID commands through the SVID bus or

to the value set by the status of the VSET1/2 pins. The ISL6353

will regulate the output voltage to VID + OFFSET (Register 33h). A

differential amplifier allows remote voltage sensing for precise

voltage regulation.

V_crs

iL

VID Table

FIGURE 7. PERIOD STRETCHING

The ISL6353 will regulate the output voltage to VID+OFFSET (33h).

Table 1 shows the output voltage setting based on the VID register

setting.

Figure 7 shows the principle of operation in diode emulation mode

at light load. The load gets incrementally lighter in the three cases

from top to bottom. The PWM on-time is determined by the VW

window size and therefore it is the same, making the inductor

current triangle the same in the three cases. The ISL6353 clamps

TABLE 1. VID TABLE

V

O

(V)

the ripple capacitor voltage V in DE mode to make it mimic the

crs

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

inductor current. It takes the COMP voltage longer to hit V

,

crs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0.0000

0.2500

0.2550

0.2600

0.2650

0.2700

0.2750

0.2800

0.2850

0.2900

0.2950

0.3000

0.3050

0.3100

0.3150

0.3200

0.3250

0.3300

0.3350

0.3400

0.3450

0.3500

naturally stretching the switching period. The inductor current

triangles move further apart from each other such that the

inductor current average value is equal to the load current. The

reduced switching frequency helps increase light load efficiency.

0

1

Start-up Timing

With the controller's V voltage above the POR threshold, the

DD

start-up sequence begins about 1.3ms after VR_ON exceeds the

logic high threshold. The ISL6353 uses digital soft-start to ramp

up the DAC to the boot voltage, V

. V is set by the PROG2

BOOT BOOT

pin resistor and the status of the VSET1/2 pins. The DAC slew

rate during soft-start is about 2.5mV/µs. PGOOD is asserted high

at the end of the start-up sequence indicating that the output

voltage has moved to the V

setting, the VR is operating

BOOT

properly and all phases are switching. Figure 8 shows the typical

start-up timing.

0

1

2

3

4

5

September 15, 2011

FN6897.0

13

ISL6353

TABLE 1. VID TABLE (Continued)

V

(V)

V

(V)

O

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6

7

8

9

A

B

C

D

E

F

0.3550

0.3600

0.3650

0.3700

0.3750

0.3800

0.3850

0.3900

0.3950

0.4000

0.4050

0.4100

0.4150

0.4200

0.4250

0.4300

0.4350

0.4400

0.4450

0.4500

0.4550

0.4600

0.4650

0.4700

0.4750

0.4800

0.4850

0.4900

0.4950

0.5000

0.5050

0.5100

0.5150

0.5200

0.5250

0.5300

0.5350

0.5400

0.5450

0.5500

0.5550

0.5600

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0.5650

0.5700

0.5750

0.5800

0.5850

0.5900

0.5950

0.6000

0.6050

0.6100

0.6150

0.6200

0.6250

0.6300

0.6350

0.6400

0.6450

0.6500

0.6550

0.6600

0.6650

0.6700

0.6750

0.6800

0.6850

0.6900

0.6950

0.7000

0.7050

0.7100

0.7150

0.7200

0.7250

0.7300

0.7350

0.7400

0.7450

0.7500

0.7550

0.7600

0.7650

0.7700

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

September 15, 2011

FN6897.0

14

ISL6353

TABLE 1. VID TABLE (Continued)

V

(V)

V

(V)

O

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6

A

B

C

D

E

F

0.7750

0.7800

0.7850

0.7900

0.7950

0.8000

0.8050

0.8100

0.8150

0.8200

0.8250

0.8300

0.8350

0.8400

0.8450

0.8500

0.8550

0.8600

0.8650

0.8700

0.8750

0.8800

0.8850

0.8900

0.8950

0.9000

0.9050

0.9100

0.9150

0.9200

0.9250

0.9300

0.9350

0.9400

0.9450

0.9500

0.9550

0.9600

0.9650

0.9700

0.9750

0.9800

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

9

4

5

6

7

8

9

A

B

C

D

E

F

0.9850

0.9900

0.9950

1.0000

1.0050

1.0100

1.0150

1.0200

1.0250

1.0300

1.0350

1.0400

1.0450

1.0500

1.0550

1.0600

1.0650

1.0700

1.0750

1.0800

1.0850

1.0900

1.0950

1.1000

1.1050

1.1100

1.1150

1.1200

1.1250

1.1300

1.1350

1.1400

1.1450

1.1500

1.1550

1.1600

1.1650

1.1700

1.1750

1.1800

1.1850

1.1900

6

7

8

9

A

B

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

0

1

2

3

September 15, 2011

FN6897.0

15

ISL6353

TABLE 1. VID TABLE (Continued)

V

(V)

V

(V)

O

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0

Hex

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

B

E

F

1.1950

1.2000

1.2050

1.2100

1.2150

1.2200

1.2250

1.2300

1.2350

1.2400

1.2450

1.2500

1.2550

1.2600

1.2650

1.2700

1.2750

1.2800

1.2850

1.2900

1.2950

1.3000

1.3050

1.3100

1.3150

1.3200

1.3250

1.3300

1.3350

1.3400

1.3450

1.3500

1.3550

1.3600

1.3650

1.3700

1.3750

1.3800

1.3850

1.3900

1.3950

1.4000

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

E

8

9

A

B

C

D

E

F

1.4050

1.4100

1.4150

1.4200

1.4250

1.4300

1.4350

1.4400

1.4450

1.4500

1.4550

1.4600

1.4650

1.4700

1.4750

1.4800

1.4850

1.4900

1.4950

1.5000

1.5050

1.5100

1.5150

1.5200

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VID OFFSET Table

The ISL6353 will regulate the output voltage to VID+OFFSET (33h).

Table 2 shows the output voltage setting based on the VID register

setting.

TABLE 2. VID TABLE

V

(V)

OFS

OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0

Hex

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

9

A

0.0000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

0.045

0.050

0

1

2

3

4

5

6

7

E

September 15, 2011

FN6897.0

16

ISL6353

TABLE 2. VID TABLE (Continued)

V

(V)

OFS

(V)

OFS

OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0

Hex

OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0

Hex

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

B

C

D

E

F

0.055

0.060

0.065

0.070

0.075

0.080

0.085

0.090

0.095

0.100

0.105

0.110

0.115

0.120

0.125

0.130

0.135

0.140

0.145

0.150

0.155

0.160

0.165

0.170

0.175

0.180

0.185

0.190

0.195

0.200

0.205

0.210

0.215

0.220

0.225

0.230

0.235

0.240

0.245

0.250

0.255

0.260

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

3

5

6

7

8

9

A

B

C

D

E

F

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0

1

2

3

4

5

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

0

1

2

3

4

September 15, 2011

FN6897.0

17

ISL6353

TABLE 2. VID TABLE (Continued)

V

OFS

(V)

OFS7 OFS6 OFS5 OFS4 OFS3 OFS2 OFS1 OFS0

Hex

VCC_SENSE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

5

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

FB

6

7

VR LOCAL

VO

“CATCH”

RESISTOR

E/A

COMP

DAC

X 1

Σ

VDAC

RTN

VSS

VSS_SENSE

INTERNAL TO IC

“CATCH”

RESISTOR

FIGURE 9. DIFFERENTIAL SENSING

Figure 9 shows the differential voltage sensing scheme. VCC

SENSE

and VSS

are the remote voltage sensing signals from the DDR

SENSE

memory. A unity gain differential amplifier senses the VSS

SENSE

voltage and adds it to the DAC output. The error amplifier regulates

the inverting and the non-inverting input voltages to be equal as

shown in Equation 1:

(EQ. 1)

VCC

= V

+ VSS

DAC SENSE

SENSE

Rewriting Equation 1 gives Equation 2:

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VCC

– VSS

= V

SENSE DAC

(EQ. 2)

SENSE

The VCC

and VSS

signals are routed from the

SENSE

memory socket. In most cases the remote sensing location will

be on the PCB right next to one of the DDR memory sockets. If a

remote sensing location is used on a module that passes through

a socket then the feedback signals will be open circuit in the

absence of the module. As shown in Figure 9, a “catch” resistor

should be added in this case to feed the local VR output voltage

back to the compensator, and another “catch” resistor should be

added to connect the local VR output ground to the RTN pin.

These resistors, typically 10Ω~100Ω, will provide voltage

feedback if the system is powered up without any memory cards

installed.

Inductor DCR Current-Sensing Network

The ISL6353 can sense the inductor current through the intrinsic DC

Resistance (DCR) of the inductors or through precision resistors in

series with the inductors. With both current-sensing methods, the

voltage across capacitor C represents the total inductor current

n

from all phases. An amplifier converts the C voltage, V , into an

n

Cn

internal current source, I

in Equation 3.

, with the gain set by resistor R shown

sense

i

V

Cn

(EQ. 3)

---------

I

=

sense

R

i

September 15, 2011

FN6897.0

18

ISL6353

The sensed current is used for current monitoring and overcurrent

protection.

(EQ. 7)

(EQ. 8)

DCR

L

-----------

ω

=

L

Phase1 Phase2 Phase3

1

------------------------------------------------------

ω

=

sns

R

sum

N

Rsum

--------------

R

×

ntcnet

-----------------------------------------

× C

n

R

sum

N

--------------

R

+

ntcnet

ISUM+

where N is the number of phases.

Transfer function A (s) always has unity gain at DC. The inductor

cs

Rntcs

L

DCR value increases as the winding temperature increases,

giving higher a reading of the inductor DC current. The NTC R

Cn Vcn

Ri

Rp

ntc

values decreases as its temperature increases. Proper selections

of R , R , R and R parameters ensure that V

Rntc

Ro

DCR

sum ntcs ntc Cn

p

ISUM-

represents the total inductor DC current over the temperature

range of interest.

Ro

There are many sets of parameters that can properly temperature-

compensate the DCR change. Since the NTC network and the R

sum

resistors form a voltage divider, V is always a fraction of the

cn

inductor DCR voltage. A higher ratio of V to the inductor DCR

cn

Io

voltage is recommended so the current monitor and OCP circuit has

a higher signal level to work with.

FIGURE 10. DCR CURRENT-SENSING NETWORK

A typical set of parameters that provide good temperature

Figure 10 shows the inductor DCR current-sensing network for a

3-phase regulator. Inductor current flows through the DCR and

compensation are: R

= 3.65kΩ, R = 11kΩ, R = 2.61kΩ

sum

p

ntcs

and R = 10kΩ (ERT-J1VR103J). The NTC network component

creates a voltage drop. Each inductor has two resistors R

and

R connected to the pads to accurately sense the inductor current

ntc

sum

values may need to be fine tuned on actual boards. To help fine

tune the network apply a full load condition to the regulator and

record the IMON pin voltage reading immediately; then record the

IMON voltage reading again when the board has reached thermal

steady state. A good NTC network can limit the IMON voltage drift

to within 1% over the temperature range. If droop is used for the

ISL6353 based regulator the output voltage can be used for this

test rather than IMON. DDR memory regulators typically do not

operate with droop enabled. The Intersil evaluation board layout

and current-sensing network parameters can be referred to in

order to help minimize engineering time.

o

by sensing the DCR voltage drop. The R

and R resistors are

sum

o

connected in a summing network as shown, and feed the total

current information to the NTC network (consisting of R , R

ntcs ntc

and R ) and capacitor C . R is a negative temperature

p

n

ntc

coefficient (NTC) thermistor, used to compensate for the increase

in inductor DCR as temperature increases.

The inductor output pads are electrically shorted in the schematic,

but have some parasitic impedance in the actual board layout,

which is why the signals cannot simply be shorted together for the

current-sense summing network. A resistor from 1Ω~10Ω for R is

o

V

(s) needs to represent real-time I (s) for the controller to

recommended to create quality signals. Since the R value is much

Cn

o

achieve best OCP and IMON response. The transfer function

smaller than the rest of the current sensing circuit, the following

analysis will ignore it for simplicity.

A

(s) has a pole ω and a zero ω . ω and ω should be

cs

sns

L

sns

matched so A (s) is unity gain at all frequencies. By forcing ω

cs

L

The summed inductor current information is represented at

equal to ω

value.

and solving for the solution, Equation 9 gives Cn

sns

capacitor C . Equations 4 through 8 describe the

n

frequency-domain relationship between total inductor current

L

-----------------------------------------------------------

C =

n

I (s) and the C voltage V (s):

o

n

Cn

R

sum

--------------

R

×

(EQ. 9)

ntcnet

N

⎛

⎜

⎝

⎞

⎟

⎠

-----------------------------------------

× DCR

R

DCR

N

ntcnet

R

sum

----------------------------------------- -----------

V

(s) =

×

× I (s) × A (s)

(EQ. 4)

(EQ. 5)

--------------

Cn

o

cs

R

+

R

ntcnet

sum

N

--------------

+

R

ntcnet

N

For example, given N = 3, R

= 3.65kΩ, R = 11kΩ,

p

sum

= 2.61kΩ, R = 10kΩ, DCR = 0.29mΩ and L = 0.22µH,

(R

+ R ) × R

ntc p

ntcs

R

ntcs

ntc

--------------------------------------------------

R

A

=

ntcnet

R

+ R

ntc p

Equation 9 gives C = 0.79µF.

ntcs

n

s

C is the capacitor used to match the inductor time constant.

n

------

1 +

ω

(EQ. 6)

Sometimes it takes the parallel combination of two or more

capacitors to get the desired value. To verify the capacitor value

is correct a repetitive load can be placed on the output voltage

and the IMON voltage can be monitored. The capacitor in parallel

with the IMON resistor needs to be removed for this test. The

L

----------------------

1 +

(s) =

cs

s

------------

ω

sns

September 15, 2011

FN6897.0

19

ISL6353

IMON voltage should be approximately a square wave with little

and 20µA in PS2 mode. For a 2-phase design, the OCP threshold

is 60µA in PS0 mode and 30µA in PS1 and PS2 mode. The

or no overshoot. In regulators without droop control the capacitor

value can be selected to err on the high side to overdamp the

current sense input to the controller to avoid overshoots.

ISL6353 declares a OCP fault when I

for 120µs.

is above the threshold

sense

Referring to Equation 3 and Figure 10, resistor R sets the sensed

i

Resistor Current-Sensing Network

current I

. In general, I

can be set to 40µA at the

sense

Phase1 Phase2 Phase3

maximum load current expected in the design. The OCP trip level

will be 1.5 times the maximum load current with a threshold at

60µA. The OCP ratio can be set to something other than 1.5

times the maximum load current by setting

L

I

= 60µA/OCP

.

sense

ratio

DCR

Rsum

For inductor DCR sensing, Equation 13 gives the DC relationship

of V (s) and I (s).

cn

o

⎛

⎜

⎝

⎞

⎟

⎠

ISUM+

ISUM-

R

DCR

N

ntcnet

----------------------------------------- -----------

V

=

×

× I

(EQ. 13)

Cn

o

R

sum

--------------

+

R

ntcnet

Rsen

Vcn

Cn

Ri

N

Ro

Substitution of Equation 13 into Equation 3 gives Equation 14:

R

1

DCR

N

ntcnet

---- ----------------------------------------- -----------

II

=

×

× I

(EQ. 14)

sense

o

R

i

sum

--------------

+

R

ntcnet

N

Io

Therefore:

R

× DCR × I

o

FIGURE 11. RESISTOR CURRENT-SENSING NETWORK

ntcnet

-------------------------------------------------------------------------------

R

=

(EQ. 15)

i

R

sum

⎛

⎞

⎠

--------------

N × R

+

× I

Figure 11 shows the precision resistor current-sensing network

for a 3-phase solution. Each inductor has a series current-sensing

ntcnet

sense

⎝

N

Substitution of Equation 5 and application of the full load

condition in Equation 15 gives Equation 16:

resistor, R . R

accurately capture the inductor current information. The R

and R are connected to the R

pads to

sen sum

o

sen

sum

and R resistors are connected to capacitor C . R

form a filter for noise attenuation. Equations 10 through 12 give

and C

n

(R

+ R ) × R

ntc p

o

n

sum

ntcs

--------------------------------------------------

× DCR × I

omax

R

+ R

ntc p

ntcs

-------------------------------------------------------------------------------------------------------------------------

=

R

V

(s) expressions:

(EQ. 16)

Cn

i

(R

+ R ) × R

R

⎛

⎜

⎝

⎞

⎟

⎠

ntcs

ntc

p

sum

R

(EQ. 10)

(EQ. 11)

sen

------------

-------------------------------------------------- --------------

N ×

+

× I

sensemax

V

(s) =

× I (s) × A

(s)

Rsen

R

+ R

p

N

Cn

o

ntcs

ntc

N

where I

is the full load current, and I is the

sensemax

1

omax

----------------------

(s) =

A

Rsen

s

corresponding sensed current based on the desired OCP to I

ratio.

omax

------------

1 +

ω

sns

For resistor sensing, Equation 17 gives the DC relationship of

1

(EQ. 12)

---------------------------

ω

=

V

(s) and I (s).

R

cn

o

sum

--------------

× C

n

R

N

(EQ. 17)

sen

------------

V

=

× I

Cn

o

N

Transfer function A

current-sensing resistor R

sen

(s) always has unity gain at DC. The

value will not have a significant

Rsen

Substitution of Equation 17 into Equation 3 gives Equation 18:

R

variation over temperature, so there is no need for the NTC

network.

1

sen

(EQ. 18)

---- ------------

× I

o

I

=

×

sense

R

N

i

Recommended values are R

sum

= 1kΩ and C = 5600pF.

n

Therefore:

R

× I

Overcurrent Protection

The ISL6353 implements overcurrent protection (OCP) by

comparing the average value of the measured current I

an internal current source reference. The OCP threshold is 60µA

for 3-phase, 2-phase and 1-phase PS0 operation. In PS1/2 mode

the OCP threshold is scaled based on the number of active

phases in PS1/2 mode divided by the number of active phases in

PS0 mode. For example, if the regulator operates in 3-phase

mode in PS0, 2-phase in PS1 mode and 1-phase in PS2 mode,

the OCP threshold will be 60µA in PS0 mode, 40µA in PS1 mode

sen

o

(EQ. 19)

(EQ. 20)

--------------------------

=

R

i

N × I

sense

with

sense

Application of the full load condition gives Equation 20:

R

× I

sen

omax

-------------------------------------

=

R

i

N × I

sensemax

where I

is the full load current, and I is the

sensemax

omax

corresponding sensed current.

September 15, 2011

FN6897.0

20

ISL6353

time constant for R C should be used such that the ISEN

voltages have minimal ripple and represent the DC current

flowing through the inductors. Recommended values are

Current Monitor

The ISL6353 provides a current monitor function. The IMON pin

outputs a high-speed analog current source that is 1/4 times the

s s

R = 10kΩ and C = 0.22µF.

s

I

current.

sense

R should be routed to the inductor phase-node pad in order to

s

help eliminate the effect of phase node parasitic PCB DCR.

Equations 26 through 28 give the ISEN pin voltages:

1

4

(EQ. 21)

--

× I

sense

I

=

IMON

A resistor R

is connected to the IMON pin to convert the

imon

(EQ. 26)

(EQ. 27)

(EQ. 28)

V

= (R

+ R

) × I

ISEN1

ISEN2

ISEN3

dcr1

dcr2

dcr3

pcb1

pcb2

pcb3

L1

L2

IMON pin current to a voltage. The voltage across R

expressed in Equation 22:

is

imon

1

4

(EQ. 22)

--

V

=

× I

× R

imon

Rimon

sense

L3

Substitution of Equation 14 into Equation 22 gives Equation 23:

R

where R

, R

and R

are inductor DCR; R

, R

dcr1 dcr2

pcb3

dcr3

pcb1 pcb2

1

DCR

N

ntcnet

-------- ----------------------------------------- -----------

× I × R

o imon

V

=

×

(EQ. 23)

and R are parasitic PCB DCR between the inductor output

pad and the output voltage rail; and I , I and I are inductor

Rimon

4R

R

i

sum

--------------

+

R

L1 L2 L3

ntcnet

N

average currents.

Rewriting Equation 23 gives Equation 24:

The ISL6353 will adjust the phase pulse-width relative to the

other phases to make V

= V

, thus to achieve

V

× R × (NR

+ R

)

sum

ISEN1

= R

ISEN2

= R

ISEN3

and

dcr3

Rimon

i

ntcnet

(EQ. 24)

---------------------------------------------------------------------------------------

=

R

I

= I = I , when R

imon

L1 L2 L3 dcr1

dcr2

1

--

R

× DCR × I

ntcnet

o

R

= R

pcb2

= R .

pcb3

4

pcb1

Using the same components for L1, L2 and L3 will provide a good

match of R , R and R . Board layout will determine

Substitution of Equation 5 and application of the full load

condition in Equation 24 gives Equation 25:

dcr1 dcr2 dcr3

R

, R

and R . Each phase should be as symmetric as

pcb1 pcb2

pcb3

(R

+ R ) × R

ntc p

possible in the PCB layout for the power delivery path between

each inductor and the output voltage load, such that

⎛

⎞

⎟

ntcs

--------------------------------------------------

V

× R × N

+ R

⎜

Rimon

i

sum

R

+ R

ntc p

⎝

⎠

ntcs

(EQ. 25)

-----------------------------------------------------------------------------------------------------------------------

R

=

R

= R

= R .

pcb1

pcb2

pcb3

imon

1

--

(R

+ R ) × R

ntcs

ntc p

L3

L2

Rdcr3

4

Rpcb3

Rpcb2

Rpcb1

V3p

V2p

------------------------------------------------------

× DCR × I

omax

Phase3

Rs

R

+ R

ntc p

ntcs

IL3

ISEN3

V3n

Rs

where I

is the full load current.

omax

Cs

INTERNAL

TO IC

A capacitor C

imon

can be paralleled with R

to filter the IMON

time constant is the user’s choice.

imon

Rdcr2

V

o

pin voltage. The R

C

imon imon

Phase2

Rs

The time constant should be long enough such that switching

frequency ripple is removed.

IL2

ISEN2

V2n

Cs

Phase Current Balancing

L1 Rdcr1

IL1

V1p

Phase1

L3

L2

L1

Rdcr3

Rdcr2

Rdcr1

Rpcb3

Rpcb2

Rpcb1

Rs

Phase3

ISEN1

V1n

Rs

IL3

IL2

IL1

ISEN3

Cs

V

INTERNAL

TO IC

o

Phase2

Rs

FIGURE 13. DIFFERENTIAL-SENSING CURRENT BALANCING

CIRCUIT

ISEN2

Cs

Phase1

Sometimes, it is difficult to implement a symmetric layout. For

the circuit shown in Figure 12, an asymmetric layout causes

Rs

ISEN1

different R

, R

and R resulting in phase current

Cs

pcb1 pcb2

pcb3

imbalance. Figure 13 shows a differential-sensing current

balancing circuit recommended for the ISL6353. The current

sensing traces should be routed to the inductor pads so they only

pick up the inductor DCR voltage. Each ISEN pin sees the average

voltage of three sources: its own phase inductor phase-node pad,

FIGURE 12. CURRENT BALANCING CIRCUIT

The ISL6353 monitors individual phase current by monitoring the

ISEN1, ISEN2, and ISEN3 pin voltages. Figure 12 shows the

current balancing circuit recommended for the ISL6353. Each

phase node voltage is averaged by a low-pass filter consisting of

R and C , and presented to the corresponding ISEN pin. A long

s

September 15, 2011

FN6897.0

21

ISL6353

and the other two phases inductor output pads. Equations 29

through 31 give the ISEN pin voltages:

–7

2

(EQ. 38)

R

(Ω) = 1.293 ⋅ 10 ⋅ F

– 0.1445 ⋅ F

+ 52055

SW

fset

SW

(EQ. 29)

(EQ. 30)

(EQ. 31)

V

= V + V + V

1p 2n

ISEN1

3n

Phase Count Configurations

The ISL6353 can be configured for 1, 2 or 3-phase operation.

V

= V + V + V

ISEN2

1n

2p

3n

For 2-phase configuration, tie the PWM3 pin to VDD. Phase 1 and

Phase 2 PWM pulses are 180° out-of-phase. Leave the ISEN3 pin

open for 2-phase configuration.

V

= V + V + V

1n 2n 3p

ISEN3

The ISL6353 will make V

Equations 32 and 33:

= V

= V as in

ISEN3

For 1-phase configuration, tie the PWM3 and ISEN2 pins to VDD.

In this configuration, only Phase 1 is active. The ISEN3, ISEN2,

ISEN1, and FB2 pins are not used because there is no need for

current balancing or the FB2 function.

ISEN1

ISEN2

(EQ. 32)

(EQ. 33)

V

+ V + V

= V + V + V

1n 2p

1p

1n

2n

3n

3p

Modes of Operation

+ V + V

= V + V + V

1n 2n

2p

TABLE 3. ISL6353 MODES OF OPERATION

Rewriting Equation 32 gives Equation 34:

CONFIGURATION

PS#

PS0

PS1

OPERATIONAL MODE

3-phase CCM

(EQ. 34)

(EQ. 35)

(EQ. 36)

V

– V

= V – V

1n 2p 2n

3-phase Configuration

1p

2-phase CCM or

1-phase CCM

and rewriting Equation 33 gives Equation 35:

V

– V

= V – V

2n 3p 3n

2p

PS2

PS3

PS0

PS1

PS2

PS3

PS0

PS1

PS2

PS3

1-phase DE

2-phase CCM

1-phase CCM

1-phase DE

1-phase CCM

1-phase DE

Combining Equations 34 and 35 gives Equation 36:

2-phase Configuration

1-phase Configuration

V

– V

= V – V

3n

1p

1n

2p

2n

3p

Therefore:

(EQ. 37)

R

× I

= R

× I

= R

× I

dcr3 L3

dcr1

L1

dcr2

L2

Current balancing (I = I = I ) is achieved when

L1 L2 L3

R

= R

. R , R

and R

will not have any

dcr1

effect.

dcr2

dcr3 pcb1 pcb2

pcb3

Since the slave ripple capacitor voltages mimic the inductor

3

currents, the R ™ modulator can naturally achieve excellent current

balancing during steady-state and dynamic operation. The inductor

currents follow the load current dynamic change, with the output

capacitors supplying the difference. The inductor currents can

track the load current well at low rep rate, but cannot keep up

when the rep rate gets into the hundred-kHz range, where it is out

of the control loop bandwidth. The controller achieves excellent

current balancing in all cases.

Table 3 shows the modes of operation for the various power states

programmed using the SetPS command through the SVID bus or

by changing the state of the PSI pin. Table 3 is used in conjunction

with the status of the PROG2 pin. Refer to Table 7 for the PROG2

programming options.

Dynamic Operation

CCM Switching Frequency

The controller responds to VID changes by slewing to the new

voltage at a slew rate indicated in the SetVID command. There

are three SetVID slew rates SetVID_fast, SetVID_slew and

SetVID_decay.

The resistor connected between the COMP pin and the VW pin

sets the VW windows size, therefore setting the steady state

PWM switching frequency. When the ISL6353 is in continuous

conduction mode (CCM), the switching frequency is not

The SetVID_fast command prompts the controller to enter CCM

and to actively drive the output voltage to the new VID value at a

minimum 10mV/µs slew rate.

3

absolutely constant due to the nature of the R modulator. As

explained in the “Multiphase R3 Modulator” on page 11, the

effective switching frequency will increase during load step-up

and will decrease during load step-down to achieve fast transient

response. On the other hand, the switching frequency is relatively

constant at steady state. Equation 38 gives an estimate of the

The SetVID_slow command prompts the controller to enter CCM

and to actively drive the output voltage to the new VID value at a

minimum 2.5mV/µs slew rate.

frequency-setting resistor R

approximately 300kHz switching frequency. Lower resistance

yields higher switching frequency.

value. 20kΩ R gives

fset

The SetVID_decay command prompts the controller to enter DE

mode. The output voltage will decay down to the new VID value at

a slew rate determined by the load. If the voltage decay rate is

September 15, 2011

FN6897.0

22

ISL6353

too fast, the controller will limit the voltage slew rate at the

SetVID_slow slew rate.

system. The VR_HOT# pin will be pulled back high if the voltage

on the NTC pin goes above 0.95V.

ALERT# will be asserted low at the end of SetVID_fast and

SetVID_slow VID transitions.

If the voltage on the NTC pin goes below 0.93V the ALERT# pin

will be pulled low indicating a thermal alert. ALERT# is reset by

checking the status register. ALERT# will be pulled low again if

the NTC pin voltage goes above 0.97V.

When the ISL6353 is in DE mode, it will actively drive the output

voltage up when the VID changes to a higher value. DE operation

will resume after reaching the new voltage level. If the load is

light enough to warrant DCM, it will enter DCM after the inductor

current has crossed zero for four consecutive cycles. The ISL6353

will remain in DE mode when the VID changes to a lower value.

The output voltage will decay to the new value and the load will

determine the slew rate.

All the above fault conditions can be reset by bringing VR_ON low

or by bringing V below the POR threshold. When VR_ON and

DD

V

return to their high operating levels, a soft-start will occur.

DD

VR_HOT#/ALERT# BEHAVIOR

VR Temperature

3% Hysteris

Temp Zone

Bit 7 =1

1111 1111

0111 1111

0011 1111

0001 1111

7

Protection Functions

The ISL6353 provides overcurrent, current-balance, overvoltage,

and over-temperature protection.

1

10

Bit 6 =1

Bit 5 =1

12

OVERCURRENT PROTECTION

Temp Zone

Register

The ISL6353 determines overcurrent protection (OCP) by

2

8

comparing the average value of the measured current I

with

sense

an internal current source threshold. ISL6353 declares OCP when

is above the threshold for 120µs.

0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111

Status 1

Register

3

= “001”

= “011”

= “001”

I

sense

13

14

15

5

GerReg

Status1

GerReg

Status1

The way-overcurrent protection threshold is significantly above

the standard overcurrent protection threshold. The

way-overcurrent function is intended to provide a fast overcurrent

detection and action mechanism in a short circuit output

condition. Once the way-overcurrent condition is detected, the

PWM outputs will immediately shut off and PGOOD will go low to

maximize protection.

SVID

ALERT#

4

6

16

VR_HOT#

9

11

FIGURE 14. VR_HOT#/ALERT# BEHAVIOR

The controller drives a 60µA current source out of the NTC pin.

The current source flows through the NTC resistor network on the

pin and creates a voltage that is monitored by the controller

through an A/D converter (ADC) to generate the Tzone value.

Table 4 shows the typical programming table for Tzone. The user

needs to scale the NTC a network resistance such that it

generates the NTC pin voltage that corresponds to the left-most

column.

CURRENT BALANCE FAULT

The ISL6353 monitors the ISEN pin voltages to detect severe

phase current imbalances. If any ISEN pin voltage is more than

20mV different than the average ISEN voltage for 1ms, the

controller will declare a fault and latch off.

OVERVOLTAGE PROTECTION

The ISL6353 will declare an OVP fault if the output voltage

exceeds 175mV above the VID set value + positive offset. In the

event of an OVP condition, the OVP pin is pulled high. OVP is

blanked during dynamic VID events to prevent false trigger.

During soft-start, the OVP threshold is set at 2.33V to avoid a

false trigger due to turn on into a precharged output capacitor

bank.

TABLE 4. TZONE TABLE

VNTC (V)

0.86

0.88

0.92

0.96

1.00

1.04

1.08

1.12

1.16

1.20

>1.20

TMAX (%)

>100

100

97

TZONE

FFh

7Fh

3Fh

1Fh

0Fh

07h

03h

01h

00h

94

POWER GOOD INDICATOR

91

The ISL6353 takes the same actions for all of the above fault

protection functions: PGOOD is set low and the high-side and low-

side MOSFETs are turned off. Any residual inductor current will

decay through the MOSFET body diodes. These fault conditions

can be reset by bringing VR_ON low or by bringing V below the

POR threshold. When VR_ON and V return to their high

DD

88

85

82

DD

79

operating levels, a soft-start will occur.

76

THERMAL MONITOR

<76

The ISL6353 has a thermal throttling feature. If the voltage on

the NTC pin goes below the 0.91V threshold, the VR_HOT# pin is

pulled low indicating the need for thermal throttling to the

September 15, 2011

FN6897.0

23

ISL6353

Figure 14 shows the how the NTC network should be designed to get

FB2 Function

correct VR_HOT#/ALERT# behavior when the system temperature

rises and falls, manifested as the NTC pin voltage falling and rising.

The series of events are:

CONTROLLER IN

3 OR 2-PHASE

MODE

CONTROLLER IN

PS1 OR PS2

MODE

C1

C3

C1

C3

R2

C2.1

R3.1

C2.1

R3.1

1. The temperature rises so the NTC pin voltage drops. Tzone

value changes accordingly.

R1

C2.2

R1

FB

VSEN

COMP

E/A

C2.2

R3.2

COMP

2. The temperature crosses the threshold where Tzone register

Bit 6 changes from 0 to 1.

FB2

Vref

FIGURE 15. FB2 FUNCTION IN 2-PHASE MODE

3. The controller changes Status_1 register bit 1 from 0 to 1.

4. The controller asserts ALERT#.

Figure 15 shows the FB2 function. In order to improve transient

response and stability when phases are disabled in PS1 or PS2

mode, the ISL6353 FB2 function allows a second type 3

compensation network to be connected from the output voltage

to the FB pin.

5. The CPU reads Status_1 register value to know that the alert

assertion is due to Tzone register bit 6 flipping.

6. The controller clears ALERT#.

7. The temperature continues rising.

In PS0 mode of operation the FB2 switch is open (off). In PS1 or

PS2 mode of operation the FB2 switch closes (on).

8. The temperature crosses the threshold where Tzone register

Bit 7 changes from 0 to 1.

The FB2 function ensures excellent transient response in both

PS0 mode and PS1/2 mode. If the FB2 function is not needed

C2.2 and R3.2 can be unpopulated and the FB2 pin can be left

unconnected.

9. The controllers asserts VR_HOT# signal. The CPU throttles

back and the system temperature starts dropping eventually.

10. The temperature crosses the threshold where Tzone register

bit 6 changes from 1 to 0. This threshold is 1 ADC step lower

than the one when VR_HOT# gets asserted, to provide 3%

hysteresis.

Adaptive Body Diode Conduction Time

Reduction

In DCM, the controller turns off the low-side MOSFET when the

inductor current approaches zero. During the on-time of the

low-side MOSFET, the phase voltage is negative and the amount

11. The controllers de-asserts VR_HOT# signal.

12. The temperature crosses the threshold where Tzone register

bit 5 changes from 1 to 0. This threshold is 1 ADC step lower

than the one when ALERT# gets asserted during the

temperature rise to provide 3% hysteresis.

is the MOSFET r

voltage drop, which is proportional to the

DS(ON)

inductor current. A phase comparator inside the controller

monitors the phase voltage during on-time of the low-side

MOSFET and compares it with a threshold to determine the

zero-crossing point of the inductor current. If the inductor current

has not reached zero when the low-side MOSFET turns off, it will

flow through the low-side MOSFET body diode, causing the phase

node to have a larger voltage drop until it decays to zero. If the

inductor current has crossed zero and reversed the direction

when the low-side MOSFET turns off, it will flow through the

high-side MOSFET body diode, causing the phase node to have a

spike until the current decays to zero. The controller continues

monitoring the phase voltage after turning off the low-side

MOSFET and adjusts the phase comparator threshold voltage

accordingly in iterative steps such that the low-side MOSFET body

diode conducts for approximately 40ns to minimize the body

diode-related loss.

13. The controller changes Status_1 register bit 1 from 1 to 0.

14. The controller asserts ALERT#.

15. The CPU reads Status_1 register value to know that the alert

assertion is due to Tzone register bit 5 flipping.

16. The controller clears ALERT#.

Table 5 summarizes the fault protection functionality.

TABLE 5. FAULT PROTECTION SUMMARY

FAULT DURATION

BEFORE

PROTECTION

ACTION

FAULT

RESET

FAULT TYPE

Overcurrent

120µs

1ms

PWM tri-state,

PGOOD latched low toggle or

VDD toggle

VR_ON

Phase Current

Unbalance

Way-Overcurrent

(1.5xOC)

Immediately

System Parameter Programming PROG1/2

Pins

ISL6353 has two system parameter programming pins PROG1

and PROG2. Some system parameters, such as maximum output

current, boot voltage, number of phases for PS1 state, can be

programmed by changing the resistors connected to these three

pins.

Overvoltage

+175mV

PGOODlatchedlow.

Actively pulls the

output voltage to

below VID value,

then tri-state.

September 15, 2011

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24

ISL6353

TABLE 7. DEFINITION OF PROG2 (Continued)

WORKING MODE

Table 6 shows the definition of PROG1. PROG1 defines the

maximum output current setting in the IMAX register of the

ISL6353.

R

V

PROG2

(Ω)

BOOT

(V)

DROOP

AT PS1

TABLE 6. DEFINITION OF PROG1

3480

4120

4750

Disabled

2 phase CCM (3-phase

Configuration)

1-Phase CCM (2-phase

configuration)

1.20

1.35

1.50

R

I

MAX 1-PHASE

PROG1

MAX 3-PHASE

MAX 2-PHASE

(Ω)

(A)

MODE

158

475

787

99

66

33

Disabled

2 phase CCM (3-phase

Configuration)

1-Phase CCM (2-phase

configuration)

90

84

81

75

69

66

60

54

51

45

39

60

56

54

50

46

44

40

36

34

30

26

30

28

27

25

23

22

20

18

17

15

13

1100

1430

1740

2050

2370

2870

3480

4120

4750

2 phase CCM (3-phase

Configuration)

1-Phase CCM (2-phase

configuration)

5360

6040

6650

7500

Disabled

1 phase CCM

1.50

1.35

1.20

0

SVID ADDRESS Setting

The SVID address of ISL6353 can be programmed by changing

the resistor connected to the ADDR pin. Table 8 shows the SVID

address definition.

Table 7 shows the definition of PROG2. PROG2 defines the boot

voltage, enable/disable droop and the working mode for PS1.

TABLE 8. SVID ADDRESS DEFINITION

TABLE 7. DEFINITION OF PROG2

R

ADDR

(Ω)

R

WORKING MODE

AT PS1

V

PROG2

(Ω)

BOOT

(V)

ADDRESS

DROOP

Enabled

158

475

0

1

2

3

4

5

6

7

8

9

A

B

C

D

158

475

787

1-phase CCM

1- phase CCM

1-phase CCM

1- phase CCM

0

1.20

1.35

1.50

787

1100

1430

1740

2050

2370

2870

3480

4120

4750

5360

6040

1100

1430

2-Phase CCM (3-Phase

Configuration)

1-Phase CCM (2-phase

configuration)

1740

2050

2370

2870

Enabled

Disabled

2-Phase CCM (3-Phase

Configuration)

1-Phase CCM (2-phase

configuration)

1.35

1.20

0

2-Phase CCM (3-Phase

Configuration)

1-Phase CCM (2-phase

configuration)

2-Phase CCM (3-Phase

Configuration)

1-Phase CCM (2-Phase

configuration)

External Control of VOUT and Power State

VSET1/2, PSI

For additional design flexibility, the ISL6353 has 3 pins that can be

used to set the output voltage and power state of the regulator

with external signals independent of the serial communication bus

register settings.

2-Phase CCM (3-Phase

Configuration)

1-Phase CCM (2-Phase

configuration)

0

September 15, 2011

FN6897.0

25

ISL6353

VSET1 and VSET2 can be used to set the output voltage of the

Supported Serial VID Data And Configuration

Registers

The controller supports the following data and configuration

registers.

regulator. Table 9 shows the available options. If VSET1 and VSET2

are connected to ground, the controller will refer only to the SVID

register setting to program the output voltage. If any other logic

combination is used on VSET1/2, the controller will ignore the

SVID register setting and program the output voltage based on

Table 8 for soft-start and steady state.

TABLE 11. SUPPORTED DATA AND CONFIGURATION

REGISTERS

TABLE 9. VSET1/2 PIN DEFINITION

REGISTER

NAME

DEFAULT

VALUE

INDEX

DESCRIPTION

V

BOOT

from PROG2

OUTPUT

VOLTAGE

00h Vendor ID

Uniquely identifies the VR

vendor. Assigned by Intel.

12h

(V)

VSET1

VSET2

1.5

1.35

1.2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SVID Setting

1.35V

01h Product ID

Uniquely identifies the VR

product. Intersil assigns this

number.

35h

1.6V

02h Product

Revision

Uniquely identifies the revision

of the VR control IC. Intersil

assigns this data.

1.65V

SVID Setting

1.2V

05h Protocol ID

06h Capability

Identifies which revision of SVID 01h

protocol the controller supports.

1.4V

Identifies the SVID VR

capabilities and which of the

optional telemetry registers are

supported.

81h

1.45V

SVID Setting

1.1V

10h Status_1

Data register read after ALERT# 00h

signal; indicating if a VR rail has

settled, has reached VRHOT

condition or has reached ICC

max.

1.25V

1.3V

SVID Setting

1.05V

11h Status_2

Data register showing Status_2 00h

communication.

0

1.55V

12h Temperature Data register showing

00h

Zone

temperature zones that have

been entered.

0

1.15V

The PSI pin can be used to set the power state of the regulator as

indicated on Table 10. If PSI is connected to ground the controller

will refer only to the SVID register contents to set the power state. If

PSI is pulled high, the controller will enter the PS2 state. If PSI is

connected to a high impedance, the controller will enter the PS1

state.

15h IOUT

Data register showing output

current information. The voltage

at the IMON pin is digitized and

stored in this register.

00h

1Ch Status_2_

LastRead

This register contains a copy of 00h

the Status_2 data that was last

read with the GetReg (Status_2)

command.

TABLE 10. PSI PIN DEFINITION

PSI

0

ADDRESS

21h ICC max

Data register containing the ICC Refer to

max the platform supports; set Table 6

at start-up by resistor on PROG1

pin. The platform design

engineer programs this value

during the design process.

Internal SVID Power State

High-Z

1

PS1

PS2

Binary format in amps, for

example 100A = 64h.

24h SR-fast

25h SR-slow

Slew Rate Normal. The fastest 0Ah

slew rate the platform VR can

sustain. Binary format in

mV/µs. i.e. 0Ah = 10mV/µs.

Is 4x slower than normal. Binary 02h

format in mV/µs. i.e.

02h = 2.5mV/µs

September 15, 2011

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26

ISL6353

TABLE 11. SUPPORTED DATA AND CONFIGURATION

REGISTERS (Continued)

REGISTER

NAME

DEFAULT

VALUE

INDEX

26h

DESCRIPTION

Vboot

If programmed by the platform, Refer to

the VR supports V voltage Table 6

BOOT

during start-up ramp. The VR

will ramp to V and hold at

BOOT

until it receives a new

V

BOOT

SetVID command to move to a

different voltage.

30h

31h

Vout max

This register is programmed by FBh

the master and sets the

maximum VID the VR will

support. If a higher VID code is

received, the VR will respond

with “not supported”

acknowledge.

VID Setting

Power State

Data register containing

currently programmed VID

voltage. VID data format.

00h

32h

33h

Register containing the

programmed power state.

Voltage Offset Sets offset in VID steps added to 00h

the VID setting for voltage

margining. Bit 7 is a sign bit,

0 = positive margin,

1 = negative margin.

Remaining 7 bits are # VID

steps for the margin.

00h = no margin,

01h = +1 VID step

02h = +2 VID steps...

34h

Multi VR

Config

Data register that configures

multiple VRs behavior on the

same SVID bus.

VR1: 00h

VR2: 01h

Layout Guidelines

ISL6353

PIN NUMBER

SYMBOL

GND

LAYOUT GUIDELINES

BOTTOM PAD

Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect

to ground planes in PCB internal layers.

1, 2, 3

SDA,

ALERT#,

SCLK

Follow Intel recommendations.

4, 5, 6, 7, 22,

28, 36, 37, 38,

39

VR_ON,

PGOOD,

IMON,

No special consideration.

VR_HOT#,

PROG1,

PWM3, PSI,

VSET1,

VSET2, OVP

8

9

NTC

The NTC thermistor needs to be placed close to the thermal source that is monitored to determine the desired VR_HOT#

and thermal ALERT# toggling. Recommend placing it at the hottest spot of the ISL6353 based regulator.

VW

Place the resistor and capacitor from VW to COMP in close proximity of the controller.

September 15, 2011

27

FN6897.0

ISL6353

Layout Guidelines(Continued)

ISL6353

PIN NUMBER

SYMBOL

LAYOUT GUIDELINES

10, 11, 12

COMP, FB, Place the compensator components in general proximity of the controller

FB2

13, 14, 15

ISEN3,

Each ISEN pin has a capacitor (Cisen) decoupling it to VSUMN, then through another capacitor (Cvsumn) to GND. Place

ISEN2, ISEN1 Cisen capacitors as close as possible to the controller and keep the following loops small:

1. Any ISEN pin to another ISEN pin

2. Any ISEN pin to GND

The red traces in the following drawing show the loops that need to minimized.

Phase1

L3

Risen

Ro

ISEN3

ISEN2

Cisen

V

o

Phase2

Risen

L2

L1

Phase3

Risen

ISEN1

GND

Vsumn

Cvsumn

16, 17

18, 19

VSEN, RTN Place the VSEN/RTN filter in close proximity of the controller for good decoupling. Route these signals differentially

from the remote sense location back to the controller.

ISUMN,

ISUMP

Place the current sensing circuit in general proximity of the controller.

Place capacitor Cn very close to the controller.

Place the NTC thermistor next to the phase 1 inductor so it senses the inductor temperature correctly.

Each phase of the power stage sends a pair of VSUMP and VSUMN signals to the controller. Run these two signals traces

in parallel fashion.

IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces

on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is

allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings

show the two preferred ways of routing current sensing traces. If possible connect the traces to the inductor pad in only

one place and isolate this connection from other planes of the same net that may be present on other layers. Also make

the connections a symmetric as possible for all phases.

Inductor

Vias

Current-Sensing

Traces

Current-Sensing

Traces

20

21

VDD

VIN

Place the decoupling capacitor a close as possible to this pin.

September 15, 2011

FN6897.0

28

ISL6353

Layout Guidelines(Continued)

ISL6353

PIN NUMBER

SYMBOL

BOOT1

LAYOUT GUIDELINES

23

Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.

24, 25

UG1, PH1

Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals

near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general

copper.

26

27

GND

LG1

Connect this pin to ground right next to the controller or to the exposed pad underneath the controller.

Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.

Place the decoupling capacitor a close as possible to this pin.

29

VDDP

LG2

30

Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.

Connect this pin to ground right next to the controller or to the exposed pad underneath the controller.

31

GND

32, 33

PH2, UG2

Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals

near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general

copper.

34

35

40

BOOT2

PROG2

ADDR

Use fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.

Place resistor close to the controller.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN6897.0

CHANGE

09/15/2011

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL6353

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

September 15, 2011

29

FN6897.0

ISL6353

Package Outline Drawing

L40.5x5

40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 9/10

4X 3.60

36X 0.40

A

B

5.00

6

PIN #1 INDEX AREA

PIN 1

INDEX AREA

0.15

(4X)

40X 0.4± 0 .1

0.20

b

BOTTOM VIEW

TOP VIEW

0.10 M

C A B

4

PACKAGE OUTLINE

0.40

0.750

SEE DETAIL “X”

0.10 C

//

BASE PLANE

SEATING PLANE

0.08 C

C

0.050

SIDE VIEW

(36X 0.40

(40X 0.20)

0.2 REF

5

C

(40X 0.60)

0.00 MIN

0.05 MAX

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.27mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

JEDEC reference drawing: MO-220WHHE-1

7.

September 15, 2011

FN6897.0

30


型号：	ISL6353IRTZ
厂家：	Intersil
描述：	Multiphase PWM Regulator for VR12 DDR Memory Systems 多相PWM稳压器用于VR12 DDR内存系统稳压器双倍数据速率
文件：	总30页 (文件大小：1278K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6353IRTZ [INTERSIL]

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