ISL6410AIR-TK [INTERSIL]

Single Synchronous Buck Regulators with Integrated FET; 单同步降压型稳压器具有集成FET


型号：	ISL6410AIR-TK
厂家：	Intersil
描述：	Single Synchronous Buck Regulators with Integrated FET 单同步降压型稳压器具有集成FET 稳压器开关
文件：	总13页 (文件大小：392K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6410, ISL6410A

Data Sheet

September 17, 2004

FN9149.3

Single Synchronous Buck Regulators

with Integrated FET

Features

• Fully Integrated Synchronous Buck Regulator

The ISL6410, ISL6410A are synchronous current-mode

PWM regulators designed to provide a total DC-DC solution

for microcontrollers, microprocessors, CPLDs, FPGAs, core

processors/BBP/MAC, and ASICs. The ISL6410 should be

selected for applications using 3.3V ±10% as an input

voltage and the ISL6410A in applications requiring 5.0V

±10%.

• PWM Fixed Output Voltage Options

- 1.8V, 1.5V or 1.2V with ISL6410 (VIN = 3.3V)

- 3.3V, 1.8V or 1.2V with ISL6410A (VIN = 5.0V)

• Continuous Output Current . . . . . . . . . . . . . . . . . . 600mA

• Ultra-Compact DC-DC Converter Design

• Stable with Small Ceramic Output Capacitors

• High Conversion Efficiency

These synchronous current mode PWM regulators have

integrated N- and P-Channel power MOSFETs and provide

pre-set pin programmable outputs. Synchronous rectification

with internal MOSFETs is used to achieve higher efficiency

and a reduced external component count. The operating

frequency of 750kHz typical allows the use of small inductor

and capacitor values. The device can be synchronized to an

external clock signal in the range of 500kHz to 1MHz. A

power good signal “PG” is generated when the output

voltage falls outside the regulation limits. Other features

include overcurrent protection and thermal overload

shutdown. The ISL6410, ISL6410A are available in an

MSOP 10 lead package.

• Extensive Circuit Protection and Monitoring features

- Overvoltage, UVLO

- Overcurrent

- Thermal Shutdown

• Available in MSOP and QFN packages

• QFN Package:

- Compliant to JEDEC PUB95 MO-220

QFN - Quad Flat No Leads - Package Outline

- Near Chip Scale Package footprint, which improves

PCB efficiency and has a thinner profile

• Pb-Free Packaging Available

Ordering Information

TEMP.

PKG.

Applications

• CPUs, DSP, CPLDs, FPGAs

PART NUMBER* RANGE (°C)

PACKAGE

DWG. #

ISL6410IR

-40 to 85 16 Ld 4x4 QFN

L16.4x4

• ASICs

ISL6410IRZ (Note)

-40 to 85 16 Ld 4x4 QFN

(Pb-free)

• DVD and DSL applications

• WLAN Cards

ISL6410IU

-40 to 85 10 Ld MSOP

M10.118

ISL6410IUZ (Note)

ISL6410AIR

-40 to 85 10 Ld MSOP (Pb-free) M10.118

• Generic 5V to 3.3V Conversion

-40 to 85 16 Ld 4x4 QFN

L16.4x4

ISL6410AIRZ (Note) -40 to 85 16 Ld 4x4 QFN

(Pb-free)

Pinouts

ISL6410 (MSOP)

ISL6410 (QFN)

ISL6410AIU

-40 to 85 10 Ld MSOP

M10.118

TOP VIEW

ISL6410AIUZ (Note) -40 to 85 10 Ld MSOP (Pb-free) M10.118

*For tape and reel, add “-T”, “-TK” or “-T5K” suffix.

PVCC

VIN

10 PGND

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which is compatible with both SnPb and

Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J Std-020B.

VIN

12 NC

GND

SYNC

VSET

11 RESET

10 EN

GND

SYNC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Functional Block Diagram for MSOP Version

VIN

0.1µF

10µF

PVCC

CURRENT

SENSE

VIN

SLOPE

SOFT

GND

COMPENSATION

START

8.2µH

VOUT

PWM

OVERCURRENT,

OVERVOLTAGE

LOGIC

GATE

DRIVE

10µF

COMPENSATION

PGND

SYNC

VSET

750kHz

OSCILLATOR

POWER GOOD

PWM

OUT

UVLO

PWM

REFERENCE

0.45V

NOTES:

1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A.

2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.

Functional Block Diagram for QFN Version

VIN

0.1µF

10µF

PVCC

CURRENT

SENSE

16 VIN

SLOPE

SOFT

START

GND

COMPENSATION

8.2µH

VOUT

PWM

OVERCURRENT,

OVERVOLTAGE

LOGIC

GATE

DRIVE

10µF

COMPENSATION

PGND

SYNC

VSET

750kHz

OSCILLATOR

POWER GOOD

PWM

RESET

OUT

UVLO

RESET

BLOCK

PWM

10 EN

REFERENCE

0.45V

NOTES:

1. VIN is 3.3V for ISL6410 and 5.0V for ISL6410A.

2. VSET in the above schematic is connected to VIN, so the VOUT is 1.8V for ISL6410 and 3.3V for ISL6410A.

ISL6410, ISL6410A

Typical Application Schematics

VIN

3.3V

±10%

10µF

0.1µF

PVCC

VIN

PGND

8.2µH

OUT

1.8V

ISL6410

GND

OUT

10µF

SYNC

VSET

FIGURE 1. SCHEMATIC USING THE ISL6410 MSOP

VIN

5.0V

±10%

10µF

0.1µF

12µH

PVCC

VIN

PGND

OUT

3.3V

ISL6410A

GND

OUT

10µF

SYNC

VSET

FIGURE 2. SCHEMATIC USING THE ISL6410A MSOP

+1.2V

VOUT

+3.3V

VIN

8.2µH

16 15 14 13

OUT

10µF

1µF

10µF

GND

RESET

VIN

GND ISL6410IR

0.1µF

SYNC

0.01µF

RESET

BAR

FIGURE 3. SCHEMATIC USING THE ISL6410 QFN

ISL6410, ISL6410A

Absolute Maximum Ratings

Thermal Information

Thermal Resistance (Typical)

MSOP Package (Note 4) . . . . . . . . . . .

QFN Package (Notes 4, 5). . . . . . . . . .

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V

(°C/W)

128

(°C/W)

7.5

SYNC, FB, VSET & Enable Input (Note 3) . . . . -0.3V to VCC+0.3V

ESD Classification (Human Body Model) . . . . . . . . . . . . . . . Class 2

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Maximum Lead Temperature (10s, soldering . . . . . . . . . . . . . 260°C

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . .-40°C to 85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. All voltages are with respect to GND.

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications Recommended operating conditions unless otherwise noted. V = 3.3V ±10% (ISL6410) or 5V ±10%

(ISL6410A), T = 25°C (Note 6).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

SUPPLY

Supply Voltage Range

VIN (ISL6410)

3.0

3.3

5.0

2.68

2.59

4.37

4.22

2.3

3.6

5.5

2.73

2.64

4.45

4.32

VIN (ISL6410A)

4.5

Input UVLO Threshold

(ISL6410) Rising

(ISL6410) Falling

(ISL6410A) Rising

(ISL6410A) Falling

2.62

2.53

4.27

4.1

Quiescent Supply Current

Shutdown Supply Current

= 0mA

µA

°C

OUT

EN = GND, T = 25°C

EN = GND, T = 85°C

Thermal Shutdown Temperature (Note 7)

Thermal Shutdown Hysteresis (Note 7)

SYNCHRONOUS BUCK PWM REGULATOR

Output Voltage

Rising Threshold

150

ISL6410, VSET = L

1.2

1.8

1.5

1.2

3.3

1.8

ISL6410, VSET = H

ISL6410, VSET = OPEN

ISL6410A, VSET = L

ISL6410A, VSET = H

ISL6410A, VSET = OPEN

-1.5

-0.5

-1.5

Output Voltage Accuracy

Line Regulation

= 3mA, T = -40°C to 85°C

+1.5

+0.5

+1.5

600

1300

OUT

= 3mA

Load Regulation

= 3mA to 600mA

Maximum Output Current

Peak Output Current Limit

mΩ

700

PMOS r

NMOS r

= 200mA

230

DS(ON)

OUT

DS(ON)

Efficiency

= 200mA, V = 3.3V, V = 1.8V (ISL6410)

ISL6410, ISL6410A

Electrical Specifications Recommended operating conditions unless otherwise noted. V = 3.3V ±10% (ISL6410) or 5V ±10%

(ISL6410A), T = 25°C (Note 6). (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Efficiency

= 200mA, V = 5.0V, V = 3.3V (ISL6410A)

OUT

Efficiency

= 600mA, V = 5.0V, V = 3.3V (ISL6410A)

OUT

Soft-Start Time

OSCILLATOR

4096 Clock Cycles @ 750kHz

5.5

Oscillator Frequency

620

500

750

860

1000

kHz

Frequency Synchronization Range (f

SYNC High Level Input Voltage

SYNC Low Level Input Voltage

Sync Input Leakage Current

)

Clock signal on SYNC pin

As % of VIN

SYNC

As % of VIN

SYNC = GND or V

-1

µA

Duty Cycle of External Clock Signal (Note 7)

PGOOD (ISL6410 interfaces to 3.3V Logic, ISL6410A interfaces to 5.0V Logic)

Rising Threshold

1mA minimum source/sink

+5.0

-10.5

8.0

-8.0

+10.5

-5.0

Falling Threshold

Rising/Falling Hysteresis

ENABLE

EN High Level Input Voltage

EN Low Level Input Voltage

EN Input Leakage Current

OVERVOLTAGE

As % of VIN

EN = GND or V

-1

µA

Overvoltage Threshold

RESET BLOCK SPECIFICATIONS

RESET (reset released)

RESET (reset asserted)

RESET Rising Threshold

RESET Falling Threshold

RESET (reset released)

RESET (reset asserted)

RESET Rising Threshold

RESET Falling Threshold

RESET Threshold Hysteresis

RESET Active Timeout Period (Note 8)

ISL6410, ISOURCE = 500µA, VIN = 2.90V

0.8V

0.3

2.81

2.79

ISL6410, ISINK = 1.2mA, VIN = 2.50V

ISL6410

2.74

2.72

2.78

2.77

ISL6410

ISL6410A, ISOURCE = 800µA, VIN = 4.70V

0.8V

ISL6410A, ISINK = 3.2mA, VIN = 4.10V

0.4

4.64

4.61

ISL6410A

ISL6410

4.5

4.58

4.55

4.47

ISL6410A

CT = 0.01mF

SET

High Level Input

Low Level Input

Open Level Input

-0.4V

0.4

NOTES:

6. Specifications at -40°C and +85°C are guaranteed by design, not production tested.

7. Guaranteed by design, not production tested.

8. The RESET Timeout period is linear with C at a slope of 2.5ms/nF, thus a 10nF capacitor provides for 25ms.

ISL6410, ISL6410A

efficiency and reduced number of external components.

Pin Description

Operating frequency of 750kHz typical allows the use of

small inductor and capacitor values. The device can be

synchronized to an external clock signal in the range of

500kHz to 1MHz. The PG output indicates loss of regulation

on PWM output.

VIN - Supply voltage for the IC. It is recommended to place a

1µF decoupling capacitor as close as possible to the IC.

GND - Small signal ground for the PWM controller stage. All

internal control circuits are referenced to this pin.

PG - The Power good is an open-drain output. A pull-up

resistor should be connected between PG and VIN. It is

asserted active high when the output voltage reaches

94.5% of the nominal value.

The PWM is based on the peak current mode control

topology with internal slope compensation. At the beginning

of each clock cycle, the high side P-channel MOSFET is

turned on. The current in the inductor ramps up and is

sensed via an internal circuit. On exceeding a preset limit the

high side switch is turned off causing the PWM comparator

to trip. This occurs whenever the output voltage is in

regulation or when the inductor current reaches the current

limit. After a minimum dead time to prevent shoot through

current, the low side N-channel MOSFET turns on and the

current ramps down. As the clock cycle is completed, the low

side switch turns off and the next clock cycle is initiated.

FB - The Feedback pin is used to sense the output voltage,

and should be connected to VOUT for normal operation.

VSET - This pin is used to program the output voltages.

Refer to Table 1 below for details.

TABLE 1.

ISL6410

ISL6410A

VSET

High

1.8V

1.5V

1.2V

3.3V

1.8V

1.2V

The control loop is internally compensated thus reducing the

amount of external components.

Open (NC)

Low

The switch current is internally sensed and the maximum

current limit is 1300mA peak.

SYNC - This pin is used for synchronization. The converter

switching frequency can be synchronized to an external

CMOS clock signal in the range of (500kHz to 1MHz).

Synchronization

The typical operating frequency for the converter is 750kHz.

It is possible to synchronize the converter to an external

clock frequency in the range of 500kHz to 1000kHz when an

external signal is applied to SYNC pin. The device will

automatically detect and synchronize to the rising edge of

the first clock pulse. If the clock signal is stopped, the

converter automatically switches back to the internal clock

and continues its operation without interruption. The switch

over will be initiated if no rising edge triggers are present on

the SYNC pin for a duration of four clock cycles.

EN - A logic high enables the converter, logic low forces the

device into shutdown mode reducing the supply current to

less than 10µA at 25°C. This pin should be pulled up to VCC

via a 10K resistor.

L - This pin is the drain junction of the internal power

MOSFETs and is to be connected to the external inductor.

PGND - Power ground. Connect all power grounds to this pin.

PVCC - This pin provides the Input supply for the internal

MOSFETs. It is recommended to place a 1µF decoupling

capacitor as close as possible to the IC.

Soft-Start

As the EN (Enable) pin goes high, the soft-start function will

generate an internal voltage ramp. This causes the start-up

current to slowly rise preventing output voltage overshoot

and high inrush currents. The soft-start duration is typically

5.5ms with 750kHz switching frequency. When the soft-start

is completed, the error amplifier will be connected directly to

the internal voltage reference.

CT - Timing capacitor connection to set the 25ms minimum

pulse width for the RESET signal.

RESET - The outputs of the reset supervisory circuit, which

monitors VIN. The IC asserts these RESET signals

whenever the supply voltage drops below a preset threshold

and keeps it asserted for at least 25ms after VCC (VIN) has

risen above the reset threshold. These outputs are push-

pull. RESET is LOW when re-setting the microprocessor.

The PWM will continue to operate until VIN drops below the

UVLO threshold.

Enable

Logic low on EN pin forces the PWM section into shutdown.

In the shutdown mode all the major blocks of the PWM

including power switches, drivers, voltage reference, and

oscillator are turned off.

Undervoltage Lockout

Functional Description

An undervoltage lockout circuit prevents the converter from

turning on when the voltage on VIN is less than the values

specified in the Input UVLO Threshold section of the

electrical specification.

The ISL6410, ISL6410A is a synchronous buck regulator

with integrated N- and P-channel power MOSFET and

provides pre-set pin programmable outputs. Synchronous

rectification with internal MOSFETs is used to achieve higher

ISL6410, ISL6410A

Power Good

Input Capacitor Selection

This output is asserted high when the PWM is enabled, and

Vout is within 8.0% typical of its final value, and is active low

outside this range. When disabled, the output turns active

low. It is recommended to leave the PG pin unconnected

when not used.

The input current to the buck converter is pulsed, and

therefore a low ESR input capacitor is required. This results

in good input voltage filtering and minimizes the interference

it causes to other circuits. The input capacitor should have a

minimum value of 10µF and a higher value can be selected

for improving input voltage filtering. The input capacitor

should be rated for the maximum input ripple current

calculated as:

PWM Overvoltage and Overcurrent Protection

The PWM output current is sampled at the end of each PWM

cycle, exceeding the overcurrent limit, causes a 4 bit

up/down counter to increment by one LSB. A normal current

state causes the counter to decrement by one LSB (the

counter will not however “rollover” or count below 0000).

When the PWM goes into overcurrent, the counter rapidly

reaches count 1111 and the PWM output is shut down and

the soft-start counter is reset. After 16 clocks the PWM

output is enabled and the soft-start cycle is started.







---------

= Io(max) ×

× 1 – ---------

RMS



Vin

The worst case RMS ripple current occurs at D = 0.5 and is

calculated as: Irms = Io/2.

D = Duty Cycle

Ceramic capacitors are preferred because of their low ESR

value. They are also less sensitive to voltage transients

when compared to tantalum capacitors. It is good practice to

place the input capacitor as close as possible to the input pin

of the IC for optimum performance.

If Vout exceeds the overvoltage limit for 32 consecutive clock

cycles the PWM output is shut off and the soft-start cycle is

initiated.

No Load Operation

If there is no load connected to the output, the converter will

regulate the output voltage by allowing the inductor current

to reverse for a short period of time.

Inductor Selection

The ISL6410 is an internally compensated device and hence

a minimum of 8.2µH must be used for the ISL6410 and a

minimum of 12µH for the ISL6410A. The selected inductor

must have a low DC resistance and a saturation current

greater than the maximum inductor current value can be

calculated from the equations below

Output Capacitor Selection

For best performance, a low ESR output capacitor is

needed. Output voltages below 1.8V require a larger output

capacitor and ESR value to improve the performance and

stability of the converter. For 1.8V output applications, a

ceramic capacitor of 10µF or higher value with ESR ≤50mΩ

is recommended.

1 – --------

Vin

------------------

dIL = Vo ×

L × f

The RMS ripple current is calculated as:

dIL

IL max = Io max + --------

1 – --------

Vin

2 ×

------------------ ----------------

= Vo ×

RMS(Co)

L × f

where

dIL = the peak to peak inductor current

L = the inductor value

f = the switching frequency

L = the inductor value

f = the switching frequency

ILmax = the max inductor current

The overall output ripple voltage is the sum of the voltage spike

caused by the output capacitor ESR and the voltage ripple

caused by charge and discharge of the output capacitor:

TABLE 3. RECOMMENDED INDUCTORS

COMPONENT

SUPPLIER

INDUCTOR VALUE

DCR (mΩ)

1 – --------

Vin





------------------

∆Vo = Vo ×

------------------------- + ESR

 

8.2µH

Coilcraft

MSS6122-822MX

L × f

8 × Co × f

12µH

100

Coilcraft

MSS6122-123MX

Where the highest output voltage ripple occurs at the highest

input voltage VIN.

TABLE 2. RECOMMENDED OUTPUT CAPACITORS

CAPACITOR ESR

COMPONENT

SUPPLIER

VALUE

(mΩ)

COMMENTS

10µF

<50 AVX 08056D106KAT2A

Ceramic

ISL6410, ISL6410A

Layout Considerations

As in all switching power supplies, the layout is an important

step in the design process, more so at high peak currents

and switching frequencies. Improper layout practice will give

rise to Stability and EMI issues. It is recommended that wide

and short traces are used for the main current paths. The

input capacitor should be placed as close as possible to the

IC pins. This applies to the output inductor and capacitor as

well. The analog ground, GND, and the power ground,

PGND, need to be separated. Use a common ground node

to minimize the effects of ground noise.

Performance Curves and Waveforms

100

VOUT = 1.8V

IOUT = 200mA

VOUT = 1.5V

VOUT = 1.2V

IOUT = 600mA

2.9

3.1

3.3

3.5

100

1000

IOUT LOAD CURRENT (mA)

VIN INPUT VOLTAGE (V)

FIGURE 4. ISL6410 EFFICIENCY vs LOAD CURRENT

FIGURE 5. ISL6410 VIN vs EFFICIENCY

100

VOUT = 3.3V

VOUT = 1.8V

IOUT = 200mA

IOUT = 600mA

VOUT = 1.2V

100

1000

4.6

4.4

4.8

5.0

VIN (V)

5.2

5.6

5.4

IOUT LOAD CURRENT (mA)

FIGURE 6. ISL6410A EFFICIENCY vs LOAD CURRENT

FIGURE 7. ISL6410A EFFICIENCY vs VIN

ISL6410, ISL6410A

Performance Curves and Waveforms (Continued)

800

790

780

770

760

750

780

770

760

750

740

730

-15

-40

TEMPERATURE (°C)

FIGURE 8. ISL6410 OSCILLATOR FREQUENCY vs

TEMPERATURE

FIGURE 9. ISL6410A OSCILLATOR FREQUENCY vs

TEMPERATURE

CH1 = Top, CH2 = Middle, CH4 = Bottom, where applicable

VOUT

L PIN VOLTAGE

L1 CURRENT

L PIN VOLTAGE

L1 CURRENT

VIN = 5.0V, VOUT = 1.2V, IOUT = 0.5A

0.5µs/DIV

CH1 = 0.1V/DIV, CH2 = 2V/DIV CH4 = 200mA/DIV

FIGURE 10. SWITCHING WAVEFORM FOR ISL6410

FIGURE 11. SWITCHING WAVEFORM FOR ISL6410A

VOUT

IOUT

VIN = 3.3V, VOUT = 1.2V

VIN = 5.0V, VOUT = 1.2V

0.5ms/DIV

CH1 = 0.2V/DIV, CH4 = 200mA/DIV

0.5ms/DIV

CH1 = 0.1V/DIV, CH4 = 200mA/DIV

FIGURE 12. TRANSIENT LOAD WAVEFORM FOR ISL6410

FIGURE 13. TRANSIENT LOAD WAVEFORM FOR ISL6410A

ISL6410, ISL6410A

Performance Curves and Waveforms (Continued)

VOUT

VIN = 3.3V, VOUT = 1.2V

VIN = 5.0V, VOUT = 1.2V

1µs/DIV

CH1 = 20mV/DIV

FIGURE 14. RIPPLE WAVEFORM FOR ISL6410

FIGURE 15. RIPPLE WAVEFORM FOR ISL6410A

-40

-50

-40

-50

VIN = 5.0V, VOUT = 1.2V

VIN = 3.3V, VOUT = 1.2V

-60

-70

-80

-90

-100

-110

-120

-100

-110

-120

NOISE LEVEL 732kHz = -65.3dBm

CENTER 2.75MHz, SPAN = 4.5MHz

NOISE LEVEL 761kHz = -54.0dBm

CENTER 2.75MHz, SPAN = 4.5MHz

FIGURE 16. SWITCHING HARMONICS AND NOISE FOR

ISL6410

FIGURE 17. SWITCHING HARMONICS AND NOISE FOR

ISL6410A

ISL6410, ISL6410A

Quad Flat No-Lead Plas tic Package (QFN)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

Micro Lead Frame Plas tic Package (MLFP)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

0.80

0.90

0.20 REF

0.23

1.95

0.28

0.35

2.25

5, 8

4.00 BSC

3.75 BSC

2.10

7, 8

4.00 BSC

3.75 BSC

2.10

7, 8

0.65 BSC

0.25

0.50

0.60

0.75

0.15

0.60

Rev. 5 5/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

ISL6410, ISL6410A

Mini Small Outline Plas tic Packages (MSOP)

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-B-

0.20 (0.008)

INDEX

AREA

1 2

TOP VIEW

4X θ

0.25

(0.010)

GAUGE

PLANE

SEATING

PLANE

0.020 BSC

0.50 BSC

-C-

4X θ

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

SEATING

PLANE

0.037 REF

0.95 REF

0.10 (0.004)

-A-

-H-

0.003

0.07

0.20 (0.008)

SIDE VIEW

-B-

Rev. 0 12/02

0.20 (0.008)

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

ISL6410AIR-TK [INTERSIL]

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