ISL6420AIRZ-TK_技术文档

ISL6420A

®

Data Sheet

October 13, 2005

FN9169.1

Advanced Single Synchronous Buck

Features

• Operates from 4.5V to 28V Input

Pulse-Width Modulation (PWM) Controller

The ISL6420A simplifies the implementation of a complete

control and protection scheme for a high-performance

DC/DC buck converter. It is designed to drive N-channel

MOSFETs in a synchronous rectified buck topology, the

ISL6420A integrates control, output adjustment, monitoring

and protection functions into a single package. Additionally,

the IC features an external reference voltage tracking mode

for externally referenced buck converter applications and

DDR termination supplies, as well as a voltage margining

mode for system testing in networking DC/DC converter

applications.

• Excellent Output Voltage Regulation

- 0.6V Internal Reference

- ±1.0% Reference Accuracy Over Line and Temperature

• Resistor-Selectable Switching Frequency

- 100kHz to 1.4MHz

• Voltage Margining and External Reference Tracking

Modes

• Output Can Sink or Source Current

• Lossless, Programmable Overcurrent Protection

- Uses Upper MOSFET’s r

DS(ON)

The ISL6420A provides simple, single feedback loop,

voltage mode control with fast transient response. The

output voltage of the converter can be precisely regulated to

as low as 0.6V, with a maximum tolerance of ±1.0% over

temperature and line voltage variations.

• Programmable Soft-Start

• Drives N-Channel MOSFETs

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

The operating frequency is fully adjustable from 100kHz to

1.4MHz. High frequency operation offers cost and space

savings.

• Fast Transient Response

- High-Bandwidth Error Amplifier

- Full 0% to 100% Duty Cycle

The error amplifier features a 15MHz gain-bandwidth

product and 6V/µs slew rate that enables high converter

bandwidth for fast transient response. The PWM duty cycle

ranges from 0% to 100% in transient conditions. Selecting

the capacitor value from the ENSS pin to ground sets a fully

adjustable PWM soft-start. Pulling the ENSS pin LOW

disables the controller.

• Extensive Circuit Protection Functions

- PGOOD, Overvoltage, Overcurrent, Shutdown

• Diode Emulation during Startup for Pre-Biased Load

Applications

• Offered in 20 Ld QFN and QSOP Packages

• QFN (4x4) Package

- QFN compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

The ISL6420A monitors the output voltage and generates a

PGOOD (power good) signal when soft-start sequence is

complete and the output is within regulation. A built-in

overvoltage protection circuit prevents the output voltage

from going above typically 115% of the set point. Protection

from overcurrent conditions is provided by monitoring the

• Pb-Free Plus Anneal Available (RoHS Compliant)

r

of the upper MOSFET to inhibit the PWM operation

DS(ON)

appropriately. This approach simplifies the implementation

and improves efficiency by eliminating the need for a current

sensing resistor.

Applications

• Power Supplies for Microprocessors/ASICs

- Embedded Controllers

- DSP and Core Processors

- DDR SDRAM Bus Termination

• Ethernet Routers and Switchers

• High-Power DC/DC Regulators

• Distributed DC/DC Power Architecture

• Personal Computer Peripherals

• Externally Referenced Buck Converters

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6420A

Ordering Information

PART

TEMP.

PKG.

PART NUMBER

ISL6420AIAZ (Note)

MARKING

RANGE (°C)

-40 to +85

PACKAGE

DWG. #

6420AIAZ

20 Ld QSOP (Pb-free)

M20.15

ISL6420AIAZ-TK (Note)

ISL6420AIRZ (Note)

6420AIAZ

6420AIRZ

20 Ld QSOP (Pb-free) Tape and Reel

20 Ld 4x4 QFN (Pb-free)

M20.15

L20.4x4

ISL6420AIRZ-TK (Note)

20 Ld 4x4 QFN (Pb-free) Tape and Reel

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Pinouts

ISL6420A (QFN)

ISL6420A (QSOP)

TOP VIEW

1

2

3

4

5

6

7

8

9

PGOOD

ENSS

CDEL

PGND

20

19

20 19 18 17 16

LGATE

18 COMP

17 FB

PVCC

GPIO2

GPIO1/REFIN

OCSET

1

2

3

4

5

15 PGND

14 CDEL

13 PGOOD

12 ENSS

11 COMP

PHASE

16 RT

UGATE

SGND

15

BOOT

14 VIN

13 VCC5

12

GPIO2

REFOUT

GPIO1/REFIN

VMSET/MODE

OCSET 10

11 REFOUT

6

7

8

9

10

FN9169.1

2

October 13, 2005

ISL6420A

Functional Block Diagram

VIN

VCC5

OCSET

PHASE

SGND

LDO

OVERCURRENT

COMP

+

-

OCFLT

BOOT

REFERENCE

0.6V

SS

UGATE

OVFLT

UVFLT

FAULT

LOGIC

PHASE

ERROR

AMP

PHASE

LOGIC

+

-

FB

COMP

PWM

-

PWM

LOGIC

PVCC

LGATE

PGND

COMP

GPIO1/REFIN

GPIO2

RAMP

GENERATOR

REFOUT

VOLTAGE

MARGINING

VMSET/MODE

OV/UV

OVFLT

UVFLT

FB

PGOOD

CDEL

VOLTAGE

MONITOR

EN/SS

ENSS

OSC

RT

Typical 5V Input DC/DC Application Schematic

5V

C6

C1

C3

C2

C5

R1

C4

PVCC

VIN

VCC5

D1

C9

OCSET

BOOT

MONITOR AND

PROTECTION

ENSS

RT

Q1

UGATE

PHASE

PGOOD

CDEL

OSC

C7

0.1µF

R2

C8

L1

REF

3.3V

SGND

FB

Q2

LGATE

PGND

C10

-

+

-

+

-

R3

COMP

GPIO1/REFIN

GPIO2

C11

R6

REFOUT

C12

R5

C13

R4

VMSET/MODE

FN9169.1

October 13, 2005

3

ISL6420A

Typical 12V Input DC/DC Application Schematic

12V

C6

C1

C5

R1

C3

C2

C4

VIN PVCC

VCC5

D1

C9

OCSET

MONITOR AND

PROTECTION

ENSS

BOOT

RT

PGOOD

CDEL

Q1

UGATE

PHASE

OSC

R2

C8

C7

L1

REF

3.3V

SGND

FB

Q2

LGATE

PGND

-

+

-

C10

+

-

R3

COMP

GPIO1/REFIN

GPIO2

C11

R6

REFOUT

C13

C12

R5

R4

VMSET/MODE

Typical 5V Input DC/DC Application Schematic

5V

C6

C1

C3

C5

R1

C2

C4

D1

C8

PVCC

VIN

VCC5

OCSET

MONITOR AND

PROTECTION

SS/EN

BOOT

RT

CDEL

Q1

UGATE

PHASE

OSC

R2

C7

L1

PGOOD

REF

2.5V/1.25V

SGND

FB

Q2

LGATE

PGND

-

+

-

C9

+

-

R3

COMP

GPIO1/REFIN <-- VREF = VDDQ/2

GPIO2

C10

C11

REFOUT

R5

1.25V VREF

TO REFIN OF VTT SUPPLY

C12

VMSET/MODE

VCC5

R4

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

FN9169.1

October 13, 2005

4

ISL6420A

Typical 12V Input DC/DC Application Schematic

12V

C6

C1

C2

C3

C5

R1

C4

VIN PVCC

VCC5

D1

C8

OCSET

MONITOR AND

PROTECTION

SS/EN

BOOT

RT

CDEL

Q1

UGATE

PHASE

OSC

R2

C7

L1

PGOOD

REF

2.5V/1.25V

VDDQ/VTT

SGND

FB

Q2

LGATE

PGND

-

+

-

C9

+

-

COMP

R3

GPIO1/REFIN <-- VREF = VDDQ/2

GPIO2

C10

C11

REFOUT

R5

1.25V VREF

TO REFIN OF VTT SUPPLY

C12

VMSET/MODE

VCC5

R4

CONFIGURATION FOR DDR TERMINATION/EXTERNALLY REFERENCED TRACKING APPLICATIONS

FN9169.1

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October 13, 2005

ISL6420A

Absolute Maximum Ratings (Note 1)

Thermal Information

Thermal Resistance (Typical)

QFN Package (Notes 2, 3). . . . . . . . . .

QSOP Package (Note 2) . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Ambient Temperature Range. . . . . . . . . -40°C to 85°C (for “I” suffix)

Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C

Bias Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V

BOOT and Ugate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +36V

ESD Classification

Human Body Model (JESD22 - A114) . . . . . . . . . . . . . . . . . 2000V

Charged Device Model (JESD22 - C101) . . . . . . . . . . . . . . 1000V

θ

(°C/W)

47

90

θ

(°C/W)

JC

8.5

NA

JA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. All voltages are with respect to GND.

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PV

shorted with V

, T = 25°C

CC5

CC

A

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VIN SUPPLY

Input Voltage Range

5.6

12

28

V

VIN SUPPLY CURRENT

Shutdown Current (Note 4)

Operating Current (Notes 4, 5)

VCC5 SUPPLY (Notes 5, 6)

Input Voltage Range

ENSS = GND

-

1.4

2.0

-

mA

3.0

VIN = VCC5 for 5V configuration

4.5

50

5.0

-

5.5

-

V

Output Voltage

VIN = 5.6V to 28V, I = 3mA to 50mA

L

Maximum Output Current

POWER-ON RESET

VIN = 12V

mA

Rising V

CC5

Threshold

VIN connected to VCC5, 5V input

operation

4.310

4.400

4.475

V

Falling V

CC5

Threshold

4.090

0.16

4.100

-

4.250

-

V

UVLO Threshold Hysteresis

PWM CONVERTERS

Min Output Voltage (Note 7)

Max Output Voltage (Note 7)

Maximum Duty Cycle

-

0.6

-

V

- 0.5

IN

96

F = 300kHz

90

-

%

nA

%

Minimum Duty Cycle

-

80

-

0

-

FB Pin Bias Current

-

Undervoltage Protection

V

Fraction of the set point; ~3µs noise filter

Fraction of the set point; ~1µs noise filter

75

85

UV1

Overvoltage Protection

OSCILLATOR

V

112

-

120

%

OVP1

Free Running Frequency

Total Variation

RT = VCC5, T = -40°C to 85°C

270

-

300

330

-

kHz

%

A

T = -40°C to 85°C, with frequency set by

A

±10%

external resistor at RT

VIN = 12V

Frequency Range (Set by RT)

Ramp Amplitude (Note 7)

100

-

1400

-

kHz

∆V

1.25

V

P-P

OSC

FN9169.1

October 13, 2005

6

ISL6420A

Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PV

shorted with V

, T = 25°C (Continued)

CC5

CC

A

PARAMETER

REFERENCE AND SOFT-START/ENABLE

Internal Reference Voltage

Reference Voltage Accuracy

Soft-Start Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

-

-1.0

-

0.600

-

+1.0

-

V

%

µA

V

REF

T

= -40°C to 85°C, VIN = 5.6V to 28V

-

10

-

A

I

SS

Soft-Start Threshold

V

1.0

-

SOFT

Enable Low (Converter disabled)

PWM CONTROLLER GATE DRIVERS

Gate Drive Peak Current

Rise Time

-

1.0

V

-

0.7

20

-

A

Co = 1000pF

ns

Fall Time

Dead Time Between Drivers

ERROR AMPLIFIER

DC Gain (Note 7)

-

88

15

6

-

dB

Gain-Bandwidth Product (Note 7)

Slew Rate (Note 7)

GBW

SR

MHz

V/µs

OVERCURRENT PROTECTION

OCSET Current Source

I

V

= 4.5V

OCSET

80

-

100

20

120

µA

ms

OCSET

Dynamic Current Limit ON time

Dynamic Current Limit OFF time

POWER GOOD AND CONTROL FUNCTIONS

Power-Good Lower Threshold

Power-Good Higher Threshold

PGOOD Leakage Current

PGOOD Voltage Low

T

Frequency = 300kHz

-

OCON

T

-

128

OCOFF

V

Fraction of the set point; ~3µs noise filter

-14

-10

-8

16

1

%

PG-

V

9

-

PG+

I

V

= 5.5V

µA

V

PGLKG

PULLUP

= 4mA

I

-

0.5

-

PGOOD

PGOOD Delay

CDEL = 0.1µF

-

125

2

ms

µA

V

CDEL Current for PGOOD

CDEL Threshold

CDEL threshold = 2.5V

-

2.5

-

EXTERNAL REFERENCE

MIn External Reference Input at

GPIO1/REFIN.

VMSET/MODE = H, C

= 2.2µF

-

0.600

-

V

REFOUT

Max External Reference Input at

GPIO1/REFIN.

1.250

REFERENCE BUFFER

Buffered Output Voltage - Internal Reference

V

I

= 1mA,

REFOUT

0.583

0.575

1.227

0.595

0.587

1.246

0.607

0.599

1.265

V

REFOUT

VMSET/MODE = High,

C

= 2.2µF, T = -40°C to 85°C

REFOUT

A

Buffered Output Voltage - Internal Reference

Buffered Output Voltage - External Reference

I

= 20mA,

REFOUT

VMSET/MODE = High,

C

= 2.2µF, T = -40°C to 85°C

A

REFOUT

V

= 1.25V, I

= 1mA,

REFIN

REFOUT

VMSET2/MODE = High,

= 2.2µF

C

REFOUT

FN9169.1

7

October 13, 2005

ISL6420A

Electrical Specifications Operating Conditions, Unless Otherwise Noted: VIN = 12V, PV

shorted with V

MIN

, T = 25°C (Continued)

CC5

CC

A

PARAMETER

SYMBOL

TEST CONDITIONS

TYP

MAX

UNITS

Buffered Output Voltage - External Reference

V

= 1.25V, I = 20mA,

1.219

1.238

1.257

V

REFOUT

REFIN

REFOUT

VMSET2/MODE = High,

C

= 2.2µF

REFOUT

Current Drive Capability

VOLTAGE MARGINING

Voltage Margining Range (Note 7)

CDEL Current for Voltage Margining

Slew Time

C

= 2.2µF

20

-

mA

REFOUT

-10

-

+10

%

-

100

2.5

-

µA

ms

µA

CDEL = 0.1µF, VMSET = 330kΩ

ISET1 on FB Pin

VMSET = 330K,

GPIO1 = L

GPIO2 = H

7.48

ISET2 on FB Pin

VMSET = 330K,

GPIO1 = H

GPIO2 = L

-

7.48

-

µA

THERMAL SHUTDOWN

Shutdown Temperature (Note 7)

Thermal Shutdown Hysteresis (Note 7)

NOTES:

-

150

20

-

°C

4. The operating supply current and shutdown current specifications for 5V input are the same as VIN supply current specifications, i.e., 5.6V to

28V input conditions. These should also be tested with part configured for 5V input configuration, i.e., VIN = VCC5 = PVCC = 5V.

5. This is the V

current consumed when the device is active but not switching. Does not include gate drive current.

CC

6. When the input voltage is 5.6V to 28V at VIN pin, the VCC5 pin provides a 5V output capable of 50mA (max) total from the internal LDO. When

the input voltage is 5V, VCC5 pin will be used as a 5V input, the internal LDO regulator is disabled and the VIN must be connected to the VCC5.

In both cases the PVCC pin should always be connected to VCC5 pin. (Refer to the Pin Descriptions sections for more details.)

7. Guaranteed by design. Not production tested.

Typical Performance Curves

0.604

0.602

0.600

0.598

0.596

0.594

320

310

300

290

280

270

-40

-15

10

35

60

85

-40

-15

10

35

60

85

TEMPERATURE (°C)

FIGURE 1. V

vs TEMPERATURE

FIGURE 2. V

vs TEMPERATURE

SW

REF

FN9169.1

8

October 13, 2005

ISL6420A

Typical Performance Curves (Continued)

94.00

92.00

90.00

88.00

86.00

84.00

82.00

80.00

1.15

1.05

I

= 5A

OUT

0.95

0.85

0

5

10

15

(V)

20

25

30

-40

-15

10

35

60

85

V

TEMPERATURE (°C)

IN

FIGURE 3. I

vs TEMPERATURE

FIGURE 4. EFFICIENCY vs V

IN

OCSET

25°C, V = 28V, I = 1.367, I

= 10A

IN

OUT

FIGURE 5.

FIGURE 6.

98

V

= 5V

IN

96

94

92

90

88

86

84

82

80

V

= 12V

IN

0

1

2

3

4

5

6

7

8

9

10

LOAD (A)

FIGURE 7. EFFICIENCY vs LOAD CURRENT (V

= 3.3V)

OUT

FN9169.1

9

October 13, 2005

ISL6420A

Pin Descriptions

1400

1300

1200

1100

1000

900

800

700

600

500

400

300

200

100

0

VIN - This pin powers the controller and must be decoupled

to ground using a ceramic capacitor as close as possible to

the VIN pin.

TABLE 1. INPUT SUPPLY CONFIGURATION

INPUT

PIN CONFIGURATION

5.6V to 28V

Connect the input to the VIN pin. The VCC5

pin will provide a 5V output from the internal

LDO. Connect PVCC to VCC5.

5V ±10%

Connect the input to the VCC5 pin. Connect

the PVCC and VIN pins to VCC5.

0

25

50

75

RT (kΩ)

100

125

150

SGND - This pin provides the signal ground for the IC. Tie

this pin to the ground plane through the lowest impedance

connection.

FIGURE 8. OSCILLATOR FREQUENCY vs RT

PGND - This pin provides the power ground for the IC. Tie

this pin to the ground plane through the lowest impedance

connection.

LGATE - This pin provides the PWM-controlled gate drive for

the lower MOSFET.

PHASE - This pin is the junction point of the output filter

inductor, the upper MOSFET source and the lower MOSFET

drain. This pin is used to monitor the voltage drop across the

upper MOSFET for overcurrent protection. This pin also

provides a return path for the upper gate drive.

PVCC - This pin is the power connection for the gate drivers.

Connect this pin to the VCC5 pin.

VCC5 – This pin is the output of the internal 5V LDO.

Connect a minimum of 4.7µF ceramic decoupling capacitor

as close to the IC as possible at this pin. Refer to Table 1.

UGATE - This pin provides the PWM-controlled gate drive

for the upper MOSFET.

ENSS - This pin provides enable/disable function and soft-

start for the PWM output. The output drivers are turned off

when this pin is held below 1V.

BOOT - This pin powers the upper MOSFET driver. Connect

this pin to the junction of the bootstrap capacitor and the

cathode of the bootstrap diode. The anode of the bootstrap

diode is connected to the VCC5 pin.

OCSET - Connect a resistor (ROCSET) from this pin to the

drain of the upper MOSFET. ROCSET, an internal 100µA

current source (IOCS), and the upper MOSFET on

FB - This pin is connected to the feedback resistor divider

and provides the voltage feedback signal for the controller.

This pin sets the output voltage of the converter.

resistance r

set the converter overcurrent (OC) trip

point according to the following equation:

DS(ON)

I

• R

OCSET

OCSSET

(EQ. 1)

COMP - This pin is the error amplifier output pin. It is used as

the compensation point for the PWM error amplifier.

I

= ------------------------------------------------------

OC

R

DS(ON)

PGOOD - This pin provides a power good status. It is an

open collector output used to indicate the status of the

output voltage.

An overcurrent trip cycles the soft-start function with an ON

time of 20ms and an OFF time of 128ms.

GPIO1/REFIN - This is a dual function pin. If VMSET/MODE

is not connected to VCC5 then this pin serves as GPIO1.

Refer to Table 2 for GPIO commands interpretation.

RT - This is the oscillator frequency selection pin.

Connecting this pin directly to VCC5 will select the oscillator

free running frequency of 300kHz. By placing a resistor from

this pin to GND, the oscillator frequency can be programmed

from 100kHz to 1.4MHz. Figure 8 shows the oscillator

frequency vs the RT resistance.

If VMSET/MODE is connected to VCC5 then this pin will

serve as REFIN. As REFIN, this pin is the non-inverting input

to the error amplifier. Connect the desired reference voltage

to this pin in the range of 0.6V to 1.25V.

CDEL - The PGOOD signal can be delayed by a time

proportional to a CDEL current of 2µA & the value of the

capacitor connected between this pin and ground. A 0.1µF

will typically provide 125ms delay. When in the Voltage

margining mode the CDEL current is 100µA typical and

provides the delay for the output voltage slew rate, 2.5ms

typical for the 0.1µF capacitor.

Connect this pin to VCC5 to use internal reference.

REFOUT - If VMSET/MODE pin is connected to VCC5, then

this pin serves as REFOUT. It provides buffered reference

output for REFIN. Connect 2.2µF capacitor to this pin when

used as REFOUT. If not used to source current, connect a

1µF bypass capacitor to this pin.

FN9169.1

10

October 13, 2005

ISL6420A

VMSET/MODE - This pin is a dual function pin. Tie this pin to

TABLE 2. VOLTAGE MARGINING CONTROLLED BY GPIO1

AND GPIO2

VCC5 to disable voltage margining. When not tied to VCC5,

this pin serves as VMSET. Connect a resistor from this pin to

ground to set delta for voltage margining. If voltage

margining and external reference tracking mode are not

needed, this pin can be tied directly to ground.

GPIO1

GPIO2

VOUT

L

H

L

No Change

+ Delta VOUT

- Delta VOUT

Ignored

H

GPIO2 - This is general purpose IO pin for voltage

margining. Refer to Table 2.

H

TABLE 3. VOLTAGE MARGINING/DDR OR TRACKING SUPPLY PIN CONFIGURATION

PIN CONFIGURATIONS

FUNCTION/MODES

VMSET/MODE

REFOUT

GPIO1/REFIN

GPIO2

COMMENTS

Enable Voltage Margining

Pin Connected Connect a 1µF

Serves as a general

Serves as a

REFIN or REFOUT functions

to GND with

resistor. It is

capacitor for

purpose I/O. Refer to general purpose will not be available in this

bypass of external Table 2

used as VMSET. reference.

I/O. Refer to

Table 2

mode. The internal 0.6V

reference is used.

No Voltage Margining. Normal

Pin Connected Connect a 1µF

L

operation using internal reference. to GND with

capacitor for

REFOUT not used.

resistor. It is

bypass of external

used as VMSET reference.

No Voltage Margining. Normal

operation with internal reference.

H

Connect a 2.2µF

capacitor to GND.

H

L

Buffered V

REFOUT

= 0.6V.

No Voltage Margining. External

reference. Buffered V

Connect a 2.2µF Connect to an external

capacitor to GND. reference voltage

source (0.6V to 1.25V)

=

REFOUT

V

REFIN

NOTES:

1. The GPIO1/REFIN and GPIO2 pins cannot be left floating.

2. Ensure that GPIO1/REFIN is tied high prior to the logic change at VMSET/MODE.

Functional Description

Initialization

When the ENSS pin voltage reaches 1V typically, the

internal 0.6V reference begins to charge following the dv/dt

of the ENSS voltage. As the soft-start pin charges from 1V to

1.6V, the reference voltage charges from 0V to 0.6V.

Figure 9 shows a typical soft-start sequence.

The ISL6420A automatically initializes upon receipt of

power. The Power-On Reset (POR) function monitors the

internal bias voltage generated from LDO output (VCC5) and

the ENSS pin. The POR function initiates the soft-start

operation after the VCC5 exceeds the POR threshold. The

POR function inhibits operation with the chip disabled

(ENSS pin <1V).

V

= 28V, V

= 3.3V, I

= 10A

OUT

IN

OUT

The device can operate from an input supply voltage of 5.6V

to 28V connected directly to the VIN pin using the internal 5V

linear regulator to bias the chip and supply the gate drivers.

For 5V ±10% applications, connect VIN to VCC5 to bypass

the linear regulator.

Soft-Start/Enable

The ISL6420A soft-start function uses an internal current

source and an external capacitor to reduce stresses and

surge current during startup.

When the output of the internal linear regulator reaches the

POR threshold, the POR function initiates the soft-start

sequence. An internal 10µA current source charges an

external capacitor on the ENSS pin linearly from 0V to 3.3V.

FIGURE 9. TYPICAL SOFT-START WAVEFORM

FN9169.1

October 13, 2005

11

ISL6420A

Overcurrent Protection

Voltage Margining

The overcurrent function protects the converter from a

The ISL6420A has a voltage margining mode that can be

used for system testing. The voltage margining percentage

is resistor selectable up to ±10%. The voltage margining

mode can be enabled by connecting a margining set resistor

from VMSET pin to ground and using the control pins

GPIO1/2 to toggle between positive and negative margining

(Refer to Table 2). With voltage margining enabled, the

VMSET resistor to ground will set a current, which is

switched to the FB pin. The current will be equal to 2.468V

divided by the value of the external resistor tied to the

VMSET pin.

shorted output by using the upper MOSFET’s on-resistance,

r

to monitor the current. This method enhances the

DS(ON)

converter’s efficiency and reduces cost by eliminating a

current sensing resistor.

The overcurrent function cycles the soft-start function in a

hiccup mode with an ON time of 20ms and an OFF time of

128ms to provide fault protection. On detecting an

overcurrent condition, the IC waits for four soft-start cycles

before the output drivers are turned ON again, this process

is repeated till the overcurrent condition is removed. A

resistor connected to the drain of the upper FET and the

OCSET pin programs the overcurrent trip level. The PHASE

node voltage will be compared against the voltage on the

OCSET pin, while the upper FET is on. A current (100µA

typically) is pulled from the OCSET pin to establish the

OCSET voltage. If PHASE is lower than OCSET while the

upper FET is on then an overcurrent condition is detected for

that clock cycle. The upper gate pulse is immediately

terminated, and a counter is incremented. If an overcurrent

condition is detected for 8 consecutive clock cycles, and the

circuit is not in soft-start, the ISL6420A enters into the soft-

start hiccup mode. During hiccup, the external capacitor on

the ENSS pin is discharged. After the cap is discharged, it is

released and a soft-start cycle is initiated. During soft-start,

pulse termination current limiting is enabled, but the 8-cycle

hiccup counter is held in reset until soft-start is completed.

2.468V

VMSET

I

= -----------------------

(EQ. 2)

VM

R

FB

-----------------------

∆V

= 2.468V

(EQ. 3)

VM

R

VMSET

The power supply output increases when GPIO2 is HIGH

and decreases when GPIO1 is HIGH. The amount that the

output voltage of the power supply changes with voltage

margining, will be equal to 2.468V times the ratio of the

external feedback resistor and the external resistor tied to

VMSET. Figure 10 shows the positive and negative

margining for a 3.3V output, using a 20.5kΩ feedback

resistor and using various VMSET resistor values.

3.7

3.6

3.5

3.4

3.3

3.2

3.1

The overcurrent function will trip at a peak inductor current

(I ) determined from Equation 1, where I

is the

OC

OCSET

internal OCSET current source.

The OC trip point varies mainly due to the upper MOSFETs

variations. To avoid overcurrent tripping in the

r

DS(ON)

normal operating load range, find the R

the equation above with:

resistor from

OCSET

3.0

2.9

1. The maximum r

temperature.

at the highest junction

DS(ON)

2.8

150 175 200 225 250 275 300 325 350 375 400

2. Determine I

for I

> I

+ (∆I) ⁄ 2 ,

OUT(MAX)

OC

where ∆I is t^Oh^Ce output inductor ripple current.

RVMSET (kΩ)

FIGURE 10. VOLTAGE MARGINING vs VMSET RESISTANCE

A small ceramic capacitor should be placed in parallel with

R

to smooth the voltage across R

in the

OCSET

presence of switching noise on the input voltage.

FN9169.1

12

October 13, 2005

ISL6420A

20mA and sinking up to 50µA current with a 2.2µF capacitor

connected to the REFOUT pin.

V

IN

= 12V, V = 3.3V, NO LOAD

OUT

If VMSET/MODE pin is tied to high but GPIO1/REFIN is

connected to an external voltage source between 0.6V to

1.25V, then this external voltage is used as the reference

voltage at the positive input of the error amplifier. The

buffered reference output on REFOUT will be Vrefin ±0.01V,

capable of sourcing 20mA and sinking up to 50µA current

with a 2.2µF capacitor on the REFOUT pin.

Power Good

The PGOOD pin can be used to monitor the status of the

output voltage. PGOOD will be true (open drain) when the

FB pin is within ±10% of the reference and the ENSS pin has

completed its soft-start ramp.

FIGURE 11A.

Additionally, a capacitor on the CDEL pin will set a delay for

the PGOOD signal. After the ENSS pin completes its soft-

start ramp, a 2µA current begins charging the CDEL

capacitor to 2.5V. The capacitor will be quickly discharged

before PGOOD goes high. The programmable delay can be

used to sequence multiple converters or as a LOW-true

reset signal.

V

IN

= 12V, V

= 3.3V, NO LOAD

OUT

V

= 12V, V

OUT

= 3.3V, I = 10A

OUT

IN

FIGURE 11B.

The slew time of the current is set by an external capacitor

on the CDEL pin, which is charged and discharged with a

100µA current source. The change in voltage on the

capacitor is 2.5V. This same capacitor is used to set the

PGOOD active delay after soft-start. When PGOOD is low,

the internal PGOOD circuitry uses the capacitor and when

PGOOD is high, the voltage margining circuit uses the

capacitor. The slew time for voltage margining can be in the

range of 300µs to 2ms.

FIGURE 12. PGOOD DELAY

If the voltage on the FB pin exceeds ±10% of the reference,

then PGOOD will go low after 1µs of noise filtering.

Over-Temperature Protection

External Reference/DDR Supply

The IC is protected against over-temperature conditions.

When the junction temperature exceeds 150°C, the PWM

shuts off. Normal operation is resumed when the junction

temperature is cooled down to 130°C.

The voltage margining can be disabled by connecting the

VMSET/MODE to VCC5. In this mode the chip can be

configured to work with an external reference input and

provide a buffered reference output.

If VMSET/MODE pin and the GPIO1/REFIN pin are both tied

to VCC5, then the internal 0.6V reference is used as the

error amplifier non-inverting input. The buffered reference

output on REFOUT will be 0.6V ±0.01V, capable of sourcing

Shutdown

When ENSS pin is below 1V, the regulator is disabled with

the PWM output drivers three-stated. When disabled, the IC

power will be reduced.

FN9169.1

13

October 13, 2005

ISL6420A

Undervoltage

V

= 12V, V = 3.3V at 25mA LOAD

OUT

IN

If the voltage on the FB pin is less than 15% of the reference

voltage for 8 consecutive PWM cycles, then the circuit enters

into soft-start hiccup mode. This mode is identical to the

overcurrent hiccup mode.

Overvoltage Protection

If the voltage on the FB pin exceeds the reference voltage by

15%, the lower gate driver is turned on continuously to

discharge the output voltage. If the overvoltage condition

continues for 32 consecutive PWM cycles, then the chip is

turned off with the gate drivers three-stated. The voltage on

the FB pin will fall and reach the 15% undervoltage

threshold. After 8 clock cycles, the chip will enter soft-start

hiccup mode. This mode is identical to the overcurrent

hiccup mode.

FIGURE 13. PREBIASED OUTPUT AT 25mA LOAD

Gate Control Logic

The gate control logic translates generated PWM control

signals into the MOSFET gate drive signals providing

necessary amplification, level shifting and shoot-through

protection. Also, it has functions that help optimize the IC

performance over a wide range of operational conditions.

Application Guidelines

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Since MOSFET switching time can vary dramatically from

type to type and with the input voltage, the gate control logic

provides adaptive dead time by monitoring the gate-to-

source voltages of both upper and lower MOSFETs. The

lower MOSFET is not turned on until the gate-to-source

voltage of the upper MOSFET has decreased to less than

approximately 1V. Similarly, the upper MOSFET is not turned

on until the gate-to-source voltage of the lower MOSFET has

decreased to less than approximately 1V. This allows a wide

variety of upper and lower MOSFETs to be used without a

concern for simultaneous conduction, or shoot-through.

V

IN

ISL6420A

Startup into Pre-Biased Load

The ISL6420A is designed to power up into a pre-biased

load. This is achieved by transitioning from Diode Emulation

mode to a Forced Continuous Conduction mode during

startup. The lower gate turns ON for a short period of time

and the voltage on the phase pin is sensed. When this goes

negative the lower gate is turned OFF and remains OFF till

the next cycle. As a result the inductor current will not go

negative during soft-start and thus will not discharge the pre-

biased load. The waveform for this condition is shown below.

UGATE

PHASE

Q1

Q2

L

O

V

OUT

C

IN

C

D2

O

LGATE

GND

RETURN

FIGURE 14. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

FN9169.1

October 13, 2005

14

ISL6420A

Figure 14 shows the critical power components of the

converter. To minimize the voltage overshoot the

Feedback Compensation

Figure 16 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(Vout) is regulated to the Reference voltage level. The error

interconnecting wires indicated by heavy lines should be part

of ground or power plane in a printed circuit board. The

components shown in Figure 14 should be located as close

amplifier (Error Amp) output (V ) is compared with the

E/A

together as possible. Please note that the capacitors C

IN

oscillator (OSC) triangular wave to provide a pulse-width

and C each represent numerous physical capacitors.

O

modulated (PWM) wave with an amplitude of V at the

IN

Locate the ISL6420A within 3 inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the ISL6420A must be sized to

handle up to 2A peak current.

PHASE node. The PWM wave is smoothed by the output filter

(L and C ).

O

The modulator transfer function is the small-signal transfer

function of Vout/V . This function is dominated by a DC

E/A

Gain and the output filter (L and C ), with a double pole

Figure 15 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

O

break frequency at F and a zero at F

LC

. The DC Gain of

ESR

the modulator is simply the input voltage (V ) divided by the

IN

current paths on the SS PIN and locate the capacitor, C

ss

peak-to-peak oscillator voltage DV

.

OSC

close to the SS pin because the internal current source is

only 30µA. Provide local V decoupling between VCC and

CC

V

IN

GND pins. Locate the capacitor, C

to the BOOT and PHASE pins.

as close as practical

OSC

BOOT

DRIVER

PWM

L

O

COMPARATOR

V

OUT

-

DRIVER

+V

Q1

PHASE

IN

+

∆V

OSC

BOOT

D1

C

O

C

L

O

BOOT

PHASE

+5V

ESR

(PARASITIC)

V

OUT

ISL6420A

Z

FB

SS/EN

V

E/A

C

Q2

O

Z

-

IN

+

VCC

REFERENCE

ERROR

AMP

C

VCC

C

SS

GND

DETAILED COMPENSATION COMPONENTS

FIGURE 15. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

Z

FB

V

OUT

C2

Z

IN

C1

C3

R3

R2

R1

COMP

FB

-

+

ISL6420A

REF

FIGURE 16. VOLTAGE - MODE BUCK CONVERTER

COMPENSATION DESIGN

FN9169.1

October 13, 2005

15

ISL6420A

Modulator Break Frequency Equations

100

F

P1

F

Z2

Z1

P2

1

F

= --------------------------------------

(EQ. 4)

(EQ. 5)

LC

80

60

40

20

0

2π •

L

• C

O

OPEN LOOP

ERROR AMP GAIN

1

F

= --------------------------------------------

ESR

2π • (ESR • C

)

20LOG

(R2/R1)

O

20LOG

IN

(V /∆V

)

OSC

The compensation network consists of the error amplifier

(internal to the ISL6420A) and the impedance networks Z

and Z . The goal of the compensation network is to provide

FB

a closed loop transfer function with the highest 0dB crossing

COMPENSATION

GAIN

IN

MODULATOR

GAIN

-20

-40

-60

CLOSED LOOP

GAIN

F

LC

frequency (f

) and adequate phase margin. Phase margin

F

0dB

ESR

is the difference between the closed loop phase at f

180°. The equations below relate the compensation

and

0dB

10

100

1K

10K

100K

1M

10M

FREQUENCY (Hz)

network’s poles, zeros and gain to the components (R1, R2,

R3, C1, C2, and C3) in Figure 16. Use these guidelines for

locating the poles and zeros of the compensation network:

FIGURE 17. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

The compensation gain uses external impedance networks

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

Compensation Break Frequency Equations

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin.

1

F

= ----------------------------------

(EQ. 6)

(EQ. 7)

Z1

2π • R2 • C1

1

F

= ------------------------------------------------------

2π • R2 •

P1

C1 • C2









Component Selection Guidelines

----------------------

C1 + C2

Output Capacitor Selection

1

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

F

= -----------------------------------------------------

(EQ. 8)

(EQ. 9)

Z2

P2

2π • (R1 + R3) • C3

1

----------------------------------

=

2π • R3 • C3

1. Pick Gain (R2/R1) for desired converter bandwidth

ST

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

2. Place 1 Zero Below Filter’s Double Pole

(~75% F

)

LC

ND

3. Place 2

Zero at Filter’s Double Pole

ST

4. Place 1 Pole at the ESR Zero

ND

5. Place 2

Pole at Half the Switching Frequency

6. Check Gain against Error Amplifier’s Open-Loop Gain

7. Estimate Phase Margin - Repeat if Necessary

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1.0µF

ceramic capacitors in the 1206 surface-mount package.

Figure 17 shows an asymptotic plot of the DC/DC

converter’s gain vs. frequency. The actual Modulator Gain

has a high gain peak due to the high Q factor of the output

filter and is not shown in Figure 17. Using the above

guidelines should give a Compensation Gain similar to the

curve plotted. The open loop error amplifier gain bounds the

compensation gain. Check the compensation gain at F

P2

with the capabilities of the error amplifier. The Closed Loop

Gain is constructed on the log-log graph of Figure 17 by

adding the Modulator Gain (in dB) to the Compensation Gain

(in dB). This is equivalent to multiplying the modulator

transfer function to the compensation transfer function and

plotting the gain.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

transient. An aluminum electrolytic capacitor's ESR value is

related to the case size with lower ESR available in larger

FN9169.1

16

October 13, 2005

ISL6420A

case sizes. However, the equivalent series inductance (ESL)

Input Capacitor Selection

of these capacitors increases with case size and can reduce

the usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current. A more specific equation for

determining the input ripple is the following,

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transients. The inductor value determines

the converter’s ripple current and the ripple voltage is a

function of the ripple current and the output capacitors ESR.

The ripple voltage and current are approximated by the

following equations:

V

- V

Fs x L

V

IN

OUT OUT

------------------------------- ---------------

∆I =

⋅

(EQ. 10)

(EQ. 11)

L

2

I

= I

⋅

(D – D )

(EQ. 14)

RMS

MAX

∆V

= ∆I ⋅ ESR

OUT

L

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

AVX, and the 593D series from Sprague are both surge

current tested.

Increasing the value of inductance reduces the ripple current

and voltage. However, larger inductance values reduce the

converter’s response time to a load transient.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6420A will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection/Considerations

The ISL6420A requires 2 N-Channel power MOSFETs.

These should be selected based upon r

, gate supply

DS(ON)

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

components; conduction loss and switching loss.

The conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor (see the equations below). Only the

upper MOSFET has switching losses, since the Schottky

rectifier clamps the switching node before the synchronous

rectifier turns on.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

L

V

× I

O

TRAN

t

= -------------------------------

(EQ. 12)

RISE

– V

OUT

IN

L

× I

O

TRAN

t

= ------------------------------

(EQ. 13)

is the

FALL

V

OUT

where: I

is the transient load current step, t

RISE

2

1

TRAN

response time to the application of load, and t

--

P

= I ⋅ R

⋅ D +

I

⋅ V ⋅ t ⋅ f

IN sw sw

(EQ. 15)

UFET

O

DS(ON)

O

2

is the

FALL

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

output voltage setting. Be sure to check both of these

equations at the minimum and maximum output levels for

the worst case response time.

2

P

= I ⋅ R

⋅ (1 – D)

(EQ. 16)

LFET

O

DS(ON)

Where D is the duty cycle = Vo/Vin, t

interval, and f

SW

is the switching

is the switching frequency.

SW

FN9169.1

17

October 13, 2005

ISL6420A

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the lower MOSFET’s body diode. The

gate-charge losses are dissipated by the ISL6420A and

don't heat the MOSFETs. However, large gate-charge

increases the switching interval, t

which increases the

SW

upper MOSFET switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at

high ambient temperature by calculating the temperature

rise according to package thermal-resistance specifications.

A separate heatsink may be necessary depending upon

MOSFET power, package type, ambient temperature and air

flow.

Schottky Selection

Rectifier D2 is a clamp that catches the negative inductor

swing during the dead time between turning off the lower

MOSFET and turning on the upper MOSFET. The diode must

be a Schottky type to prevent the parasitic MOSFET body

diode from conducting. It is acceptable to omit the diode and

let the body diode of the lower MOSFET clamp the negative

inductor swing, but efficiency will drop one or two percent as a

result. The diode's rated reverse breakdown voltage must be

greater than the maximum input voltage.

FN9169.1

18

October 13, 2005

ISL6420A

Quad Flat No-Lead Plas tic Package (QFN)

Micro Lead Frame Plas tic Package (MLFP)

L20.4x4

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VGGD-1 ISSUE I)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

0.02

-

0.65

9

0.20 REF

9

0.18

1.95

0.25

0.30

2.25

5, 8

D

4.00 BSC

-

D1

D2

E

3.75 BSC

9

2.10

7, 8

4.00 BSC

-

E1

E2

e

3.75 BSC

9

2.10

7, 8

0.50 BSC

-

k

0.20

0.35

-

0.60

20

5

-

L

0.75

8

N

2

Nd

Ne

P

3

5

3

-

0.60

12

9

θ

-

9

Rev. 2 11/04

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

FN9169.1

19

October 13, 2005

ISL6420A

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M20.15

N

20 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

0.25(0.010)

M

B M

H

AREA

E

GAUGE

PLANE

INCHES

MIN

0.053

0.004

-

MILLIMETERS

-B-

SYMBOL

MAX

0.069

0.010

0.061

0.012

0.010

0.344

0.157

MIN

1.35

0.10

-

MAX

1.75

0.25

1.54

0.30

0.25

8.74

3.98

NOTES

A

A1

A2

B

-

1

2

3

-

L

0.25

0.010

SEATING PLANE

A

-

-A-

0.008

0.007

0.337

0.150

0.20

0.18

8.56

3.81

9

D

h x 45°

C

D

E

-

-C-

3

α

4

A2

e

A1

C

e

0.025 BSC

0.635 BSC

-

B

0.10(0.004)

H

h

0.228

0.0099

0.016

0.244

0.0196

0.050

5.80

0.26

0.41

6.19

0.49

1.27

-

0.17(0.007) M

C

A M B S

5

NOTES:

L

6

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

N

α

20

7

Publication Number 95.

0°

8°

0°

8°

-

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

Rev. 1 6/04

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable dam-

bar protrusion shall be 0.10mm (0.004 inch) total in excess of “B” di-

mension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9169.1

20

October 13, 2005


型号：	ISL6420AIRZ-TK
厂家：	Intersil
描述：	Advanced Single Synchronous Buck Pulse-Width Modulation (PWM) Controller 高级单同步降压脉宽调制（ PWM ）控制器控制器
文件：	总20页 (文件大小：558K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6420AIRZ-TK [INTERSIL]

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