ISL6440A_技术文档

ISL6440A

TM

Data Sheet

October 2001

File Number 9041

Advanced PWM and Triple Linear Power

Controller for Gateway Applications

Features

• Provides four regulated voltages

The ISL6440A provides the power control and protection for

four output voltages required by microprocessors used in

high-performance, graphics-intensive gateway applications.

The IC integrates a voltage-mode PWM controller and three

linear controllers, as well as the monitoring and protection

functions into a 28 lead SOIC package.

- Microprocessor core, AGP bus, memory, and GTL bus

power

• Drives N-Channel MOSFETs

• Linear regulator drives compatible with both MOSFET and

bipolar series pass transistors

• Fixed or externally resistor-adjustable linear outputs

The synchronous rectified buck converter includes an Intel®-

compatible, TTL five-input, digital-to-analog converter (DAC)

• Simple single-loop control design

- Voltage-mode PWM control

that adjusts the core PWM output voltage from 1.3V

to

• Fast PWM converter transient response

- High-bandwidth error amplifier

- Full 0–100% duty ratio

DC

in 0.1V

2.05V

in 0.05V steps and from 2.1V

to 3.5V

DC

DC DC

increments. The precision reference and voltage-mode

control provide ±1% static regulation. A TTL-compatible

signal applied to the SELECT pin dictates which method of

control is used for the AGP bus power. A low state results in

linear control of the AGP bus to 1.5V, while a high state

transitions the output through a linearly controlled soft-start

to 3.3V, followed by full enhancement of the external

MOSFET to pass the input voltage. The other two linear

regulators provide fixed output voltages of 1.5V GTL bus

power and 1.8V power for the north/south bridge core and/or

cache memory. These levels are user-adjustable by means

of an external resistor divider and pulling the FIX pin low. All

linear controllers can employ either N-Channel MOSFETs or

bipolar NPNs for the pass transistor.

• Excellent output voltage regulation

- Core PWM output: ±1% over temperature

- Other outputs: ±3% over temperature

• TTL-compatible 5-bit DAC core output voltage selection

- Shutdown feature removed when all inputs high

- Wide range 1.3V

to 3.5V

DC

• Power-good output voltage monitor

• Overvoltage and overcurrent fault monitors

- Switching regulator does not require extra current

Sensing element, uses upper MOSFET’s r

DS(ON)

• Small converter size

- Constant frequency operation

- 200kHz free-running oscillator; programmable from

50kHz to over 1MHz

- Small external component count

The ISL6440A monitors all the output voltages. A single

power good signal is issued when the core is within ±10% of

the DAC setting and all other outputs are above their under-

voltage levels. Additional built-in overvoltage protection for

the core output uses the lower MOSFET to prevent output

voltages above 115% of the DAC setting. The PWM

Applications

•

Power regulation for gateway processors

controller’s overcurrent function monitors the output current

by using the voltage drop across the upper MOSFET’s

Pinout

ISL6440A (SOIC)

TOP VIEW

r

.

DS(ON)

28

27

26

25

24

23

22

21

20

19

1

2

3

4

5

6

7

8

9

DRIVE2

FIX

VCC

Ordering Information

UGATE

PHASE

LGATE

PGND

OCSET

VSEN1

FB

VID4

TEMP.

PKG.

NO.

o

VID3

PART NUMBER RANGE ( C)

PACKAGE

28 Ld SOIC

VID2

ISL6440ACB

0 to 70

M28.3

VID1

VID0

PGOOD

SD

COMP

VSEN3

10

VSEN2

SELECT 11

SS 12

18 DRIVE3

17 GND

FAULT/RT

16 VAUX

15 DRIVE4

13

VSEN4 14

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

1

Intel® is a registered trademark of Intel Corporation.

ISL6440A

Block Diagram

2

ISL6440A

Simplified Power System Diagram

+5V

IN

+3.3V

IN

Q1

Q2

V

OUT1

LINEAR

CONTROLLER

PWM

CONTROLLER

Q3

V

OUT2

ISL6440A

Q4

LINEAR

CONTROLLER

LINEAR

CONTROLLER

V

Q5

OUT3

V

OUT4

Typical Application

+12V

IN

+5V

IN

L

IN

C

IN

VCC

OCSET

PGOOD

+3.3V

IN

POWERGOOD

Q3

DRIVE2

VSEN2

V

OUT2

1.5V OR 3.3V

UGATE

PHASE

Q1

Q2

V

L

OUT1

IN

1.3V TO 3.5V

C

OUT2

LGATE

PGND

C

OUT1

SELECT

VAUX

TYPEDET

VSEN1

FB

ISL6440A

Q4

DRIVE3

VSEN3

COMP

V

OUT3

1.5V

C

OUT3

FIX

FAULT / RT

VID0

VID1

VID2

VID3

VID4

DRIVE4

VSEN4

Q5

V

OUT4

1.8V

SS

C

OUT4

C

SS

GND

3

ISL6440A

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

CC

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Thermal Resistance (Typical, Note 1)

θ

( C/W)

JA

PGOOD, RT/FAULT, DRIVE, PHASE,

and GATE Voltage . . . . . . . . . . . . . . . . GND -0.3V to V

Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

45

o

+ 0.3V

CC

o

(SOIC - Lead Tips Only)

Operating Conditions

Supply Voltage, V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0 C to 125 C

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

CC

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic

PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY CURRENT

Nominal Supply Current

I

UGATE, LGATE, DRIVE2, DRIVE3, and

DRIVE4 Open

-

9

-

mA

CC

POWER-ON RESET

Rising VCC Threshold

Falling VCC Threshold

Rising VAUX Threshold

VAUX Threshold Hysteresis

V

= 4.5V

-

10.4

V

OCSET

8.2

-

2.5

0.5

1.26

Rising V

Threshold

OCSET

OSCILLATOR

Free Running Frequency

F

RT = OPEN

185

-15

-

200

-

215

+15

-

kHz

%

OSC

Total Variation

6kΩ < RT to GND < 200kΩ

RT = Open

Ramp Amplitude

∆V

1.9

V

P-P

OSC

DAC AND BANDGAP REFERENCE

DAC(VID0-VID4) Input Low Voltage

DAC(VID0-VID4) Input High Voltage

DACOUT Voltage Accuracy

Bandgap Reference Voltage

Bandgap Reference Tolerance

-

0.8

-

V

2.0

-1.0

-

1.265

-

+1.0

-

%

V

BG

-2.5

+2.5

%

LINEAR REGULATORS (OUT2, OUT3, AND OUT4)

Regulation (All Linears)

Except OUT2 when SELECT > 2.0V

SELECT < 0.8V

-

3

-

%

V

VSEN2 Regulation Voltage

VREG

1.5

1.8

75

7

2

3

VSEN3 Regulation Voltage

VREG

-

VSEN4 Regulation Voltage

-

4

Undervoltage Level (VSEN/VREG)

Undervoltage Hysteresis (VSEN/VREG)

Output Drive Current (All Linears)

VSEN

VSEN Rising

VSEN Falling

-

%

UV

-

VAUX-V

DRIVE

> 0.6V

20

40

mA

SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER

4

ISL6440A

Electrical Specifications

PARAMETER

Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic (Continued)

SYMBOL

TEST CONDITIONS

MIN

TYP

88

15

6

MAX

UNITS

dB

DC Gain

-

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

COMP = 10pF

PWM CONTROLLER GATE DRIVER

UGATE Source

I

VCC = 12V, V

UGATE

= 6V

= 1V

-

1

1.7

1

-

A

Ω

A

Ω

UGATE

UGATE Sink

R

V

= 1V

3.5

-

UGATE

GATE-PHASE

LGATE Source

I

VCC = 12V, V

LGATE

LGATE Sink

R

V

= 1V

1.4

3.0

LGATE

PROTECTION

VSEN1 Overvoltage (VSEN1/DACOUT)

FAULT Sourcing Current

OCSET1 Current Source

Soft-Start Current

VSEN1 Rising

-

115

8.5

200

28

120

%

mA

µA

I

V

= 2.0V

-

170

-

230

-

OVP

FAULT/RT

I

= 4.5V

DC

OCSET

I

SS

POWER GOOD

VSEN1 Upper Threshold

(VSEN1/DACOUT)

VSEN1 Rising

108

92

-

110

94

%

VSEN1 Undervoltage

(VSEN1/DACOUT)

VSEN1 Hysteresis (VSEN1/DACOUT)

PGOOD Voltage Low

Upper/Lower Threshold

= -4mA

-

2

-

%

V

I

0.8

PGOOD

Typical Performance Curve

1000

R

PULLUP

T

TO +12V

100

10

R

PULLDOWN TO V

SS

T

10

100

SWITCHING FREQUENCY (kHz)

1000

FIGURE 1. R RESISTANCE vs FREQUENCY

T

5

ISL6440A

internal circuitry insures the core output voltage does not go

Functional Pin Descriptions

negative during this process. When re-enabled, the IC

undergoes a new soft-start cycle. Left open, this pin is pulled

low by an internal pull-down resistor, enabling operation.

VCC (Pin 28)

Provide a 12V bias supply for the IC to this pin. This pin also

provides the gate bias charge for all the MOSFETs

controlled by the IC. The voltage at this pin is monitored for

power-on reset (POR) purposes.

FIX (Pin 2)

Grounding this pin bypasses the internal resistor dividers

that set the output voltage of the 1.5V and 1.8V linear

regulators. This way, the output voltage of the two regulators

can be adjusted from 1.26V up to the input voltage (+3.3V or

+5V) by way of an external resistor divider connected at the

corresponding VSEN pin. The new output voltage set by the

external resistor divider can be determined using the

following formula:

GND (Pin 17)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

PGND (Pin 24)

This is the power ground connection. Tie the synchronous

PWM converter’s lower MOSFET source to this pin.

R





OUT

V

= 1.265V × 1 + ----------------





OUT

R

VAUX (Pin 16)





GND

This pin provides boost current for the linear regulators’

output drives in the event bipolar NPN transistors (instead

of N-Channel MOSFETs) are employed as pass elements.

The voltage at this pin is monitored for POR purposes.

where R

is the resistor connected from VSEN to the

OUT

output of the regulator, and R

is the resistor connected

GND

from VSEN to ground. Left open, the FIX pin is pulled high,

enabling fixed output voltage operation.

SS (Pin 12)

VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 28µA current source, sets the soft-start

interval of the converter.

VID0-4 are the TTL-compatible input pins to the 5-bit DAC.

The logic states of these five pins program the internal

voltage reference (DACOUT). The level of DACOUT sets the

microprocessor core converter output voltage, as well as the

corresponding PGOOD and OVP thresholds.

FAULT / RT (Pin 13)

This pin provides oscillator switching frequency adjustment.

By placing a resistor (R ) from this pin to GND, the nominal

200kHz switching frequency is increased according to the

following equation:

T

OCSET (Pin 23)

Connect a resistor from this pin to the drain of the respective

upper MOSFET. This resistor, an internal 200µA current

source, and the upper MOSFET’s on-resistance set the

converter overcurrent trip point. An overcurrent trip cycles

the soft-start function.

6

5 × 10

Fs ≈ 200kHz + --------------------

(R to GND)

T

R (kΩ)

T

Conversely, connecting a resistor from this pin to VCC

reduces the switching frequency according to the following

equation:

The voltage at this pin is monitored for POR purposes and

pulling this pin low with an open drain device will shutdown

the IC.

7

4 × 10

Fs ≈ 200kHz – --------------------

(R to 12V)

T

R (kΩ)

T

PHASE (Pin 26)

Connect the PHASE pin to the PWM converter’s upper

MOSFET source. This pin represents the gate drive return

current path and is used to monitor the voltage drop across

the upper MOSFET for overcurrent protection.

Nominally, the voltage at this pin is 1.26V. In the event of an

overvoltage or overcurrent condition, this pin is internally

pulled to VCC.

PGOOD (Pin 8)

UGATE (Pin 27)

PGOOD is an open collector output used to indicate the

status of the output voltages. This pin is pulled low when the

synchronous regulator output is not within ±10% of the

DACOUT reference voltage or when any of the other outputs

are below their undervoltage thresholds.

Connect UGATE pin to the PWM converter’s upper

MOSFET gate. This pin provides the gate drive for the upper

MOSFET.

LGATE (Pin 25)

The PGOOD output is open for ‘11111’ VID code.

Connect LGATE to the PWM converter’s lower MOSFET

gate. This pin provides the gate drive for the lower MOSFET.

SD (Pin 9)

This pin shuts down all the outputs. A TTL-compatible, logic

level high signal applied at this pin immediately discharges

the soft-start capacitor, disabling all the outputs. Dedicated

COMP and FB (Pin 20 and 21)

COMP and FB are the available external pins of the PWM

converter error amplifier. The FB pin is the inverting input of the

6

ISL6440A

error amplifier. Similarly, the COMP pin is the error amplifier

output. These pins are used to compensate the voltage-mode

control feedback loop of the synchronous PWM converter.

The AGP bus voltage (VOUT2) is set using the SELECT

pin to either a 1.5V linear regulated output or to the 3.3V

through a pass device. Selection of either output voltage is

set depending on the logic level of the SELECT pin.

IN

VSEN1 (Pin 22)

The two remaining linear controllers supply the 1.5V GTL

This pin is connected to the PWM converter’s output voltage.

The PGOOD and OVP comparator circuits use this signal to

report output voltage status and for overvoltage protection.

bus power (V

) and the 1.8V memory power (V

).

OUT3

OUT4

These output voltages are user adjustable. All linear

controllers are designed to employ an external pass

transistor.

DRIVE2 (Pin 1)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the AGP regulator’s pass transistor.

Initialization

The ISL6440A automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The POR function continually monitors the input

supply voltages. The POR monitors the bias voltage

VSEN2 (Pin 10)

Connect this pin to the output of the AGP linear regulator.

The voltage at this pin is regulated to the level

predetermined by the logic-level status of the SELECT pin.

This pin is also monitored for undervoltage events.

(+12V ) at the VCC pin, the 5V input voltage (+5V ) on the

OCSET pin, and the 3.3V input voltage (+3.3V ) at the

IN

IN IN

VAUX pin. The normal level on OCSET is equal to +5V

IN

SELECT (Pin 11)

less a fixed voltage drop (see overcurrent protection). The

POR function initiates soft-start operation after all supply

voltages exceed their POR thresholds.

This pin determines the output voltage of the AGP bus linear

regulator. A low TTL input sets the output voltage to 1.5V

and the linear controller regulates this voltage to within ±3%.

Soft-Start

A TTL high input turns Q3 on continuously, providing a DC

current path from the input (+3.3V ) to the output (V

of the AGP controller.

The POR function initiates the soft-start sequence. Initially,

the voltage on the SS pin rapidly increases to approximately

1V (this minimizes the soft-start interval). Then an internal

)

IN

OUT2

28µA current source charges an external capacitor (C ) on

DRIVE3 (Pin 18)

SS

the SS pin to 4.5V. The PWM error amplifier reference input

(+ terminal) and output (COMP pin) are clamped to a level

proportional to the SS pin voltage. As the SS pin voltage

slews from 1V to 4V, the output clamp allows generation of

PHASE pulses of increasing width that charge the output

capacitor(s). After the output voltage increases to

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.5V regulator’s pass transistor.

VSEN3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.

This pin is monitored for undervoltage events.

approximately 70% of the set value, the reference input

clamp slows the output voltage rate-of-rise and provides a

smooth transition to the final set voltage. Additionally, all

linear regulators’ reference inputs are clamped to a voltage

proportional to the SS pin voltage. This method provides a

rapid and controlled output voltage rise.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.8V regulator’s pass transistor.

VSEN4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.

This pin is monitored for under voltage events.

Figure 2 shows the soft-start sequence for the typical

application. At t0 the SS voltage rapidly increases to

approximately 1V. At t1, the SS pin and error amplifier

output voltage reach the valley of the oscillator’s triangle

wave. The oscillator’s triangular waveform is compared to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pulse width on the PHASE pin

increases. The interval of increasing pulse width continues

until each output reaches sufficient voltage to transfer

control to the input reference clamp. If we consider the

Description

Operation

The ISL6440A monitors and precisely controls 4 output

voltage levels (Refer to Block and Simplified Power System

Diagrams, and Typical Application Schematic). It is

designed for microprocessor computer applications with

3.3V, 5V, and 12V bias input from an ATX power supply.

The microprocessor core voltage (V

) is controlled in a

OUT1

2.5V core output (V

) in Figure 2, this time occurs at t2.

OUT1

synchronous rectified buck converter configuration. The

PWM controller regulates the microprocessor core voltage

to a level programmed by the 5-bit digital-to-analog

converter (DAC).

During the interval between t2 and t3, the error amplifier

reference ramps to the final value and the converter

regulates the output a voltage proportional to the SS pin

voltage. At t3 the input clamp voltage exceeds the

reference voltage and the output voltage is in regulation.

7

ISL6440A

LUV

OVER-

CURRENT

LATCH

INHIBIT

PGOOD

0V

S

Q

OC1

SOFT-START

(1V/DIV)

R

0.15V

+

-

COUNTER

FAULT

LATCH

VCC

R

S

Q

UP

SS

OV

+

-

V

(= 3.3V )

IN

OUT2

4V

R

POR

FAULT

V

(DAC = 2.5V)

OUT1

FIGURE 3. FAULT LOGIC - SIMPLIFIED SCHEMATIC

V

(= 1.8V)

OUT4

OUTPUT

VOLTAGES

(0.5V/DIV)

Overvoltage Protection

V

(= 1.5V)

OUT3

During operation, a short on the upper MOSFET of the PWM

regulator (Q1) causes V

to increase. When the output

OUT1

exceeds the overvoltage threshold of 115% of DACOUT, the

overvoltage comparator trips to set the fault latch and turns

0V

Q2 on. This blows the input fuse and reduces V

fault latch raises the FAULT/RT pin to VCC.

. The

OUT1

T0 T1

T2

T3

T4

TIME

A separate overvoltage circuit provides protection during the

initial application of power. For voltages on the VCC pin

below the POR (and above ~4V), the output level is

monitored for voltages above 1.3V. Should VSEN1 exceed

this level, the lower MOSFET, Q2 is driven on.

FIGURE 2. SOFT-START INTERVAL

The remaining outputs are also programmed to follow the

SS pin voltage. The PGOOD signal toggles ‘high’ when all

output voltage levels have exceeded their undervoltage

levels. The waveform for V

represents the case where

OUT2

Overcurrent Protection

SELECT is held ‘high’. The AGP bus voltage is controlled in

the same manner as the other linear regulators during the

soft-start sequence. Once the soft-start sequence is

complete (t4), the gate of the external pass device is fully

All outputs are protected against excessive overcurrents.

The PWM controller uses the upper MOSFET’s

on-resistance, r

to monitor the current for protection

DS(ON)

enhanced and V

Soft-Start Interval section under Applications Guidelines for

a procedure to determine the soft-start interval.

tracks the 3.3V voltage. See the

against shorted output. All linear controllers monitor their

respective VSEN pins for undervoltage events to protect

against excessive currents.

OUT2

IN

Fault Protection

Figure 4 illustrates the overcurrent protection with an

overload on OUT1. The overload is applied at T0 and the

All four outputs are monitored and protected against extreme

overload. A sustained overload on any output or an

current increases through the inductor (L

). At time t1,

OUT1

the OVERCURRENT comparator trips when the voltage

across Q1 (i • r ) exceeds the level programmed by

overvoltage on V

output (VSEN1) disables all outputs

OUT1

and drives the FAULT/RT pin to VCC.

D

DS(ON)

ROCSET. This inhibits all outputs, discharges the soft-start

capacitor (C ) with a 10mA current sink, and increments

Figure 3 shows a simplified schematic of the fault logic. An

overvoltage detected on VSEN1 immediately sets the fault

latch. A sequence of three overcurrent fault signals also sets

the fault latch. The overcurrent latch is set dependent upon

the states of the overcurrent (OC), linear undervoltage (LUV)

and the soft-start signals. A window comparator monitors the

SS pin and indicates when C is fully charged to 4V (UP

signal). An undervoltage on either linear output (VSEN2,

VSEN3, or VSEN4) is ignored until after the soft-start interval

(t4 in Figure 2). This allows V

increase without fault at start-up. Cycling the bias input

voltage (+12V on the VCC pin off, then on) resets the

IN

counter and the fault latch.

SS

the counter. C recharges at t2 and initiates a soft-start

SS

cycle with the error amplifiers clamped by soft-start. With

OUT1 still overloaded, the inductor current increases to trip

the overcurrent comparator. Again, this inhibits all outputs,

but the soft-start voltage continues increasing to 4V before

discharging. The counter increments to 2. The soft-start

cycle repeats at t3 and trips the overcurrent comparator. The

SS pin voltage increases to 4V at t4 and the counter

increments to 3. This sets the fault latch to disable the

converter. The fault is reported on the FAULT/RT pin.

SS

, V

, and V to

OUT4

OUT2

OUT3

The linear controllers operate in the same way as the PWM

in response to overcurrent faults. The differentiating factor

8

ISL6440A

for the linear controllers is that they monitor the VSEN pins

OVERCURRENT TRIP:

V

= +5V

IN

V

> V

> I

for undervoltage events. Should excessive currents cause

the voltage at the VSEN pins to fall below the linear

undervoltage threshold, the LUV signal sets the

DS

SET

i

× r

× R

D

DS(ON) OCSET

OCSET

R

OCSET

overcurrent latch if C

signal during the C

is fully charged. Blanking the LUV

SS

charge interval allows the linear

I

i

OCSET

D

V

SS

+

SET

200µA

outputs to build above the undervoltage threshold during

normal operation. Cycling the bias input power off then on

resets the counter and the fault latch.

VCC

UGATE

OVER-

CURRENT

+

DRIVE

V

DS

OC

+

-

PHASE

FAULT

REPORTED

V

= V – V

IN

10V

0V

PHASE

DS

SET

PWM

GATE

CONTROL

V

= V – V

OCSET

IN

COUNT

= 1

COUNT

= 2

COUNT

= 3

FIGURE 5. OVERCURRENT DETECTION

4V

2V

0V

The OC trip point varies with MOSFET’s r

DS(ON)

temperature variations. To avoid overcurrent tripping in the

normal operating load range, determine the R

resistor from the equation above with:

OCSET

OVERLOAD

APPLIED

1. The maximum r

2. The minimum I

at the highest junction temperature.

from the specification table.

DS(ON)

OCSET

3. Determine I

PEAK

for I

> I

+ (∆I)/2, where

OUT(MAX)

PEAK

∆I is the output inductor ripple current.

0A

For an equation for the ripple current see the section under

T0 T1

T2

T3

T4

component guidelines titled PWM Output Inductor Selection.

TIME

OUT1 Voltage Program

FIGURE 4. OVERCURRENT OPERATION

The output voltage of the PWM converter is programmed to

discrete levels between 1.3V

and 3.5V . This output

DC

A resistor (R

) programs the overcurrent trip level for

OCSET

the PWM converter. As shown in Figure 5, the internal

200µA current sink, I develops a voltage across

(OUT1) is designed to supply the core voltage of Intel’s

advanced microprocessors. The voltage identification (VID)

pins program an internal voltage reference (DACOUT) with a

TTL-compatible 5-bit digital-to-analog converter. The level of

DACOUT also sets the PGOOD and OVP thresholds.

Table 1 specifies the DACOUT voltage for the different

combinations of connections on the VID pins. The VID pins

can be left open for a logic 1 input, because they are

internally pulled up to an internal voltage of about 5V by a

10µA current source. Changing the VID inputs during

operation is not recommended and could toggle the PGOOD

signal and exercise the overvoltage protection.

OCSET

) that is referenced to V . The DRIVE

R

(V

OCSET SET

IN

signal enables the overcurrent comparator (OVER-

CURRENT). When the voltage across the upper MOSFET

(V ) exceeds V

, the overcurrent comparator trips to

set the overcurrent latch. Both V and V are

DS SET

SET

DS

referenced to V and a small capacitor across R

IN

OCSET

helps V

track the variations of V due to MOSFET

OCSET

IN

switching. The overcurrent function will trip at a peak

inductor current (I determined by:

PEAK)

× R

OCSET

I

OCSET

I

= ---------------------------------------------------

PEAK

r

DS(ON)

9

ISL6440A

circuitry. Left open, the SELECT pin is internally pulled ‘high’

TABLE 1. OUT1 VOLTAGE PROGRAM

PIN NAME

and the AGP voltage is regulated to 3.3V during the soft-start

sequence. Once complete, the gate drive is increased and

the regulator becomes a simple pass circuit for the 3.3V

input voltage.

NOMINAL

DACOUT

VOLTAGE

VID4

0

1

VID3

1

0

1

0

VID2

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

2.00

2.1

OUT3 and OUT4 Voltage Adjustability

The GTL bus voltage (1.5V, OUT3) and the chip set and/or

cache memory voltage (1.8V, OUT4) are internally set for

simple, low-cost implementation in typical Intel motherboard

architectures. However, if different voltage settings are

desired for these two outputs, the FIX pin provides the

necessary adaptability. Left open (NC), this pin sets the fixed

output voltages described above. Grounding this pin allows

both output voltages to be set by means of external resistor

dividers as shown in Figure 6.

VAUX

+3.3V

IN

Q4

DRIVE3

VSEN3

V

OUT3

R

S3

C

R

P3

OUT3

ISL6440A

Q5

DRIVE4

VSEN4

V

OUT4

2.2

R

S4

C

FIX

R

OUT4

P4

2.3

2.4

R





S

2.5

V

= V

×

1 + --------





OUT

BG

R





P

2.6

FIGURE 6. ADJUSTING THE OUTPUT VOLTAGE OF

OUTPUTS 3 AND 4

2.7

2.8

2.9

Application Guidelines

3.0

Soft-Start Interval

3.1

Initially, the soft-start function clamps the error amplifier’s

output of the PWM converter. This generates PHASE pulses

of increasing width that charge the output capacitor(s). After

the output voltage increases to approximately 70% of the set

value, the reference input of the error amplifier is clamped to

a voltage proportional to the SS pin voltage. The resulting

output voltages start-up as shown in Figure 2.

3.2

3.3

3.4

3.5

NOTE: 0 = connected to GND, 1 = open or connected to 5V through

pull-up resistors.

The soft-start function controls the output voltage rate of rise

to limit the current surge at start-up. The soft-start interval and

the surge current are programmed by the soft-start capacitor,

OUT2 Voltage Selection

The AGP output voltage is internally set to one of two levels,

based on the status of the SELECT pin. Grounding the

SELECT pin enables the internal 1.5V regulator control

C

. Programming a faster soft-start interval increases the

SS

peak surge current. The peak surge current occurs during the

initial output voltage rise to 70% of the set value.

10

ISL6440A

control IC. Minimize any leakage current paths from SS

Shutdown

node, since the internal current source is only 28µA.

The ISL6440A features a dedicated shutdown pin (SD). A

TTL-compatible, logic high signal applied to this pin shuts

down (disables) all four outputs and discharges the soft-start

capacitor. Following a shutdown, a logic low signal

re-enables the outputs through initiation of a new soft-start

cycle. Left open this pin will asses a logic low state, due to its

internal pull-down resistor, thus enabling normal operation of

all outputs.

A multi-layer printed circuit board is recommended.

Figure 7 shows the connections of the critical components

in the converter. Note that the capacitors C and C

IN

OUT

each represent numerous physical capacitors. Dedicate

one solid layer for a ground plane and make all critical

component ground connections with vias to this layer.

Dedicate another solid layer as a power plane and break

this plane into smaller islands of common voltage levels.

The power plane should support the input power and

output power nodes. Use copper filled polygons on the top

and bottom circuit layers for the PHASE nodes, but do not

unnecessarily oversize these particular islands. Since the

PHASE nodes are subjected to very high dv/dt voltages,

the stray capacitor formed between these islands and the

surrounding circuitry will tend to couple switching noise.

Use the remaining printed circuit layers for small signal

wiring. The wiring traces from the control IC to the

MOSFET gate and source should be sized to carry 2A peak

currents.

The PWM output does not switch until the soft-start voltage

(V ) exceeds the oscillator’s valley voltage. The references

SS

on each linear’s error amplifier are clamped to the soft-start

voltage. Holding the SS pin low (with an open drain or

collector signal) turns off all four regulators.

The ‘11111’ VID code also shuts down the IC.

Layout Considerations

MOSFETs switch quickly and efficiently. The speed with

which the current transitions from one device to another

causes voltage spikes across the interconnecting

impedances and parasitic circuit elements. The voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device overvoltage stress. Careful component

layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-

off transition of the upper PWM MOSFET. Prior to turn-off,

the upper MOSFET was carrying the full load current.

During the turn-off, current stops flowing in the upper

MOSFET and is picked up by the lower MOSFET or

Schottky diode. Any inductance in the switched current

path generates a large voltage spike during the switching

interval. Careful component selection, tight layout of the

critical components, and short, wide circuit traces minimize

the magnitude of voltage spikes. See Application Note

AN9836 for evaluation board drawings of the component

placement and the printed circuit board layout of a typical

application.

PWM Controller Feedback Compensation

The PWM controller uses voltage-mode control for output

regulation. This section highlights the design consideration

for a PWM voltage-mode controller. Apply the methods and

considerations only to the PWM controller.

Figure 8 highlights the voltage-mode control loop for a

synchronous rectified buck converter. The output voltage

(V

) is regulated to the Reference voltage level. The

OUT

reference voltage level is the DAC output voltage

(DACOUT). The error amplifier (Error Amp) output (V ) is

compared with the oscillator (OSC) triangular wave to

provide a pulse-width modulated (PWM) wave with an

E/A

amplitude of V at the PHASE node. The PWM wave is

IN

smoothed by the output filter (L and C ).

O

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

OUT E/A

gain, given by V /V

There are two sets of critical components in a DC-DC

converter using a ISL6440A controller. The switching power

components are the most critical because they switch large

amounts of energy, and as such, they tend to generate

equally large amounts of noise. The critical small signal

components are those connected to sensitive nodes or

those supplying critical bypass current.

, and shaped by the output filter,

and a zero

IN OSC

with a double pole break frequency at F

LC

at F

.

ESR

Modulator Break Frequency Equations

1

F

= ---------------------------------------

F

= -----------------------------------------

LC

ESR

2π × ESR × C

2π ×

L × C

O O

O

The power components and the controller IC should be

placed first. Locate the input capacitors, especially the high-

frequency ceramic decoupling capacitors, close to the power

switches. Locate the output inductor and output capacitors

between the MOSFETs and the load. Locate the PWM

controller close to the MOSFETs.

The compensation network consists of the error amplifier

(internal to the ISL6440A) and the impedance networks Z

IN

and Z . The goal of the compensation network is to provide

FB

a closed loop transfer function with high 0dB crossing

frequency (f

) and adequate phase margin. Phase margin

0dB

is the difference between the closed loop phase at f

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R1, R2,

and

0dB

The critical small signal components include the bypass

capacitor for VCC and the soft-start capacitor, C . Locate

SS

these components close to their connecting pins on the

11

ISL6440A

R3, C1, C2, and C3) in Figure 7. Use these guidelines for

locating the poles and zeros of the compensation network:

V

IN

OSC

DRIVER

PWM

1. Pick gain (R2/R1) for desired converter bandwidth

L

O

COMP

V

OUT

2. Place first zero below filter’s double pole (~75% F

3. Place second zero at filter’s double pole

4. Place first pole at the ESR zero

)

LC

-

PHASE

+

C

∆V

O

OSC

ESR

(PARASITIC)

5. Place second pole at half the switching frequency

Z

FB

6. Check gain against error amplifier’s open-loop gain

7. Estimate phase margin - repeat if necessary

V

E/A

Z

-

IN

+

REFERENCE

ERROR

AMP

L

IN

+5V

IN

DETAILED COMPENSATION COMPONENTS

C

IN

+12V

C

Z

VCC

VCC GND

OCSET1

FB

V

OUT

C

C2

OCSET1

R

Z

IN

+3.3V

IN

C1

C3

R3

R2

OCSET1

Q3

DRIVE2

Q1

UGATE1

R1

V

OUT2

L

OUT1

COMP

V

OUT1

PHASE1

FB

-

C

OUT2

C

+

OUT1

CR1

LGATE1

SS

ISL6440A

Q2

DACOUT

C

SS

ISL6440A

V

OUT3

V

OUT4

FIGURE 8. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

C

OUT3

DRIVE4

DRIVE3

C

OUT4

PGND

Q5

Q4

Compensation Break Frequency Equations

+3.3V

IN

1

F

= -----------------------------------

2π × R2 × C1

F

= ------------------------------------------------------

KEY

Z1

P1

C1 × C2

----------------------

C1 + C2







2π × R

×

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

2



1

F

= ------------------------------------------------------

2π × (R1 + R3) × C3

F

= -----------------------------------

2π × R3 × C3

Z2

P2

FIGURE 7. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

OPEN LOOP

F

P1

F

P2

Z1

Z2

ERROR AMP GAIN

100

80

60

40

20

0

Figure 9 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual modulator gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown in Figure 8. Using the above guidelines

should yield a compensation gain similar to the curve plotted.

V









IN

20log

------------



V



PP

COMPENSATION

GAIN

Check the compensation gain at F with the capabilities of the

P2

error amplifier. The closed loop gain is constructed on the log-

log graph of Figure 9 by adding the modulator gain (in dB) to

the compensation gain (in dB). This is equivalent to multiplying

the modulator transfer function to the compensation transfer

function and plotting the gain.

R2









20log

-------

R1

-20

-40

-60

CLOSED LOOP

GAIN

MODULATOR

GAIN

F

LC

ESR

10K

The compensation gain uses external impedance networks

10

100

1K

100K

1M

10M

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

FREQUENCY (Hz)

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst-case component variations when

determining phase margin.

FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

12

ISL6440A

Component Selection Guidelines

V

– V

V

OUT

IN

∆I = ------------------------------- × ---------------

× L

OUT

∆V

= ∆I × ESR

OUT

F

V

S

IN

Output Capacitors

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values increase

the converter’s response time to a load transient.

The output capacitors for each output have unique

requirements. In general, the output capacitors should be

selected to meet the dynamic regulation requirements.

Additionally, the PWM converters require an output capacitor

to filter the current ripple. The load transient for the

microprocessor core requires high quality capacitors to

supply the high slew rate (di/dt) current demands.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6440A will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

interval required to slew the inductor current from an initial

current value to the post-transient current level. During this

interval the difference between the inductor current and the

transient current level must be supplied by the output

capacitor(s). Minimizing the response time can minimize the

output capacitance required.

PWM Output

Modern microprocessors produce transient load rates above

1A/ns. High frequency capacitors initially supply the transient

current and slow the load rate-of-change seen by the bulk

capacitors. The bulk filter capacitor values are generally

determined by the ESR (effective series resistance) and

voltage rating requirements rather than actual capacitance

requirements.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

L

× I

L

× I

O

TRAN

O

TRAN

t

= -------------------------------

t

= ------------------------------

RISE

FALL

V

– V

V

IN

OUT

where: I

TRAN

response time to the application of load, and t

is the transient load current step, t

is the

RISE

FALL

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR determines the output ripple voltage and

the initial voltage drop following a high slew-rate transient’s

edge. An aluminum electrolytic capacitor’s ESR value is

related to the case size with lower ESR available in larger

case sizes. However, the equivalent series inductance (ESL)

of these capacitors increases with case size and can reduce

the usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter. Work

with your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

response time to the removal of load. Be sure to check both

of these equations at the minimum and maximum output

levels for the worst case response time.

Input Capacitors

The important parameters for the bulk input capacitors are

the voltage rating and the RMS current rating. For reliable

operation, select bulk input capacitors with voltage and

current ratings above the maximum input voltage and largest

RMS current required by the circuit. The capacitor voltage

rating should be at least 1.25 times greater than the

maximum input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

½ the summation of the DC load current.

Linear Output Capacitors

The output capacitors for the linear regulators provide

dynamic load current. The linear controllers use dominant

pole compensation integrated into the error amplifier and are

insensitive to output capacitor selection. Output capacitors

should be selected for transient load regulation.

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitance

for the high frequency decoupling and bulk capacitors to

supply the RMS current. Small ceramic capacitors can be

placed very close to the upper MOSFET to suppress the

voltage induced in the parasitic circuit impedances.

PWM Output Inductor

For a through-hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX

or equivalent) may be needed. For surface mount designs,

solid tantalum capacitors can be used, but caution must be

exercised with regard to the capacitor surge current rating.

These capacitors must be capable of handling the surge-

current at power-up. The TPS series available from AVX, and

the 593D series from Sprague are both surge current tested.

The PWM converter requires an output inductor. The output

inductor is selected to meet the output voltage ripple

requirements and sets the converter’s response time to a

load transient. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current. The ripple voltage and current are approximated by

the following equations:

13

ISL6440A

MOSFET Considerations

+5V OR LESS

+12V

The ISL6440A requires five external transistors. Two

VCC

N-Channel MOSFETs are used in the synchronous rectified

buck topology of PWM1 converter. It is recommended that

the AGP linear regulator pass element be a N-Channel

MOSFET as well. The GTL and memory linear controllers

can also each drive a MOSFET or a NPN bipolar as a pass

transistor. All these transistors should be selected based

ISL6440A

Q1

UGATE

PHASE

NOTE:

_GS≈ V -5V

V

CC

upon r

, current gain, saturation voltages, gate supply

CR1

DS(ON)

LGATE

PGND

Q2

-

+

requirements, and thermal management considerations.

NOTE:

_GS≈ V

PWM MOSFETs

V

CC

GND

In high-current PWM applications, the MOSFET power

dissipation, package selection and heat sink are the

dominant design factors. The power dissipation includes two

loss components; conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty factor (see the equations

below). The conduction losses are the main component of

power dissipation for the lower MOSFETs. Only the upper

MOSFET has significant switching losses, since the lower

device turns on and off into near zero voltage.

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

CC

Rectifier CR1 is a clamp that catches the negative inductor

swing during the dead time between the turn off of the lower

MOSFET and the turn on of the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to

omit the diode and let the body diode of the lower MOSFET

clamp the negative inductor swing, but efficiency could drop

one or two percent as a result. The diode's rated reverse

breakdown voltage must be greater than the maximum input

voltage.

The equations below assume linear voltage-current

transitions and do not model power loss due to the reverse-

recovery of the lower MOSFET’s body diode. The gate-

charge losses are dissipated by the ISL6440A and do not

heat the MOSFETs. However, large gate-charge increases

Linear Controller Transistors

The main criteria for selection of transistors for the linear

regulators is package selection for efficient removal of heat.

The power dissipated in a linear regulator is:

the switching time, t

which increases the upper MOSFET

SW

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature at high ambient temperature

by calculating the temperature rise according to package

thermal-resistance specifications. A separate heat sink may

be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

P

= I × (V – V

IN OUT

)

LINEAR

O

Select a package and heat sink that maintains the junction

temperature below the rating with a the maximum expected

ambient temperature.

2

I

× r

× V

I

× V × t

IN

× F

S

O

DS(ON)

OUT

O

SW

P

= ------------------------------------------------------------ + ----------------------------------------------------

UPPER

LOWER

V

2

IN

When selecting bipolar NPN transistors for use with the

linear controllers, insure the current gain at the given

operating VCE is sufficiently large to provide the desired

output load current when the base is fed with the minimum

driver output current.

2

I

× r

× (V – V

OUT

)

O

DS(ON)

IN

= --------------------------------------------------------------------------------

V

IN

The r

DS(ON)

is different for the two equations above even if

the same device is used for both. This is because the gate

drive applied to the upper MOSFET is different than the

lower MOSFET. Figure 10 shows the gate drive where the

upper MOSFET’s gate-to-source voltage is approximately

VCC less the input supply. For +5V main power and

+12VDC for the bias, the gate-to-source voltage of Q1 is 7V.

The lower gate drive voltage is +12VDC. A logic-level

MOSFET is a good choice for Q1 and a logic-level MOSFET

can be used for Q2 if its absolute gate-to-source voltage

rating exceeds the maximum voltage applied to VCC.

14

ISL6440A

ISL6440A DC-DC Converter Application Circuit

Figure 11 shows an application circuit of a power supply for a

microprocessor computer system. The power supply provides

the microprocessor core voltage (VOUT1), the AGP bus

voltage (VOUT2), the GTL bus voltage (VOUT3), and the

memory voltage (VOUT4) from +3.3V, +5VDC, and +12VDC.

For detailed information on the circuit, including a bill of

materials and circuit board description, see Application Note

AN9836. Also see Intersil’s web page (http://www.intersil.com)

for the latest information.

+12V

IN

L1

+5V

1µH

+

C1-6

C7

1µF

6x1000µF

GND

C8

1000pF

C9

1µF

VCC

28

R1

23

8

FAULT/RT

VAUX

OCSET

PGOOD

13

16

1.0K

POWERGOOD

+3.3V

IN

DRIVE2

Q1, 2

2xHUF76143S3S

UGATE

PHASE

V

27

26

1

OUT1

L2

V

(1.3V-3.5V)

OUT2

10

VSEN2

4.2µH

Q3

HUF76121D3S

(3.3V OR 1.5V)

IN

+

C10, 11

2x1000µF

+

C12-19

8x1000µF

LGATE

PGND

25

24

R2

10.2K

SELECT

11

VSEN1

FB

TYPEDET

22

21

U1

ISL6440A

R3

1.62K

C20

0.22µF

C21

10pF

Q4

DRIVE3

VSEN3

HUF76107D3S

COMP

18

19

20

V

OUT3

(1.5V)

+

C23, 24

2x1000µF

R5

499K

R4

150K

C22

2.7nF

VID0

VID1

VID2

VID3

VID4

7

6

Q5

DRIVE4

VSEN4

5

4

3

HUF76107D3S

15

14

V

OUT4

(1.8V)

SD

+

SS

9

2

C25, 26

2x1000µF

12

FIX

C27

0.1µF

17

GND

FIGURE 11. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM

15

ISL6440A

Small Outline Plastic Packages (SOIC)

M28.3 (JEDEC MS-013-AE ISSUE C)

N

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

0.25(0.010)

M

B M

H

AREA

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

17.70

7.40

MAX

2.65

0.30

0.51

0.32

18.10

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.0200

0.0125

0.7125

0.2992

-

1

2

3

L

9

SEATING PLANE

A

0.0091

0.6969

0.2914

-

3

-A-

o

h x 45

D

4

0.05 BSC

1.27 BSC

-

-C-

α

µ

H

h

0.394

0.01

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

0.016

6

0.25(0.010) M

C A M B S

N

α

28

7

o

0

o

8

o

0

o

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2

of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

16


型号：	ISL6440A
厂家：	Intersil
描述：	Advanced PWM and Triple Linear Power Controller for Gateway Applications 先进的PWM和三线性电源控制器，用于网关应用栅控制器
文件：	总16页 (文件大小：746K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6440A [INTERSIL]

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