ISL6504EVAL1_技术文档

ISL6504, ISL6504A

®

Data Sheet

April 13, 2004

FN9062.2

Multiple Linear Power Controller with

ACPI Control Interface

Features

• Provides four ACPI-Controlled Voltages

- 5V

DUAL

USB/Keyboard/Mouse

The ISL6504 and ISL6504A complement other power

building blocks (voltage regulators) in ACPI-compliant

designs for microprocessor and computer applications. The

IC integrates three linear controllers/regulators, switching,

monitoring and control functions into a 16-pin wide-body

SOIC or 20-pin QFN 6x6 package. The ISL6504, ISL6504A

operating mode (active outputs or sleep outputs) is

selectable through two digital control pins, S3 and S5.

- 3.3V

- 1.2V

/3.3V PCI/Auxiliary/LAN

DUAL

SB

Processor VID Circuitry

VID

- 1.5V ICH4 Resume Well

SB

• Excellent Output Voltage Regulation

- All Outputs: ±2.0% over temperature (as applicable)

• Small Size; Very Low External Component Count

• Undervoltage Monitoring of All Outputs with Centralized

FAULT Reporting and Temperature Shutdown

One linear controller generates the 3.3V

/3.3V

DUAL SB

voltage plane from the ATX supply’s 5V output, powering

SB

the south bridge and the PCI slots through an external NPN

pass transistor during sleep states (S3, S4/S5). In active

• QFN Package:

- Near Chip Scale Package Footprint; Improved PCB

Efficiency; Thinner profile

state (during S0 and S1/S2), the 3.3V

/3.3V linear

DUAL

SB

regulator uses an external N-channel pass MOSFET to

connect the outputs directly to the 3.3V input supplied by an

ATX power supply, for minimal losses.

• Pb-Free Available (RoHS Compliant)

Applications

A controller powers up the 5V

plane by switching in the

DUAL

ATX 5V output through an NMOS transistor in active states,

•

ACPI-Compliant Power Regulation for Motherboards

- ISL6504: 5V is shut down in S4/S5 sleep states

DUAL

- ISL6504A: 5V

or by switching in the ATX 5V through a PMOS (or PNP)

transistor in S3 sleep state. In S4/S5 sleep states, the

SB

stays on in S4/S5 sleep states

DUAL

ISL6504 5V

output is shut down. In the ISL6504A, the

DUAL

output stays on during S4/S5 sleep states. This is

5V

DUAL

the only difference between the two parts; see Table 1.

An internal linear regulator supplies the 1.2V for the voltage

identification circuitry (VID) only during active states (S0 and

S1/S2), and uses the 3V3 pin as input source for its internal

pass element. Another internal regulator outputs a 1.5V

SB

chip-set standby supply, which uses the 3V3DL pin as input

source for its internal pass element. The 3.3V /3.3V

DUAL SB

and 1.5V outputs are active for as long as the ATX 5V

SB

voltage is applied to the chip.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6504, ISL6504A

Ordering Information

Pinouts

ISL6504/A (WIDE BODY SOIC)

TOP VIEW

TEMP.

PKG.

DWG. #

16

15

14

13

1

2

3

4

5

6

7

8

5VSB

VID_CT

VID_PG

SS

1V5SB

3V3DLSB

3V3DL

o

PART NUMBER RANGE ( C)

PACKAGE

16 Ld SOIC

ISL6504CB

0 to 70

M16.3

ISL6504CBZ

(Note)

16 Ld SOIC

(Pb-free)

1V2VID

3V3

12 5VDL

ISL6504CBN

0 to 70

16 Ld SOIC

M16.15

5VDLSB

11

10

9

S3

DLA

S5

ISL6504CBNZ

(Note)

16 Ld SOIC

(Pb-free)

FAULT

GND

ISL6504CR

0 to 70

20 Ld 6x6 QFN

L20.6x6

NOTE: SOIC layout should accomodate both wide and narrow footprints.

ISL6504CRZ

(Note)

20 Ld 6x6 QFN

(Pb-free)

ISL6504/A (6X6 QFN)

TOP VIEW

ISL6504EVAL1

ISL6504ACB

Evaluation Board

0 to 70

16 Ld SOIC

M16.3

ISL6504ACBZ

(Note)

16 Ld SOIC

(Pb-free)

20 19 18 17 16

3V3DL

NC

VID_PG

SS

1

2

3

4

5

15

14

13

12

11

ISL6504ACBN

0 to 70

16 Ld SOIC

M16.15

ISL6504ACBNZ

(Note)

16 Ld SOIC

(Pb-free)

1V2VID

3V3

NC

ISL6504ACR

0 to 70

20 Ld 6x6 QFN

L20.6x6

5VDL

5VDLSB

ISL6504ACRZ

(Note)

20 Ld 6x6 QFN

(Pb-free)

S3

ISL6504AEVAL1

Evaluation Board

6

7

8

9

10

Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

NOTE: The QFN bottom pad is electrically connected to the IC substrate, at

GND potential. It can be left unconnected, or connected to GND; do NOT

connect to another potential.

FN9062.2

2

April 13, 2004

ISL6504, ISL6504A

Simplified Power Sys tem Diagram

+5VIN

+12VIN

+5VSB

+3.3VIN

1.5VSB

LINEAR

REGULATOR

1.2VVID

1.2V

LINEAR

REGULATOR

1.5V

Q2

LINEAR

CONTROLLER

Q3

VID_PG

3.3VDUAL/3.3VSB

Q4

3.3V

CONTROL

LOGIC

Q5

FAULT

ISL6504/A

5VDUAL

5V

SHUTDOWN

SX

2

FIGURE 2.

Typical Application

+5VIN

+12VIN

+5VSB

+3.3VIN

5VSB

3V3

VOUT1

1V5SB

VOUT2

1.5VSB

COUT1

1V2VID

VID_CT

1.2VVID

RDLA

COUT2

CCT_VID

3V3DLSB

3V3DL

Q1

Q2

VID_PG

VOUT3

VID PGOOD

ISL6504/A

3.3VDUAL/3.3VSB

COUT3

Q3

5VDLSB

DLA

FAULT

S3

S5

Q4

SLP_S3

SLP_S5

VOUT4

5VDL

5VDUAL

SS

COUT4

CSS

SHUTDOWN

GND

FIGURE 3.

FN9062.2

April 13, 2004

4

ISL6504, ISL6504A

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

Thermal Resistance (Typical)

θ_JA( C/W) θ_JC( C/W)

5VSB

DLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V

All Other Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+ 7.0V

ESD Classification (Human Body Model) . . . . . . . . . . . . . . . . . .2kV

SOIC Package (Note 1) . . . . . . . . . . .

QFN Package (Note 2) . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

70

32

N/A

4.0

o

Recommended Operating Conditions

(SOIC - Lead Tips Only)

For Recommended soldering conditions see Tech Brief TB389.

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

5VSB

Lowest 5VSB Supply Voltage Guaranteeing Parameters . . . . +4.5V

Digital Inputs, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to +5.5V

Sx

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0 C to 125 C

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

the

JA

JC,

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply Current

Shutdown Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

-

17

4

-

mA

5VSB

I

V

= 0.8V

SS

5VSB(OFF)

POWER-ON RESET, SOFT-START, AND VOLTAGE MONITORS

Rising 5VSB POR Threshold

-

4.5

V

5VSB POR Hysteresis

0.9

2.75

150

10

-

Rising 3V3 Threshold

-

V

3V3 Hysteresis

-

mV

µs

µA

V

Falling Threshold Timeout (All Monitors)

-

Soft-Start Current

I

10

-

0.8

-

SS

Shutdown Voltage Threshold

VID_PG Rising Threshold

VID_PG Hysteresis

V

-

SD

1.02

56

V

-

mV

1.5V

LINEAR REGULATOR (V

)

OUT1

SB

Regulation

-

1.5

1.25

75

-

2.0

%

V

1V5SB Nominal Voltage Level

V

-

1V5SB

1V5SB Undervoltage Rising Threshold

1V5SB Undervoltage Hysteresis

1V5SB Output Current

-

V

-

mV

mA

I

V

= 3.3V

85

1V5SB

3V3DL

1.2V

LINEAR REGULATOR (V

)

OUT2

VID

Regulation

-

1.2

0.96

60

-

2.0

%

V

1V2VID Nominal Voltage Level

V

-

1V2VID

1V2VID Undervoltage Rising Threshold

1V2VID Undervoltage Hysteresis

1V2VID Output Current

-

V

-

mV

mA

I

V

= 3.3V

40

3V3

FN9062.2

5

April 13, 2004

ISL6504, ISL6504A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted Refer to Figures 1, 2 and 3 (Continued)

PARAMETER

/3.3V LINEAR REGULATOR (V

OUT3

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

3.3V

)

DUAL

SB

Sleep State Regulation

-

2.0

%

V

3V3DL Nominal Voltage Level

3V3DL Undervoltage Rising Threshold

3V3DL Undervoltage Hysteresis

3V3DLSB Output Drive Current

V

3.3

2.75

150

8

-

3V3DL

-

V

-

mV

mA

I

V

= 5V

5VSB

5

3V3DLSB

5V

SWITCH CONTROLLER (V

)

OUT4

DUAL

5VDL Undervoltage Rising Threshold

5VDL Undervoltage Hysteresis

5VDLSB Output Drive Current

TIMING INTERVALS

-

4.10

200

-

V

mV

mA

I

= 4V V = 5V

, 5VSB

-20

-40

5VDLSB

Active State Assessment Past Input UV

Thresholds (Note 3)

20

25

30

ms

Active-to-Sleep Control Input Delay

VID_CT Charging Current

-

200

10

-

µs

I

V

= 0V

VID_CT

µA

VID_CT

CONTROL I/O (S3, S5, FAULT)

High Level Input Threshold

Low Level Input Threshold

-

0.8

-

2.2

V

-

S3, S5 Internal Pull-up Impedance to 5VSB

FAULT Output Impedance

50

100

kΩ

Ω

FAULT = high

-

TEMPERATURE MONITOR

o

Fault-Level Threshold (Note 4)

Shutdown-Level Threshold (Note 4)

125

-

C

o

155

C

NOTES:

3. Guaranteed by Correlation.

4. Guaranteed by Design.

FN9062.2

6

April 13, 2004

ISL6504, ISL6504A

DLA (Pin 10)

Functional Pin Des cription (SOIC pinout)

This pin is an open-collector output. Connect a 1kΩ resistor

from this pin to the ATX 12V output. This resistor is used to

pull the gates of suitable N-MOSFETs to 12V, which in

active state, switch in the ATX 3.3V and 5V outputs into the

3V3 (Pin 5)

Connect this pin to the ATX 3.3V output. This pin provides

the output current for the 1V2VID pin, and is monitored for

power quality.

3.3V

/3.3V and 5V

SB

outputs, respectively.

DUAL

5VSB (Pin 16)

5VDL (Pin 12)

Provide a very well de-coupled 5V bias supply for the IC to

this pin by connecting it to the ATX 5V output. This pin

provides all the chip’s bias as well as the base current for Q2

(see typical application diagram). The voltage at this pin is

monitored for power-on reset (POR) purposes.

Connect this pin to the 5V

output (V

). In either

OUT4

DUAL

SB

operating state (when on), the voltage at this pin is provided

through a fully-on MOS transistor. This pin is also monitored

for undervoltage events.

5VDLSB (Pin 11)

GND (Pin 8)

Connect this pin to the gate of a suitable P-MOSFET or

bipolar PNP. ISL6504: In S3 sleep state, this transistor is

switched on, connecting the ATX 5V output to the

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

SB

5V

regulator output. ISL6504A: In S3 and S4/S5 sleep

state, this transistor is switched on, connecting the ATX

DUAL

S3 and S5 (Pins 6 and 7)

These pins switch the IC’s operating state from active (S0,

S1/S2) to S3 and S4/S5 sleep states. These are digital

inputs featuring internal 50kΩ (typical) resistor pull-ups to

5VSB. Internal circuitry de-glitches these pins for

disturbances lasting as long as 2µs (typically). Additional

circuitry blocks any illegal state transitions (such as S3 to

S4/S5 or vice versa). Respectively, connect S3 and S5 to

the computer system’s SLP_S3 and SLP_S5 signals.

5V output to the 5V

SB

regulator output.

DUAL

1V5SB (Pin 1)

This pin is the output of the internal 1.5V regulator (V

This internal regulator operates for as long as 5V is

applied to the IC and draws its output current from the

3V3DL pin. This pin is monitored for undervoltage events.

).

OUT1

SB

1V2VID (Pin 4)

FAULT (Pin 9)

This pin is the output of the internal 1.2V voltage

In case of an undervoltage on any of the controlled outputs,

on any of the monitored ATX voltages, or in case of an

overtemperature event, this pin is used to report the fault

condition by being pulled to 5VSB. Connect a 1kΩ resistor

from this pin to GND.

identification (VID) regulator (V

). This internal regulator

OUT2

operates only in active states (S0, S1/S2) and is shut off

during any sleep state. This regulator draws its output

current from the 3V3 pin. This pin is monitored for

undervoltage events.

SS (Pin 13)

VID_PG (Pin 14)

Connect this pin to a small ceramic capacitor (no less than

5nF; 0.1µF recommended). The internal soft-start (SS)

current source along with the external capacitor creates a

voltage ramp used to control the ramp-up of the output

voltages. Pulling this pin low with an open-drain device shuts

down all the outputs as well as force the FAULT pin low. The

This pin is the open collector output of the 1V2VID power

good comparator. Connect a 10kΩ pull-up resistor from this

pin to the 1V2VID output. As long as the 1V2VID output is

below its UV threshold, this pin is pulled low.

VID_CT (Pin 15)

C

capacitor is also used to provide a controlled voltage

Connect a small capacitor from this pin to ground. The

capacitor is used to delay the VID_PG reporting the 1V2VID

has reached power good limits.

SS

slew rate during active-to-sleep transitions on the

3.3V /3.3V output.

DUAL

SB

3V3DL (Pin 3)

Des cription

Connect this pin to the 3.3V dual/stand-by output (V

).

OUT3

Operation

In sleep states, the voltage at this pin is regulated to 3.3V; in

active states, ATX 3.3V output is delivered to this node

through a fully-on N-MOS transistor. During all operating

states, this pin is monitored for undervoltage events. This pin

provides all the output current delivered by the 1V5SB pin.

The ISL6504/A controls 4 output voltages (Refer to Figures

1, 2, and 3). It is designed for microprocessor computer

applications with 3.3V, 5V, 5V , and 12V bias input from an

ATX power supply. The IC is composed of three linear

controllers/regulators supplying the computer system’s

SB

3V3DLSB (Pin 2)

1.5V (V

), 3.3V and PCI slots’ 3.3V power

SB OUT1

SB AUX

Connect this pin to the base of a suitable NPN transistor. In

sleep state, this transistor is used to regulate the voltage at

the 3V3DL pin to 3.3V.

(V

OUT3

), the 1.2V VID circuitry power (V

), a dual

voltage (V

OUT2

switch controller supplying the 5V

), as

OUT4

DUAL

FN9062.2

April 13, 2004

7

ISL6504, ISL6504A

well as all the control and monitoring functions necessary for

complete ACPI implementation.

5VSB

S3

Initialization

The ISL6504/A automatically initializes upon receipt of input

power. The Power-On Reset (POR) function continually

S5

monitors the 5V input supply voltage, initiating

SB

3.3V, 5V

3.3V

/3.3V and 1.5V soft-start operation shortly

SB SB

DUAL

after exceeding POR threshold.

3V3DLSB

DLA

Dual Outputs Operational Truth Table

Table 1 describes the truth combinations pertaining to the

3V3DL

5VDLSB

5VDL

3.3V

and 5V

outputs. The last two lines

DUAL/SB

DUAL

highlight the only difference between the ISL6504 and

ISL6504A. The internal circuitry does not allow the transition

from an S3 (suspend to RAM) state to an S4/S5 (suspend to

disk/soft off) state or vice versa. The only ‘legal’ transitions

are from an active state (S0, S1) to a sleep state (S3, S5)

and vice versa.

FIGURE 4. 5V

AND 3.3V

DIAGRAM; ISL6504

/3.3V TIMING

DUAL SB

DUAL

TABLE 1. 5V

OUTPUT (V

OUT4

) TRUTH TABLE

COMMENTS

DUAL

S5

1

S3

1

3.3VDL/SB

3.3V

5VDL

5V

S0/S1/S2 States (Active)

S3

5VSB

S3

1

0

3.3V

5V

0

1

Note

Maintains Previous State

S4/S5 (ISL6504)

S4/S5 (ISL6504A)

S5

0

3.3V

0V

5V

3.3V, 5V

3V3DLSB

DLA

0

NOTE: Combination Not Allowed.

Functional Timing Diagrams

Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams,

detailing the power up/down sequences of all the outputs in

response to the status of the sleep-state pins (S3, S5), as well

as the status of the input ATX supply. Not shown in these

diagrams is the deglitching feature used to protect against false

sleep state tripping. Both S3 and S5 pins are protected against

noise by a 2µs filter (typically 1–4µs). This feature is useful in

noisy computer environments if the control signals have to

travel over significant distances. Additionally, the S3 pin

features a 200µs delay in transitioning to sleep states. Once the

S3 pin goes low, an internal timer is activated. At the end of

the 200µs interval, if the S5 pin is low, the ISL6504/A

switches into S5 sleep state; if the S5 pin is high, the

ISL6504/A goes into S3 sleep state.

3V3DL

5VDLSB

5VDL

FIGURE 5. 5V

AND 3.3V

/3.3V TIMING

SB

DUAL

DIAGRAM; ISL6504A

DUAL

5VSB

S3

S5

3.3V,

5V, 12V

DLA

1V5SB

1V2VID

FIGURE 6. 1.5V , AND 1.2V

SB

TIMING DIAGRAM

VID

FN9062.2

April 13, 2004

8

ISL6504, ISL6504A

Soft-Start into Sleep States (S3, S4/S5)

The 5V POR function initiates the soft-start sequence. An

SB

5VSB

internal 10µA current source charges an external capacitor.

The error amplifiers reference inputs are clamped to a level

proportional to the SS (soft-start) pin voltage. As the SS pin

voltage slews from about 1.25V to 2.5V, the input clamp

allows a rapid and controlled output voltage rise.

(1V/DIV)

SOFT-START

(1V/DIV)

Figures 7 (ISL6504) and 8 (ISL6504A) show the soft-start

sequence for the typical application start-up into a sleep

0V

state. At time T0 5V (bias) is applied to the circuit. At time

T1, the 5V surpasses POR level. An internal fast charge

SB

VOUT4 (5VDUAL)

circuit quickly raises the SS capacitor voltage to

approximately 1V, then the 10µA current source continues

the charging.

VOUT3 (3.3VDUAL/3.3VSB)

OUTPUT

VOLTAGES

(1V/DIV)

VOUT1 (1.5VSB)

VOUT2

(1.2VVID)

0V

5VSB

(1V/DIV)

T0 T1 T2

T4

T3

T5

SOFT-START

(1V/DIV)

TIME

FIGURE 8. SOFT-START INTERVAL IN A SLEEP

STATE; ISL6054A

0V

The soft-start capacitor voltage reaches approximately

1.25V at time T2, at which point the 3.3V /3.3V and

DUAL SB

1.5V error amplifiers’ reference inputs start their

VOUT4 (5VDUAL) IF S3

VOUT3 (3.3VDUAL/3.3VSB)

SB

transition, resulting in the output voltages ramping up

proportionally. The ramp-up continues until time T3 when the

two voltages reach the set value. As the soft-start capacitor

voltage reaches approximately 2.75V, the undervoltage

monitoring circuit of this output is activated and the soft-start

capacitor is quickly discharged to approximately 1.25V.

Following the 3ms (typical) time-out between T3 and T4, the

soft-start capacitor commences a second ramp-up designed

to smoothly bring up the remainder of the voltages required

by the system. At time T5, voltages are within regulation

limits, and as the SS voltage reaches 2.75V, all the

OUTPUT

VOLTAGES

VOUT1 (1.5VSB)

(1V/DIV)

VOUT2

(1.2VVID)

0V

VOUT4 (5VDUAL) if S5

T5

T0 T1 T2

T4

T3

TIME

remaining UV monitors are activated and the SS capacitor is

quickly discharged to 1.25V, where it remains until the next

FIGURE 7. SOFT-START INTERVAL IN A SLEEP

STATE; ISL6504

transition. As the 1.2V

output is only active while in an

VID

active state, it does not come up, but rather waits until the

main ATX outputs come up within regulation limits.

Soft-Start into Active States (S0, S1)

If both S3 and S5 are logic high at the time the 5V is

SB

applied, the ISL6504/A will assume active state wake-up and

keep off the required outputs until some time (typically

25ms) after the monitored main ATX output (3.3V) exceeds

the set threshold. This time-out feature is necessary in order

to ensure the main ATX outputs are stabilized. The time-out

also assures smooth transitions from sleep into active when

sleep states are being supported. 3.3V

/3.3V and

DUAL SB

1.5V outputs will come up right after bias voltage

SB

surpasses POR level.

FN9062.2

April 13, 2004

9

ISL6504, ISL6504A

the maximum current rating of an integrated regulator

(output with pass regulator on chip) can lead to output

voltage drooping; if excessive, this droop can ultimately trip

the undervoltage detector and send a FAULT signal to the

computer system.

+12VIN

DLA PIN

(2V/DIV)

INPUT VOLTAGES

(2V/DIV)

+5VIN

+5VSB

0V

A FAULT condition occurring on an output when controlled

through an external pass transistor will only set off the

FAULT flag, and it will not shut off or latch off any part of the

circuit. A FAULT condition occurring on an output controlled

through an internal pass transistor, will set off the FAULT

flag, and it will shut off the respective faulting regulator only.

If shutdown or latch off of the entire circuit is desired in case

of a fault, regardless of the cause, this can be achieved by

externally pulling or latching the SS pin low. Pulling the SS

pin low will also force the FAULT pin to go low and reset any

internally latched-off output.

+3.3VIN

SOFT-START

(1V/DIV)

OUTPUT

VOUT4 (5VDUAL)

VOLTAGES

(1V/DIV)

VOUT3 (3.3VDUAL/3.3VSB)

Special consideration is given to the initial start-up

sequence. If, following a 5V POR event, any of the

SB

VOUT1 (1.5VSB)

1.5V or 3.3V

/3.3V outputs is ramped up and is

DUAL SB

SB

VOUT2 (1.2VVID)

subject to an undervoltage event before the end of the

second soft-start ramp, then the FAULT output goes high

and the entire IC latches off. Latch-off condition can be reset

0V

T3

T0

T1

T2

TIME

by cycling the bias power (5V ). Undervoltage events on

SB

the 1.5V and the 3.3V

SB

times are handled according to the description found in the

/3.3V outputs at any other

SB

DUAL

FIGURE 9. SOFT-START INTERVAL IN ACTIVE STATE

second paragraph under the current heading.

During sleep-to-active state transitions from conditions

where the 5V

output is initially 0V (such as S5 to S0

DUAL

Another condition that could set off the FAULT flag is chip

overtemperature. If the ISL6504/A reaches an internal

temperature of 140 C (typical), the FAULT flag is set, but the

transition, or simple power-up sequence directly into active

state), the circuit goes through a quasi soft-start, the

o

5V

output being pulled high through the body diode of

the N-Channel MOSFET connected between it and the 5V

DUAL

chip continues to operate until the temperature reaches

o

155 C (typical), when unconditional shutdown of all outputs

ATX. Figure 9 exemplifies this start-up case. 5V is already

present when the main ATX outputs are turned on, at time

T0. As a result of +5V ramping up, the 5V

capacitors charge up through the body diode of Q4 (see

Typical Application). At time T1, all main ATX outputs

exceed the ISL6504/A’s undervoltage thresholds, and the

internal 25ms (typical) timer is initiated. At T2, the time-out

initiates a soft-start, and the 1.2V voltage ID output is

ramped-up, reaching regulation limits at time T3.

SB

takes place. Operation resumes only after powering down

the IC (to create a 5V POR event) and a start-up

SB

output

IN

DUAL

(assuming the cause of the fault has been removed; if not,

as it heats up again, it will repeat the FAULT cycle).

In ISL6504/A applications, loss of the active ATX output

(3.3V ; as detected by the on-board voltage monitor) during

IN

active state operation causes the chip to switch to S5 sleep

state, in addition to reporting the input UV condition on the

FAULT pin. Exiting from this forced S5 state can only be

achieved by returning the faulting input voltage above its UV

Simultaneous with the beginning of this ramp-up, at time T2,

the DLA pin is released, allowing the pull-up resistor to turn

threshold, by resetting the chip through removal of 5V

on Q2 and Q4, and bring the 5V

output in regulation.

SB

DUAL

bias voltage, or by bringing the SS pin at a potential lower

than 0.8V.

Shortly after time T3, as the SS voltage reaches 2.75V, the

soft-start capacitor is quickly discharged down to

approximately 2.45V, where it remains until a valid sleep

state request is received from the system.

Application Guidelines

Soft-Start Interval

Fault Protection

The 5V output of a typical ATX supply is capable of

SB

725mA, with newer models rated for 1.0A, and even 2.0A.

All the outputs are monitored against undervoltage events. A

severe overcurrent caused by a failed load on any of the

outputs, would, in turn, cause that specific output to

During power-up in a sleep state, the 5V ATX output

SB

needs to provide sufficient current to charge up all the

applicable output capacitors and, simultaneously, provide

some amount of current to the output loads. Drawing

suddenly drop. If any of the output voltages drops below

80% (typical) of their set value, such event is reported by

having the FAULT pin pulled to 5V. Additionally, exceeding

FN9062.2

10

April 13, 2004

ISL6504, ISL6504A

excessive amounts of current from the 5V output of the

ATX can lead to voltage collapse and induce a pattern of

consecutive restarts with unknown effects on the system’s

behavior or health.

SB

80

70

60

50

40

30

20

The built-in soft-start circuitry allows tight control of the slew-

up speed of the output voltages controlled by the ISL6504,

thus enabling power-ups free of supply drop-off events.

Since the outputs are ramped up in a linear fashion, the

current dedicated to charging the output capacitors can be

calculated with the following formula:

I

SS

× V

BG

-----------------------------

I

=

× Σ(C

× V

)

OUT

COUT

OUT

, where

10

0

C

SS

I

- soft-start current (typically 10µA)

SS

0

1

2

3

4

5

6

7

8

9

10

C

- soft-start capacitor

VID_PG Delay (ms)

SS

V

- bandgap voltage (typically 1.26V)

x V ) - sum of the products between the

BG

FIGURE 10. VID_PG DELAY DEPENDENCE ON VID_CT

CAPACITOR

Σ(C

OUT

capacitance and the voltage of an output (total charge

delivered to all outputs)

Layout Cons iderations

The typical application employing an ISL6504/A is a fairly

straight forward implementation. Like with any other linear

regulator, attention has to be paid to the few potentially

sensitive small signal components, such as those connected

to sensitive nodes or those supplying critical bypass current.

Due to the various system timing events and their

interaction, it is recommended that the soft-start interval not

be set to exceed 30ms. For most applications, a 0.1µF

capacitor is recommended.

Shutdown

The power components (pass transistors) and the controller

IC should be placed first. The controller should be placed in

a central position on the motherboard, closer to the memory

controller chip and processor, but not excessively far from

In case of a FAULT condition that might endanger the

computer system, or at any other time, all the ISL6504/A

outputs can be shut down by pulling the SS pin below the

specified shutdown level (typically 0.8V) with an open drain

or open collector device capable of sinking a minimum of

2mA. Pulling the SS pin low effectively shuts down all the

pass elements. Upon release of the SS pin, the ISL6504

undergoes a new soft-start cycle and resumes normal

operation in accordance to the ATX supply and control pins

status.

the 3.3V

island or the I/O circuitry. Ensure the 1V5SB,

DUAL

1V2VID, 3V3, and 3V3DL connections are properly sized to

carry 100mA without exhibiting significant resistive losses at

the load end. Similarly, the input bias supply (5V ) can

SB

carry a significant level of current - for best results, ensure it

is connected to its respective source through an adequately

sized trace. The pass transistors should be placed on pads

capable of heatsinking matching the device’s power

dissipation. Where applicable, multiple via connections to a

large internal plane can significantly lower localized device

temperature rise.

VID_PG Delay

During power-up and initial soft-start, the VID_PG and

VID_CT pins are held low. As the 1V2VID output exceeds its

rising power-good threshold, the capacitor connected at the

VID_CT pin starts to charge up through the internal 10µA

current source. As the voltage on this capacitor exceeds

1.25V, the open-collector VID_PG pin is released and VID

POWER GOOD status is thus reported.

Placement of the decoupling and bulk capacitors should

follow a placement reflecting their purpose. As such, the

high-frequency decoupling capacitors should be placed as

close as possible to the load they are decoupling; the ones

decoupling the controller close to the controller pins, the

ones decoupling the load close to the load connector or the

load itself (if embedded). Even though bulk capacitance

(aluminum electrolytics or tantalum capacitors) placement is

not as critical as the high-frequency capacitor placement,

having these capacitors close to the load they serve is

preferable.

The value of the VID_CT capacitor to be used to obtain a

given VID_PG delay can be determined from the graph in

Figure 10. For extended delays exceeding the range of the

graph, use the following formula:

t

DELAY

, where

C = --------------------

125000

t

- desired delay time (s)

DELAY

The critical small signal components include the soft-start

capacitor, C , as well as all the high-frequency decoupling

capacitors. Locate these components close to the respective

SS

C - VID_CT capacitor to obtain desired delay time (F)

FN9062.2

11

April 13, 2004

ISL6504, ISL6504A

pins of the control IC, and connect them to ground through a

high quality capacitors to supply the high slew rate (di/dt)

current demands. Thus, it is recommended that the output

capacitors be selected for transient load regulation, paying

attention to their parasitic components (ESR, ESL).

via placed close to the ground pad. Minimize any leakage

current paths from the SS node, as the internal current

source is only 10µA (typical).

+12VIN

+5VSB

Also, during the transition between active and sleep states

on the 3.3V

/3.3V and 5V outputs, there is a

DUAL

SB DUAL

CIN

short interval of time during which none of the power pass

elements are conducting - during this time the output

capacitors have to supply all the output current. The output

voltage drop during this brief period of time can be easily

approximated with the following formula:

C5VSB

5VSB

Q3

SS

5VDLSB

VOUT4

CHF4

Q4

CSS

CBULK1

CHF1

5VDL

t





t

∆V

= I

× ESR

+ --------------- , where

1V5SB





OUT

C

CBULK4





VOUT1

OUT

∆V

- output voltage drop

OUT

Q1

CHF3

3V3DLSB

ESR

OUT

- output capacitor bank ESR

DLA

VOUT3

I

- output current during transition

OUT

3V3DL

+5VIN

C

- output capacitor bank capacitance

OUT

CBULK3

ISL6504/A

t - active-to-sleep or sleep-to-active transition time (10µs typ.)

t

CBULK2

VOUT2

1V2VID

GND

The output voltage drop is heavily dependent on the ESR

(equivalent series resistance) of the output capacitor bank,

the choice of capacitors should be such as to maintain the

output voltage above the lowest allowable regulation level.

Q2

3V3

CHF2

Input Capacitors Selection

+3.3VIN

The input capacitors for an ISL6504/A application must have

a sufficiently low ESR so as not to allow the input voltage to

dip excessively when energy is transferred to the output

capacitors. If the ATX supply does not meet the

specifications, certain imbalances between the ATX’s

outputs and the ISL6504/A’s regulation levels could have as

a result a brisk transfer of energy from the input capacitors to

the supplied outputs. At the transition between active and

sleep states, such phenomena could be responsible for the

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT/POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 11. PRINTED CIRCUIT BOARD ISLANDS

A multi-layer printed circuit board is recommended.

Figure 11 shows the connections to most of the components

in the circuit. Note that the individual capacitors shown each

could represent numerous physical capacitors. Dedicate one

solid layer for a ground plane and make all critical

5V voltage drooping excessively and affecting the output

SB

regulation. The solution to such a potential problem is using

larger input capacitors with a lower total combined ESR.

component ground connections through vias placed as close

to the component terminal as possible. Dedicate another

solid layer as a power plane and break this plane into

smaller islands of common voltage levels. Ideally, the power

plane should support both the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers to create power islands connecting the filtering

components (output capacitors) and the loads. Use the

remaining printed circuit layers for small signal wiring.

Trans is tor Selection/Cons iderations

The ISL6504/A usually requires one P-Channel (or bipolar

PNP), two N-Channel MOSFETs, and one bipolar NPN

transistors.

One important criteria for selection of transistors for all the

linear regulators/switching elements is package selection for

efficient removal of heat. The power dissipated in a linear

regulator or an ON/OFF switching element is

P

= I × (V – V

)

OUT

LINEAR

O

IN

Component Selection Guidelines

Output Capacitors Selection

Select a package and heatsink that maintains the junction

temperature below the rating with the maximum expected

ambient temperature.

The output capacitors should be selected to allow the output

voltage to meet the dynamic regulation requirements of

active state operation (S0, S1). The load transient for the

various microprocessor system’s components may require

FN9062.2

April 13, 2004

12

ISL6504, ISL6504A

Q1

The NPN transistor used as sleep state pass element on the

3.3V output has to have a minimum current gain of 100

Q3

If a P-Channel MOSFET is used to switch the 5V output of

SB

the ATX supply into the 5V

output during sleep states,

DUAL

at 1.5V V

DUAL

then the selection criteria of this device is proper voltage

budgeting. The maximum r , however, has to be

and 650mA I

CE

throughout the in-circuit

CE

operating temperature range. For larger current ratings on

the 3.3V output (providing the ATX 5V output rating

DS(ON)

achieved with only 4.5V of gate-to-source voltage, so a logic

level MOSFET needs to be selected. If a PNP device is

chosen to perform this function, it has to have a low-

saturation voltage while providing the maximum sleep

current and have a current gain sufficiently high to be

saturated using the minimum drive current (typically 20mA).

DUAL

SB

is equally extended), selection criteria for Q1 include an

appropriate current gain (h ) and saturation characteristics.

fe

Q2, Q4

These N-Channel MOSFETs are used to switch the 3.3V

and 5V inputs provided by the ATX supply into the

3.3V

/3.3V and 5V outputs while in active (S0,

ISL6504 Application Circuit

Figure 12 shows a typical application circuit for the

DUAL

SB DUAL

S1) state. The main criteria for the selection of these

transistors is output voltage budgeting. The maximum

ISL6504/A. The circuit provides the 3.3V

/3.3V

SB

DUAL

voltage, the ICH4 resume well 1.5V voltage, the 1.2V

r

allowed at highest junction temperature can be

DS(ON)

expressed with the following equation:

SB

voltage identification output, and the 5V

VID

DUAL

V

– V

INmin

OUTmin

keyboard/mouse voltage from +3.3V, +5V , +5V, and

+12VDC ATX supply outputs. Q3 can also be a PNP

r

= -------------------------------------------------- , where

SB

DS(ON)max

I

OUTmax

transistor, such as an MMBT2907AL. For additional, more

detailed information on the circuit, including a Bill-of-

Materials and circuit board description, see Application Note

AN1001. Also see Intersil Corporation’s web page

(www.intersil.com).

V

- minimum input voltage

INmin

- minimum output voltage allowed

- maximum output current

OUTmin

OUTmax

I

+5VIN

R1

+12VIN

1k

+3.3VIN

+5VSB

C1

5VSB

16

1mF

VID_PG

‘VID PGOOD’

+1.2VVID

3V3

5

2

14

15

VID_CT

C2

3V3DLSB

0.1mF

R2

10k

Q1

2SD1802

Q2

HUF76113T3S

1V2VID

+3.3VDUAL/3.3VSB

4

3V3DL

3

+

C3

+

C4

U1

10mF

330mF

ISL6504/A

‘FAULT’

+1.5VSB

FAULT

1V5SB

5VDLSB

9

1

11

Q3

FDV304P

Q4

+

C5

10mF

DLA

HUF76113T3S

R3

1k

10

12

S3

S5

+5VDUAL

5VDL

6

7

S3

S5

+

C6

220mF

SS

13

8

GND

C7

0.1mF

FIGURE 12. TYPICAL ISL6504/A APPLICATION DIAGRAM

FN9062.2

13

April 13, 2004

ISL6504, ISL6504A

Small Outline Plas tic Packages (SOIC)

M16.3 (JEDEC MS-013-AA ISSUE C)

N

16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

0.30

0.51

0.32

10.50

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.0200

0.0125

-

1

2

3

L

9

SEATING PLANE

A

0.0091

0.3977

0.2914

-

-A-

o

0.4133 10.10

3

h x 45

D

0.2992

7.40

4

-C-

0.050 BSC

1.27 BSC

-

α

µ

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C A M B S

N

α

16

7

o

0

8

0

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm (0.024

inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

FN9062.2

14

April 13, 2004

ISL6504, ISL6504A

Quad Flat No-Lead Plas tic Package (QFN)

L20.6x6

20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VJJB ISSUE C)

Micro Lead Frame Plas tic Package (MLFP)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.28

3.55

0.33

0.40

3.85

5, 8

D

6.00 BSC

-

D1

D2

E

5.75 BSC

9

3.70

7, 8

6.00 BSC

-

E1

E2

e

5.75 BSC

9

3.70

7, 8

0.80 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

20

5

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

FN9062.2

15

April 13, 2004

ISL6504, ISL6504A

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INCHES MILLIMETERS

INDEX

M

B

0.25(0.010)

H

SYMBOL

MIN

MAX

0.069

0.010

0.019

0.010

0.394

0.157

MIN

1.35

0.10

0.35

0.19

9.80

3.80

MAX

1.75

NOTES

AREA

E

A

A1

B

C

D

E

e

0.053

0.004

0.014

0.007

0.386

0.150

-

-B-

0.25

-

0.49

9

1

2

3

L

0.25

-

10.00

4.00

3

SEATING PLANE

A

4

-A-

o

D

h x 45

0.050 BSC

1.27 BSC

-

H

h

0.228

0.010

0.016

0.244

0.020

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

-C-

α

µ

5

e

A1

L

6

C

B

0.10(0.004)

N

α

16

7

M

S

B

o

0.25(0.010)

C

A

0

8

0

8

-

Rev. 1 02/02

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. In-

terlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9062.2

16

April 13, 2004


型号：	ISL6504EVAL1
厂家：	Intersil
描述：	Multiple Linear Power Controller with ACPI Control Interface 多元线性电源控制器与ACPI控制接口控制器
文件：	总16页 (文件大小：401K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6504EVAL1 [INTERSIL]

相关型号：

ISL6504EVAL1-T

ISL6505

ISL6505AEVAL2

ISL6505CB

ISL6505CB

ISL6505CB

ISL6505CBZ

ISL6505CBZ-T

ISL6505CR

ISL6505CR

ISL6505CR-T

ISL6505CR-T