ISL6532ACR-T_技术文档

ISL6532A

®

Data Sheet

August 2004

FN9099.3

ACPI Regulator/Controller for

Dual Channel DDR Memory Systems

Features

• Generates 3 Regulated Voltages

The ISL6532A provides a complete ACPI compliant power

solution for up to 4 DIMM dual channel DDR/DDR2 Memory

systems. Included are both a synchronous buck controller

- Synchronous Buck PWM Controller with Standby LDO

- 3A Integrated Sink/Source Linear Regulator with

Accurate VDDQ/2 Divider Reference.

and integrated LDO to supply V

with high current during

DDQ

- Glitch-free Transitions During State Changes

- LDO Regulator for 1.5V Video and Core voltage

S0/S1 states and standby current during S3 state. During

S0/S1 state, a fully integrated sink-source regulator

generates an accurate (V

/2) high current V voltage

• ACPI compliant sleep state control

DDQ

TT

without the need for a negative supply. A buffered version of

the V /2 reference is provided as V . An LDO

controller is also integrated for AGP core voltage regulation.

• Integrated V

REF

Buffer

DDQ REF

• PWM Controller Drives Low Cost N-Channel MOSFETs

• 250kHz Constant Frequency Operation

• Tight Output Voltage Regulation

The switching PWM controller drives two N-Channel

MOSFETs in a synchronous-rectified buck converter

topology. The synchronous buck converter uses voltage-

mode control with fast transient response. Both the switching

regulator and standby LDO provide a maximum static

regulation tolerance of ±2% over line, load, and temperature

ranges. The output is user-adjustable by means of external

resistors down to 0.8V.

- All Outputs: ±2% Over Temperature

• 5V or 3.3V Down Conversion

• Fully-Adjustable Outputs with Wide Voltage Range: Down

to 0.8V supports DDR and DDR2 Specifications

• Simple Single-Loop Voltage-Mode PWM Control Design

• Fast PWM Converter Transient Response

• Under and Over-voltage Monitoring on All Outputs

• OCP on the Switching Regulator

Switching memory core output between the PWM regulator

and the standby LDO during state transitions is

accomplished smoothly via the internal ACPI control

circuitry. The NCH signal provides synchronized switching of

a backfeed blocking switch during the transitions eliminating

the need to route 5V Dual to the memory supply.

• Integrated Thermal Shutdown Protection

• QFN Package Option

- QFN Compliant to JEDEC PUB95 MO-220 QFN - Quad

Flat No Leads - Product Outline

An integrated soft-start feature brings all outputs into

regulation in a controlled manner when returning to S0/S1

state from any sleep state. During S0 the PGOOD signal

- QFN Near Chip Scale Package Footprint; Improves

PCB Efficiency, Thinner in Profile

• Pb-free available

indicates V is within spec and operational.

TT

Each output is monitored for under and over-voltage events.

The switching regulator has over current protection. Thermal

shutdown is integrated.

Applications

•

Single and Dual Channel DDR Memory Power Systems in

ACPI compliant PCs

Pinout

ISL6532A (QFN) TOP VIEW

•

Graphics cards - GPU and memory supplies

• ASIC power supplies

• Embedded processor and I/O supplies

• DSP supplies

28

27

26

25

24

23

22

GNDP

5VSBY

GNDQ

VTT

1

2

3

4

5

6

7

21 PGOOD

Ordering Information

20

19

PHASE

DRIVE2

TEMP. RANGE

o

PKG.

DWG. #

PART NUMBER

( C)

PACKAGE

GND

29

18 FB2

ISL6532ACR

0 to 70

28 Ld 6x6 QFN

L28.6x6

ISL6532ACRZ

(See Note)

28 Ld 6x6 QFN

(Pb-free)

17

16

15

GNDA

COMP

FB

VTT

*Add “-T” suffix to part number for tape and reel packaging.

VDDQ

NOTE: Intersil Pb-free products employ special Pb-free material sets; molding

compounds/die attach materials and 100% matte tin plate termination finish, which

is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that meet or

exceed the Pb-free requirements of IPC/JEDEC J Std-020B.

8

9

10

11

12

13

14

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL6532A

Simplified Power System Diagram

12V

5VSBY

5V

ISL6532A

NCH

Q1

SLP_S3

SLP_S5

SLEEP

STATE

LOGIC

V

DDQ

PWM

CONTROLLER

+

Q2

5VSBY/3V3SBY

STANDBY

LDO

V

DDQ

V

REF

TT

LINEAR

CONTROLLER

Q3

VTT

REGULATOR

V

AGP

+

Typical Application - 5V or 3.3V Input

5VSBY

+12V

+3.3V

C

BP

+5V or +3.3V

R

NCH

PGOOD

S3#

S5#

V

DDQ

SLP_S3

SLP_S5

NCH

Q4

V

REF

+

VREF_OUT

OCSET

C

IN

R

OCSET

VREF_IN

+

UGATE

PHASE

Q1

Q2

V

DDQ

2.5V

L

OUT

+

ISL6532A

VTT

LGATE

V

C

TT

VDDQ_OUT

VDDQ

+

C

VTT_OUT

V

DDQ

GNDQ

VTTSNS

DRIVE2

Q3

FB

COMP

V

AGP

1.5V

FB2

+

GNDP

GNDA

C

OUT2

3

ISL6532A

Typical Application - Input From 5V Dual

5VSBY

+12V

+3.3V

C

BP

5V Dual

PGOOD

S3#

S5#

V

DDQ

SLP_S3

SLP_S5

NCH

V

REF

+

VREF_OUT

VREF_IN

OCSET

C

IN

R

OCSET

UGATE

PHASE

Q1

Q2

V

DDQ

2.5V

L

OUT

+

ISL6532A

VTT

LGATE

V

TT

C

VDDQ_OUT

VDDQ

+

C

VTT_OUT

V

DDQ

GNDQ

VTTSNS

DRIVE2

Q3

FB

V

COMP

AGP

1.5V

FB2

+

GNDP

GNDA

C

OUT2

4

ISL6532A

Absolute Maximum Ratings

Thermal Information

o

5VSBY, P5VSBY . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V

P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V

UGATE, LGATE, NCH . . . . . . . . . . . . . . GND - 0.3V to P12V + 0.3V

All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LEVEL 1

Thermal Resistance (Typical, Notes 1, 2) θ_JA( C/W) θ_JC( C/W)

QFN Package . . . . . . . . . . . . . . . . . . . 32

Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C

5

o

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

o

(SOIC - Lead Tips Only)

Recommended Operating Conditions

Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

Supply Voltage onP5VSBY . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%

o

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 70 C

o

Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0 C to 125 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams and Typical Application Schematics

PARAMETER

5VSBY SUPPLY CURRENT

Nominal Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

S3# & S5# HIGH, UGATE/LGATE Open

3.00

3.50

5.25

-

7.25

4.75

mA

CC_S0

CC_S3

S3# LOW, S5# HIGH, UGATE/LGATE

Open

I

S5# LOW, S3# Dont’t Care,

UGATE/LGATE Open

300

-

800

µA

CC_S5

POWER-ON RESET

Rising 5VSBY POR Threshold

Falling 5VSBY POR Threshold

Rising P12V POR Threshold

Falling P12V POR Threshold

OSCILLATOR AND SOFT-START

PWM Frequency

4.00

3.60

10.0

8.80

-

4.35

3.95

10.5

9.75

V

f

220

-

250

280

-

kHz

V

OSC

Ramp Amplitude

∆V

1.5

OSC

Error Amp Reset Time

VDDQ Soft-Start Interval

REFERENCE VOLTAGE

Reference Voltage

t

Mechanical Off/S5 to S0

6.5

-

9.5

ms

RESET

t

SS

V

-

0.800

-

V

REF

System Accuracy

-2.0

+2.0

%

PWM CONTROLLER ERROR AMPLIFIER

DC Gain

Guaranteed By Design

-

15

-

80

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

6

STATE LOGIC

S3# Transition Level

V

-

1.5

-

V

S3

S5

S5# Transition Level

5

ISL6532A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System

Diagrams and Typical Application Schematics (Continued)

PARAMETER

PWM CONTROLLER GATE DRIVERS

UGATE and LGATE Source

UGATE and LGATE Sink

NCH BACKFEED CONTROL

NCH Current Sink

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

-

-0.8

0.8

-

A

GATE

I

NCH = 0.8V

-

6

mA

V

NCH

NCH Trip Level

V

9.0

9.5

10.0

NCH

VDDQ STANDBY LDO

Output Drive Current

P5VSBY = 5.0V

P5VSBY = 3.3V

-

650

550

mA

VTT REGULATOR

Upper Divider Impedance

Lower Divider Impedance

VREF_OUT Buffer Source Current

R

-

2.5

-

kΩ

mA

A

U

R

L

I

-

2

3

VREF_OUT

Maximum V Load Current

TT

I

Periodic load applied with 30% duty cycle

and 10ms period using ISL6532AEVAL1

evaluation board (see Application Note

AN1056)

-3

-

VTT_MAX

LINEAR REGULATOR

DC GAIN

Guaranteed By Design

-

15

-

80

-

dB

MHz

V/µs

V

Gain Bandwidth Product

Slew Rate

GBWP

SR

-

6

-

DRIVE2 High Output Voltage

DRIVE2 Low Output Voltage

DRIVE2 High Output Source Current

DRIVE2 Low Output Sink Current

PGOOD

10.0

-

10.2

0.16

-1.4

1.3

-

0.40

V

-.5

.85

-

mA

PGOOD Rising Threshold

PGOOD Falling Threshold

PROTECTION

V

S0

-

57.5

45.0

-

%

VTTSNS/ VDDQ

V

VTTSNS/ VDDQ

OCSET Current Source

VDDQ OV Level

I

17

-

20

115

85

22

-

µA

%

OCSET

V

/V

S0

FB REF

VDDQ UV Level

/V

S0

-

%

FB REF

/V

Linear Regulator OV Level

Linear Regulator UV Level

Thermal Shutdown Limit

V

S0

-

115

85

-

%

FB2 REF

/V

S0

-

%

FB2 REF

T

By Design

-

140

-

°C

SD

6

ISL6532A

The FB pin is also monitored for under and over-voltage

events.

Functional Pin Description

5VSBY (Pin 2)

PHASE (Pin 20)

5VSBY is the bias supply of the ISL6532A. It is typically

connected to the 5V standby rail of an ATX power supply.

During S4/S5 sleep states the ISL6532A enters a reduced

Connect this pin to the upper MOSFET’s source. This pin is

used to monitor the voltage drop across the upper MOSFET

for over-current protection.

power mode and draws less than 1mA (I

) from the

CC_S5

5VSBY supply. The supply to 5VSBY should be locally

bypassed using a 0.1µF capacitor.

OCSET (Pin 12)

Connect a resistor (R

) from this pin to the drain of the

OCSET

P12V (Pin 25)

upper MOSFET. R

, an internal 20µA current source

OCSET

(I

), and the upper MOSFET on-resistance (r

)

P12V provides the gate drive to the switching MOSFETs of

OCSET DS(ON)

set the converter over-current (OC) trip point according to

the following equation:

the PWM power stage. The V regulation circuit and the

TT

Linear Driver are also powered by P12V. P12V is not

required except during S0/S1/S2 operation. P12V is typically

connected to the +12V rail of an ATX power supply.

I

xR

OCSET

I

= -------------------------------------------------

PEAK

r

DS(ON)

5VSBY (Pin 11)

An over-current trip cycles the soft-start function.

This pin provides the V

state. The regulator is capable of providing standby V

power from either the 5VSBY or 3.3VSBY rail. It is

recommended that the 5VSBY rail be used as the output

current handling capability of the standby LDO is higher than

with the 3.3VSBY rail.

output power during S3 sleep

DDQ

VDDQ (Pins 7, 8, 9)

DDQ

The VDDQ pins should be connected externally together to

the regulated V output. During S0/S1 states, the VDDQ

DDQ

pins serve as inputs to the V regulator and to the V

Reference precision divider. During S3 state, the VDDQ pins

serve as an output from the integrated standby LDO.

TT TT

GND, GNDA, GNDP, GNDQ (Pins 1, 3, 4, 17, 29)

VTT (Pins 5, 6)

The GND terminals of the ISL6532A provide the return path

The VTT pins should be connect externally together. During

for the V LDO, standby LDO and switching MOSFET gate

TT

S0/S1 states, the VTT pins serve as the outputs of the V

TT

drivers. High ground currents are conducted directly through

the exposed paddle of the QFN package which must be

electrically connected to the ground plane through a path as

low in inductance as possible. GNDA is the Analog ground

pin, GNDQ is the return for the VTT regulator and GNDP is

the return for the upper and lower gate drives.

linear regulator. During S3 state, the V regulator is

TT

disabled.

VTTSNS (Pin 10)

VTTSNS is used as the feedback for control of the V linear

TT

regulator. Connect this pin to the V output at the physical

TT

point of desired regulation.

UGATE (Pin 26)

UGATE drives the upper (control) FET of the V

DDQ

synchronous buck switching regulator. UGATE is driven

between GND and P12V.

VREF_OUT (Pin 13)

VREF_OUT is a buffered version of V and also acts as the

TT

reference voltage for the V linear regulator. It is

TT

recommended that a minimum capacitance of 0.1µF is

LGATE (Pin 27)

connected between V

between VREF_OUT and ground for proper operation.

and VREF_OUT and also

DDQ

LGATE drives the lower (synchronous) FET of the V

synchronous buck switching regulator. LGATE is driven

between GND and P12V.

DDQ

VREF_IN (Pin 14)

A capacitor, C , connected between VREF_IN and ground

SS

FB (Pin 15) and COMP (Pin 16)

is required. This capacitor and the parallel combination of

The V

DDQ

switching regulator employs a single voltage

the Upper and Lower Divider Impedance (R ||R ), sets the

U

L

control loop. FB is the negative input to the voltage loop error

amplifier. The positive input of the error amplifier is

connected to a precision 0.8V reference and the output of

time constant for the start up ramp when transitioning from

S3 to S0/S1/S2.

the error amplifier is connected to the COMP pin. The V

output voltage is set by an external resistor divider

DDQ

The minimum value for C can be found through the

SS

following equation:

connected to FB. With a properly selected divider, V

can

DDQ

C

⋅ V

DDQ

VTTOUT

be set to any voltage between the power rail (reduced by

converter losses) and the 0.8V reference. Loop

compensation is achieved by connecting an AC network

across COMP and FB.

------------------------------------------------

>

C

SS

||

10 ⋅ 2A ⋅ R

R

L

U

7

ISL6532A

The calculated capacitance, C , will charge the output

SS

ACPI compliance is realized through the SLP_S3 and

SLP_S5 sleep signals and through monitoring of the 12V

ATX bus.

capacitor bank on the V rail in a controlled manner without

TT

reaching the current limit of the V LDO.

TT

NCH (Pin 22)

Initialization

NCH is an open-drain output that controls the MOSFET

The ISL6532A automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltages. The POR monitors

the bias voltage at the 5VSBY and P12V pins. The POR

function initiates soft-start operation after the bias supply

voltages exceed their POR thresholds.

blocking backfeed from V

to the input rail during sleep

DDQ

states. A 2kΩ or larger resistor is to be tied between the 12V

rail and the NCH pin. Until the voltage on the NCH pin

reaches the NCH trip level, the PWM is disabled.

If NCH is not actively utilized, it still must be tied to the 12V

rail through a resistor. For systems using 5V dual as the

input to the switching regulator, a time constant, in the form

of a capacitor, can be added to the NCH pad to delay start of

the PWM switcher until the 5V dual has switched from

5VSBY to 5VATX.

ACPI State Transitions

Cold Start (S4/S5 to S0 Transition)

At the onset of a mechanical start, the ISL6532A receives it’s

bias voltage from the 5V Standby bus (5VSBY). As soon as

the SLP_S3 and SLP_S5 have transitioned HIGH, the

ISL6532A starts an internal counter. Following a cold start or

any subsequent S4/S5 state, state transitions are ignored

until the system enters S0/S1. None of the regulators will

begin the soft start procedure until the 5V Standby bus has

PGOOD (Pin 21)

Power Good is an open-drain logic output that changes to a

logic low if any of the three regulators are out of regulation in

S0/S1/S2 state. PGOOD will always be low in any state other

than S0/S1/S2.

exceeded POR, the 12V bus has exceeded POR and V

SLP_S5# (Pin 24)

NCH

has exceeded the trip level.

This pin accepts the SLP_S5# sleep state signal.

Once all of these conditions are met, the PWM error

amplifier will first be reset by internally shorting the COMP

pin to the FB pin. This reset lasts for 2048 clock cycles,

SLP_S3# (Pin 23)

This pin accepts the SLP_S3# sleep state signal.

which is typically 8.2ms (one clock cycle = 1/f

digital soft start sequence will then begin.

). The

OSC

FB2 (Pin 18)

Connect the output of the external linear regulator to this pin

through a properly sized resistor divider. The voltage at this

pin is regulated to 0.8V. This pin is monitored for under and

over-voltage events.

The PWM error amplifier reference input is clamped to a

level proportional to the soft-start voltage. As the soft-start

voltage slews up, the PWM comparator generates PHASE

pulses of increasing width that charge the output

DRIVE2 (Pin 19)

capacitor(s). The internal VTT LDO will also soft start

through the reference that tracks the output of the PWM

regulator. The reference for the AGP LDO controller will rise

relative to the soft start reference. The soft start lasts for

2048 clock cycles, which is typically 8.2ms. This method

provides a rapid and controlled output voltage rise.

Connect this pin to the gate terminal of an external N-

Channel MOSFET transistor. This pin provides the gate

voltage for the linear regulator pass transistor. It also

provides a means of compensating the error amplifier for

applications requiring the transient response of the linear

regulator to be optimized.

Figure 1 shows the soft start sequence for a typical cold

Functional Description

start. Due to the soft start capacitance, C , on the

VREF_IN pin, the S5 to S0 transition profile of the V rail

TT

will have a more rounded features at the start and end of the

SS

Overview

The ISL6532A provides complete control, drive, protection

and ACPI compliance for a regulator powering DDR memory

systems. It is primarily designed for computer applications

powered from an ATX power supply. A 250kHz Synchronous

Buck Regulator with a precision 0.8V reference provides the

proper Core voltage to the system memory of the computer.

An internal LDO regulator with the ability to both sink and

source current and an externally available buffered reference

soft start whereas the V

profile has distinct starting and

DDQ

ending points to the ramp up.

By directly monitoring 12VATX and the SLP_S3 and SLP_S5

signals the ISL6532A can achieve PGOOD status

significantly faster than other devices that depend on

Latched_Backfeed_Cut for timing.

Active to Sleep (S0 to S3 Transition)

that tracks the V

output by 50% provides the V

DDQ

TT

When SLP_S3 goes LOW with SLP_S5 still HIGH, the

ISL6532A will disable the V linear regulator and the AGP

LDO controller. The V

DDQ

termination voltage. The ISL6532A also features an LDO

regulator for 1.5V AGP Video and Core voltage.

TT

standby regulator will be enabled

8

ISL6532A

should be noted that the soft start profile of the V LDO

TT

output will vary according to the value of the capacitor on the

VREF_IN pin.

S3

S5

12VATX 2V/DIV

5VSBY

1V/DIV

V

S3

DDQ

500mV/DIV

S5

V

AGP

500mV/DIV

12VATX 2V/DIV

V

TT

V

DDQ

500mV/DIV

V

AGP

500mV/DIV

PGOOD

5V/DIV

V

TT_FLOAT

V

TT

2048 CLOCK

CYCLES

2048 CLOCK

CYCLES

500mV/DIV

SOFT START ENDS

PGOOD COMPARATOR

ENABLED

SOFT START

INITIATES

12V POR

PGOOD

5V/DIV

FIGURE 1. TYPICAL COLD START

2048 CLOCK

CYCLES

PGOOD COMPARATOR

ENABLED

and the V

switching regulator will be disabled. NCH is

DDQ

12V POR

pulled low to disable the backfeed blocking MOSFET.

PGOOD will also transition LOW. When V is disabled, the

FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION

TT

internal reference for the V regulator is internally shorted

TT

to the V rail. This allows the V rail to float. When

Active to Shutdown (S0 to S5 Transition)

TT

floating, the voltage on the V rail will depend on the

leakage characteristics of the memory and MCH I/O pins. It

is important to note that the V rail may not bleed down to 0V.

TT

When the system transitions from active, S0, state to

shutdown, S4/S5, state, the ISL6532A IC disables all

regulators and forces the PGOOD pin and the NCH pin

LOW.

The V

DDQ

rail will be supported in the S3 state through the

LDO. When S3 transitions LOW, the Standby

standby V

DDQ

V

Over Current Protection (S0 State)

DDQ

regulator is immediately enabled. The switching regulator is

disabled synchronous to the switching waveform. The shut

off time will range between 4 and 8us. The standby LDO is

capable of supporting up to 650mA of load with P5VSBY tied

to the 5V Standby Rail. The standby LDO may receive input

from either the 3.3V Standby rail or the 5V Standby rail

through the P5VSBY pin. It is recommended that the 5V

Standby rail be used as the current delivery capability of the

LDO is greater.

The over-current function protects the switching converter

from a shorted output by using the upper MOSFET on-

resistance, r

, to monitor the current. This method

DS(ON)

enhances the converter’s efficiency and reduces cost by

eliminating a current sensing resistor.

The over-current function cycles the soft-start function in a

hiccup mode to provide fault protection. A resistor (R

)

OCSET

programs the over-current trip level (see Typical Application

diagrams on pages 3 and 4). An internal 20µA (typical)

Sleep to Active (S3 to S0 Transition)

current sink develops a voltage across R

that is

OCSET

When SLP_S3 transitions from LOW to HIGH with SLP_S5

held HIGH and after the 12V rail exceeds POR, the

referenced to the converter input voltage. When the voltage

across the upper MOSFET (also referenced to the converter

ISL6532A will enable the V

switching regulator, disable

DDQ

standby regulator, enable the V LDO and force

input voltage) exceeds the voltage across R

, the over-

OCSET

the V

DDQ

TT

current function initiates a soft-start sequence. The initiation

the NCH pin to a high impedance state turning on the

blocking MOSFET. The AGP LDO goes through a 2048 clock

cycle soft-start. The internal short between the V

reference and the V rail is released. Upon release of the

TT

short, the capacitor on VREF_IN is then charged up through

the internal resistor divider network. The V output will

of soft start will affect all regulators. The V regulator is

TT

directly affected as it receives it’s reference from V

. The

DDQ

TT

AGP LDO will also be soft started, and as such, the AGP

LDO voltage will be disabled while the V

disabled.

regulator is

DDQ

TT

Figure 3 illustrates the protection feature responding to an

over current event. At time T0, an over current condition is

sensed across the upper MOSFET. As a result, the regulator

is quickly shutdown and the internal soft-start function

begins producing soft-start ramps. The delay interval seen

follow this capacitor charge up, and acting as the S3 to S0

transition soft start for the V rail. The PGOOD comparator

TT

is enabled only after 2048 clock cycles, or typically 8.2ms,

have passed following the S3 transition to a HIGH state.

Figure 2 illustrates a typical state transition from S3 to S0. It

9

ISL6532A

by the output is equivalent to three soft-start cycles. The

fourth internal soft-start cycle initiates a normal soft-start

ramp of the output, at time T1. The output is brought back

into regulation by time T2, as long as the over current event

has cleared.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

A small ceramic capacitor should be placed in parallel with

R

to smooth the voltage across

R

in the

OCSET

presence of switching noise on the input voltage.

Had the cause of the over current still been present after the

delay interval, the over current condition would be sensed

and the regulator would be shut down again for another

delay interval of three soft start cycles. The resulting hiccup

mode style of protection would continue to repeat indefinitely.

Over/Under Voltage Protection

All three regulators are protected from faults through internal

Over/Under voltage detection circuitry. If the any rail falls

below 85% of the targeted voltage, then an undervoltage

event is tripped. An under voltage will disable all three

regulators for a period of 3 soft-start cycles, after which a

normal soft-start is initiated. If the output is still under 85% of

target, the regulators will continue to be disabled and soft-

started in a hiccup mode until the fault is cleared. This

protection feature works much the same as the VDDQ PWM

over current protection works. See Figure 3.

V

DDQ

V

AGP

If the any rail exceeds 115% of the targeted voltage, then all

three outputs are immediately disabled. The ISL6532A will

not re-enable the outputs until either the bias voltage is

toggled in order to initiate a POR or the S5 signal is forced

LOW and then back to HIGH.

V

TT

500mV/DIV

Thermal Protection (S0/S3 State)

INTERNAL SOFT-START FUNCTION

DELAY INTERVAL

If the ISL6532A IC junction temperature reaches a nominal

o

temperature of 140 C, all regulators will be disabled. The

ISL6532A will not re-enable the outputs until the junction

o

temperature drops below 110 C and either the bias voltage

is toggled in order to initiate a POR or the SLP_S5 signal is

forced LOW and then back to HIGH.

T0

T1

T2

Shoot-Through Protection

TIME

A shoot-through condition occurs when both the upper and

lower MOSFETs are turned on simultaneously, effectively

shorting the input voltage to ground. To protect from a shoot-

through condition, the ISL6532A incorporates specialized

circuitry which insures that complementary MOSFETs are

not ON simultaneously.

FIGURE 3. V

V

OVER CURRENT PROTECTION AND

DDQ

/V

LDO UNDER VOLTAGE PROTECTION

TT AGP

RESPONSES

The over-current function will trip at a peak inductor current

(I

determined by:

PEAK)

The adaptive shoot-through protection utilized by the V

DDQ

I

x R

OCSET

I

= ----------------------------------------------------

PEAK

regulator looks at the lower gate drive pin, LGATE, and the

upper gate drive pin, UGATE, to determine whether a

MOSFET is ON or OFF. If the voltage from UGATE or from

LGATE to GND is less than 0.8V, then the respective

MOSFET is defined as being OFF and the other MOSFET is

r

DS(ON)

where I

is the internal OCSET current source (20µA

OCSET

typical). The OC trip point varies mainly due to the MOSFET

variations. To avoid over-current tripping in the

normal operating load range, find the R

the equation above with:

r

DS(ON)

allowed to turned ON. This method allows the V

regulator to both source and sink current.

DDQ

resistor from

OCSET

Since the voltage of the MOSFET gates are being measured

to determine the state of the MOSFET, the designer is

encouraged to consider the repercussions of introducing

external components between the gate drivers and their

respective MOSFET gates before actually implementing

such measures. Doing so may interfere with the shoot-

through protection.

1. The maximum r

temperature.

at the highest junction

DS(ON)

2. The minimum I

from the specification table.

OCSET

3. Determine I

for:

PEAK

(∆I)

----------

I

> I

+

,where ∆I is

PEAK

OUT(MAX)

2

the output inductor ripple current.

10

ISL6532A

12V

ATX

Application Guidelines

P12V

C

BP

Layout Considerations

GNDP

V

IN_DDR

Layout is very important in high frequency switching

ISL6532A

converter design. With power devices switching efficiently at

250kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage

spikes can degrade efficiency, radiate noise into the circuit,

and lead to device over-voltage stress. Careful component

layout and printed circuit board design minimizes these

voltage spikes.

NCH

5VSBY

P5VSBY

5VSBY

C

IN

C

BP

GNDP

L

UGATE

PHASE

OUT

Q

1

V

DDQ

As an example, consider the turn-off transition of the control

MOSFET. Prior to turn-off, the MOSFET is carrying the full

load current. During turn-off, current stops flowing in the

MOSFET and is picked up by the lower MOSFET. Any

parasitic inductance in the switched current path generates a

large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components,

and short, wide traces minimizes the magnitude of voltage

spikes.

C

OUT1

LGATE

COMP

Q

2

C

2

C

1

R

2

R

1

FB

C

R

3

R

4

VDDQ(3)

VTT(2)

V

DDQ

There are two sets of critical components in the ISL6532A

switching converter. The switching components are the most

critical because they switch large amounts of energy, and

therefore tend to generate large amounts of noise. Next are

the small signal components which connect to sensitive

nodes or supply critical bypass current and signal coupling.

V

TT

C

OUT2

V

IN_AGP

Q

3

DRIVE2

FB2

R

V

AGP

5

A multi-layer printed circuit board is recommended. Figure 4

shows the connections of the critical components in the

GND PAD

R

6

C

OUT3

converter. Note that capacitors C and C

could each

IN OUT

represent numerous physical capacitors. Dedicate one solid

layer, usually a middle layer of the PC board, for a ground

plane and make all critical component ground connections

with vias to this layer. Dedicate another solid layer as a

power plane and break this plane into smaller islands of

common voltage levels. Keep the metal runs from the

PHASE terminals to the output inductor short. The power

plane should support the input power and output power

nodes. Use copper filled polygons on the top and bottom

circuit layers for the phase nodes. Use the remaining printed

circuit layers for small signal wiring. The wiring traces from

the GATE pins to the MOSFET gates should be kept short

and wide enough to easily handle the 1A of drive current.

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 4. PRINTED CIRCUIT BOARD POWER PLANES

AND ISLANDS

possible. Position the output inductor and output capacitors

between the upper and lower MOSFETs and the load.

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Place the PWM converter compensation

components close to the FB and COMP pins. The feedback

resistors should be located as close as possible to the FB

pin with vias tied straight to the ground plane as required.

In order to dissipate heat generated by the internal V LDO,

TT

the ground pad, pin 29, should be connected to the internal

ground plane through at least four vias. This allows the heat

to move away from the IC and also ties the pad to the ground

plane through a low impedance path.

Feedback Compensation - PWM Buck Converter

Figure 5 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

The switching components should be placed close to the

ISL6532A first. Minimize the length of the connections

(V

) is regulated to the Reference voltage level. The error

OUT

between the input capacitors, C , and the power switches

IN

amplifier output (V ) is compared with the oscillator (OSC)

E/A

by placing them nearby. Position both the ceramic and bulk

input capacitors as close to the upper MOSFET drain as

triangular wave to provide a pulse-width modulated (PWM)

wave with an amplitude of V at the PHASE node.

IN

11

ISL6532A

ND

The PWM wave is smoothed by the output filter (L and C ).

5. Place 2

Pole at Half the Switching Frequency.

O

V

6. Check Gain against Error Amplifier’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

DRIVER

IN

OSC

PWM

L

O

COMPARATOR

V

DDQ

Compensation Break Frequency Equations

-

DRIVER

PHASE

+

∆V

OSC

C

O

1

F

= -----------------------------------

F

= --------------------------------------------------------

Z1

P1

2π x R x C

C

x C

2













1

ESR

(PARASITIC)

---------------------

2π x R

x

2

C

+ C

1

2

Z

FB

1

V

= ------------------------------------------------------

= -----------------------------------

E/A

Z2

P2

2π x (R + R ) x C

2π x R x C

1

3

Z

-

IN

+

REFERENCE

Figure 6 shows an asymptotic plot of the DC-DC converter’s

gain vs. frequency. The actual Modulator Gain has a high

gain peak due to the high Q factor of the output filter and is

not shown in Figure 6. Using the above guidelines should

give a Compensation Gain similar to the curve plotted. The

open loop error amplifier gain bounds the compensation

ERROR

AMP

DETAILED COMPENSATION COMPONENTS

Z

FB

V

DDQ

C

1

Z

IN

C

R

3

2

3

2

gain. Check the compensation gain at F with the

P2

capabilities of the error amplifier. The Closed Loop Gain is

constructed on the graph of Figure 6 by adding the

Modulator Gain (in dB) to the Compensation Gain (in dB).

This is equivalent to multiplying the modulator transfer

function to the compensation transfer function and plotting

the gain.

R

1

COMP

FB

-

+

R

4

ISL6532A

REFERENCE

The compensation gain uses external impedance networks

R









1

V

= 0.8 × 1 + ------



Z

and Z to provide a stable, high bandwidth (BW) overall

DDQ

FB

IN

R



4

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

FIGURE 5. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN AND OUTPUT

VOLTAGE SELECTION

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

OUT E/A

Gain and the output filter (L and C ), with a double pole

100

F

P1

F

P2

Z2

Z1

O

break frequency at F and a zero at F

the modulator is simply the input voltage (V ) divided by the

. The DC Gain of

80

60

40

20

0

LC ESR

OPEN LOOP

ERROR AMP GAIN

IN

peak-to-peak oscillator voltage ∆V

OSC

.

20LOG

(R /R )

Modulator Break Frequency Equations

2

1

20LOG

1

(V /∆V

)

F

= ------------------------------------------

F

= -------------------------------------------

IN OSC

LC

ESR

2π x ESR x C

2π x

L

x C

O O

O

COMPENSATION

GAIN

MODULATOR

GAIN

-20

-40

-60

The compensation network consists of the error amplifier

(internal to the ISL6532A) and the impedance networks Z

CLOSED LOOP

GAIN

IN

F

LC

F

and Z . The goal of the compensation network is to provide

ESR

100K

FREQUENCY (Hz)

FB

10

100

1K

10K

1M

10M

a closed loop transfer function with the highest 0dB crossing

frequency (f

) and adequate phase margin. Phase margin

is the difference between the closed loop phase at f and

0dB

FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

0dB

180 degrees. The equations below relate the compensation

Feedback Compensation - AGP LDO Controller

network’s poles, zeros and gain to the components (R , R ,

1

2

R , C , C , and C ) in Figure 5. Use these guidelines for

locating the poles and zeros of the compensation network:

Figure 7 shows the AGP LDO power and control stage. This

LDO, which uses a MOSFET as the linear pass element,

requires feedback compensation to insure stability of the

system. The LDO requires compensation because of the

output impedance of the error amplifier.

3

1

2

3

1. Pick Gain (R /R ) for desired converter bandwidth.

2

1

ST

2. Place 1 Zero Below Filter’s Double Pole (~75% F ).

LC

ND

3. Place 2

Zero at Filter’s Double Pole.

ST

4. Place 1 Pole at the ESR Zero.

12

ISL6532A

Component Selection Guidelines

ISL6532A

V

DDQ

Output Capacitor Selection - PWM Buck Converter

0.8V

REFERENCE

An output capacitor is required to filter the inductor current

and supply the load transient current. The filtering

requirements are a function of the switching frequency and

the ripple current. The load transient requirements are a

function of the slew rate (di/dt) and the magnitude of the

transient load current. These requirements are generally met

with a mix of capacitors and careful layout.

650Ω

DRIVE2

+

-

OUTPUT

IMPEDANCE

V

C

R

AGP

25

10

FB2

R

8

R

9

DDR memory systems are capable of producing transient

load rates above 1A/ns. High frequency capacitors initially

supply the transient and slow the current load rate seen by

the bulk capacitors. The bulk filter capacitor values are

generally determined by the ESR (Effective Series

Resistance) and voltage rating requirements rather than

actual capacitance requirements.

ESR

OUT

R

LOAD

+

R









C

8

V

= 0.8 × 1 + ------



AGP

R



9

FIGURE 7. COMPENSATION AND OUTPUT VOLTAGE

SELECTION OF THE LINEAR

To properly compensate the LDO system, a 100kΩ 1%

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

resistor and a 680pF X5R ceramic capacitor, represented as

R10 and C25 in Figure 7, are used. This compensation will

insure a stable system with any MOSFET given the following

conditions:

τ = C

⋅ ESR > 10µs

OUT

R

= R = 249Ω

8

FB

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient.

An aluminum electrolytic capacitor’s ESR value is related to

the case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

Maximum bandwidth will be realized at full load while

minimum bandwidth will be realized at no load. Bandwidth at

no load will be maximized as τ becomes closer to 10µs.

Output Voltage Selection

The output voltage of the V

PWM converter can be

DDQ

programmed to any level between V and the internal

IN

reference, 0.8V. An external resistor divider is used to scale

the output voltage relative to the reference voltage and feed

it back to the inverting input of the error amplifier, see

Figure 5. However, since the value of R1 affects the values of

the rest of the compensation components, it is advisable to

keep its value less than 5kΩ. Depending on the value chosen

for R1, R4 can be calculated based on the following equation:

R1 × 0.8V

R4 = -----------------------------------

V

- 0.8V

Output Capacitor Selection - LDO Regulators

DDQ

The output capacitors used in LDO regulators are used to

provide dynamic load current. The amount of capacitance

and type of capacitor should be chosen with this criteria in

mind.

If the output voltage desired is 0.8V, simply route V

to the FB pin through R1, but do not populate R4.

back

DDQ

The output voltage for the internal V linear regulator is set

TT

internal to the ISL6532A to track the V

voltage by 50%.

DDQ

Output Inductor Selection

There is no need for external programming resistors.

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

As with the V PWM regulator, the AGP linear regulator

DDQ

output voltage is set by means of an external resistor divider

as shown in Figure 7. For stability concerns described

earlier, the recommended value of the feedback resistor, R8,

is 249Ω. The voltage programming resistor, R9 can be

calculated based on the following equation:

V

- V

OUT

V

OUT

IN

Fs x L

R

× 0.8V

∆V = ∆I x ESR

OUT

∆I =

x

8

R

= ----------------------------------

V

IN

9

V

- 0.8V

AGP

13

ISL6532A

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

For a through hole design, several electrolytic capacitors

may be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These

capacitors must be capable of handling the surge-current at

power-up. Some capacitor series available from reputable

manufacturers are surge current tested.

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6532A will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

MOSFET Selection - PWM Buck Converter

The ISL6532A requires 2 N-Channel power MOSFETs for

switching power and a third MOSFET to block backfeed from

V

to the Input in S3 Mode. These should be selected

DDQ

based upon r

, gate supply requirements, and thermal

DS(ON)

management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor. The switching losses seen when

sourcing current will be different from the switching losses

seen when sinking current. When sourcing current, the

upper MOSFET realizes most of the switching losses. The

lower switch realizes most of the switching losses when the

converter is sinking current (see the equations below).

These equations assume linear voltage-current transitions

and do not adequately model power loss due the reverse-

recovery of the upper and lower MOSFET’s body diode. The

gate-charge losses are dissipated in part by the ISL6532A

and do not significantly heat the MOSFETs. However, large

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

V

OUT

IN

where: I

is the transient load current step, t

is the

TRAN

RISE

is the

response time to the application of load, and t

FALL

response time to the removal of load. The worst case

response time can be either at the application or removal of

load. Be sure to check both of these equations at the

minimum and maximum output levels for the worst case

response time.

Input Capacitor Selection - PWM Buck Converter

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time the upper MOSFET

turns on. Place the small ceramic capacitors physically close

to the MOSFETs and between the drain of upper MOSFET

and the source of lower MOSFET.

gate-charge increases the switching interval, t

which

SW

increases the MOSFET switching losses. Ensure that both

MOSFETs are within their maximum junction temperature at

high ambient temperature by calculating the temperature

rise according to package thermal-resistance specifications.

A separate heatsink may be necessary depending upon

MOSFET power, package type, ambient temperature and air

flow.

The important parameters for the bulk input capacitance are

the voltage rating and the RMS current rating. For reliable

operation, select bulk capacitors with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. Their voltage rating should be

at least 1.25 times greater than the maximum input voltage,

while a voltage rating of 1.5 times is a conservative

guideline. For most cases, the RMS current rating

Approximate Losses while Sourcing current

2

1

--

P

= Io × r

× D + ⋅ Io × V × t

× f

SW

UPPER

LOWER

DS(ON)

IN

2

s

2

P

= Io x r

x (1 - D)

DS(ON)

Approximate Losses while Sinking current

2

P

= Io x r

x D

UPPER

DS(ON)

requirement for the input capacitor of a buck regulator is

approximately 1/2 the DC load current.

2

1

--

P

= Io × r

× (1 - D) + ⋅ Io × V × t

× f

SW s

LOWER

DS(ON)

IN

2

Where: D is the duty cycle = V

OUT

/ V ,

IN

is the combined switch ON and OFF time, and

The maximum RMS current required by the regulator may be

closely approximated through the following equation:

t

SW

f is the switching frequency.

s

2

V_OUT

-------------

V_IN

V_IN- V_OUTV_OUT

2

1

12





 

------

----------------------------- -------------

I_RMS

=

× I_OUT

+

×



 

V_IN

L × f_s

MAX

14

ISL6532A

ISL6532A Application Circuit

MOSFET Selection - AGP LDO

The main criteria for selection of the linear regulator pass

transistor is package selection for efficient removal of heat.

Select a package and heatsink that maintains the junction

temperature below the rating with a maximum expected

ambient temperature.

Figure 8 shows an application circuit utilizing the ISL6532A.

Detailed information on the circuit, including a complete Bill-

of-Materials and circuit board description, can be found in

Application Note AN1056.

The power dissipated in the linear regulator is:

P

≅ I × (V - V

)

OUT

LINEAR

O

IN

where I is the maximum output current and V

O

is the

OUT

nominal output voltage of the linear regulator.

VCC5

5VSBY

VCC12

R

1

+3.3V

4.99kΩ

C

17,18

1µF

Q

5

R

C

2

16

1µF

10.0kΩ

L

PGOOD

S5#

1

NCH

2.1µH

V

DDQ

SLP_S5

SLP_S3

C

1000pF

22

S3#

C

26

0.1µF

V

REF

+

C

1-3

4,5

1µF

OCSET

VREF_OUT

VREF_IN

2200µF

R

7

8.87kΩ

C

0.1µF

27

V

UGATE

PHASE

Q

DDQ

1,3

C

19

0.47µF

2.5V 15A

MAX

V

DDQ

L

2

C

+

6-8

+

ISL6532A

2.1µH

V

C

TT

1.25V

20

220µF

1800µF

VTT

C

22µF

LGATE

9-12

Q

2,4

VDDQ

+

C

220µF

21

V

DDQ

VTTSNS

DRIVE2

R

4

1.74kΩ

GNDQ

Q

4

R

100kΩ

10

FB

V

AGP

1.5V

C

R

5

22.6Ω

COMP

680pF

25

13

56nF

FB2

C

15

R

1000pF

8

+

R

9

C

220µF

23

249Ω

C

287Ω

24

1µF

C

6.8nF

R

14

3

19.1kΩ

R

6

825Ω

FIGURE 8. DDR SDRAM AND AGP VOLTAGE REGULATOR USING THE ISL6532A

15

ISL6532A

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L28.6x6

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

A

A1

A2

A3

b

0.80

0.90

-

9

0.20 REF

9

0.23

3.95

0.28

0.35

4.25

5, 8

D

6.00 BSC

-

D1

D2

E

5.75 BSC

9

4.10

7, 8

6.00 BSC

-

E1

E2

e

5.75 BSC

9

4.10

7, 8

0.65 BSC

-

k

0.25

0.35

-

L

0.60

0.75

0.15

8

L1

N

-

28

7

-

10

2

Nd

Ne

P

3

-

0.60

12

9

θ

-

9

Rev. 1 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

16


型号：	ISL6532ACR-T
厂家：	Intersil
描述：	ACPI Regulator/Controller for Dual Channel DDR Memory Systems ACPI稳压器/控制器双通道DDR内存系统稳压器开关双倍数据速率控制器
文件：	总16页 (文件大小：495K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6532ACR-T [INTERSIL]

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