ISL6537ACRZA [INTERSIL]
ACPI Regulator/Controller for Dual Channel DDR Memory Systems; ACPI稳压器/控制器双通道DDR内存系统型号: | ISL6537ACRZA |
厂家: | Intersil |
描述: | ACPI Regulator/Controller for Dual Channel DDR Memory Systems |
文件: | 总16页 (文件大小:407K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ISL6537A
®
Data Sheet
July 18, 2007
FN9143.5
ACPI Regulator/Controller for
Features
Dual Channel DDR Memory Systems
• Generates 5 Regulated Voltages
- Synchronous Buck PWM Controller for DDR V
The ISL6537A provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
DDQ
- 3A Integrated Sink/Source Linear Regulator with
Accurate VDDQ/2 Divider Reference for DDR V
TT
supply V
during S0/S1 and S3 states. During S0/S1 state,
DDQ
- PWM Regulator for GMCH Core
a fully integrated sink-source regulator generates an accurate
(V /2) high current V voltage without the need for a
- LDO Regulator for CPU/GMCH V Termination
TT
DDQ
TT
- LDO Regulator for DAC
negative supply. A buffered version of the V
/2 reference is
DDQ
provided as V
. A second PWM controller, which requires
REF
• ACPI Compliant Sleep State Control
• Glitch-Free Transitions During State Changes
external MOSFET drivers, is available for regulation of the
GMCH Core voltage. An LDO controller is also integrated for
the CPU V termination voltage regulation and the DAC.
TT
• Integrated V
Buffer
REF
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±2% over line, load, and temperature ranges. The output is
user-adjustable by means of external resistors down to 0.8V.
• V
DDQ
MOSFETs
PWM Controller Drives Low Cost N-Channel
• 250kHz Constant Frequency Operation
- Both PWM Controllers are Phase Shifted 180°
• Tight Output Voltage Regulation
- All Outputs: ±2% Over Temperature
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
• Fully-Adjustable Outputs with Wide Voltage Range: Down
to 0.8V Supports DDR and DDR2 Specifications
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring
indicates that the GMCH and CPU V termination voltage
TT
is within spec and operational.
All outputs, except VDAC, have undervoltage protection.
The switching regulator also has overvoltage and
overcurrent protection. Thermal shutdown is integrated.
• OCP on the V
DDQ
Switching Regulator
• Integrated Thermal Shutdown Protection
Pinout
ISL6537A (6X6 QFN)
• Pb-Free Plus Anneal Available (RoHS Compliant)
TOP VIEW
Applications
•
Single and Dual Channel DDR Memory Power Systems in
ACPI Compliant PCs
28 27 26 25 24 23 22
1
2
3
4
5
6
7
21
20
19
5VSBY
S3#
DRIVE3
FB3
•
Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
P12V
PWM4
• Embedded Processor and I/O Supplies
• DSP Supplies
GND
29
GND
18 FB4
17
DDR_VTT
DDR_VTT
VDDQ
COMP4
16 COMP
15 FB
8
9
10 11 12 13 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6537A
Ordering Information
TEMPERATURE
PKG.
PART NUMBER
ISL6537ACR
PART MARKING
ISL6537ACR
RANGE (°C)
PACKAGE
28 Ld 6x6 QFN
DWG. #
0 to +70
L28.6x6
ISL6537ACRZ (Note)
ISL6537ACRZA (Note)
ISL6537ACRZ
ISL6537ACRZ
0 to +70
28 Ld 6x6 QFN (Pb-free)
28 Ld 6x6 QFN (Pb-free)
L28.6x6
L28.6x6
0 to +70
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN9143.5
2
Block Diagram
S3# S5#
FB
COMP
5VSBY
P12V
BOOT
180°
PHASE
SHIFT
250kHz
OSCILLATOR
PWM4
EA1
POR
UGATE
PWM
COMP4
5VSBY
EA1 ACTIVE
IN S3
EA4
MONITOR AND CONTROL
LGATE
FB4
SOFTSTART & ENABLE A
SOFTSTART & ENABLE B
SOFTSTART & ENABLE C
ENABLE DDR_VTT
ENABLE VIDPGD
FAULT
PHASE
OCSET
OC
COMP
VOLTAGE
REFERENCE
20µA
0.800V
P12V
0.680V (-15%)
0.920V (+15%)
VTTSNS
VDDQ(2)
VTT(2)
EA2
S3
DRIVE2
FB2
VTT
REG
UV
R
U
UV/OV
UV
UV/OV
VREF_IN
P12V
R
L
EA3
VREF_OUT
DRIVE3
FB3
VIDPGD
GND PAD
GND(2)
ISL6537A
Simplified Power System Diagram
12V
5VSBY
5VDUAL
3V3ATX
SLP_S3
ISL6537A
SLEEP
STATE
LOGIC
SLP_S5
Q1
Q2
V
DDQ
PWM
CONTROLLER
+
Q3
V
GMCH
PWM
CONTROLLER
+
Q4
V
REF
VTT
REGULATOR
V
TT
+
3V3ATX
Q6
LINEAR
CONTROLLER
Q5
TT_GMCH/CPU
LINEAR
CONTROLLER
V
V
DAC
+
+
Typical Application
5VSBY
12V
3VDUAL
5VDUAL
D
BOOT
VIDPGD
BOOT
ATX3V3
SLP_S5
S5#
S3#
R
OCSET
OCSET
SLP_S3
C
BOOT
Q1
UGATE
PHASE
ISL6537A
Q3
Q4
V
+
DDQ_DDR
V
GMCH
PWM4
Q2
R3
LGATE
C5
C6
COMP4
FB4
DDR_VDDQ(x2)
COMP
R6
C1
C2
R5
R2
C3
R8
FB
R1
R7
C7
Q5
R4
DRIVE2
FB2
V
V
TT_GMCH/CPU
REF
VREF_OUT
VREF_IN
R9
ATX3V3
R10
V
TT_DDR
DDR_VTT(x2)
DDR_VTTSNS
DRIVE3
FB3
Q6
V
DAC
R11
R12
FN9143.5
4
ISL6537A
Absolute Maximum Ratings
Thermal Information
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V
Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W)
QFN Package . . . . . . . . . . . . . . . . . . .
32
5
Absolute Boot Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
BOOT
Upper Driver Supply Voltage, V
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
- V
. . . . . . . . 7.0V (DC)
BOOT
8.0V (<10ns Pulse Width, 10μJ)
PHASE
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER
5VSBY SUPPLY CURRENT
Nominal Supply Current
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
UNITS
I
I
S3# and S5# HIGH, UGATE/LGATE Open
5.5
-
7.0
8.0
mA
CC_S0
CC_S5
S5# LOW, S3# Don’t Care, UGATE/LGATE Open
700
850
μA
POWER-ON RESET
Rising 5VSBY POR Threshold
Falling 5VSBY POR Threshold
Rising P12V POR Threshold
Falling P12V POR Threshold
OSCILLATOR AND SOFT-START
PWM Frequency
4.10
3.60
10.0
8.80
-
-
-
-
4.45
3.95
10.5
9.75
V
V
V
V
f
220
-
250
1.5
8.2
280
-
kHz
V
OSC
Ramp Amplitude
ΔV
OSC
SS
Soft-Start Interval
t
6.5
9.5
ms
REFERENCE VOLTAGE
Reference Voltage
V
-
0.800
-
-
V
REF
System Accuracy
-2.0
+2.0
%
V
AND V
PWM CONTROLLER ERROR AMPLIFIERS
GMCH
DDQ
DC Gain
(Note 3)
-
15
-
80
-
-
-
-
dB
Gain-Bandwidth Product
Slew Rate
GBWP
SR
(Note 3)
(Note 3)
MHz
V/μs
6
CONTROL I/O (S3#, S5#)
LOW Level Input Threshold
HIGH Level Input Threshold
0.75
-
-
-
-
V
V
2.2
FN9143.5
5
ISL6537A
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
UGATE and LGATE Sink
SYMBOL
TEST CONDITIONS
MIN
TYP MAX
UNITS
I
I
-
-
-0.8
0.8
-
-
A
A
GATE
GATE
VTT REGULATOR
Upper Divider Impedance
R
-
-
2.5
2.5
-
-
-
kΩ
kΩ
mA
A
U
Lower Divider Impedance
R
L
VREF_OUT Buffer Source Current
I
-
2
3
VREF_OUT
Maximum V Load Current
TT
I
Periodic load applied with 30% duty cycle and
10ms period using ISL6537A_6506EVAL1
evaluation board (see Application Note AN1124)
-3
-
VTT_MAX
LINEAR REGULATORS
DC Gain
(Note 3)
-
80
-
-
dB
MHz
V/μs
V
Gain Bandwidth Product
Slew Rate
GBWP
SR
(Note 3)
15
-
(Note 3)
-
6
-
DRIVEn High Output Voltage
DRIVEn Low Output Voltage
DRIVEn High Output Source Current
DRIVEn Low Output Sink Current
VIDPGD
DRIVEn Unloaded
9.75
10.0
0.16
1.7
1.20
-
-
-
-
0.50
V
V
V
= 770mV, V
= 830mV, V
= 0V
-
-
mA
mA
FB
FB
DRIVEn
DRIVEn
= 10V
V
V
Rising Threshold
Falling Threshold
S0
S0
.725
-
.740
-
V
V
TT_GMCH/CPU
TT_GMCH/CPU
0.700 0.715
PROTECTION
OCSET Current Source
I
18
20
-
22
μA
A
OCSET
V
V
V
V
V
V
V
Current Limit
(Note 3)
S0/S3
S0/S3
S0
-3.3
3.3
TT_DDR
OV Level
V
V
/V
FB REF
-
-
-
-
-
-
-
115
75
-
-
-
-
-
-
-
%
%
%
%
%
%
°C
DDQ
UV Level
/V
FB REF
DDQ
OV Level
UV Level
V
V
/V
TT VREF_IN
115
85
TT_DDR
TT_DDR
/V
TT VREF_IN
S0
UV Level
V
V
/V
FB4 REF
S0
75
GMCH
TT_GMCH/CPU
UV Level
/V
FB2 REF
S0
75
Thermal Shutdown Limit
NOTE:
T
(Note 3)
140
SD
3. Limits should be considered typical and are not production tested
P12V (Pin 3)
The V regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
Functional Pin Description
TT
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537A enters a reduced
GND (Pins 4, 27, 29)
power mode and draws less than 1mA (I
) from the
CC_S5
5VSBY supply. The supply to 5VSBY should be locally
The GND terminals of the ISL6537A provide the return path
bypassed using a 0.1μF capacitor.
for the V LDO, and switching MOSFET gate drivers. High
TT
FN9143.5
6
ISL6537A
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
pins serve as inputs to the V regulator and to the V
TT
Reference precision divider.
TT
DDR_VTT (Pins 5, 6)
The DDR_VTT pins should be connected externally
together. During S0/S1 states, the DDR_VTT pins serve as
the outputs of the V linear regulator. During S3 state, the
UGATE (Pin 26)
Connect this pin to the upper MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the upper
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the upper
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the upper MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
TT
regulator is disabled.
V
TT
DDR_VTTSNS (Pin 9)
VTTSNS is used as the feedback for control of the V linear
TT
regulator. Connect this pin to the V output at the physical
TT
point of desired regulation.
VREF_OUT (Pin 13)
VREF_OUT is a buffered version of V and also acts as the
TT
LGATE (Pin 28)
reference voltage for the V linear regulator. It is
recommended that a minimum capacitance of 0.1μF is
TT
Connect this pin to the lower MOSFET’s gate. This pin
provides the PWM-controlled gate drive for the lower
MOSFET. This pin is also monitored by the adaptive shoot-
through protection circuitry to determine when the lower
MOSFET has turned off. Do not insert any circuitry between
this pin and the gate of the lower MOSFET, as it may
interfere with the internal adaptive shoot-through protection
circuitry and render it ineffective.
connected between V
and VREF_OUT and also
DDQ
between VREF_OUT and ground for proper operation.
VREF_IN (Pin 14)
A capacitor, C , connected between VREF_IN and ground
SS
is required. This capacitor and the parallel combination of
the Upper and Lower Divider Impedance (R ||R ), sets the
U
L
time constant for the start up ramp when transitioning from
S3/S4/S5 to S0/S1/S2.
FB (Pin 15) and COMP (Pin 16)
The V
DDQ
switching regulator employs a single voltage
control loop. FB is the negative input to the voltage loop error
amplifier. The V output voltage is set by an external
The minimum value for C can be found through the
SS
following equation:
DDQ
resistor divider connected to FB. With a properly selected
divider, V can be set to any voltage between the power
C
⋅ V
DDQ
VTTOUT
(EQ. 2)
------------------------------------------------
>
SS
DDQ
C
||
10 ⋅ 2A ⋅ R
R
L
U
rail (reduced by converter losses) and the 0.8V reference.
Loop compensation is achieved by connecting an AC
network across COMP and FB.
The calculated capacitance, C , will charge the output
SS
capacitor bank on the V rail in a controlled manner without
TT
The FB pin is also monitored for under and overvoltage
events.
reaching the current limit of the V LDO.
TT
BOOT (Pin 25)
PHASE (Pin 24)
This pin provides ground referenced bias voltage to the
upper MOSFET driver. A bootstrap circuit is used to create a
voltage suitable to drive a logic-level N-channel MOSFET.
Connect this pin to the upper MOSFET’s source. This pin is
used to monitor the voltage drop across the upper MOSFET
for overcurrent protection.
PWM4 (Pin 19)
OCSET (Pin 22)
Connect a resistor (R
This pin provides the PWM output for the GMCH core
switching regulator. Connect this pin to the PWM input of an
Intersil MOSFET driver.
) from this pin to the drain of the
, an internal 20μA current source
OCSET
upper MOSFET. R
(I
OCSET
), and the upper MOSFET on-resistance (r
DS(ON)
)
OCSET
FB4 (Pin 19) and COMP4 (Pin 17)
set the converter overcurrent (OC) trip point according to the
following equation:
The GMCH core switching regulator employs a single
voltage control loop. FB4 is the negative input to the voltage
loop error amplifier. The GMCH core output voltage is set by
an external resistor divider connected to FB4. With a
I
xR
OCSET
OCSET
(EQ. 1)
I
= -------------------------------------------------
PEAK
r
DS(ON)
properly selected divider, V
can be set to any voltage
GMCH
An overcurrent trip cycles the soft-start function.
between the power rail (reduced by converter losses) and
the 0.8V reference. Loop compensation is achieved by
connecting an AC network across COMP4 and FB4.
VDDQ (Pins 7, 8)
The VDDQ pins should be connected externally together to
the regulated V
output. During S0/S1 states, the VDDQ
DDQ
The FB4 pin is also monitored for undervoltage events.
FN9143.5
7
ISL6537A
FB2 (Pin 18)
Initialization
Connect the output of the V
linear regulator to
The ISL6537A automatically initializes upon receipt of input
power. Special sequencing of the input supplies is not
necessary. The Power-On Reset (POR) function continually
monitors the input bias supply voltages. The POR monitors
the bias voltage at the 5VSBY and P12V pins. The POR
function initiates soft-start operation after the bias supply
voltages exceed their POR thresholds.
TT_GMCH/CPU
this pin through a properly sized resistor divider. The voltage
at this pin is regulated to 0.8V. This pin is monitored for
undervoltage events.
DRIVE2 (Pin 10)
This pin provides the gate voltage for the V
TT_GMCH/CPU
linear regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
ACPI State Transitions
Figure 1 shows how the individual regulators are controlled
during all state transitions. All references to timing in this
section are in reference to Figure 1.
FB3 (Pin 18)
Connect the output of the DAC linear regulator to this pin
through a properly sized resistor divider. The voltage at this
pin is regulated to 0.8V.
Cold Start (S4/S5 to S0 Transition)
At the onset of a mechanical start, time t in Figure 1, the
0
DRIVE3 (Pin 10)
ISL6537A receives its bias voltage from the 5V Standby bus
(5VSBY). Once the 5VSBY rail has exceeded the POR
threshold, the ISL6537A will remain in an internal S5 state
until both the SLP_S3 and SLP_S5 signal have transitioned
high and the 12V POR threshold has been exceeded by the
This pin provides the gate voltage for the DAC linear
regulator pass transistor. Connect this pin to the gate
terminal of an external N-Channel MOSFET transistor.
VIDPGD (Pin 12)
+12V rail from the ATX, which occurs at time t .
1
The VIDPGD pin is an open-drain logic output that changes
to a logic low if the V
regulation in S0/S1/S2 state. VIDPGD will always be low in
any state other than S0/S1/S2.
linear regulator is out of
Once all of these conditions are met, the PWM error
amplifiers will first be reset by internally shorting the COMP
pins to the respective FB pins. This reset lasts for three soft-
start cycles, which is typically 24ms (one soft-start cycle is
typically 8.2ms). The digital soft-start sequence will then
begin. Each regulator is enabled and soft-started according
to a preset sequence.
TT_GMCH/CPU
SLP_S5# (Pin 23)
This pin accepts the SLP_S5# sleep state signal.
SLP_S3# (Pin 2)
This pin accepts the SLP_S3# sleep state signal.
At time t , the 3 soft-start cycle reset has ended and the
2
V
rail is digitally soft-started.
DDQ_DDR
Functional Description
The digital soft-start for both PWM regulators is accomplished
by clamping the error amplifier reference input to a level
proportional to the internal digital soft-start voltage. As the soft-
start voltage slews up, the PWM comparator generates PHASE
pulses of increasing width that charge the output capacitor(s).
This method provides a rapid and controlled output voltage rise.
Overview
The ISL6537A provides complete control, drive, protection
and ACPI compliance for regulator powering DDR memory
systems and the GMCH core and GMCH/CPU termination
rails. It is primarily designed for computer applications
powered from an ATX power supply.
The linear regulators, with the exception of the internal
V
LDO, are soft-started in a similar manner. The
A 250kHz Synchronous Buck Regulator with a precision
0.8V reference provides the proper Core voltage to the
system memory of the computer. An internal LDO regulator
with the ability to both sink and source current and an
TT_DDR
error amplifier reference is clamped to the internal digital
soft-start voltage. As the soft-start voltage ramps up, the
respective DRIVE pin voltages increase, thus enhancing the
N-MOSFETs and charging the output capacitors in a
controlled manner.
externally available buffered reference that tracks the V
DDQ
output by 50% provides the V termination voltage.
TT
At time t , the V
DDQ_DDR
rail is in regulation and the
rail is in
and the DAC linear
A second 250kHz PWM Buck regulator, which requires an
external MOSFET driver, provides the GMCH core voltage.
This PWM regulator is +180° out of phase with the PWM
regulator used for the Memory core. Two additional LDO
controllers are included, one for the regulation of the
GMCH/CPU termination rail and the second for the DAC.
3
V
rail is soft-started. At time t , the V
GMCH
regulation and the V
4
GMCH
TT_GMCH/CPU
regulators are soft-started. At time t , the V
5
TT_GMCH/CPU
internal
rail and DAC rails are in regulation and the V
regulator is soft-started.
TT_DDR
The V
LDO soft-starts in a manner unlike the other
regulators. When the V regulator is disabled, the
ACPI compliance is realized through the SLP_S3 and
SLP_S5 sleep signals and through monitoring of the 12V
ATX bus.
TT_DDR
TT_DDR
reference is internally shorted to the V
output. This
TT_DDR
FN9143.5
8
SLP_S3#
SLP_S5#
12V
POR
12V
0V
V
DDQ_DDR
0V
V
GMCH
0V
V
TT_GMCH/CPU
0V
V
DAC
0V
DDQ_DDR
V
TT_DDR Soft-Start Rise Time Dependent Upon Capacitor On V
Pin
REF_IN
V
V
TT_DDR
0V
V
FLOATING
TT_DDR
VIDPGD
(3 SOFTSTART CYCLES)
(3 SOFTSTART CYCLES)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
FIGURE 1. ISL6537A TIMING DIAGRAM
ISL6537A
allows the termination voltage to float during the S3 sleep
state. When the ISL6537A enables the V regulator
or enters S0 state from a sleep state, this short is released
and the internal divide down resistors which set the
Fault Protection
The ISL6537A monitors the V
TT_DDR
regulator for under and
regulator also has overcurrent
DDQ
overvoltage events. The V
DDQ
protection. The internal V
LDO regulator is monitored
TT_DDR
V
voltage to 50% of V will provide a
TT_DDR
DDQ_DDR
for under and overvoltage events. All other regulators, with the
exception of the DAC LDO, are monitored for undervoltage
events.
controlled voltage rise on the capacitor that is tied to the
VREF_IN pin. The voltage on this capacitor is the reference
for the V
regulator and the output will track it as it
TT_DDR
settles to 50% of the V
An overvoltage event on either the V
or V
TT_DDR
DDQ
voltage. The combination of the
capacitor will determine
DDQ
internal resistors and the V
the rise time of the V
regulator will cause an immediate shutdown of all regulators.
This can only be cleared by toggling the SLP_S5 signal such
that the system enters the S5 sleep state and then
transitions back to the active, S0, state.
REF_IN
regulator (see the Functional
TT_DDR
Pin Description section for proper sizing of the VREF_IN
capacitor).
If a regulator experiences any other fault condition (an
At time t , a full soft-start cycle has passed from the time that
6
undervoltage or an overcurrent on V
), then that
DDQ
the V
regulator was enabled. At this time the
TT_DDR
VIDPGD comparator is enabled. Once enabled if the
output is within regulation, the VIDPGD pin
regulator, and only that regulator, will be disabled and an
internal fault counter will be incremented by 1. If the disabled
regulator is used as the input for another regulator, then that
cascoded regulator will also experience a fault condition due
to a loss of input. The cascoded regulator will be disabled
and the fault counter incremented by 1.
V
TT_GMCH/CPU
will be forced to a high impedance state.
Active to Sleep (S0 to S3 Transition)
When SLP_S3 goes LOW with SLP_S5 still HIGH, the
ISL6537A will disable all the regulators except for the V
DDQ
At every fault occurrence, the internal fault counter is
incremented by 1 and an internal Fault Reset Counter is
cleared to zero. The Fault Reset Counter will increment once
for every clock cycle (1 clock cycle is typically 1/250kHz, or
4μs). If the Fault Reset Counter reaches a count of 16384
before another fault occurs, then the Fault Counter is
cleared to 0. If a fault occurs prior to the Fault Reset Counter
reaching a count of 16384, then the Fault Reset Counter is
set back to zero.
regulator, which is continually supplied by the 5VDUAL rail.
VIDPGD will also transition LOW. When V is disabled, the
TT
internal reference for the V regulator is internally shorted
TT
to the V rail. This allows the V rail to float. When
TT TT
floating, the voltage on the V rail will depend on the
TT
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V rail may not bleed down to
TT
0V. Figure 1 shows how the individual regulators are
affected by the S3 state at time t .
7
The ISL6537A will immediately shut down when the Fault
Counter reaches a count of 4 when the system is restarting
from an S5 state into the active, or S0, state. The ISL6537A
will immediately shut down when the Fault Counter reaches
a count of 5 at any other time.
Sleep to Active (S3 to S0 Transition)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6537A will initiate the soft-start sequence. This sequence
is very similar to the mechanical start soft-start sequencing.
The transition from S3 to S0 is represented in Figure 1
The 16384 counts that are required to reset the Fault Reset
Counter represent 8 soft-start cycles, as one soft-start cycle is
2048 clock cycles. This allows the ISL6537A to attempt at least
one full soft-start sequence to restart the faulted regulators.
between times t and t
.
8
14
At time t , the SLP_S3 signal transitions HIGH. This enables
8
the ATX, which brings up the 12V rail. At time t , the 12V rail
has exceeded the POR threshold and the ISL6537A enters a
reset mode that lasts for 3 soft-start cycles. At time t , the 3
soft-start cycle reset is ended and the individual regulators
are enabled and soft-started in the same sequence as the
mechanical cold start sequence, with the exception that the
9
When attempting to restart a faulted regulator, the ISL6537A
will follow the preset start up sequencing. If a regulator is
already in regulation, then it will not be affected by the start
up sequencing.
10
V
Overcurrent Protection
DDQ
V
regulator is already enabled and in regulation.
DDQ
The overcurrent function protects the switching converter from
a shorted output by using the upper MOSFET on-resistance,
Active to Shutdown (S0 to S5 Transition)
r
, to monitor the current. This method enhances the
DS(ON)
When the system transitions from active, S0, state to
shutdown, S4/S5, state, the ISL6537A IC disables all
regulators and forces the VIDPGD pin LOW. This transition
converter’s efficiency and reduces cost by eliminating a
current sensing resistor.
is represented on Figure 1 at time t
.
15
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R
)
OCSET
programs the overcurrent trip level (see Typical Application
FN9143.5
10
ISL6537A
diagrams on page 4). An internal 20μA (typical) current sink
develops a voltage across R that is referenced to the
converter input voltage. When the voltage across the upper
MOSFET (also referenced to the converter input voltage)
Since the voltage of the MOSFET gates are being measured
to determine the state of the MOSFET, the designer is
encouraged to consider the repercussions of introducing
external components between the gate drivers and their
respective MOSFET gates before actually implementing
such measures. Doing so may interfere with the shoot-
through protection.
OCSET
exceeds the voltage across R
, the overcurrent function
OCSET
initiates a soft-start sequence. The initiation of soft-start may
affect other regulators. The V regulator is directly
TT_DDR
affected as it receives its reference and input from V
.
DDQ
Application Guidelines
The overcurrent function will trip at a peak inductor current
Layout Considerations
(I
I
determined by:
PEAK)
Layout is very important in high frequency switching
converter design. With power devices switching efficiently at
250kHz, the resulting current transitions from one device to
another cause voltage spikes across the interconnecting
impedances and parasitic circuit elements. These voltage
spikes can degrade efficiency, radiate noise into the circuit,
and lead to device overvoltage stress. Careful component
layout and printed circuit board design minimizes these
voltage spikes.
I
x R
OCSET
OCSET
(EQ. 3)
= ----------------------------------------------------
PEAK
r
DS(ON)
where I
is the internal OCSET current source (20μA
OCSET
typical). The OC trip point varies mainly due to the MOSFET
variations. To avoid overcurrent tripping in the
r
DS(ON)
normal operating load range, find the R
the equation above with:
resistor from
OCSET
1. The maximum r
temperature.
at the highest junction
DS(ON)
As an example, consider the turn-off transition of the control
MOSFET. Prior to turn-off, the MOSFET is carrying the full
load current. During turn-off, current stops flowing in the
MOSFET and is picked up by the lower MOSFET. Any
parasitic inductance in the switched current path generates a
large voltage spike during the switching interval. Careful
component selection, tight layout of the critical components,
and short, wide traces minimizes the magnitude of voltage
spikes.
2. The minimum I
from the specification table.
OCSET
(ΔI)
2
----------
,
3. Determine I
for I
> I
+
OUT(MAX)
PEAK
PEAK
where ΔI is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
A small ceramic capacitor should be placed in parallel with
R
to smooth the voltage across
R
in the
There are two sets of critical components in the ISL6537A
switching converter. The switching components are the most
critical because they switch large amounts of energy, and
therefore tend to generate large amounts of noise. Next are
the small signal components which connect to sensitive
nodes or supply critical bypass current and signal coupling.
OCSET
OCSET
presence of switching noise on the input voltage.
Thermal Protection (S0/S3 State)
If the ISL6537A IC junction temperature reaches a nominal
temperature of +140°C, all regulators will be disabled. The
ISL6537A will not re-enable the outputs until the junction
temperature drops below +110°C and either the bias voltage
is toggled in order to initiate a POR or the SLP_S5 signal is
forced LOW and then back to HIGH.
A multi-layer printed circuit board is recommended. Figure 2
shows the connections of the critical components in the
converter. Note that capacitors C and C
could each
IN OUT
represent numerous physical capacitors. Dedicate one solid
layer, usually a middle layer of the PC board, for a ground
plane and make all critical component ground connections
with vias to this layer. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the
PHASE terminals to the output inductor short. The power
plane should support the input power and output power
nodes. Use copper filled polygons on the top and bottom
circuit layers for the phase nodes. Use the remaining printed
circuit layers for small signal wiring. The wiring traces from
the GATE pins to the MOSFET gates should be kept short
and wide enough to easily handle the 1A of drive current.
Shoot-Through Protection
A shoot-through condition occurs when both the upper and
lower MOSFETs are turned on simultaneously, effectively
shorting the input voltage to ground. To protect from a shoot-
through condition, the ISL6537A incorporates specialized
circuitry on the V
regulator which insures that
DDQ
complementary MOSFETs are not ON simultaneously.
The adaptive shoot-through protection utilized by the V
DDQ
regulator looks at the lower gate drive pin, LGATE, and the
upper gate drive pin, UGATE, to determine whether a
MOSFET is ON or OFF. If the voltage from UGATE or from
LGATE to GND is less than 0.8V, then the respective
MOSFET is defined as being OFF and the other MOSFET is
In order to dissipate heat generated by the internal V
TT
allowed to turned ON. This method allows the V
regulator to both source and sink current.
LDO, the ground pad, pin 29, should be connected to the
internal ground plane through at least four vias. This allows
DDQ
FN9143.5
11
ISL6537A
the heat to move away from the IC and also ties the pad to
12V
ATX
the ground plane through a low impedance path.
P12V
GNDP
C
BP
The switching components should be placed close to the
ISL6537A first. Minimize the length of the connections
5VDUAL
5VSBY
5VSBY
between the input capacitors, C , and the power switches
IN
C
IN
C
BP
by placing them nearby. Position both the ceramic and bulk
input capacitors as close to the upper MOSFET drain as
possible. Position the output inductor and output capacitors
between the upper and lower MOSFETs and the load.
ISL6537A
L
UGATE
PHASE
1
Q
1
V
DDQ
The critical small signal components include any bypass
capacitors, feedback components, and compensation
components. Place the PWM converter compensation
components close to the FB and COMP pins. The feedback
resistors should be located as close as possible to the FB
pin with vias tied straight to the ground plane as required.
C
OUT1
LGATE
COMP
Q
2
C
2
C
1
R
2
R
1
FB
C
R
3
3
R
4
Feedback Compensation - PWM Buck Converters
V
DDQ
Figure 3 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
VDDQ(2)
VTT(2)
V
TT
(V
) is regulated to the Reference voltage level. The error
OUT
amplifier output (V ) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
E/A
C
3.3VATX
OUT2
wave with an amplitude of V at the PHASE node. The
C
IN
IN
PWM wave is smoothed by the output filter (L and C ).
O
O
Q
1
V
IN
DRIVER
PWM4
OSC
PWM
COMPARATOR
L
O
V
DDQ
Q
L
2
2
-
DRIVER
PHASE
V
GMCH
+
ΔV
C
O
OSC
ESR
(PARASITIC)
COMP4
FB4
C
OUT3
C
6
Z
FB
C
5
V
R
E/A
6
R
5
Z
-
IN
+
C
R
7
7
R
REFERENCE
8
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
Q
3
DRIVE2
FB2
V
R
TT_GMCH/CPU
9
Z
FB
V
DDQ
C
1
Z
IN
R
10
C
C
R
C
R
2
3
2
3
OUT4
3.3VATX
R
1
COMP
Q
3
DRIVE3
FB3
FB
V
R
DAC
-
+
11
R
4
GND PAD
R
12
ISL6537A
C
OUT5
REFERENCE
KEY
R
⎛
⎞
⎟
⎠
1
V
= 0.8 × 1 + ------
⎜
ISLAND ON POWER PLANE LAYER
DDQ
R
⎝
4
ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 3. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
FIGURE 2. PRINTED CIRCUIT BOARD POWER PLANES
AND ISLANDS
FN9143.5
12
ISL6537A
The modulator transfer function is the small-signal transfer
function of V /V . This function is dominated by a DC
100
F
F
P1
F
F
OUT E/A
Gain and the output filter (L and C ), with a double pole
Z2
Z1
P2
O
O
80
60
40
20
0
break frequency at F and a zero at F
. The DC Gain of
LC ESR
OPEN LOOP
ERROR AMP GAIN
the modulator is simply the input voltage (V ) divided by the
IN
peak-to-peak oscillator voltage ΔV
OSC
.
20LOG
(R /R )
2
1
Modulator Break Frequency Equations
20LOG
(V /ΔV
)
1
1
IN OSC
F
= ------------------------------------------
F
= -------------------------------------------
(EQ. 4)
LC
ESR
2π x ESR x C
2π x
L
x C
O
COMPENSATION
GAIN
O
O
MODULATOR
GAIN
-20
-40
-60
The compensation network consists of the error amplifier
(internal to the ISL6537A) and the impedance networks Z
CLOSED LOOP
GAIN
IN
F
LC
F
ESR
100K
FREQUENCY (Hz)
and Z . The goal of the compensation network is to provide
FB
10
100
1K
10K
1M
10M
a closed loop transfer function with the highest 0dB crossing
frequency (f
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f and
0dB
0dB
180 degrees. The equations below relate the compensation
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
network’s poles, zeros and gain to the components (R , R ,
1
2
R , C , C , and C ) in Figure 3. Use these guidelines for
locating the poles and zeros of the compensation network:
Output Voltage Selection
3
1
2
3
The output voltage of all the external voltage regulators can
be programmed to any level between their individual input
voltage and the internal reference, 0.8V. An external resistor
divider is used to scale the output voltage relative to the
reference voltage and feed it back to the inverting input of the
error amplifier, refer to the Typical Application on page 4.
1. Pick Gain (R /R ) for desired converter bandwidth.
2
1
ST
2. Place 1 Zero Below Filter’s Double Pole (~75% F ).
LC
ND
3. Place 2
Zero at Filter’s Double Pole.
ST
4. Place 1 Pole at the ESR Zero.
ND
5. Place 2
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
The output voltage programming resistor will depend on the
value chosen for the feedback resistor and the desired
output voltage of the particular regulator.
Compensation Break Frequency Equations
1
1
R1 × 0.8V
F
F
= -----------------------------------
F
F
= --------------------------------------------------------
R4 = ----------------------------------
Z1
P1
2π x R x C
C
x C
V
– 0.8V
2
1
⎛
⎜
⎝
⎞
⎟
⎠
1
2
DDQ
---------------------
2π x R
x
2
C
+ C
2
1
1
1
(EQ. 5)
R5 × 0.8V
R8 = ---------------------------------------
= ------------------------------------------------------
2π x (R + R ) x C
= -----------------------------------
2π x R x C
3
Z2
P2
V
– 0.8V
1
3
3
3
GMCH
(EQ. 6)
Figure 4 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 4. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
R9 × 0.8V
R10 = ----------------------------------------------------------
V
– 0.8V
TT_GMCH/CPU
R11 × 0.8V
R12 = ----------------------------------
V
– 0.8V
DAC
Check the compensation gain at F with the capabilities of
P2
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 4 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
If the output voltage desired is 0.8V, simply route the output
voltage back to the respective FB pin through the feedback
resistor and do not populate the output voltage programming
resistor.
compensation transfer function and plotting the gain.
The output voltage for the internal V
linear regulator
TT_DDR
The compensation gain uses external impedance networks
is set internal to the ISL6537A to track the V
voltage by
DDQ
50%. There is no need for external programming resistors.
Z
and Z to provide a stable, high bandwidth (BW) overall
FB
IN
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
FN9143.5
13
ISL6537A
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6537A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
DDR memory systems are capable of producing transient
load rates above 1A/ns. High frequency capacitors initially
supply the transient and slow the current load rate seen by the
bulk capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
L x I
L x I
TRAN
OUT
TRAN
V
OUT
(EQ. 8)
t
=
t
=
FALL
RISE
V
- V
IN
where: I
is the transient load current step, t
RISE
is the
TRAN
response time to the application of load, and t
is the
FALL
response time to the removal of load. The worst case
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection - PWM Buck Converter
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of upper MOSFET
and the source of lower MOSFET.
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
Output Capacitor Selection - LDO Regulators
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance
and type of capacitor should be chosen with this criteria in
mind.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
2
VOUT
-------------
VIN
VIN – VOUT VOUT
2
1
12
V
- V
V
OUT
⎛
⎛
⎝
⎞ ⎞
⎠ ⎠
IN
OUT
(EQ. 7)
------
---------------------------- -------------
×
IRMS
=
× IOUT
+
×
ΔV
= ΔI x ESR
ΔI =
x
OUT
⎝
L × fs
VIN
MAX
MAX
Fs x L
V
IN
(EQ. 9)
FN9143.5
14
ISL6537A
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
increases the MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal-resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
MOSFET Selection - PWM Buck Converter
Approximate Losses while Sourcing current
2
1
2
The ISL6537A requires 2 N-Channel power MOSFETs for
switching power and a third MOSFET to block backfeed from
--
× D + ⋅ Io × V × t
P
= Io × r
× f
SW s
UPPER
LOWER
DS(ON)
IN
2
P
= Io x r
x (1 - D)
DS(ON)
V
to the Input in S3 Mode. These should be selected
DDQ
based upon r
, gate supply requirements, and thermal
DS(ON)
Approximate Losses while Sinking current
(EQ. 10)
management requirements.
2
P
= Io x r
x D
DS(ON)
UPPER
2
1
2
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
--
× (1 – D) + ⋅ Io × V × t
P
= Io × r
× f
LOWER
DS(ON)
IN
SW
s
Where: D is the duty cycle = V ,
/V
is the combined switch ON and OFF time, and
OUT IN
t
SW
f is the switching frequency.
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the
upper MOSFET realizes most of the switching losses. The
lower switch realizes most of the switching losses when the
converter is sinking current (see the equations below).
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated in part by the ISL6537A
and do not significantly heat the MOSFETs. However, large
s
MOSFET Selection - LDO
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in the linear regulator is:
(EQ. 11)
is the
P
≅ I × (V – V
)
OUT
LINEAR
O
IN
where I is the maximum output current and V
O
nominal output voltage of the linear regulator.
OUT
gate-charge increases the switching interval, t
which
SW
FN9143.5
15
ISL6537A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L28.6x6
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VJJC ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
0.90
-
-
-
-
-
-
9
0.20 REF
9
0.23
3.95
3.95
0.28
0.35
4.25
4.25
5, 8
D
6.00 BSC
-
D1
D2
E
5.75 BSC
9
4.10
7, 8
6.00 BSC
-
E1
E2
e
5.75 BSC
9
4.10
7, 8
0.65 BSC
-
k
0.25
0.35
-
-
-
-
L
0.60
0.75
0.15
8
L1
N
-
28
7
7
-
10
2
Nd
Ne
P
3
3
-
-
0.60
12
9
θ
-
9
Rev. 1 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN9143.5
16
相关型号:
ISL6537ACRZA-T
3.3A DUAL SWITCHING CONTROLLER, 280kHz SWITCHING FREQ-MAX, PQCC28, 6 X 6 MM, ROHS COMPLIANT, PLASTIC, MO-220VJJC, QFN-28
RENESAS
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