ISL6540AIRZ_技术文档

ISL6540A

®

Data Sheet

March 12, 2007

FN6288.2

Single-Phase Buck PWM Controller with

Integrated High Speed MOSFET Driver

and Pre-Biased Load Capability

Features

• VIN and Power Rail Operation from +3.3V to +20V

• Fast Transient Response - 0 to 100% Duty Cycle

- 15MHz Bandwidth Error Amplifier with 6V/μs Slew Rate

- Voltage-Mode PWM Leading and Trailing-Edge

Modulation Control

The ISL6540A is an improved version of the ISL6540

single-phase voltage-mode PWM controller with input voltage

feedforward compensation to maintain a constant loop gain for

optimal transient response, especially for applications with a

wide input voltage range. Its integrated high speed

synchronous rectified MOSFET drivers and other sophisticated

features provide complete control and protection for a DC/DC

converter with minimum external components, resulting in

minimum cost and less engineering design efforts.

- Input Voltage Feedforward Compensation

• 2.9V to 5.5V High Speed 2A/4A MOSFET Gate Drivers

- Tri-state for Power Stage Shutdown

• Internal Linear Regulator (LR) - 5.5V Bias from VIN

• External LR Drive for Optimal Thermal Performance

• Voltage Margining with Independently Adjustable Upper and

Lower Settings for System Stress Testing & Over Clocking

The output voltage of the converter can be precisely regulated

with an internal reference voltage of 0.591V, and has an

improved system tolerance of ±0.68% over commercial

temperature and line load variations. An external voltage can

be used in place of the internal reference for voltage

tracking/DDR applications.

• Reference Voltage I/O for DDR/Tracking Applications

• Improved 0.591V Internal Reference with Buffered Output

- ±0.68%/±1.0% Over Commercial/Industrial Range

• Source and Sink Overcurrent Protections

- Low- and High-Side MOSFET r

DS(ON)

Sensing

• Overvoltage and Undervoltage Protections

The ISL6540A has an internal linear regulator or external linear

regulator drive options for applications with only a single supply

rail. The internal oscillator is adjustable from 250kHz to 2MHz.

The integrated voltage margining, programmable pre-biased

soft-start, differential remote sensing amplifier, and

programmable input voltage POR features enhance the

ISL6540A value.

• Small Converter Size - QFN package

• Oscillator Programmable from 250kHz to 2MHz

• Differential Remote Voltage Sensing with Unity Gain

• Programmable Soft-Start with Pre-Biased Load Capability

• Power Good Indication with Programmable Delay

• EN Input with Voltage Monitoring Capability

• Pb-Free Plus Anneal Available (RoHS Compliant)

Pinout

ISL6540A

(28 LD 5x5 QFN)

TOP VIEW

Applications

• Power Supply for some Microprocessors and GPUs

• Wide and Narrow Input Voltage Range Buck Regulators

• Point of Load Applications

28 27 26 25 24 23 22

• Low-Voltage and High Current Distributed Power Supplies

VSEN+

1

2

3

4

5

6

7

21 BOOT

20 UGATE

19 PHASE

Ordering Information

VSEN-

REFOUT

REFIN

SS

PART

NUMBER*

(Note)

TEMP.

RANGE

(°C)

PART

MARKING

PACKAGE

(Pb-Free)

PKG.

DWG. #

GND

PGND

LGATE

PVCC

18

17

16

15

BOTTOM

SIDE PAD

ISL6540ACRZ ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5

ISL6540ACRZA ISL6540ACRZ 0 to +70 28 Ld 5x5 QFN L28.5x5

OFS+

ISL6540AIRZ

ISL6540AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5

ISL6540AIRZA ISL6540AIRZ -40 to +85 28 Ld 5x5 QFN L28.5x5

LINDRV

OFS-

*Add “-T” suffix for tape and reel.

8

9

10 11 12 13 14

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL6540A

Block Diagram

FN6288.2

March 12, 2007

2

ISL6540A

Typical Application I (Internal Linear Regulator with Remote Sense)

+3.3V to +20V

L

IN

R

D

CC

BOOT

C

HFIN

C

BIN

C

F2

R

VIN

C

F1

R

BOOT

VCC

PVCC

VIN

Internal 5.6V Bias

Linear Regulator

BOOT

HSOC

R

VFF

R

HSOC

VFF

C

VFF

C

F3

BOOT

C

HSOC

UGATE

PHASE

Q1

L

OUT

EN

V

OUT

VCC

REFIN

C

HFOUT

C

BOUT

REFOUT

PG

LGATE

PGND

LSOC

Q2

R

C

LSOC

C

PG_DLY

FS

ISL6540A

10Ω

LSOC

R

FS

COMP

C

2

C

R

3

Z

FB

C

1

MARCTRL

OFS+

R

2

Z

IN

R

1

FB

R

OFS+

VMON

R

MARG

R

V

SENSE+

FB

VSEN+

R

OFS-

SS

C

SEN

R

OS

V

SENSE-

VSEN-

LINDRV

GND GND

C

SS

FN6288.2

March 12, 2007

3

ISL6540A

Typical Application II (External Linear Regulator without Remote Sense)

+3.3V to +20V

L

IN

D

BOOT

C

HFIN

C

BIN

C

F2

R

DRV

R

CC

R

C

BOOT

F1

C

R

LC

VCC

PVCC

BOOT

R

VIN

LINDRV

R

HSOC

C

F3

R

VFF

VIN

C

BOOT

C

HSOC

VFF

REFOUT

REFIN

EN

C

VFF

UGATE

PHASE

Q1

L

OUT

V

VCC

OUT

C

BOUT

C

Q2

HFOUT

LGATE

PGND

LSOC

PG

C

PG_DLY

R

LSOC

PG_DLY

FS

ISL6540A

R

FS

C

LSOC

COMP

C

2

Z

C

R

3

FB

3

C

1

MARCTRL

OFS+

R

2

Z

IN

R

1

FB

R

OFS+

R

VMON

OS

R

MARG

R

VCC

OFS-

SS

VSEN+

VSEN-

R

vmon1

R

GND

vmonOS

C

SS

FN6288.2

March 12, 2007

4

ISL6540A

Typical Application III (Dual Data Rate I or II)

VDDQ

1.8V or 2.5V

L

IN

5V

D

BOOT

C

HFIN

C

BIN

R

CC

C

R

F2

VFF

C

F1

C

VFF

VIN

VCC

PVCC

BOOT

R

VFF

EN

EN1

R

HSOC

C

BOOT

C

R

F4

EN2

C

V

HSOC

TT

(DDR I)

(DDR II)

1.25V

0.9V

UGATE

Q1

L

OUT

1K

PHASE

LGATE

PGND

LSOC

REFIN

C

HFOUT

C

BOUT

REFOUT

15nF

DIMM

1K

Q2

PG

PG_DLY

FS

R

C

LSOC

PG_DLY

ISL6540A

C

R

LSOC

FS

COMP

C

2

Z

FB

C

R

3

C

1

MARCTRL

OFS+

R

2

Z

IN

R

1

FB

R

OFS+

R

VMON

R

MARG

FB

VSEN+

R

OFS-

SS

C

SEN

VSEN-

LINDRV GND GND

C

SS

FN6288.2

March 12, 2007

5

ISL6540A

Absolute Maximum Ratings

Thermal Information

Input Voltage, VIN, VFF, HSOC . . . . . . . . . . . . . . . . -0.3V to +22.0V

Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V

Thermal Resistance (Note 1, 2)

θ

(°C/W)

θ

(°C/W)

5

JA

JC

QFN Package (Note 1, 2). . . . . . . . . 32

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

BOOT Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V

BOOT To PHASE Voltage (V ). . . . . -0.3V to 7V (DC)

BOOT

V

BOOT- PHASE

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 9V (<10ns)

PHASE Voltage, V

. . . . . . . . . V

BOOT

- 7V to V

+ 0.3V

PHASE

BOOT

- 9V (<10ns) to V

BOOT

. . . . . . . . . . . . . . . . . . . . . .V

BOOT

UGATE Voltage . . . . . . . . . . . . . . . . V

- 0.3V (DC) to V

PHASE

- 5V (<20ns Pulse Width, 10μJ) to V

BOOT

V

PHASE

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V

Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2

Recommended Operating Conditions

Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V ±10%

Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V

Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.5V

Boot to Phase Voltage (Overcharged), V

- V

. . . . . .<6V

BOOT

PHASE

Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to +85°C

Junction Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

JA

2. θ , "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.

JC

3. Test conditions identified as “GBD” are guaranteed by design simulation.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

INPUT SUPPLY CURRENTS

I

Nominal VCC Supply Current

Nominal PVCC Supply Current

Nominal Vin Supply Current

Shutdown VCC Supply Current

VIN = VCC = PVCC = 5V, Fs = 600kHz,

UGATE and LGATE Open

-

8

3

13

4

mA

VCC

I

VIN = VCC = PVCC = 5V; Fs = 600kHz,

UGATE and LGATE Open

PVCC

I

VIN = VCC = PVCC = 5V; Fs = 600kHz,

UGATE and LGATE Open

0.5

1

VIN

I

EN = 0V, VCC = PVCC = VIN = 5V

-

3

1

4

2

1

mA

VCC_S

I

Shutdown PVCC Supply Current EN = 0V, VCC = PVCC = VIN = 5V

Shutdown VIN Supply Current EN = 0V, VCC = PVCC = VIN = 5V

POWER-ON RESET

PVCC_S

I

0.5

VIN_S

POR

Rising VCC Threshold

Falling VCC Threshold

VCC Hysterisis

2.79

2.59

187

-

2.89

2.69

250

V

VCC_R

-

VCC_F

215

mV

V

VCC_H

POR

Rising PVCC Threshold

Falling PVCC Threshold

PVCC Hysterisis

2.79

2.59

193

-

2.91

2.70

250

PVCC_R

PVCC_F

PVCC_H

-

215

-

V

mV

V

POR

Rising VFF Threshold

Falling VFF Threshold

VFF Hysterisis

1.48

1.35

127

1.54

1.41

146

VFF_R

VFF_F

VFF_H

-

V

137

mV

FN6288.2

March 12, 2007

6

ISL6540A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

SYMBOL

ENABLE

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Reference Voltage

Hysteresis Source Current

Maximum Input Voltage

0.485

7.5

-

0.500

10

0.515

11.5

-

V

μA

V

EN_REF

I

EN_HYS

V

VCC + 0.3

EN

OSCILLATOR

OSC

Nominal Maximum Frequency

Nominal Minimum Frequency

Total Variation

GBD

-

2000

250

-

kHz

%

FMAX

OSC

-

FMIN

ΔOSC

FS = 250kHz to 2MHz, VFF = 3.3V to 20V

-17

-

+17

ΔV

Ramp Amplitude

-

0.16*VFF

1.0

-

V

OSC

P-P

V

Ramp Bottom

OSC_MIN

VFF

Minimum Usable VFF Voltage

VCC = 5V

3.3

V

PWM

D

Maximum Duty Cycle

Minimum Duty Cycle

Leading and Trailing-edge Modulation

-

100

0

-

%

MAX

D

MIN

REFERENCE TRACKING

V

Input Voltage Range

VCC = 5V

0.068

-

0

VCC - 1.8V

V

REFIN

V

External Reference Offset

Maximum Drive Current

Output Voltage Range

REFIN = 0.6V

-1.8

2.2

mV

mA

V

REFIN_OS

I

C = 1μF, VCC = 5V, REFOUT = 1.25V

-

19

-

REFOUT

L

V

C = 1μF

0.01

VCC - 1.8V

REFOUT

L

V

Maximum Output Voltage Offset C = 1μF REFOUT = 1.25V

-6

-

11

mV

μF

V

REFOUT_OS

REFOUT_MIN

L

C

Minimum Load Capacitance

Input Disable Voltage

REFOUT = 1.25V

VCC = 5V

-

1.0

-

V

VCC - 0.6

VCC - 0.58

REFIN_DIS

REFERENCE

V

Reference Voltage

T

= 0°C to +70°C

= -40°C to +85°C

= 0°C to +70°C

T = -40°C to +85°C

A

0.587

0.585

-0.68

-1.0

0.591

0.595

0.597

0.68

1.0

V

REF_COM

A

V

T

0.591

REF_IND

A

V

System Accuracy

T

-

%

SYS_COM

A

V

SYS_IND

ERROR AMPLIFIER

DC Gain

R = 10k, C = 100p, at COMP Pin

-

88

15

6

-

dB

L

UGBW

SR

Unity Gain-Bandwidth

Slew Rate

R = 10k, C = 100p, at COMP Pin

MHz

V/μs

L

R = 10k, C = 100p, at COMP Pin

L

DIFFERENTIAL AMPLIFIER

UG

UGBW

SR

DC Gain

Standard Instrumentation Amplifier

COMP = 10pF

-

0

-

dB

MHz

V/μs

mV

μA

V

Unity Gain Bandwidth

Slew Rate

-

20

-

10

-

V

Offset

-1.9

0

6

1.9

OFFSET_IND

I

Negative Input Source Current

Input Common Mode Range Max

Input Common Mode Range Min

VSEN- Disable Voltage

-

VSEN-

VCC - 1.8

-0.2

V

VCC

V

VSEN_DIS

INTERNAL LINEAR REGULATOR

I

Maximum Current

-

200

-

mA

VIN

FN6288.2

March 12, 2007

7

ISL6540A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

2

MAX

3.9

5.71

-

UNITS

Ω

R

Saturated Equivalent Impedance VIN = 3.3V, Load = 100mA

-

LIN

Linear Regulator Voltage

Maximum Vin DV/DT

VIN = 22V, Load = 0 to 100mA

5.42

5.50

1

V

PVCC

VIN

VIN = 0 V to 12V step, PVCC = 0 V

VIN = 5.0 V to 12V step, PVCC = 5.0 V

-

V/μs

DV/DT_Max

0.05

-

EXTERNAL LINEAR REGULATOR

LIN_DRV Maximum Sinking Drive Current

OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA)

3.2

5

6.4

mA

DC Gain

C

= 0.1μF, at SS Pin

-

88

37

-

dB

SS

Drive Capability

30

44

μA

GATE DRIVERS

R

Ugate Source Resistance

Ugate Source Saturation Current

Ugate Sink Resistance

500mA Source Current, PVCC = 5.0V

= 2.5V, PVCC = 5.0V

-

1.0

2.0

1.0

2.0

1.0

2.0

0.4

4.0

-

Ω

A

Ω

A

Ω

A

Ω

A

UGATE

I

V

UGATE

UGATE-PHASE

500mA Sink Current, PVCC = 5.0V

= 2.5V, PVCC = 5.0V

R

UGATE

I

Ugate Sink Saturation Current

Lgate Source Resistance

Lgate Source Saturation Current

Lgate Sink Resistance

V

UGATE

UGATE-PHASE

500mA Source Current, PVCC = 5.0V

= 2.5V, PVCC = 5.0V

R

LGATE

I

V

LGATE

500mA Sink Current, PVCC = 5.0V

= 2.5V, PVCC = 5.0V

R

LGATE

I

Lgate Sink Saturation Current

V

LGATE

OVERCURRENT PROTECTION (OCP)

I

Low Side OCP (LSOC) Current

Source

LSOC = 0V to Vcc - 1.0V, T = 0°C to +70°C

86

84

-

100

±2

107

109

-

μA

mV

μA

mV

LSOC

A

LSOC = 0V to Vcc - 1.0V, T = -40°C to +85°C

A

I

LSOC Maximum Offset Error

Vcc = 2.9V and 5.6V T < 10μs

SAMPLE

LSOC_OFSET

I

High Side OCP (HSOC) Current HSOC = 0.8V to 22V T = 0°C to +70°C

A

Source

91

89

84

-

100

-

106

107

-

HSOC

HSOC = 0.8V to 22V T = -40°C to +85°C

A

I

HSOC = 0.3V to 0.8V

HSOC_LOW

I

HSOC Maximum Offset Error

VCC = 2.9V and 5.5V T

< 10μs

SAMPLE

±2

HSOC_OFSET

MARGINING CONTROL

V

N

Minimum Margining Voltage of

Internal Reference

R

= 10kΩ, R

= 6.01kΩ,

-187

185

-197

197

-209

208

mV

MARG

MAR_CRTL = 0V

OFS-

Maximum Margining Voltage of

Internal Reference

R

= 10kΩ, R

MARG OFS+

MAR_CRTL = VCC

Margining Transfer Ratio

Positive Margining Threshold

Negative Margining Threshold

Tri-state Input Level

N

= (V -V )/V

OFS- OFS+ MARG

4.84

1.51

0.75

1.21

5

5.22

2.02

1.05

1.40

SDR

V

MARG

1.8

MAR_CTRL

0.9

V

Disable Mode

1.325

V

POWER GOOD MONITOR

V

Undervoltage Rising Trip Point

Undervoltage Falling Trip Point

Overvoltage Rising Trip Point

Overvoltage Falling Trip Point

PGOOD Delay

-7%

-13%

13%

7%

-9%

-15%

15%

9%

-11%

-17%

17%

11%

-

V

UVR

SS

V

UVF

SS

V

OVR

SS

V

OVF

SS

T

I

C

= 0.1μF

-

7.1

ms

μA

V

PG_DLY

PGOOD Delay Source Current

PGOOD Delay Threshold Voltage

17

21

24

PG_DLY

V

1.45

1.49

1.52

PG_DLY

FN6288.2

March 12, 2007

8

ISL6540A

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

= 5mA

MIN

TYP

MAX

UNITS

I

PGOOD Low Output Voltage

Maximum Sinking Current

Maximum Open Drain Voltage

I

-

23

-

0.150

V

mA

V

PG_LOW

PGOOD

I

V

= 0.8V

-

PG_MAX

PGOOD

V

VCC = 3.3V

6

PG_MAX

OFS- (Pin 7)

This pin sets the negative margining offset voltage. Resistors

should be connected to GND (R ) and OFS+ (R

from this pin. With MAR_CTRL logic low, the internal 0.591V

reference is developed at the OFS- pin across resistor

Functional Pin Description

VSEN+ (Pin 1)

)

OFS- MARG

This pin provides differential remote sense for the ISL6540A.

It is the positive input of a standard instrumentation amplifier

topology with unity gain, and should connect to the positive

rail of the load/processor. The voltage at this pin should be

set equal to the internal system reference voltage (0.591V

typical.)

R

. The voltage on OFS- is driven from OFS+ through

OFS-

. The resulting voltage differential between OFS+

MARG

and OFS- is divided by 5 and imposed on the system

reference. The maximum designed offset of -1V between

OFS+ and OFS- pins translates to a -200mV offset of the

system reference.

VSEN- (Pin 2)

This pin provides differential remote sense for the regulator.

It is the negative input of the instrumentation amplifier, and

should connect to the negative rail of the load/processor.

Typically 6μA is sourced from this pin. The output of the

remote sense buffer is disabled (High Impedance) by pulling

VSEN- to VCC.

VCC (Pin 8, Analog Circuit Bias)

This pin provides power for the ISL6540A analog circuitry.

The pin should be connected to a 2.9V to 5.5V bias through

an RC filter from PVCC to prevent noise injection into the

analog circuitry. This pin can be powered off the internal or

external linear regulator options.

REFOUT (Pin 3)

This pin connects to the unmargined system reference

through an internal buffer. It has a 19mA drive capability with

an output common mode range of GND to VCC. The

REFOUT buffer requires at least 1μF of capacitive loading to

be stable. This pin should not be left floating.

MARCTRL (Pin 9)

The MARCTRL pin controls margining function, a logic high

enables positive margining, a logic low sets negative

margining, a high impedance disables margining.

PG_DLY (Pin 10)

REFIN (Pin 4)

Provides the ability to delay the output of the PGOOD

assertion by connecting a capacitor from this pin to GND. A

0.1μF capacitor produces approximately a 7ms delay.

When the external reference pin (REFIN) is NOT within

~1.8V of VCC, the REFIN pin is used as the system

reference instead of the internal 0.591V reference. The

recommended REFIN input voltage range is ~68mV to

VCC - 1.8V.

PGOOD (Pin 11)

Provides an open drain Power Good signal when the output

is within 9% of nominal output regulation point with 6%

hysteresis (15%/9%), and after soft-start is complete.

PGOOD monitors the VMON pin.

SS (Pin 5)

This pin provides softstart functionality for the ISL6540A. A

capacitor connected to ground along with the internal 37µA

Operational Transconductance Amplifier (OTA), sets the

soft-start interval of the converter. This pin is directly

connected to the non-inverting input of the error amplifier. To

prevent noise injection into the error amplifier the SS

capacitor should be located next to the SS and GND pins.

EN (Pin 12)

This pin is compared with an internal 0.50V reference and

enables the soft-start cycle. This pin also can be used for

voltage monitoring. A 10μA current source to GND is active

while the part is disabled, and is inactive when the part is

enabled. This provides functionality for programmable

hysteresis when the EN pin is used for voltage monitoring.

OFS+ (Pin 6)

This pin sets the positive margining offset voltage. Resistors

VFF (Pin 13)

should be connected to GND (R

) and OFS- (R

)

OFS+

MARG

from this pin. With MAR_CTRL logic low, the internal 0.591V

reference is developed at the OFS+ pin across resistor

The voltage at this pin is used for input voltage feed forward

compensation and sets the internal oscillator ramp peak to

peak amplitude at 0.16 * VFF. An external RC filter may be

required at this pin in noisy input environments. The

minimum recommended VFF voltage is 2.97V.

R

. The voltage on OFS+ is driven from OFS- through

. The resulting voltage differential between OFS+

OFS+

MARG

and OFS- is divided by 5 and imposed on the system

reference. The maximum designed offset of 1V between

OFS+ and OFS- pins translates to a 200mV offset.

FN6288.2

March 12, 2007

9

ISL6540A

the bootstrap diode to prevent over charging of the BOOT

VIN (Pin 14, Internal Linear Regulator Input)

capacitor during normal operation.

This pin should be tied directly to the input rail when using

the internal or external linear regulator options. It provides

power to the External/Internal linear drive circuitry. When

used with an external 3.3V to 5V supply, this pin should be

tied directly to PVCC.

HSOC (Pin 22)

The high side sourcing current limit is set by connecting this

pin with a resistor and capacitor to the drain of the high side

MOSEFT. A 100μA current source develops a voltage across

the resistor which is then compared with the voltage

developed across the high side MOSFET. An initial ~120ns

blanking period is used to eliminate sampling error due to

the switching noise before the current is measured.

LIN_DRV (Pin 15, External Linear Regulator Drive)

This pin allows the use of an external pass element to power

the IC for input voltages above 5.0V. It should be connected

to GND when using an external 5V supply or the internal

linear regulator. When using the external linear regulator

option, this pin should be connected to the gate of a PMOS

pass element, a pull up resistor must be connected between

the PMOS device’s gate and source for proper operation.

LSOC (Pin 23)

The low side source and sinking current limit is set by

placing a resistor (R

) and capacitor between this pin

LSOC

and PGND. A 100μA current source develops a voltage

across R which is then compared with the voltage

PVCC (Pin 16, Driver Bias Voltage)

LSOC

developed across the low side MOSFET when on. The

sinking current limit is set at 1x of the nominal sourcing limit

in ISL6540A. An initial ~120ns blanking period is used to

eliminate the sampling error due to switching noise before

the current is measured.

This pin is the output of the internal series linear regulator. It

also provides the bias for both low side and high side

MOSFET drivers. The maximum voltage differential between

PVCC and PGND is 6V. Its recommended operational

voltage range is 2.9V to 5.5V. At minimum a 10μF capacitor

is required for decoupling PVCC to PGND. For proper

operation the PVCC capacitor should be located next to the

PVCC and the PGND pins and should be connected to these

pins with dedicated traces.

FS (Pin 24)

This pin provides oscillator switching frequency adjustment

by placing a resistor (R ) from this pin to GND.

FS

COMP (Pin 25)

LGATE (Pin 17)

This pin is the error amplifier output. It should be connected

to the FB pin through the desired compensation network.

This pin provides the drive for the low side MOSFET and

should be connected to its gate.

FB (Pin 26)

PGND (Pin 18, Power Ground)

This pin is the inverting input of the error amplifier and has a

maximum usable voltage of VCC - 1.8V. When using the

internal differential remote sense functionality, this pin

should be connected to VMON by a standard feedback

network. In the event the remote sense buffer is disabled,

the VMON pin should be connected to VOUT by a resistor

divider along with FB’s compensation network.

This pin connects to the low side MOSFET's source and

provides the ground return path for the lower MOSFET driver

and internal power circuitries. In addition, PGND is the return

path for the low side MOSFET’s r

circuit.

current sensing

DS(ON)

PHASE (Pin 19)

This pin connects to the source of the high side MOSFET

and the drain of the low side MOSFET. This pin represents

the return path for the high side gate driver. During normal

switching, this pin is used for high side and low side current

sensing.

GND (Pin 27, Analog Ground)

Signal ground for the IC. All voltage levels are measured

with respect to this pin. This pin should not be left floating.

VMON (Pin 28)

This pin is the output of the differential remote sense

instrumentation amplifier. It is connected internally to the

OV/UV/PGOOD comparators. The VMON pin should be

connected to the FB pin by a standard feedback network. In

the event of the remote sense buffer is disabled, the VMON

pin should be connected to VOUT by a resistor divider along

with FB’s compensation network. An RC filter should be

used if VMON is to be connected directly to FB instead of to

VOUT through a separate resistor divider network.

UGATE (Pin 20)

This pin provides the drive for the high side MOSFET and

should be connected to its gate.

BOOT (Pin 21)

This pin provides the bootstrap bias for the high side driver.

The absolute maximum voltage differential between BOOT

and PHASE is 6.0V (including the voltage added due to the

overcharging of the bootstrap capacitor); its operational

voltage range is 2.5V to 5.5V with respect to PHASE. It is

recommended that a 2.2Ω resistor be placed in series with

GND (Bottom Side Pad, Analog Ground)

Signal ground for the IC. All voltage levels are measured

with respect to this pin. This pin should not be left floating.

FN6288.2

March 12, 2007

10

ISL6540A

continues to charge the SS pin until the voltage on COMP

Functional Description

exceeds the bottom of the oscillator ramp, at which point, the

driver outputs are enabled, with the low side MOSFET first

being held low for 200ns to provide for charging of the bootstrap

capacitor. Once the driver outputs are enabled, the OTA’s target

voltage is then changed to the margined (if margining is being

Initialization

The ISL6540A automatically initializes upon receipt of power

without requiring any special sequencing of the input

supplies. The Power-On Reset (POR) function continually

used) reference voltage (V

), and the SS pin is

REF_MARG

HIGH = ABOVE POR; LOW = BELOW POR

ramped up or down accordingly. This method reduces startup

surge currents due to a pre-charged output by inhibiting

regulator switching until the control loop enters its linear region.

By ramping the positive input of the error amplifier to VCC and

VCC POR

VFF POR

AND

SOFT-START

PVCC POR

EN POR

then to V

, it is even possible to mitigate surge

REF_MARG

currents from outputs that are pre-charged above the set output

voltage. As the SS pin connects directly to the non-inverting

input of the error amplifier, noise on this pin should be kept to a

minimum through careful routing and part placement. To

prevent noise injection into the error amplifier the SS capacitor

should be located within 150 mils of the SS and GND pins.

Soft-start is declared done when the drivers have been enabled

FIGURE 1. SOFT-START INITIALIZATION LOGIC

monitors the input supply voltages (PVCC, VFF, VCC) and

the voltage at the EN pin. Assuming the EN pin is pulled to

above ~0.50V, the POR function initiates soft-start operation

after all input supplies exceed their POR thresholds.

VIN

and the SS pin is within ±3mV of V

.

REF_MARG

R

UP

VMON

V

REF

Sys_Enable

+15%

R

+9%

DOWN

I

=10μA

EN_HYS

V

REF_MARG

-9%

V

EN_HYS

-------------------------

R

=

UP

I

-15%

EN_HYS

R

• V

EN_REF

– V

EN_REF

UP

--------------------------------------------------------

=

DOWN

GOOD

V

GOOD

EN_FTH

UV

OV

UV

V

= V

– V

EN_RTH EN_HYS

EN_FTH

FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW

FIGURE 2. ENABLE POR CIRCUIT

1.49V

21μA

With all input supplies above their POR thresholds, driving

the EN pin above 0.50V initiates a soft-start cycle. In addition

to normal TTL logic, the enable pin can be used as a voltage

monitor with programmable hysteresis through the use of the

internal 10μA sink current and an external resistor divider.

This feature is especially designed for applications that have

input rails greater than a 3.3V and require a specific input rail

POR and Hysteresis levels for better undervoltage

---------------

⋅

PG_DLY

T

= C

PG_DLY

Power Good

The power good comparator references the voltage on the

soft-start pin to prevent accidental tripping during margining.

The trip points are shown on Figure 3. Additionally, power

good will not be asserted until after the completion of the

soft-start cycle. A 0.1μF capacitor at the PG_DLY pin will add

an additional ~7ms delay to the assertion of power good.

PG_DLY does not delay the de-assertion of power good.

protection. Consider for a 12V application choosing

R

= 100kΩ and R

= 5.76kΩ there by setting the

) to ~10V and the falling threshold

UP

rising threshold (V

(V

DOWN

EN_RTH

) to ~9V, for 1V of hysteresis (V

). Care

EN_FTH

EN_HYS

should be taken to prevent the voltage at the EN pin from

exceeding VCC when using the programmable UVLO

functionality.

Under and Overvoltage Protection

The Undervoltage (UV) and Overvoltage (OV) protection

circuitry compares the voltage on the VMON pin with the

reference that tracks with the margining circuitry to prevent

accidental tripping. UV and OV functionality is not enabled

until the end of soft-start.

Soft-Start

The POR function activates the internal 37μA OTA which

begins charging the external capacitor (C ) on the SS pin to a

SS

target voltage of VCC. The ISL6540A’s soft-start logic

FN6288.2

March 12, 2007

11

ISL6540A

An OV event is detected asynchronously and causes the

smooth the voltage across R in the presence of

HSOC

high side MOSFET to turn off, the low side MOSFET to turn

on (effectively a 0% duty cycle), and PGOOD to pull low. The

regulator stays in this state and overrides sourcing and

sinking OCP protections until the OV event is cleared.

switching noise on the input bus.

Simple Low Side OCP Equation

I

• r

OC_SOURCE

DS(ON)LowSide

--------------------------------------------------------------------------------------

=

R

LSOC

100μA

An UV event is detected asynchronously and results in the

PGOOD pulling low.

Detailed Low Side OCP Equations

ΔI

2

⎛

⎝

⎞

⎠

Overcurrent Protection

----

I

+

• r

OC_SOURCE

DS(ON),L

--------------------------------------------------------------------------------------

R

=

The ISL6540A monitors both the high side MOSFET and low

side MOSFET for overcurrent events. Dual sensing allows the

ISL6540A to detect overcurrent faults at the very low and very

high duty cycles that can result from the ISL6540A’s wide input

range. The OCP function is enabled with the drivers at startup

and detects the peak current during each sensing period. A

resistor and a capacitor between the LSOC pin and GND set

the low side source and sinking current limits. A 100μA current

source develops a voltage across the resistor which is then

compared with the voltage developed across the low side

MOSFET at conduction mode. The measurement comparator

uses offset correcting circuitry to provide precise current

measurements with roughly ±2mV of offset error. An ~120ns

blanking period, implemented on the upper and lower MOSFET

current sensing circuitries, is used to reduce the current

sampling error due to the leading-edge switching noise. An

additional 120ns low pass filter is used to further reduce

measurement error due to noise. In sourcing current

LSOC

V

I

• N

L

LSOC

- V

V

OUT

V

IN

F

OUT

------------------------------- ---------------

ΔI =

•

L

S

I

• N • R

LSOC

ΔI

LSOC

L

------------------------------------------------------- ----

I

=

–

OC_SINK

r

2

DS(ON),L

N

= Number of low side MOSFETs

L

Sourcing OCP faults cause the regulator to disable (Ugate and

Lgate drives pulled low, PGOOD pulled low, soft-start capacitor

discharged) itself for a fixed period of time after which a normal

soft-start sequence is initiated. The period of time the regulator

waits before attempting a soft-start sequence is set by three

charge and discharge cycles of the soft-start capacitor.

Simple High Side OCP Equation

I

• r

OC_SOURCE

DS(ON)HighSide

applications, the LSOC voltage is inverted and compared with

the voltage across the MOSFET while on. When this voltage

exceeds the LSOC set voltage, a sourcing OCP fault is

triggered. A 1000pF or greater filter capacitor should be used in

----------------------------------------------------------------------------------------

=

R

HSOC

100μA

Detailed High Side OCP Equation

parallel with R

impacting the accuracy of the OCP measurement.

to prevent on chip parasitics from

LSOC

ΔI

2

⎛

⎝

⎞

⎠

----

I

+

• r

OC_SOURCE

DS(ON),U

---------------------------------------------------------------------------------------

R

N

=

HSOC

I

• N

U

HSOC

The ISL6540A’s sinking current limit is set to the same

voltage as its sourcing limit. In sinking applications, when the

voltage across the MOSFET is greater than the voltage

= Number of high side MOSFETs

U

developed across the resistor (R

) a sinking OCP event

LSOC

is triggered. To avoid non-synchronous operation at light

load, the peak to peak output inductor ripple current should

not be greater than twice of the sinking current limit.

Sinking OCP faults cause the low side MOSFET drive to be

disabled, effectively operating the ISL6540A in a

non-synchronous manner. The fault is maintained for three

clock cycles at which point it is cleared and normal operation

is restored. OVP fault implementation overrides sourcing

and sinking OCP events, immediately turning on the low side

MOSFET and turning off the high side MOSFET. The OC trip

The high side sourcing current limit is set by connecting the

HSOC pin with a resistor (R

) and a capacitor to the drain

HSOC

of the high side MOSEFT. A 100μA current source develops a

voltage across the resistor which is then compared with the

voltage developed across the high side MOSFET while on.

When the voltage drop across the MOSFET exceeds the

voltage drop across the resistor, a sourcing OCP event

occurs. A 1000pF or greater filter capacitor should be used in

point varies mainly due to the MOSFETs r

variations

DS(ON)

and system noise. To avoid overcurrent tripping in the

normal operating load range, find the R and/or R

HSOC

resistor from the previous detailed equations with:

LSOC

parallel with R

impacting the accuracy of the OCP measurement and to

to prevent on chip parasitics from

HSOC

1. Maximum r at the highest junction temperature.

DS(ON)

and/or I

2. Minimum I

from specification table.

HSOC

LSOC

3. Determine the overcurrent trip point greater than the

maximum output continuous current at maximum

inductor ripple current.

FN6288.2

March 12, 2007

12

ISL6540A

(VIN) can range between 3.3V to 20V ±10%. The internal

Frequency Programming

linear regulator is to provide power for both the internal

MOSFET drivers through the PVCC pin and the analog

circuitry through the VCC pin. The VCC pin should be

connected to the PVCC pin with an RC filter to prevent high

frequency driver switching noise from entering the analog

circuitry. When VIN drops below 5.5V, the pass element will

saturate; PVCC will track VIN, minus the dropout of the

By tying a resistor to GND from FS pin, the switching

frequency can be set between 250kHz and 2MHz.

Oscillator/VFF

The Oscillator is a triangle waveform, providing for leading

and falling edge modulation. The bottom of the oscillator

waveform is set at 1.0V. The ramp's peak to peak amplitude

is determined from the voltage on the VFF (Voltage Feed

Forward) pin by the equation: ΔVosc = 0.16*VFF. An internal

RC filter of 233kΩ and 2pF (341kHz) provides filtering of the

VFF voltage. An external RC filter may be required to

augment this filter in the event that it is insufficient to prevent

noise injection or control loop interactions. Voltages below

2.9V on the VFF pin may result in undesirable operation due

to extremely small peak to peak oscillator waveforms. The

oscillator waveform should not exceed VCC -1.0V. For high

VFF voltages the internal/external 5.5V linear regulator

should be used. 5.5V on VCC provides sufficient headroom

for 100% duty cycle operation when using the maximum

VFF voltage of 22V. In the event of sustained 100% duty

cycle operation, defined as 32 clock cycles where no LG

pulse is detected, LG will be pulsed on to refresh the

design’s bootstrap capacitor.

linear regulator: PVCC = VIN-2xI

. When used with an

VIN

external 5V supply, the VIN pin should be tied directly to

PVCC.

At startup (PVCC = 0V and Vin = 0V) the DV/DT on VIN

should be kept below 1V/μs to prevent electrical overstress

on PVCC. Care should be taken to keep the DV/DT on Vin

below 0.05V/μs if the initial steady state voltage on PVCC is

between 2.0V and 5.5V, as electrical overstress on PVCC is

otherwise possible.

External Series Linear Regulator

The LIN_DRV pin provides sinking drive capability for an

external pass element linear regulator controller. The

external linear options are especially useful when the

internal linear dropout is too large for a given application.

When using the external linear regulator option, the

LIN_DRV pin should be connected to the gate of a PMOS

device, and a resistor should be connected between its gate

and source. A resistor and a capacitor should be connected

from gate to source to compensate the control loop. A PNP

device can be used instead of a PMOS device in which case

the LIN_DRV pin should be connected to the base of the

PNP pass element. The sinking capability of the LIN_DRV

pin is 5mA, and should not be exceeded if using an external

resistor for a PMOS device. The designer should take care

in designing a stable system when using external pass

elements. The VCC pin should be connected to the PVCC

pin with an RC filter to prevent high frequency driver

switching noise from entering the analog circuitry.

100

10

1

100

1000

10000

FREQUENCY (kHz)

High Speed MOSFET Gate Driver

FIGURE 4. R RESISTANCE vs FREQUENCY

FS

The integrated driver has similar drive capability and

features to Intersil's ISL6605 stand alone gate driver. The

PWM tri-state feature helps prevent a negative transient on

the output voltage when the output is being shut down. This

eliminates the schottky diode that is used in some systems

for protecting the microprocessor from reversed-output-

voltage damage. See the ISL6605 datasheet for

10

–0.973

Fs[Hz] ≈ 1.178×10 • R [Ω]

(R TO GND)

T

Internal Series Linear Regulator

The VIN pin is connected to PVCC with a 2Ω internal series

linear regulator, which is internally compensated. The

external series linear regulator option should be used for

applications requiring pass elements of less than 2Ω. When

using the internal regulator, the LIN_DRV pin should be

connected directly to GND. The PVCC and VIN pins should

have a bypasses capacitor (at least 10μF on PVCC is

required) connected to PGND. For proper operation the

PVCC capacitor must be within 150 mils of the PVCC and

the PGND pins, and be connected to these pins with

dedicated traces. The internal series linear regulator’s input

specification parameters that are not defined in the current

ISL6540A electrical specifications table.

A 1-2Ω resistor is recommended to be in series with the

bootstrap diode when using VCCs above 5.0V to prevent the

bootstrap capacitor from overcharging due to the negative

swing of the trailing edge of the phase node.

Margining Control

When the MAR_CTRL is pulled high or low, the positive or

negative margining functionality is respectively enabled.

FN6288.2

March 12, 2007

13

ISL6540A

When MAR_CTRL is left floating, the function is disabled.

Upon UP margining, an internal buffer drives the OFS- pin

VCC

from VCC to maintain OFS+ at 0.591V. The resistor divider,

and R , causes the voltage at OFS- to be

REFERENCE

=0.591V

ISL6540A

STATE

V

R

REF

MARG

OFS+

MACHINE

increased. Similarly, upon DOWN margining, an internal

buffer drives the OFS+ pin from VCC to maintain OFS- at

REFIN

0.591V. The resistor divider, R

and R

, causes the

MARG

OFS-

800mV

voltage at OFS+ to be increased. In both modes the voltage

difference between OFS+ and OFS- is then sensed with an

instrumentation amplifier and is converted to the desired

margining voltage by a 5:1 ratio. The maximum designed

margining range of the ISL6540A is ±200mV, this sets the

REFOUT

V

REF_MARG

MARGINING

BLOCK

OTA

MINIMUM value of R

or R at approximately 5.9K

OFS+

OFS-

for an R

MARG

of 10K for a MAXIMUM of 1V across R .

MARG

FIGURE 5. SIMPLIFIED REFERENCE BUFFER

The OFS pins are completely independent and can be set to

different margining levels. The maximum usable reference

voltage for the ISL6540A is VCC-1.8V, and should not be

exceeded when using the margining functionality, i.e,

Internal Reference and System Accuracy

The internal reference is trimmed to 0.591V. The total DC

system accuracy of the system is within ±0.68% over

commercial temperature range, and ±1.00% over industrial

temperature range. System accuracy includes error amplifier

offset, OTA error, and bandgap error. Differential remote

sense offset error is not included. As a result, if the

differential remote sense is used, then an extra 1.9mV of

offset error enters the system. The use of REFIN may add

up to 2.2mV of additional offset error.

V

< VCC - 1.8V.

REF_MARG

V

R

MARG

REF

5

-------------- --------------------

V

=

•

MARG_UP

R

OFS+

V

R

REF

5

MARG

-------------- --------------------

V

=

•

MARG_DOWN

R

OFS-

An alternative calculation provides for a desired percentage

change in the output voltage when using the internal 0.591V

reference:

Differential Remote Sense Buffer

The differential remote sense buffer is essentially an

instrumentation amplifier with unity gain. The offset is

trimmed to 1.5mV for high system accuracy. As with any

instrumentation amplifier typically 6μA are sourced from the

VSEN- pin. The output of the remote sense buffer is

connected directly to the internal OV/UV comparator. As a

result, a resistor divider should be placed on the input of the

buffer for proper regulation, as shown in Figure 6. The

VMON pin should be connected to the FB pin by a standard

R

MARG

--------------------

V

= 20 •

--------------------

V

= 20 •

pct_DOWN

PCT_UP

R

OFS-

OFS+

When not used in a design OFS+, OFS-, and MARCTRL

should be left floating. To prevent damage to the part, OFS+

and OFS- should not be tied to VCC or PVCC.

Reference Output Buffer

The internal buffer’s output tracks the unmargined system

reference. It has a 19mA drive capability, with maximum and

minimum output voltage capabilities of VCC and GND

respectively. Its capacitive loading can range from 1μF to

above 17.6μF, which is designed for 1 to 8 DIMM systems in

DDR (Dual Data Rate) applications. 1μF of capacitance

should always be present on REFOUT. It is not designed to

drive a resistive load and any such load added to the system

should be kept above 300kΩ total impedance. The

feed-back network. A small capacitor, C

in Figure 6, can

SEN

is chosen so the

be added to filter out noise, typically C

SEN

corresponding time constant does not reduce the overall

phase margin of the design, typically this is 2x to 10x

switching frequency of the regulator.

As some applications will not use the differential remote

sense, the output of the remote sense buffer can be disabled

(high impedance) by pulling VSEN- within 1.8V of VCC. As

the VMON pin is connected internally to the OV/UV/PGOOD

comparator, an external resistor divider must then be

connected to VMON to provide correct voltage information

for the OV/UV comparator. An RC filter should be used if

VMON is to be connected directly to FB instead of to VOUT

through a separate resistor divider network. This filter

prevents noise injection from disturbing the OV/UV/PGOOD

comparators on VMON. VMON may also be connected to

the SS pin, which completely bypasses the OV/UV/PGOOD

functionality.

Reference Output Buffer should not be left floating.

Reference Input

The REFIN pin allows the user to bypass the internal 0.591V

reference with an external reference. Asynchronously if

REFIN is NOT within ~1.8V of VCC, the external reference

pin is used as the control reference instead of the internal

0.591V reference. The minimum usable REFIN voltage is

~68mV while the maximum is VCC - 1.8V - V

present).

(if

MARG

FN6288.2

March 12, 2007

14

ISL6540A

VSENSE-

(REMOTE)

VSENSE+

(REMOTE)

10Ω

VOUT (LOCAL)

GND (LOCAL)

R

FB

R

OS

C

SEN

Z

IN

FB

VSEN+

VCC

VSEN-

VMON

COMP

FB

OV/UV

COMP

ERROR AMP

1.8V

GAIN=1

V

SS

FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION

components shown in Figure 8 should be located as close

together as possible. Please note that the capacitors C

Application Guidelines

IN

Layout Considerations

and C each represent numerous physical capacitors.

O

As in any high frequency switching converter, layout is very

important. Switching current from one power device to

another can generate voltage transients across the

impedances of the interconnecting bond wires and circuit

traces. These interconnecting impedances should be

minimized by using wide, short printed circuit traces. The

critical components should be located as close together as

possible using ground plane construction or single point

grounding.

Locate the ISL6540A within 3 inches of the MOSFETs, Q1

and Q2. The circuit traces for the MOSFETs’ gate and

source connections from the ISL6540A must be sized to

handle up to 4A peak current.

+V

Q1

IN

BOOT

D1

C

L

O

BOOT

PHASE

+5V

PVCC

PGND

V

OUT

ISL6540A

SS

V

C

O

Q2

IN

C

PVCC

C

SS

ISL6540A

GND

UGATE

PHASE

Q1

Q2

L

O

V

OUT

FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

C

IN

C

O

LGATE

PGND

Proper grounding of the IC is important for correct operation

in noisy environments. The PGND pin should be connected

to board ground at the source of the low side MOSFET with

a wide short trace. The GND pin should be connected to a

large copper fill under the IC which is subsequently

connected to board ground at a quite location on the board,

typically found at an input or output bulk (electrolytic)

capacitor.

RETURN

FIGURE 7. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

Figure 7 shows the critical power components of the

converter. To minimize the voltage overshoot/undershoot the

interconnecting wires indicated by heavy lines should be part

of ground or power plane in a printed circuit board. The

Figure 8 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

FN6288.2

March 12, 2007

15

ISL6540A

current paths on the SS pin and locate the capacitor, C

SS

poles, zeros and gain to the components (R , R , R , C , C ,

1 2 3 1 2

close to the SS pin (as described earlier) as the internal

current source is only 37μA. Provide local decoupling

between PVCC and PGND pins as described earlier. Locate

and C ) in Figures 9 and 10. Use the following guidelines for

locating the poles and zeros of the compensation network:

3

C

2

the capacitor, C

PHASE pins.

as close as practical to the BOOT and

BOOT

C

R

3

R

C

2

1

Compensating the Converter

COMP

The ISL6540A single-phase converter is a voltage-mode

controller. This section highlights the design considerations for

a voltage-mode controller requiring external compensation. To

address a broad range of applications, a type-3 feedback

network is recommended (see Figure 9).

-

R

FB

1

+

E/A

VREF

VMON

R

FB

C

2

-

VSEN-

VSEN+

C

SEN

R

OS

+

C

R

1

2

COMP

FB

V

OSCILLATOR

OUT

C

3

V

IN

R

1

ISL6540A

V

R

OSC

3

PWM

CIRCUIT

VMON

L

DCR

C

UGATE

PHASE

HALF-BRIDGE

DRIVE

FIGURE 9. COMPENSATION CONFIGURATION FOR

ISL6540A WHEN USING DIFFERENTIAL REMOTE

SENSE

ESR

LGATE

Figure 10 highlights the voltage-mode control loop for a

synchronous-rectified buck converter, when using an internal

differential remote sense amplifier. The output voltage

ISL6540A

EXTERNAL CIRCUIT

(V

) is regulated to the reference voltage, VREF, level.

OUT

FIGURE 10. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

The error amplifier output (COMP pin voltage) is compared

with the oscillator (OSC) triangle wave to provide a

pulse-width modulated wave with an amplitude of V at the

IN

PHASE node. The PWM wave is smoothed by the output

filter (L and C). The output filter capacitor bank’s equivalent

series resistance is represented by the series resistor ESR.

1. Select a value for R (1kΩ to 10kΩ, typically). Calculate

1

value for R for desired converter bandwidth (F ). If

2

0

setting the output voltage to be equal to the reference set

voltage as shown in Figure 9, the design procedure can

be followed as presented. However, when setting the

output voltage via a resistor divider placed at the input of

the differential amplifier (as shown in Figure 10), in order

to compensate for the attenuation introduced by the

The modulator transfer function is the small-signal transfer

function of V

DC gain, given by D

/V

. This function is dominated by a

V /V , and shaped by the

OUT COMP

MAX IN OSC

output filter, with a double pole break frequency at F and a

LC

resistor divider, the below obtained R value needs be

multiplied by a factor of (R +R )/R . The remainder

OS FB OS

of the calculations remain unchanged, as long as the

zero at F . For the purpose of this analysis C and ESR

CE

represent the total output capacitance and its equivalent

series resistance.

2

compensated R value is used.

2

1

---------------------------

F

=

---------------------------------

F

=

LC

CE

2π ⋅ C ⋅ ESR

2π ⋅ L ⋅ C

V

⋅ R ⋅ F

1 0

⋅ V ⋅ F

IN LC

OSC

---------------------------------------------

=

R

2

d

MAX

The compensation network consists of the error amplifier

(internal to the ISL6540A) and the external R -R , C -C

3

A small capacitor, C_SENin Figure 10, can be added to filter

out noise, typically C_SENis chosen so the corresponding

time constant does not reduce the overall phase margin

of the design, typically this is 2x to 10x switching

1

3

1

components. The goal of the compensation network is to

provide a closed loop transfer function with high 0dB crossing

frequency (F ; typically 0.1 to 0.3 of F ) and adequate

SW

0

frequency of the regulator. As the ISL6540A supports

phase margin (better than 45°). Phase margin is the

100% duty cycle, d

equals 1. The ISL6540A also

MAX

difference between the closed loop phase at F and 180°.

0dB

uses feedforward compensation, as such V

is equal

OSC

The equations that follow relate the compensation network’s

FN6288.2

March 12, 2007

16

ISL6540A

to 0.16 multiplied by the voltage at the VFF pin. When

peak dependent on the quality factor (Q) of the output filter,

tieing VFF to V the above equation simplifies to:

which is not shown. Using the above guidelines should yield a

compensation gain similar to the curve plotted. The open loop

IN

0.16 ⋅ R ⋅ F

1

0

----------------------------------

R

=

2

F

1

LC

--------------------------------------------

F

=

------------------------------

F

=

P1

Z1

C

⋅ C

2

2π ⋅ R ⋅ C

1

2

1

--------------------

⋅

2π ⋅ R

2. Calculate C such that F is placed at a fraction of the F

,

2

1

Z1 LC

C

+ C

2

1

at 0.1 to 0.75 of F (to adjust, change the 0.5 factor to

LC

1

-------------------------------------------------

2π ⋅ (R + R ) ⋅ C

------------------------------

2π ⋅ R ⋅ C

F

=

F

=

desired number). The higher the quality factor of the output

Z2

P2

1

3

filter and/or the higher the ratio F /F , the lower the F

CE LC Z1

frequency (to maximize phase boost at F ).

LC

error amplifier gain bounds the compensation gain. Check the

compensation gain at F against the capabilities of the error

1

----------------------------------------------

C

=

P2

1

2π ⋅ R ⋅ 0.5 ⋅ F

2

LC

amplifier. The closed loop gain, G , is constructed on the

CL

3. Calculate C such that F is placed at F

.

log-log graph of Figure 11 by adding the modulator gain,

2

P1 CE

G

(in dB), to the feedback compensation gain, G (in

C

MOD

FB

1

-------------------------------------------------------

=

C

dB). This is equivalent to multiplying the modulator transfer

function and the compensation transfer function and then

plotting the resulting gain.

2

2π ⋅ R ⋅ C ⋅ F – 1

CE

2

1

4. Calculate R such that F is placed at F . Calculate C

3

Z2

LC

such that F is placed below F

(typically, 0.5 to 1.0

P2 SW

times F ). F

represents the regulator’s switching

MODULATOR GAIN

SW SW

F

P1

F

Z1 Z2

P2

COMPENSATION GAIN

CLOSED LOOP GAIN

OPEN LOOP E/A GAIN

frequency. Change the numerical factor to reflect desired

placement of this pole. Placement of F lower in frequency

P2

helps reduce the gain of the compensation network at high

frequency, in turn reducing the HF ripple component at the

COMP pin and minimizing resultant duty cycle jitter.

R

1

---------------------

R

=

R2

-------

3

⎛

⎝

⎞

⎠

F

20log

D

⋅ V

IN

SW

R1

MAX

------------

– 1

20log----------------------------------

F

LC

V

0

OSC

1

G

FB

------------------------------------------------

2π ⋅ R ⋅ 0.7 ⋅ F

C

=

3

G

3

SW

CL

It is recommended that a mathematical model is used to plot

the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. The following equations describe the

G

MOD

FREQUENCY

LOG

F

0

LC

CE

FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

D

⋅ V

IN

1 + s(f) ⋅ ESR ⋅ C

MAX

V

------------------------------ -----------------------------------------------------------------------------------------------------------

G

(f) =

⋅

MOD

2

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

OSC

1 + s(f) ⋅ (ESR + DCR) ⋅ C + s (f) ⋅ L ⋅ C

1 + s(f) ⋅ R ⋅ C

2

1

----------------------------------------------------

G

(f) =

⋅

FB

s(f) ⋅ R ⋅ (C + C )

1

2

1 + s(f) ⋅ (R + R ) ⋅ C

3

1

3

-------------------------------------------------------------------------------------------------------------------------

C

⋅ C

⎛

⎜

⎝

⎞⎞

⎟⎟

⎠⎠

1

2

--------------------

(1 + s(f) ⋅ R ⋅ C ) ⋅ 1 + s(f) ⋅ R ⋅

2

⎜

3

C

+ C

2

⎝

1

the switching frequency, F

.

G

(f) = G

(f) ⋅ G (f)

MOD FB

SW

where, s(f) = 2π ⋅ f ⋅ j

CL

Component Selection Guidelines

frequency response of the modulator (G

compensation (G ) and closed-loop response (G ):

FB CL

), feedback

MOD

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

As before when tieing VFF to VIN terms in the above

equations can be simplified as follows:

D

⋅ V

1 ⋅ V

IN

MAX

V

IN

------------------------------

--------------------------

=

= 6.25

0.16 ⋅ V

OSC

IN

COMPENSATION BREAK FREQUENCY EQUATIONS

Figure 11 shows an asymptotic plot of the DC/DC converter’s

gain vs. frequency. The actual modulator gain has a high gain

FN6288.2

March 12, 2007

17

ISL6540A

Modern microprocessors produce transient load rates above

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

The response time to a transient is different for the

application of load and the removal of load. The following

equations give the approximate response time interval for

application and removal of a transient load:

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements. For example, Intel

recommends that the high frequency decoupling for the

Pentium Pro be composed of at least forty (40) 1.0μF

ceramic capacitors in the 1206 surface-mount package.

Follow on specifications have only increased the number

and quality of required ceramic decoupling capacitors.

L

× I

L × I

O TRAN

O

TRAN

-------------------------------

------------------------------

t

=

t

=

FALL

RISE

V

– V

V

IN

OUT

where: I

is the transient load current step, t

is the

TRAN

response time to the application of load, and t

RISE

FALL

response time to the removal of load. With a lower input

source such as 1.8V or 3.3V, the worst case response time

can be either at the application or removal of load and

dependent upon the output voltage setting. Be sure to check

both of these equations at the minimum and maximum

output levels for the worst case response time.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient.

An aluminum electrolytic capacitor's ESR value is related to

the case size with lower ESR available in larger case sizes.

However, the equivalent series inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient

loading. Unfortunately, ESL is not a specified parameter.

Work with your capacitor supplier and measure the

capacitor’s impedance with frequency to select a suitable

component. In most cases, multiple electrolytic capacitors of

small case size perform better than a single large case

capacitor.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q1 turns on. Place the

small ceramic capacitors physically close to the MOSFETs

and between the drain of Q1 and the source of Q2.

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximated

below.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

V

2

O

ΔI

-------

2

----------

D =

I

=

I

(D – D ) +

D

IN, RMS

O

VIN

12

OR

V

- V

V

OUT

V

IN

F

OUT

ΔV

= ΔI × ESR

------------------------------- ---------------

ΔI =

•

OUT

I

= K

• I

x L

IN, RMS

ICM

O

S

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

For a through hole design, several electrolytic capacitors

(Panasonic HFQ series or Nichicon PL series or Sanyo

MV-GX or equivalent) may be needed. For surface mount

designs, solid tantalum capacitors can be used, but caution

must be exercised with regard to the capacitor surge current

rating. These capacitors must be capable of handling the

surge-current at power-up. The TPS series available from

One of the parameters limiting the converter’s response to a

load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

ISL6540A will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

FN6288.2

March 12, 2007

18

ISL6540A

MOSFET Selection/Considerations

The ISL6540A requires 2 N-Channel power MOSFETs.

These should be selected based upon r , gate supply

0.60

0.50

0.40

0.30

0.20

0.10

0.00

DS(ON)

0.5Io

requirements, and thermal management requirements.

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss

0.25Io

components; conduction loss and switching loss. The

conduction losses are the largest component of power

dissipation for both the upper and the lower MOSFETs.

These losses are distributed between the two MOSFETs

according to duty factor (see the equations below). The

upper MOSFET exhibits turn-on and turn-off switching

losses as well as the reverse recover loss, while the

synchronous rectifier exhibits body-diode conduction losses

during the leading and trailing edge dead times.

ΔI=0Io

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

DUTY CYCLE (D)

1

FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR

SINGLE-PHASE BUCK CONVERTER

r

2

DS(ON),L

ΔI

2

⎛

⎝

⎞

⎠

---------------------------

P

=

I

+

•

• (1 – D) + P

-------

AVX, and the 593D series from Sprague are both surge

current tested.

LOWER

O

DEAD

N

L

12

ΔI

⎛

⎝

⎞

⎠

⎛

⎞

⎠

------

=

I

+

• V

• t

+ I

–

• V • t

• F

------

DEAD

O

DT DT

O

DL DL S

⎝

12

r

2

DS(ON),U

ΔI

2

⎛

⎞

⎠

---------------------------

P

=

I

+

•

• D + P

+ P

-------

UPPER

O

SW

Qrr

⎝

N

U

12

ΔI

12

ΔI

⎛

⎝

⎞

⎛

⎞

------

=

I

+

• t

+ I

–

• t

• VIN • F

S

------

SW

O

OFF

O

ON

⎠

⎝

⎠

12

P

= Q • VIN • F

rr S

Qrr

where D is the duty cycle = V /VIN; Q is the reverse

rr

O

recover charge; t and t are leading and trailing edge

DL

DT

dead time, and t

& t

are the switching intervals.

ON

OFF

These equations do not include the gate-charge losses that

are proportional to the total gate charge and the switching

frequency and partially dissipated by the internal gate

resistance of the MOSFETs. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate

heatsink may be necessary depending upon MOSFET

power, package type, ambient temperature and air flow.

ISL6540A DC/DC Converter Application Circuit

Detailed information on the application circuit, including a

complete Bill-of-Materials and circuit board description, can

be found in application note AN1253. See Intersil’s home

page on the web: http://www.intersil.com.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6288.2

March 12, 2007

19

ISL6540A

Quad Flat No-Lead Plastic Package (QFN)

Micro Lead Frame Plastic Package (MLFP)

L28.5x5

28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220VHHD-1 ISSUE I)

2X

0.15

C A

D

A

MILLIMETERS

9

D/2

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

D1

A

A1

A2

A3

b

0.80

0.90

-

D1/2

2X

-

0.02

-

N

0.15 C

B

6

0.65

9

INDEX

AREA

0.20 REF

9

1

2

3

E1/2

E/2

9

0.18

2.95

0.25

0.30

3.25

5,8

E1

E

B

D

5.00 BSC

-

D1

D2

E

4.75 BSC

9

2X

3.10

7,8

0.15 C

B

2X

5.00 BSC

-

TOP VIEW

0.15 C A

E1

E2

e

4.75 BSC

9

0

A2

4X

3.10

7,8

A

/ /

0.10 C

0.08 C

C

0.50 BSC

-

k

0.20

0.50

-

0.60

28

7

-

SEATING PLANE

A1

A3

SIDE VIEW

L

0.75

8

9

N

2

5

NX b

Nd

Ne

P

3

0.10 M C A B

4X P

7

3

D2

8

7

NX k

-

0.60

12

9

(DATUM B)

2

N

θ

-

9

4X P

Rev. 1 11/04

1

(DATUM A)

2

3

NOTES:

(Ne-1)Xe

REF.

E2

6

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

INDEX

AREA

7

8

E2/2

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

NX L

8

N

e

9

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

(Nd-1)Xe

REF.

CORNER

OPTION 4X

BOTTOM VIEW

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

A1

NX b

5

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare provided toassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

SECTION "C-C"

C

L

C

L

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

L

10

L1

e

C

TERMINAL TIP

FOR ODD TERMINAL/SIDE

FOR EVEN TERMINAL/SIDE

FN6288.2

March 12, 2007

20


型号：	ISL6540AIRZ
厂家：	Intersil
描述：	Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability 单相降压PWM控制器，集成高速MOSFET驱动器和预偏置负载能力驱动器开关控制器
文件：	总20页 (文件大小：427K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6540AIRZ [INTERSIL]

相关型号：

ISL6540AIRZ-T

ISL6540AIRZ-TS2568

ISL6540AIRZA

ISL6540AIRZA

ISL6540AIRZA-T

ISL6540AIRZA-T

ISL6540CRZ

ISL6540CRZ-T

ISL6540CRZA

ISL6540CRZA-T

ISL6540IRZ

ISL6540IRZ-T