ISL6609IBZ-T_技术文档

ISL6609, ISL6609A

®

Data Sheet

April 27, 2009

FN9221.2

Synchronous Rectified MOSFET Driver

Features

The ISL6609, ISL6609A is a high frequency, MOSFET driver

optimized to drive two N-Channel power MOSFETs in a

synchronous-rectified buck converter topology. This driver

combined with an Intersil ISL63xx or ISL65xx multiphase

PWM controller forms a complete single-stage core-voltage

regulator solution with high efficiency performance at high

switching frequency for advanced microprocessors.

• Drives Two N-Channel MOSFETs

• Adaptive Shoot-Through Protection

• 0.4Ω On-Resistance and 4A Sink Current Capability

• Supports High Switching Frequency

- Fast Output Rise and Fall

- Ultra Low Three-State Hold-Off Time (20ns)

The IC is biased by a single low voltage supply (5V),

minimizing driver switching losses in high MOSFET gate

capacitance and high switching frequency applications.

Each driver is capable of driving a 3nF load with less than

10ns rise/fall time. Bootstrapping of the upper gate driver is

implemented via an internal low forward drop diode,

reducing implementation cost, complexity, and allowing the

use of higher performance, cost effective N-Channel

MOSFETs. Adaptive shoot-through protection is integrated

to prevent both MOSFETs from conducting simultaneously.

• ISL6605 Replacement with Enhanced Performance

• BOOT Capacitor Overcharge Prevention (ISL6609A)

• Low V Internal Bootstrap Diode

F

• Low Bias Supply Current

• Enable Input and Power-On Reset

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN-Quad Flat

No Leads-Product Outline

The ISL6609, ISL6609A features 4A typical sink current for

the lower gate driver, enhancing the lower MOSFET gate

hold-down capability during PHASE node rising edge,

preventing power loss caused by the self turn-on of the lower

MOSFET due to the high dV/dt of the switching node.

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile

• Pb-Free (RoHS Compliant)

Applications

The ISL6609, ISL6609A also features an input that

• Core Voltage Supplies for Intel® and AMD®

Microprocessors

recognizes a high-impedance state, working together with

Intersil multiphase PWM controllers to prevent negative

transients on the controlled output voltage when operation is

suspended. This feature eliminates the need for the schottky

diode that may be utilized in a power system to protect the

load from negative output voltage damage. In addition, the

ISL6609A’s bootstrap function is designed to prevent the

BOOT capacitor from overcharging, should excessively large

negative swings occur at the transitions of the PHASE node.

• High Frequency Low Profile High Efficiency DC/DC

Converters

• High Current Low Voltage DC/DC Converters

• Synchronous Rectification for Isolated Power Supplies

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

AMD® is a registered trademark of Advanced Micro Devices, Inc. All other trademarks mentioned are the property of their respective owners.

ISL6609, ISL6609A

Ordering Information

PART NUMBER

(Note)

PART

MARKING

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL6609CBZ

ISL66 09CBZ

0 to +70

8 Ld SOIC

M8.15

L8.3x3

M8.15

L8.3x3

M8.15

L8.3x3

M8.15

L8.3x3

ISL6609CBZ-T*

ISL6609CRZ

8 Ld SOIC

609Z

0 to +70

8 Ld 3x3 QFN

8 Ld SOIC

ISL6609CRZ-T*

ISL6609IBZ

609Z

0 to +70

ISL66 09IBZ

09IZ

-40 to +85

0 to +70

ISL6609IBZ-T*

ISL6609IRZ

8 Ld SOIC

8 Ld 3x3 QFN

8 Ld SOIC

ISL6609IRZ-T*

ISL6609ACBZ

ISL6609ACBZ-T*

ISL6609ACRZ

ISL6609ACRZ-T*

ISL6609AIBZ

09IZ

6609 ACBZ

09AZ

0 to +70

8 Ld SOIC

0 to +70

8 Ld 3x3 QFN

8 Ld SOIC

09AZ

0 to +70

6609 AIBZ

9AIZ

-40 to +85

ISL6609AIBZ-T*

ISL6609AIRZ

8 Ld SOIC

8 Ld 3x3 QFN

ISL6609AIRZ-T*

ISL6609AIRZ-TK*

9AIZ

*Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

Pinouts

ISL6609, ISL6609A

(8 LD SOIC)

ISL6609, ISL6609A

(8 LD QFN)

TOP VIEW

UGATE

BOOT

PWM

1

2

3

4

8

7

6

5

PHASE

EN

8

3

7

4

VCC

6

BOOT

PWM

1

2

EN

GND

LGATE

5

VCC

FN9221.2

April 27, 2009

2

ISL6609, ISL6609A

Block Diagram

ISL6609 and ISL6609A

R

BOOT

VCC

EN

BOOT

UGATE

PHASE

VCC

4.25k

SHOOT-

THROUGH

PROTECTION

PWM

CONTROL

LOGIC

VCC

LGATE

GND

4k

INTEGRATED 3Ω RESISTOR (R

) AVAILABLE ONLY IN ISL6609A

BOOT

FN9221.2

April 27, 2009

3

ISL6609, ISL6609A

Typical Application - Multiphase Converter Using ISL6609 Gate Drivers

V

IN

+5V

BOOT

VCC

EN

PWM

+5V

FB

COMP

R

UGPH

VCC

UGATE

VSEN

PWM1

PWM2

ISL6609

PHASE

LGATE

PGOOD

PWM

CONTROL

(ISL63XX

or ISL65XX)

ISEN1

ISEN2

VID

(OPTIONAL)

+V

CORE

+5V

V

IN

BOOT

VCC

FS/EN

R

EN

UGPH

GND

UGATE

PWM

ISL6609

PHASE

LGATE

R

IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS

(SEE APPLICATION INFORMATION SECTION ON PAGE 8)

UGPH

FN9221.2

April 27, 2009

4

ISL6609, ISL6609A

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V

Input Voltage (V , V ) . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V

Thermal Resistance (Notes 1, 2, 3)

θ

(°C/W)

θ

(°C/W)

JA

JC

EN PWM

BOOT Voltage (V

SOIC Package (Note 1) . . . . . . . . . . . .

QFN Package (Notes 2, 3). . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

110

95

N/A

36

). . . -0.3V to 27V (DC) or 36V (<200ns)

BOOT-GND

BOOT To PHASE Voltage (V

). . . . . . -0.3V to 7V (DC)

-0.3V to 9V (<10ns)

BOOT-PHASE

PHASE Voltage . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 27V (DC)

GND -8V (<20ns Pulse Width, 10μJ) to 30V (<100ns)

UGATE Voltage . . . . . . . . . . . . . . . . V

- 0.3V (DC) to V

PHASE

BOOT

- 5V (<20ns Pulse Width, 10μJ) to V

BOOT

V

PHASE

LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V

GND - 2.5V (<20ns Pulse Width, 5μJ) to VCC + 0.3V

Ambient Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +125°C

Recommended Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 100°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

JA

3. θ , “case temperature” location is at the center of the package underside exposed pad. See Tech Brief TB379 for details.

JC

Electrical Specifications These specifications apply for T_A= -40°C to 100°C, unless otherwise noted. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

PARAMETER

VCC SUPPLY CURRENT

Bias Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

PWM pin floating, V

VCC

= 5V

-

132

3.4

3.0

400

-

4.2

-

μA

VCC

POR Rising

POR Falling

2.2

-

Hysteresis

-

mV

PWM INPUT

Sinking Impedance

R

2.75

4

5.5

5.75

2.00

-

kΩ

V

PWM_SNK

Source Impedance

3

4.25

1.70

3.41

20

PWM_SRC

Three-State Rising Threshold

Three-State Falling Threshold

Three-State Shutdown Holdoff Time

EN INPUT

V

= 5V (100mV Hysteresis)

-

3.10

-

VCC

V

VCC

t

or t + Gate Falling Time

PDLL

-

ns

TSSHD

PDLU

EN LOW Threshold

1.0

-

1.3

1.6

-

V

EN HIGH Threshold

2.0

SWITCHING TIME (See Figure 1 on Page 7)

UGATE Rise Time (Note 4)

LGATE Rise Time (Note 4)

UGATE Fall Time (Note 4)

LGATE Fall Time (Note 4)

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

t

V

= 5V, 3nF Load

-

8.0

4.0

18

-

ns

RU

VCC

t

= 5V, 3nF Load

RL

= 5V, 3nF Load

FU

t

= 5V, 3nF Load

FL

t

= 5V, Outputs Unloaded

PDLU

t

25

PDLL

FN9221.2

April 27, 2009

5

ISL6609, ISL6609A

Electrical Specifications These specifications apply for T_A= -40°C to 100°C, unless otherwise noted. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

= 5V, Outputs Unloaded

MIN

TYP

18

MAX

UNITS

ns

UGATE Turn-On Propagation Delay

LGATE Turn-On Propagation Delay

t

V

-

PDHU

VCC

t

23

ns

PDHL

Three-state to UG/LG Rising Propagation

Delay

t

20

ns

PTS

OUTPUT

Upper Drive Source Resistance

Upper Drive Sink Resistance

Lower Drive Source Resistance

Lower Drive Sink Resistance

NOTE:

R

250mA Source Current

250mA Sink Current

250mA Source Current

250mA Sink Current

-

1.0

0.4

2.5

1.0

Ω

UG_SRC

UG_SNK

R

LG_SRC

LG_SNK

R

4. Limits established by characterization and are not production tested

LGATE (Pin 5)

Functional Pin Description

Lower gate drive output. Connect to gate of the low side

N-Channel power MOSFET. A gate resistor is never

recommended on this pin, as it interferes with the operation

shoot-through protection circuitry.

Note: Pin numbers refer to the SOIC package. Check

diagram for corresponding QFN pinout.

UGATE (Pin 1)

Upper gate drive output. Connect to gate of high-side

N-Channel power MOSFET. A gate resistor is never

recommended on this pin, as it interferes with the operation

shoot-through protection circuitry.

VCC (Pin 6)

Connect this pin to a +5V bias supply. Locally bypass with a

high quality ceramic capacitor to ground.

EN (Pin 7)

BOOT (Pin 2)

Enable input pin. Connect this pin high to enable and low to

disable the driver.

Floating bootstrap supply pin for the upper gate drive.

Connect a bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge

used to turn on the upper MOSFET. See “Bootstrap

Considerations” on page 7 for guidance in choosing the

appropriate capacitor value.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET. This

pin provides the return path for the upper gate driver current.

Thermal Pad (in QFN only)

PWM (Pin 3)

The metal pad underneath the center of the IC is a thermal

substrate. The PCB “thermal land” design for this exposed

die pad should include vias that drop down and connect to

one or more buried copper plane(s). This combination of

vias for vertical heat escape and buried planes for heat

spreading allows the QFN to achieve its full thermal

potential. This pad should be either grounded or floating,

and it should not be connected to other nodes. Refer to

TB389 for design guidelines.

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see

“Three-State PWM Input” on page 7 for further details. Connect

this pin to the PWM output of the controller.

GND (Pin 4)

Ground pin. All signals are referenced to this node.

FN9221.2

April 27, 2009

6

ISL6609, ISL6609A

Timing Diagram

2.5V

t

PWM

PDHU

t

PDLU

TSSHD

t

RU

t

FU

t

PTS

1V

UGATE

LGATE

t

PTS

1V

t

RL

t

TSSHD

t

PDHL

t

PDLL

FL

FIGURE 1. TIMING DIAGRAM

current capability enable the lower gate driver to absorb the

current injected into the lower gate through the drain-to-gate

capacitor of the lower MOSFET and help prevent shoot

through caused by the self turn-on of the lower MOSFET due

to high dV/dt of the switching node.

Operation and Adaptive Shoot-Through Protection

Designed for high speed switching, the ISL6609, ISL6609A

MOSFET driver controls both high-side and low-side N-

Channel FETs from one externally provided PWM signal.

A rising transition on PWM initiates the turn-off of the lower

MOSFET (see “Timing Diagram”). After a short propagation

Three-State PWM Input

delay [t

], the lower gate begins to fall. Typical fall times

A unique feature of the ISL6609, ISL6609A is the adaptable

three-state PWM input. Once the PWM signal enters the

shutdown window, either MOSFET previously conducting is

turned off. If the PWM signal remains within the shutdown

window for longer than the gate turn-off propagation delay of

the previously conducting MOSFET, the output drivers are

disabled and both MOSFET gates are pulled and held low.

The shutdown state is removed when the PWM signal moves

outside the shutdown window. The PWM rising and falling

thresholds outlined in the “Electrical Specifications” table on

page 5 determine when the lower and upper gates are

enabled. During normal operation in a typical application, the

PWM rise and fall times through the shutdown window should

not exceed either output’s turn-off propagation delay plus the

MOSFET gate discharge time to ~1V. Abnormally long PWM

signal transition times through the shutdown window will

simply introduce additional dead time between turn off and

turn on of the synchronous bridge’s MOSFETs. For optimal

performance, no more than 100pF parasitic capacitive load

should be present on the PWM line of ISL6609, ISL6609A

(assuming an Intersil PWM controller is used).

PDLL

[t ] are provided in the “Electrical Specifications” table on

FL

page 5. Adaptive shoot-through circuitry monitors the

LGATE voltage and turns on the upper gate following a short

delay time [t

~1V. The upper gate drive then begins to rise [t ] and the

upper MOSFET turns on.

] after the LGATE voltage drops below

PDHU

RU

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t

gate begins to fall [t ]. The adaptive shoot-through circuitry

monitors the UGATE-PHASE voltage and turns on the lower

] is encountered before the upper

PDLU

FU

MOSFET a short delay time, t , after the upper

MOSFET’s gate voltage drops below 1V. The lower gate then

PDHL

rises [t ], turning on the lower MOSFET. These methods

RL

prevent both the lower and upper MOSFETs from conducting

simultaneously (shoot-through), while adapting the dead

time to the gate charge characteristics of the MOSFETs

being used.

This driver is optimized for voltage regulators with large step

down ratio. The lower MOSFET is usually sized larger

compared to the upper MOSFET because the lower MOSFET

conducts for a longer time during a switching period. The

lower gate driver is therefore sized much larger to meet this

application requirement. The 0.4Ω ON-resistance and 4A sink

Bootstrap Considerations

This driver features an internal bootstrap diode. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit. The ISL6609A’s internal

FN9221.2

April 27, 2009

7

ISL6609, ISL6609A

bootstrap resistor is designed to reduce the overcharging of

allowable power dissipation level will push the IC beyond the

maximum recommended operating junction temperature of

+125°C. The maximum allowable IC power dissipation for

the SO8 package is approximately 800mW at room

temperature, while the power dissipation capacity in the

QFN package, with an exposed heat escape pad, is slightly

better. See “Layout Considerations” on page 9 for thermal

transfer improvement suggestions. When designing the

driver into an application, it is recommended that the

following calculation is used to ensure safe operation at the

desired frequency for the selected MOSFETs. The total gate

drive power losses due to the gate charge of MOSFETs and

the driver’s internal circuitry and their corresponding average

driver current can be estimated with Equations 2 and 3,

respectively,

the bootstrap capacitor when exposed to excessively large

negative voltage swing at the PHASE node. Typically, such

large negative excursions occur in high current applications

2

that use D -PAK and D-PAK MOSFETs or excessive layout

parasitic inductance.

The following equation helps select a proper bootstrap

capacitor size:

Q

GATE

-------------------------------------

C

≥

BOOT_CAP

ΔV

BOOT_CAP

(EQ. 1)

Q

• VCC

G1

V

-------------------------------

Q

=

• N

Q1

GATE

GS1

where Q is the amount of gate charge per upper MOSFET

G1

(EQ. 2)

P

= P

+ P

+ I • VCC

Q

Qg_TOT

Qg_Q1

Q

Qg_Q2

2

at V

gate-source voltage and N is the number of

GS1

control MOSFETs. The ΔV

Q1

term is defined as the

BOOT_CAP

• VCC

G1

V

----------------------------------

allowable droop in the rail of the upper gate drive.

P

=

• F

• N

Qg_Q1

Qg_Q2

SW

Q1

GS1

As an example, suppose two IRLR7821 FETs are chosen as

2

Q

• VCC

G2

the upper MOSFETs. The gate charge, Q , from the data

G

----------------------------------

P

=

• F

SW

Q2

V

sheet is 10nC at 4.5V (V ) gate-source voltage. Then the

GS

GS2

Q

is calculated to be 22nC at VCC level. We will

GATE

assume a 200mV droop in drive voltage over the PWM

cycle. We find that a bootstrap capacitance of at least

0.110µF is required. The next larger standard value

capacitance is 0.22µF. A good quality ceramic capacitor is

recommended.

Q

• UVCC • N

Q

• LVCC • N

G2 Q2

⎛

⎜

⎝

⎞

⎟

⎠

G1

Q1

----------------------------------------------------- ----------------------------------------------------

I

=

+

• F

+ I

DR

SW

Q

V

GS2

GS1

(EQ. 3)

where the gate charge (Q and Q ) is defined at a

G1

G2

2.0

particular gate to source voltage (V

and V

) in the

GS1

GS2

corresponding MOSFET datasheet; I is the driver’s total

Q

1.8

1.6

1.4

1.2

1.0

0.8

0.6

quiescent current with no load at both drive outputs; N

Q1

and N are number of upper and lower MOSFETs,

Q2

respectively. The I

V

product is the quiescent power of

Q

CC

the driver without capacitive load and is typically negligible.

The total gate drive power losses are dissipated among the

resistive components along the transition path. The drive

resistance dissipates a portion of the total gate drive power

losses, the rest will be dissipated by the external gate

Q

= 100nC

GATE

resistors (R and R , should be a short to avoid

G1 G2

0.4

interfering with the operation shoot-through protection

circuitry) and the internal gate resistors (R and R ) of

50nC

0.2

0.0

GI1

GI2

20nC

MOSFETs. Figures 3 and 4 show the typical upper and lower

gate drives turn-on transition path. The power dissipation on

the driver can be roughly estimated as:

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

ΔV (V)

BOOT

FIGURE 2. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE

VOLTAGE

P

= P

+ P

+ I • VCC

(EQ. 4)

DR

DR_UP

DR_LOW

Q

R

P

Qg_Q1

⎛

⎞

Power Dissipation

HI1

LO1

-------------------------------------- --------------------------------------- ---------------------

=

+

•

⎜

⎝

⎟

⎠

DR_UP

R

+ R

R

+ R

EXT1

2

HI1

EXT1

LO1

Package power dissipation is mainly a function of the

switching frequency (F ), the output drive impedance, the

SW

R

P

Qg_Q2

⎛

⎜

⎝

⎞

HI2

LO2

external gate resistance, and the selected MOSFET’s

internal gate resistance and total gate charge. Calculating

the power dissipation in the driver for a desired application is

critical to ensure safe operation. Exceeding the maximum

-------------------------------------- --------------------------------------- ---------------------

P

R

=

+

•

⎟

DR_LOW

R

+ R

R

+ R

⎠

EXT2

2

HI2

EXT2

LO2

R

GI1

GI2

-------------

= R

+

R

= R +

G2

EXT2

G1

EXT2

N

Q1

Q2

FN9221.2

April 27, 2009

8

ISL6609, ISL6609A

Layout Considerations

VCC

BOOT

A good layout helps reduce the ringing on the switching

node (PHASE) and significantly lower the stress applied to

the output drives. The following advice is meant to lead to an

optimized layout:

D

C

GD

R

HI1

G

C

DS

R

LO1

R

GI1

C

G1

• Keep decoupling loops (VCC-GND and BOOT-PHASE) as

short as possible.

UGATE

PHASE

GS

Q1

S

• Minimize trace inductance, especially on low-impedance

lines. All power traces (UGATE, PHASE, LGATE, GND,

VCC) should be short and wide, as much as possible.

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

• Minimize the inductance of the PHASE node. Ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

VCC

• Minimize the current loop of the output and input power

trains. Short the source connection of the lower MOSFET

to ground as close to the transistor pin as feasible. Input

capacitors (especially ceramic decoupling) should be

placed as close to the drain of upper and source of lower

MOSFETs as possible.

D

C

GD

LGATE

R

HI2

G

C

DS

R

LO2

R

GI2

C

G2

In addition, connecting the thermal pad of the QFN package

to the power ground through a via, or placing a low noise

copper plane underneath the SOIC part is recommended for

high switching frequency, high current applications. This is to

improve heat dissipation and allow the part to achieve its

full thermal potential.

GS

Q2

S

GND

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Upper MOSFET Self Turn-On Effects at Startup

Application Information

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, because of

MOSFET and Driver Selection

The parasitic inductances of the PCB and of the power

devices’ packaging (both upper and lower MOSFETs) can

cause serious ringing, exceeding absolute maximum rating

of the devices. The negative ringing at the edges of the

PHASE node could increase the bootstrap capacitor voltage

through the internal bootstrap diode, and in some cases, it

may overstress the upper MOSFET driver. Careful layout,

proper selection of MOSFETs and packaging, as well as the

proper driver can go a long way toward minimizing such

unwanted stress.

self-coupling via the internal C

of the MOSFET, the

GD

UGATE could momentarily rise up to a level greater than the

threshold voltage of the MOSFET. This could potentially turn

on the upper switch and result in damaging inrush energy.

Therefore, if such a situation (when input bus powered up

before the bias of the controller and driver is ready) could

conceivably be encountered, it is a common practice to

place a resistor (R

) across the gate and source of the

UGPH

upper MOSFET to suppress the Miller coupling effect. The

value of the resistor depends mainly on the input voltage’s

2

The selection of D -PAK, or D-PAK packaged MOSFETs, is a

rate of rise, the C /C

ratio, as well as the gate-source

GD GS

much better match (for the reasons discussed) for the

ISL6609A. Low-profile MOSFETs, such as Direct FETs and

multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK),

have low parasitic lead inductances and can be driven by

either ISL6609 or ISL6609A (assuming proper layout design).

The ISL6609, missing the 3Ω integrated BOOT resistor,

typically yields slightly higher efficiency than the ISL6609A.

threshold of the upper MOSFET. A higher dV/dt, a lower

/C ratio, and a lower gate-source threshold upper

FET will require a smaller resistor to diminish the effect of

the internal capacitive coupling. For most applications, a

5k to 10kΩ resistor is typically sufficient, not affecting normal

performance and efficiency.

C

DS GS

The coupling effect can be roughly estimated with the

following equations, which assume a fixed linear input ramp

and neglect the clamping effect of the body diode of the

upper drive and the bootstrap capacitor. Other parasitic

components such as lead inductances and PCB

capacitances are also not taken into account. These

equations are provided for guidance purpose only.

FN9221.2

April 27, 2009

9

ISL6609, ISL6609A

Therefore, the actual coupling effect should be examined

using a very high impedance (10MΩ or greater) probe to

ensure a safe design margin.

–V

DS

⎛

⎜

⎝

⎞

⎟

⎠

---------------------------------

dV

-------

⋅ R ⋅ C

dV

dt

iss

dt

-------

V

=

⋅ R ⋅ C

1 – e

(EQ. 5)

GS_MILLER

rss

C

= C

+ C

C

= C

R = R

+ R

iss

GD

GS

rss

GD

UGPH

GI

VCC

VIN

BOOT

D

C

BOOT

C

GD

DU

DL

G

UGATE

C

DS

R

GI

C

Q

GS

UPPER

S

PHASE

FIGURE 5. GATE TO SOURCE RESISTOR TO REDUCE

UPPER MOSFET MILLER COUPLING

FN9221.2

April 27, 2009

10

ISL6609, ISL6609A

Package Outline Drawing

L8.3x3

8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 3/07

4X

8

0.65

3.00

A

6

B

7

PIN #1 INDEX AREA

6

PIN 1

INDEX AREA

6

5

1

2

1 .10 ± 0 . 15

(4X)

0.15

4

3

0.10 M C A B

8X 0.28 ± 0.05

4

TOP VIEW

8X 0.60 ± 0.15

BOTTOM VIEW

SEE DETAIL "X"

C

0.10

C

0 . 90 ± 0.1

( 4X 0 . 65 )

BASE PLANE

SEATING PLANE

0.08

( 2. 60 TYP )

C

(

1. 10 )

SIDE VIEW

( 8X 0 . 28 )

5

0 . 2 REF

C

0 . 00 MIN.

0 . 05 MAX.

( 8X 0 . 80)

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN9221.2

April 27, 2009

11

ISL6609, ISL6609A

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

N

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9221.2

April 27, 2009

12


型号：	ISL6609IBZ-T
厂家：	Intersil
描述：	Synchronous Rectified MOSFET Driver 同步整流MOSFET驱动器驱动器接口集成电路光电二极管
文件：	总12页 (文件大小：1669K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL6609IBZ-T [INTERSIL]

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