ISL70001SRH_技术文档

Radiation Hardened and SEE Hardened 6A

Synchronous Buck Regulator with Integrated

MOSFETs

ISL70001SRH

Features

• Electrically Screened to DSCC SMD 5962-09225

The ISL70001SRH is a radiation hardened and SEE

hardened high efficiency monolithic synchronous buck

regulator with integrated MOSFETs. This single chip

power solution operates over an input voltage range

of 3V to 5.5V and provides a tightly regulated output

voltage that is externally adjustable from 0.8V to

~85% of the input voltage. Output load current

• QML Qualified per MIL-PRF-38535 Requirements

• Full Mil-Temp Range Operation (T = -55°C to

A

+125°C)

• Radiation Hardness

- Total Dose [50-300rad(Si)/s] . . . 100krad(Si) min

capacity is 6A for T < +145°C.

• SEE Hardness

- SEL and SEB LET

J

2

. . . . . . 86.4MeV/mg/cm min

2

eff

The ISL70001SRH utilizes peak current-mode control

with integrated compensation and switches at a fixed

frequency of 1MHz. Two ISL70001SRH devices can be

synchronized 180° out-of-phase to reduce input RMS

ripple current. These attributes reduce the number and

size of external components required, while providing

excellent output transient response. The internal

synchronous power switches are optimized for high

efficiency and good thermal performance.

- SEFI X-section (LET = 86.4MeV/mg/cm )

eff

1.4 x 10 cm max

-6

2

- SET LET (< 1 Pulse Perturbation)

eff

2

86.4MeV/mg/cm min

• High Efficiency > 90%

• Fixed 1MHz Operating Frequency

• Operates from 3V to 5.5V Supply

• ±1% Reference Voltage over Line, Load,

Temperature and Radiation

The chip features a comparator type enable input that

provides flexibility. It can be used for simple digital

on/off control or, alternately, can provide

• Adjustable Output Voltage

undervoltage lockout capability by precisely sensing

the level of an external supply voltage using two

external resistors. A power-good signal indicates

when the output voltage is within ±11% typical of the

nominal output voltage.

- Two External Resistors Set V

from 0.8V to

OUT

~85% of V

IN

• Excellent Dynamic Response

• Bi-directional SYNC Pin Allows Two Devices to be

Synchronized 180° Out-of-Phase

Regulator start-up is controlled by an analog soft-start

circuit, which can be adjusted from approximately 2ms

to 200ms using an external capacitor.

• Device Enable with Comparator Type Input

• Power-Good Output Voltage Monitor

• Adjustable Analog Soft-Start

The ISL70001SRH incorporates fault protection for

the regulator. The protection circuits include input

undervoltage, output undervoltage and output

overcurrent.

• Input Undervoltage, Output Undervoltage and

Output Overcurrent Protection

• Starts Into Pre-Biased Load

High integration makes the ISL70001SRH an ideal

choice to power many of today’s small form factor

applications. Two devices can be synchronized to

provide a complete power solution for large scale

digital ICs, like field programmable gate arrays

(FPGAs), that require separate core and I/O voltages.

Applications*(see page 16)

• FPGA, CPLD, DSP, CPU Core or I/O Voltages

• Low-Voltage, High-Density Distributed Power

Systems

Specifications for Rad Hard QML devices are

controlled by the Defense Supply Center in

Columbus (DSCC). The SMD numbers listed in the

Ordering Information Table on page 2 must be

used when ordering.

Detailed Electrical Specifications for these

devices are contained in SMD 5962-09225. A link

is provided on our website for downloading.

December 15, 2009

FN6947.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL70001SRH

Functional Block Diagram

POWER-ON

RESET (POR)

PORSEL

PVINx

CURRENT

SENSE

SLOPE

COMPENSATION

SOFT

START

SS

FB

PWM

CONTROL

LOGIC

GATE

DRIVE

LXx

EA

GM

COMPENSATION

PGNDx

UV

POWER-GOOD

PGOOD

REF

PWM

REFERENCE

0.6V

TDI

BIT

TDO

TRIM

ZAP

SYNC

M/S

Ordering Information

PART NUMBER

TEMP. RANGE

(°C)

ORDERING NUMBER

5962R0922501QXC

5962R0922501VXC

5962R0922501V9A

ISL70001SRHF/PROTO

ISL70001SRHX/SAMPLE

NOTE:

(Note 2)

PACKAGE

ISL70001SRHQF (Note 1)

ISL70001SRHVF (Note 1)

ISL70001SRHVX

-55 to +125

48 Ld CQFP (Pb-Free)

Die

ISL70001SRHF/PROTO (Note 1)

ISL70001SRHX/SAMPLE

48 Ld CQFP (Pb-Free)

Die

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant

and compatible with both SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70001SRH. For more information on MSL

please see techbrief TB363.

FN6947.0

December 15, 2009

2

ISL70001SRH

Pin Configuration

ISL70001SRH

(48 LD CQFP)

TOP VIEW

6

5

4

3

2

1484746 45 4443

42

PVIN3

LX3

7

M/S

41

40

39

38

37

36

35

34

33

32

31

ZAP

TDI

TDO

8

9

PGND3

PGND4

10

11

PGOOD

SS

12

13

LX4

DVDD

PVIN4

DVDD

14

15

16

DGND

PVIN5

LX5

AGND

17

18

1920 2122232425 26 2728 2930

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1, 2, 27, 28, 29,

30, 37, 38, 39,

40, 47, 48

PGNDx

These pins are the power grounds associated with the corresponding internal power blocks.

Connect these pins directly to the ground plane. These pins should also connect to the

negative terminals of the input and output capacitors. Locate the input and output capacitors

as close as possible to the IC.

3, 26, 31, 36,

41, 46

LXx

These pins are the outputs of the corresponding internal power blocks and should be

connected to the output filter inductor. Internally, these pins are connected to the synchronous

MOSFET power switches. To minimize voltage undershoot, it is recommended that a Schottky

diode be connected from these pins to PGNDx. The Schottky diode should be located as close

as possible to the IC.

4, 5, 24, 25, 32,

33, 34, 35, 42,

43, 44, 45

PVINx

SYNC

These pins are the power supply inputs to the corresponding internal power blocks. These pins

must be connected to a common power supply rail, which must fall in the range of 3V to 5.5V.

Bypass these pins directly to PGNDx with ceramic capacitors located as close as possible to

the IC.

6

This pin is the synchronization I/O for the IC. When configured as an output (Master Mode),

this pin drives the SYNC input of another ISL70001SRH. When configured as an input (Slave

Mode), this pin accepts the SYNC output from another ISL70001SRH or an external clock.

Synchronization of the slave unit is 180° out-of-phase with respect to the master unit. If

synchronizing to an external clock, the clock must be SEE hardened and the frequency must

be within the range of 1MHz ±20%.

7

8

M/S

ZAP

This pin is the Master/Slave input for selecting the direction of the bi-directional SYNC pin. For

SYNC = Output (Master Mode), connect this pin to DVDD. For SYNC = Input (Slave Mode),

connect this pin to DGND.

This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to

DGND.

9

TDI

This pin is the test data input of the internal BIT circuitry. Connect this pin to DGND.

This pin is the test data output of the internal BIT circuitry. Connect this pin to DGND.

10

TDO

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3

ISL70001SRH

Pin Descriptions(Continued)

PIN NUMBER

PIN NAME

DESCRIPTION

11

PGOOD

This pin is the power-good output. This pin is an open drain logic output that is pulled to DGND

when the output voltage is outside a ±11% typical regulation window. This pin can be pulled

up to any voltage from 0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ

pull-up resistor is recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to

mitigate SEE.

12

SS

This pin is the soft-start input. Connect a ceramic capacitor from this pin to DGND to set the

soft-start output ramp time in accordance with Equation 1:

t

= C

⋅ V ⁄ I

REF SS

(EQ. 1)

SS

Where:

t

C

V

I

= Soft-start output ramp time

= Soft-start capacitor

SS

= Reference voltage (0.6V typical)

REF

= Soft-start charging current (23µA typical)

SS

Soft-start time is adjustable from approximately 2ms to 200ms.

The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.

13, 14

DVDD

These pins are the bias supply inputs to the internal digital control circuitry. Connect these

pins together at the IC and locally filter them to DGND using a 1Ω resistor and a 1µF ceramic

capacitor. Locate both filter components as close as possible to the IC.

15, 16

17, 18

19

DGND

AGND

AVDD

These pins are the digital ground associated with the internal digital control circuitry. Connect

these pins directly to the ground plane.

These pins are the analog ground associated with the internal analog control circuitry. Connect

these pins directly to the ground plane.

This pin is the bias supply input to the internal analog control circuitry. Locally filter this pin

to AGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter components as

close as possible to the IC.

20

21

REF

FB

This pin is the internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic

capacitor located as close as possible to the IC. The bypass capacitor is needed to mitigate

SEE. No current (sourcing or sinking) is available from this pin.

This pin is the voltage feedback input to the internal error amplifier. Connect a resistor from

FB to VOUT and from FB to AGND to adjust the output voltage in accordance with Equation 2:

V

= V

⋅ [1 + (R ⁄ R )]

REF T B

(EQ. 2)

OUT

Where:

V

= Output voltage

= Reference voltage (0.6V typical)

OUT

REF

R = Top divider resistor (Must be 1kΩ)

T

R = Bottom divider resistor

B

The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across

RT to mitigate SEE and to improve stability margins.

22

23

EN

This pin is the enable input to the IC. This is a comparator type input with a rising threshold

of 0.6V and programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this

pin to AGND with a 10nF ceramic capacitor to mitigate SEE.

PORSEL

This pin is the input for selecting the rising and falling POR (Power-On-Reset) thresholds. For

a nominal 5V supply, connect this pin to DVDD. For a nominal 3.3V supply, connect this pin to

DGND. For nominal supply voltages between 5V and 3.3V, connect this pin to DGND.

FN6947.0

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ISL70001SRH

Typical Application Schematic

LX1

LX2

LX3

LX4

LX5

LX6

PVIN1

PVIN2

PVIN3

PVIN4

PVIN5

PVIN6

5V

100µF

1µF

1µH

1.8V

6A

470µF

20V

3A

4.7nF

1kΩ

1

DVDD

FB

1µF

ISL70001SRH

0V TO 5.5V

499Ω

DGND

1

PGOOD

AVDD

10nF

1µF

VSENSE

SYNC

REF

AGND

EN

220nF

10nF

M/S

PORSEL

TDI

SS

TDO

ZAP

100nF

FIGURE 1. 5V INPUT SUPPLY VOLTAGE WITH MASTER MODE SYNCHRONIZATION

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December 15, 2009

5

ISL70001SRH

Typical Application Schematic(Continued)

LX1

LX2

LX3

LX4

LX5

LX6

PVIN1

3.3V

PVIN2

100µF

1µF

PVIN3

PVIN4

PVIN5

PVIN6

1µF

1

1µH

1.8V

6A

470µF

20V

3A

4.7nF

1kΩ

DVDD

FB

1µF

ISL70001SRH

0V TO 5.5V

499Ω

DGND

1

PGOOD

AVDD

10nF

1µF

VSENSE

SYNC

REF

AGND

EN

220nF

M/S

10nF

PORSEL

TDI

SS

TDO

ZAP

100nF

FIGURE 2. 3.3V INPUT SUPPLY VOLTAGE WITH SLAVE MODE SYNCHRONIZATION

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6

ISL70001SRH

Electrical Specifications Unless otherwise noted, V = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND

IN

= DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = V for 4.5V ≤ V ≤ 5.5V

IN

and GND for V < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to V with a 1k

I

N

I

N

resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF

capacitor; I = 0A; T = T = +25°C. (Note 3)

OUT

A

J

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Operating Supply Current

V

= 5.5V

= 3.6V

40

25

6

mA

IN

Shutdown Supply Current

= 5.5V, EN = GND

= 3.6V, EN = GND

3

OUTPUT VOLTAGE

Reference Voltage Tolerance

Output Voltage Tolerance

0.6

0

V

I

= 0.8V to 2.5V for V = 4.5V to 5.5V,

%

OUT

IN

= 0.8V to 2.5V for V = 3V to 3.6V,

IN

= 0A to 6A (Notes 4, 5)

Feedback (FB) Input Leakage Current V = 5.5V, V = 0.6V

0

µA

IN

FB

PWM CONTROL LOGIC

Oscillator Accuracy

1

MHz

ns

External Oscillator Range

Minimum LXx On Time

Minimum LXx Off Time

Minimum LXx On Time

Minimum LXx Off Time

Master/Slave (M/S) Input Voltage

V

= 5.5V, Test Mode

= 3V, Test Mode

110

40

150

50

1.3

1.2

0

IN

ns

Input High Threshold

Input Low Threshold

V

Master/Slave (M/S) Input Leakage

Current

V

= 5.5V, M/S = GND or V

IN

µA

IN

Synchronization (SYNC) Input

Voltage

Input High Threshold, M/S = GND

Input Low Threshold, M/S = GND

1.7

1.5

0

V

Synchronization (SYNC) Input

Leakage Current

V

= 5.5V, M/S = GND, SYNC = GND or V

IN

µA

IN

Synchronization (SYNC) Output

Voltage

V

- V

@ I

= -1mA

0.15

V

IN

OH

= 1mA

OL

@ I

OL

POWER BLOCKS

Upper Device r

V

= 3V, 0.4A Per Power Block, Test Mode

215

146

0

mΩ

µA

DS(ON)

IN

(Note 5)

Lower Device r

V

= 3V, 0.4A Per Power Block, Test Mode

DS(ON)

IN

(Note 5)

LXx Output Leakage

V

= 5.5V, EN = LXx = GND, Single LXx

IN

Output

V

= 5.5V, EN = GND, LXx = V , Single LXx

IN

0

µA

IN

Output

Deadtime

Efficiency

Within a Single Power Block or between Power

Blocks (Note 5)

5

ns

V

= 3.3V, V

OUT

= 1.8V, I

= 3A

90

92

%

IN

OUT

= 5V, V

OUT

= 2.5V, I

OUT

FN6947.0

December 15, 2009

7

ISL70001SRH

Electrical Specifications Unless otherwise noted, V = AVDD = DVDD = PVINx = EN = M/S = 3V or 5.5V; GND = AGND

IN

= DGND = PGNDx = TDI = TDO = ZAP = 0V; FB = 0.65V; PORSEL = V for 4.5V ≤ V ≤ 5.5V

IN

and GND for V < 4.5V, SYNC = LXx = Open Circuit; PGOOD is pulled up to V with a 1k

I

N

I

N

resistor; REF is bypassed to GND with a 220nF capacitor; SS is bypassed to GND with a 100nF

capacitor; I = 0A; T = T = +25°C. (Note 3) (Continued)

OUT

A

J

PARAMETER

POWER-ON RESET

TEST CONDITIONS

MIN

TYP

MAX

UNITS

POR Select (PORSEL)

Input High Threshold

Input Low Threshold

1.4

1.2

0

V

POR Select (PORSEL) Input Leakage

Current

V

= 5.5V, PORSEL = GND or V

IN

µA

IN

VIN POR

Rising Threshold, PORSEL = V

4.25

325

2.8

175

0.6

0

V

mV

V

IN

Hysteresis, PORSEL = V

IN

Rising Threshold, PORSEL = GND

Hysteresis, PORSEL = GND

Rising/Falling Threshold

mV

V

Enable (EN) Input Voltage

Enable (EN) Input Leakage Current

Enable (EN) Sink Current

SOFT-START

V

= 5.5V, EN = GND or V

IN

µA

IN

EN = 0.3V

11

Soft-Start Source Current

Soft-Start Discharge ON-Resistance

Soft-Start Discharge Time

POWER-GOOD SIGNAL

Rising Threshold

SS = GND

23

2.2

256

µA

Ω

Clock Cycles

V

as a % of V

, Test Mode

111

3.5

89

%

FB

IN

REF

Rising Hysteresis

, Test Mode

REF

Falling Threshold

, Test Mode

REF

%

Falling Hysteresis

, Test Mode

REF

3.5

%

Power-Good Drive

= 3V, PGOOD = 0.4V, EN = GND

= PGOOD = 5.5V

mA

µA

Power-Good Leakage

0

PROTECTION FEATURES

Undervoltage Monitor

Undervoltage Trip Threshold

Undervoltage Recovery Threshold

Overcurrent Monitor

V

= 3V, V as a % of V

, Test mode

75

88

%

IN

FB REF

= 3V, V as a % of V

IN

FB REF

Overcurrent Trip Level

LX4 Power Block, Test Mode, (Note 6)

= 3V, SS interval = 200µs, Test Mode,

1.9

0.8

A

Overcurrent or Short-Circuit

Duty-Cycle

V

%

IN

Fault interval divided by hiccup interval

NOTES:

3. Typical values shown are not guaranteed.

4. Limits do not include tolerance of external feedback resistors. The 0A to 6A output current range may be reduced by Minimum LXx

On Time and Minimum LXx Off Time specifications.

5. Limits established by characterization or analysis and are not production tested.

6. During an output short-circuit, peak current through the power block(s) can continue to build beyond the overcurrent trip level by

up to 3A. With all six power blocks connected, peak current through the power blocks and output inductor could reach (6 x 2.5A)

+ 3A = 18A. The output inductor must support this peak current without saturating.

FN6947.0

December 15, 2009

8

ISL70001SRH

pilot. If V

is low, the current level of the pilot is

OUT

Functional Description

increased and the trip off current level of the output is

increased. The increased output current raises V

until it is in agreement with the reference voltage.

The ISL70001SRH is a monolithic, fixed frequency,

current-mode synchronous buck regulator with user

configurable power blocks. Two ISL70001SRH devices

can be used to provide a total DC/DC solution for

FPGAs, CPLDs, DSPs and CPUs.

OUT

Output Voltage Selection

PVIN1

LX1

PGND1

PVIN6

LX6

PGND6

V

C

= 0.6V

REF

R

L

POWER BLOCK 1 POWER BLOCK 6

POWER BLOCK 2 POWER BLOCK 5

OUT

= 220nF

V

OUT

LXx

= 1k

= 4.7nF

T

C

OUT

PVIN2

LX2

PGND2

PVIN5

LX5

PGND5

C

R

C

T

ERROR

AMPLIFIER

FB

-

PVIN3

LX3

PGND3

PVIN4

LX4

PGND4

V

REF

R

B

+

POWER BLOCK 3 POWER BLOCK 4

FIGURE 3. POWER BLOCK DIAGRAM

C

REF

FIGURE 4. OUTPUT VOLTAGE SELECTION

The output voltage of the ISL70001SRH can be

adjusted using an external resistor divider as shown in

Power Blocks

Figure 4. R should be selected as 1kΩ to mitigate SEE.

T

The power output stage of the regulator consists of six

1A capable power blocks that are paralleled to provide

full 6A output current capability. The block diagram in

Figure 3 shows a top level view of the individual power

blocks.

R should be shunted by a 4.7nF ceramic capacitor, C ,

T

C

to mitigate SEE and to improve loop stability margins.

The REF pin should be bypassed to AGND with a 220nF

ceramic capacitor to mitigate SEE. It should be noted

that no current (sourcing or sinking) is available from

the REF pin. R can be determined from Equation 3.

The designer can configure the output voltage from

0.8V to 85% of the input voltage.

B

Each power block has a power supply input pin, PVINx,

a phase output pin, LXx, and a power supply ground

pin, PGNDx. All PVINx pins must be connected to a

common power supply rail and all PGNDx pins must be

connected to a common ground. LXx pins should be

connected to the output inductor based on the required

load current, but must include the LX4 pin. For

example, if 3A of output current is needed, any three

LXx pins can be connected to the inductor as long as

one of them is the LX4 pin. The unused LXx pins

should be left unconnected. Connecting all six LXx pins

to the output inductor provides a maximum 6A of

output current. See the “Typical Application Schematic”

on page 5 for pin connection guidance.

V

(EQ. 3)

REF

– V

REF

-------------------------------------

= R ⋅

T

R

B

V

OUT

Switching Frequency/Synchronization

The ISL70001SRH features an internal oscillator

running at a fixed frequency of 1MHz ±15% over

recommended operating conditions. The regulator can

be configured to run from the internal oscillator or can

be synchronized to another ISL70001SRH or an SEE

hardened external clock with a frequency range of

1MHz ±20%.

A scaled pilot device associated with each power block

provides current feedback. Power block 4 contains the

master pilot device and this is why it must be

connected to the output inductor.

To run the regulator from the internal oscillator,

connect the M/S pin to DVDD. In this case the output

of the internal oscillator appears on the SYNC pin. To

synchronize the regulator to the SYNC output of

another ISL70001SRH regulator or to an SEE hardened

external clock, connect the M/S pin to DGND. In this

case the SYNC pin is an input that accepts an external

synchronizing signal. When synchronizing multiple

devices, Slave regulators are synchronized 180°

out-of-phase with respect to the SYNC output of a

Master regulator or to an external clock.

Main Control Loop

During normal operation, the internal top power switch

is turned on at the beginning of each clock cycle.

Current in the output inductor ramps up until the

current comparator trips and turns off the top power

MOSFET. The bottom power MOSFET turns on and the

inductor current ramps down for the rest of the cycle.

Operation Initialization

The current comparator compares the output current

at the ripple current peak to a current pilot. The error

The ISL70001SRH initializes based on the state of the

power-on reset (POR) monitor of the PVINx inputs and

the state of the EN input. Successful initialization

prompts a soft-start interval and the regulator begins

amplifier monitors V

and compares it with an

OUT

internal reference voltage. The output voltage of the

error amplifier drives a proportional current to the

FN6947.0

December 15, 2009

9

ISL70001SRH

slowly ramping the output voltage. Once the

commanded output voltage is within the proper

window of operation, the power-good signal changes

state from low to high indicating proper regulator

operation.

The EN pin should be bypassed to the AGND pin with a

10nF ceramic capacitor to mitigate SEE.

V

I

EN

= 0.6V

R

= 11µA

V

EN

IN1

C

= 10nF

Power-On Reset

PVINx

The POR circuitry prevents the controller from

attempting to soft-start before sufficient bias is

present at the PVINx pins.

V

IN2

The POR threshold of the PVINx pins is controlled by

the PORSEL pin. For a nominal 5V supply voltage,

PORSEL should be connected to DVDD. For a nominal

3.3V supply voltage, PORSEL should be connected to

DGND. For nominal supply voltages between 5V and

3.3V, PORSEL should be connected to DGND. The POR

rising and falling thresholds are shown in the

ENABLE

COMPARATOR

R1

EN

+

C

V

R

R2

EN

-

POR

LOGIC

I

EN

“Electrical Specifications” table on page 8.

Hysteresis between the rising and falling thresholds

insures that small perturbations on PVINx seen during

turn-on/turn-off of the regulator do not cause

inadvertent turn-off/turn-on of the regulator. When the

PVINx pins are below the POR rising threshold, the

internal synchronous power MOSFET switches are

turned off and the LXx pins are held in a

FIGURE 5. ENABLE CIRCUIT

Soft-Start

Once the POR and enable circuits are satisfied, the

regulator initiates a soft-start. Figure 6 shows that the

soft-start circuit clamps the error amplifier reference

voltage to the voltage on an external soft-start

capacitor connected to the SS pin. The soft-start

high-impedance state.

Enable and Disable

After the POR input requirement is met, the

ISL70001SRH remains in shutdown until the voltage at

the enable input rises above the enable threshold. As

shown in Figure 5, the enable circuit features a

comparator type input. In addition to simple logic

on/off control, the enable circuit allows the level of an

external voltage to precisely gate the turn-on/turn-off

capacitor is charged by an internal I

current source.

SS

As the soft-start capacitor is charged, the output

voltage slowly ramps to the set point determined by

the reference voltage and the feedback network. Once

the voltage on the SS pin is equal to the internal

reference voltage, the soft-start interval is complete.

The controlled ramp of the output voltage reduces the

inrush current during start-up. The soft-start output

ramp interval is defined in Equation 6 and is adjustable

from approximately 2ms to 200ms. The value of the

of the regulator. An internal I

current sink with a

EN

typical value of 11µA is only active when the voltage

on the EN pin is below the enable threshold. The

current sink pulls the EN pin low. As V

rises, the

IN2

enable level is not set exclusively by the resistor

divider from V . With the current sink active, the

soft-start capacitor, C , should range from 8.2nF to

SS

8.2µF, inclusive. The peak inrush current can be

computed from Equation 7. The soft-start interval

should be selected long enough to insure that the peak

inrush current plus the peak output load current does

not exceed the overcurrent trip level of the regulator.

IN2

enable level is defined by Equation 4. R1 is the resistor

from the EN pin to V and R2 is the resistor from the

IN2

EN pin to the AGND pin.

R1

R2

V

-------

V

= V

⋅

1 +

+ I

⋅ R1

EN

(EQ. 4)

REF

ENABLE

R

--------------

t

= C

⋅

(EQ. 6)

SS

I

SS

Once the voltage at the EN pin reaches the enable

threshold, the I current sink turns off.

V

EN

With the part enabled and the I

OUT

---------------

I

= C

⋅

(EQ. 7)

INRUSH

OUT

t

SS

current sink off, the

EN

disable level is set by the resistor divider. The disable

level is defined by Equation 5.

The soft-start capacitor is immediately discharged by a

2.2Ω resistor whenever POR conditions are not met or

EN is pulled low. The soft-start discharge time is equal

to 256 clock cycles.

R1

(EQ. 5)

-------

= V ⋅ 1 +

R

V

DISABLE

R2

The difference between the enable and disable levels

provides adjustable hysteresis so that noise on V

IN2

does not interfere with the enabling or disabling of the

regulator.

FN6947.0

December 15, 2009

10

ISL70001SRH

Undervoltage Protection

A hysteretic comparator monitors the FB pin of the

regulator. The feedback voltage is compared to an

undervoltage threshold that is a fixed percentage of

the reference voltage. Once the comparator trips,

indicating a valid undervoltage condition, a 3-bit

undervoltage counter increments. The counter is reset

if the feedback voltage rises back above the

undervoltage threshold plus a specified amount of

hysteresis outlined in the “Electrical Specifications”

table on page 8. If the 3-bit counter overflows, the

undervoltage protection logic shuts down the regulator.

V

I

R

= 0.6V

REF

SS

D

V

= 23µA

OUT

= 2.2Ω

R

T

FB

R

B

ERROR

AMPLIFIER

SS

-

C

SS

+

REF

V

REF

PWM

LOGIC

C

R

REF

D

I

SS

After the regulator shuts down, it enters a delay

interval, equivalent to the soft-start interval, allowing

the device to cool. The undervoltage counter is reset

entering the delay interval. The protection logic

initiates a normal soft-start once the delay interval

ends. If the output successfully soft-starts, the power-

good signal goes high and normal operation continues.

If undervoltage conditions continue to exist during the

soft-start interval, the undervoltage counter must

overflow before the regulator shuts down again. This

hiccup mode continues indefinitely until the output

soft-starts successfully.

FIGURE 6. SOFT-START CIRCUIT

Power-Good

The power-good (PGOOD) pin is an open-drain logic

output which indicates when the output voltage of the

regulator is within regulation limits. The power-good

pin pulls low during shutdown and remains low when

the controller is enabled. After a successful soft-start,

the PGOOD pin releases and the voltage rises with an

external pull-up resistor. The power-good signal

transitions low immediately when the EN pin is pulled

low.

Overcurrent Protection

A pilot device integrated into the PMOS transistor of

Power Block 4 samples current each cycle. This current

feedback is scaled and compared to an overcurrent

threshold based on the number of Power Blocks

connected. Each additional Power Block connected

beyond Power Block 4 increases the overcurrent limit by

2A. For example, if three Power Blocks are connected,

the typical current limit threshold would be 3 x 2A = 6A.

The power-good circuitry monitors the FB pin and

compares it to the rising and falling thresholds shown

in the “Electrical Specifications” table on page 8. If the

feedback voltage exceeds the typical rising limit of

111% of the reference voltage, the PGOOD pin pulls

low. The PGOOD pin continues to pull low until the

feedback voltage falls to a typical of 107.5% of the

reference voltage. If the feedback voltage drops below

a typical of 89% of the reference voltage, the PGOOD

pin pulls low. The PGOOD pin continues to pull low until

the feedback voltage rises to a typical 92.5% of the

reference voltage. The PGOOD pin then releases and

signals the return of the output voltage within the

power-good window.

If the sampled current exceeds the overcurrent

threshold, a 3-bit overcurrent counter increments by

one LSB. If the sampled current falls below the

threshold before the counter overflows, the counter is

reset. Once the overcurrent counter reaches 111, the

regulator shuts down.

After the regulator shuts down, it enters a delay

interval, equivalent to the soft-start interval, allowing

the device to cool. The overcurrent counter is reset

entering the delay interval. The protection logic

initiates a normal soft-start once the delay interval

ends. If the output successfully soft-starts, the power-

good signal goes high and normal operation continues.

If overcurrent conditions continue to exist during the

soft-start interval, the overcurrent counter must

overflow before the regulator shut downs the output

again. This hiccup mode continues indefinitely until the

output soft-starts successfully.

The PGOOD pin can be pulled up to any voltage from

0V to 5.5V, independent of the supply voltage. The

pull-up resistor should have a nominal value from 1kΩ

to 10kΩ. The PGOOD pin should be bypassed to DGND

with a 10nF ceramic capacitor to mitigate SEE.

Fault Monitoring and Protection

The ISL70001SRH actively monitors output voltage

and current to detect fault conditions. Fault conditions

trigger protective measures to prevent damage to the

regulator and external load device.

Note: It is recommended that a Schottky diode of

appropriate rating be added from the LXx pins to the

PGNDx pins to prevent severe negative ringing that

can disturb the overcurrent counter.

FN6947.0

December 15, 2009

11

ISL70001SRH

and source the inductor AC ripple current, a voltage,

, develops across the bulk capacitor

according to Equation 9.

Component Selection Guide

V

P-P(MAX)

This design guide is intended to provide a high-level

explanation of the steps necessary to create a power

converter. It is assumed the reader is familiar with

many of the basic skills and techniques referenced

below. In addition to this guide, Intersil provides a

complete evaluation board that includes schematic,

BOM, and an example PCB layout.

(V – V

)V

OUT OUT

× f × V

s IN

IN

----------------------------------------------------

= ESR ×

V

(EQ. 9)

P-P(MAX)

L

OUT

Another consideration in selecting the output

capacitors is loop stability. The total output

capacitance sets the dominant pole of the PWM.

Because the ISL70001SRH uses integrated

Output Filter Design

The output inductor and the output capacitor bank

together form a low-pass filter responsible for

smoothing the pulsating voltage at the phase node.

The filter must also provide the transient energy until

the regulator can respond. Since the filter has low

bandwidth relative to the switching frequency, it limits

the system transient response. The output capacitors

must supply or sink current while the current in the

output inductor increases or decreases to meet the

load demand.

compensation techniques, it necessary to restrict the

output capacitance in order to optimize loop stability.

The recommended load capacitance can be estimated

using Equation 10.

1.8V

---------------

C

= 75μF × NumberofLXxPinsConnected ×

OUT

V

OUT

(EQ. 10)

OUTPUT INDUCTOR SELECTION

Once the output capacitors are selected, the maximum

allowable ripple voltage, V , determines the

OUTPUT CAPACITOR SELECTION

P-P(MAX)

lower limit on the inductance as shown in Equation 11.

The critical load parameters in choosing the output

capacitors are the maximum size of the load step

(V – V

)V

OUT OUT

IN

------------------------------------------------------

L

≥ ESR ×

(EQ. 11)

(ΔI

), the load-current slew rate (di/dt), and the

STEP

OUT

f × V × V

P-P(MAX)

s

IN

maximum allowable output voltage deviation under

transient loading (ΔV ). Capacitors are characterized

MAX

according to their capacitance, ESR (Equivalent Series

Since the output capacitors are supplying a decreasing

portion of the load current while the regulator recovers

from the transient, the capacitor voltage becomes

slightly depleted. The output inductor must be capable

of assuming the entire load current before the output

Resistance) and ESL (Equivalent Series Inductance).

At the beginning of a load transient, the output

capacitors supply all of the transient current. The output

voltage will initially deviate by an amount approximated

by the voltage drop across the ESL. As the load current

increases, the voltage drop across the ESR increases

linearly until the load current reaches its final value.

Neglecting the contribution of inductor current and

regulator response, the output voltage initially deviates

by an amount shown in Equation 8.

voltage decreases more than ΔV

upper limit on inductance.

. This places an

MAX

Equation 12 gives the upper limit on output inductance

for the case when the trailing edge of the current

transient causes the greater output voltage deviation

than the leading edge. Equation 13 addresses the

leading edge. Normally, the trailing edge dictates the

inductance selection because duty cycles are usually

<50%. Nevertheless, both inequalities should be

evaluated, and inductance should be governed based

di

dt

----

ΔV

≈

ESL ×

+ [ESR × ΔI

]

STEP

(EQ. 8)

MAX

The filter capacitors selected must have sufficiently low

ESL and ESR such that the total output voltage

deviation is less than the maximum allowable ripple.

on the lower of the two results. In each equation, L

OUT

is the output inductance, C

capacitance and ΔI

L(P-P)

is the total output

is the peak to peak ripple

OUT

current in the output inductor.

Most capacitor solutions rely on a mixture of high

frequency capacitors with relatively low capacitance in

combination with bulk capacitors having high

capacitance but larger ESR. Minimizing the ESL of the

high-frequency capacitors allows them to support the

output voltage as the current increases. Minimizing the

ESR of the bulk capacitors allows them to supply the

increased current with less output voltage deviation.

2 ⋅ C

⋅ V

OUT

(EQ. 12)

L

≤ -------------------------------------------- ΔV

– (ΔI

⋅ ESR)

L(P-P)

OUT

MAX

2

(ΔI

)

STEP

2 ⋅ C

OUT

⎛

⎝

⎞

≤ ---------------------------- ΔV

– (ΔI

⋅ ESR)

V

– V

MAX

L(P-P)

IN

OUT

2

⎠

(ΔI

)

STEP

(EQ. 13)

The other concern when selecting an output inductor is

to insure there is adequate slope compensation when

the regulator is operated above 50% duty cycle. Since

the internal slope compensation is fixed, output

Ceramic capacitors with X7R dielectric are

recommended. Alternately, a combination of low ESR

solid tantalum capacitors and ceramic capacitors with

X7R dielectric may be used.

The ESR of the bulk capacitors is responsible for most

of the output voltage ripple. As the bulk capacitors sink

FN6947.0

December 15, 2009

12

ISL70001SRH

inductance should satisfy Equation 14 to insure this

requirement is met.

PCB Component Placement

Components should be placed as close as possible to

the IC to minimize stray inductance and resistance.

Prioritize the placement of bypass capacitors on the

pins of the IC in the order shown: REF, SS, AVDD,

DVDD, PVINx (high frequency capacitors), EN, PGOOD,

PVINx (bulk capacitors).

4.32μH

---------------------------------------------------------------------------------------

≥

(EQ. 14)

L

OUT

NumberofLXxPinsConnected

Input Capacitor Selection

Input capacitors are responsible for sourcing the AC

component of the input current flowing into the

switching power devices. Their RMS current capacity

must be sufficient to handle the AC component of the

current drawn by the switching power devices which is

related to duty cycle. The maximum RMS current

required by the regulator is closely approximated by

Equation 15.

Locate the output voltage resistive divider as close as

possible to the FB pin of the IC. The top leg of the

divider should connect directly to the POL (Point Of

Load) and the bottom leg of the divider should connect

directly to AGND. The junction of the resistive divider

should connect directly to the FB pin.

Locate a Schottky clamp diode as close as possible to

the LXx and PGNDx pins of the IC. A small series R-C

snubber connected from the LXx pins to the PGNDx

pins may be used to damp high frequency ringing on

the LXx pins if desired.

2

V

– V

V

⎛

⎜

⎝

⎛

⎜

⎝

⎞

⎟

⎠

⎞

2

OUT

1

12

IN

OUT

-----------------

------

--------------------------------- -----------------

I

=

×

I

+

×

⎟

RMS

OUT

V

L

× f

⎠

MAX

IN

OUT

s

(EQ. 15)

The important parameters to consider when selecting

an input capacitor are the voltage rating and the RMS

ripple current rating. For reliable operation, select

capacitors with voltage ratings at least 1.5x greater

than the maximum input voltage. The capacitor RMS

ripple current rating should be higher than the largest

RMS ripple current required by the circuit.

PCB Layout

Use a small island of copper to connect the LXx pins of

the IC to the output inductor on layers 1 and 4. Void

the copper on layers 2 and 3 adjacent to the island to

minimize capacitive coupling to the power and ground

planes. Place most of the island of layer 4 to minimize

the amount of copper that must be voided from the

ground plane (layer 2).

Ceramic capacitors with X7R dielectric are

recommended. Alternately, a combination of low ESR

solid tantalum capacitors and ceramic capacitors with

X7R dielectric may be used. The ISL70001SRH

requires a minimum effective input capacitance of

100µF for stable operation.

Keep all other signal traces as short as possible.

For an example layout refer to ANxxxx.

Thermal Management

For optimum thermal performance, place a pattern of

vias on the top layer of the PCB directly underneath

the IC. Connect the vias to the ground plane on layer

2, which serves as a heatsink. To insure good thermal

contact, thermal interface material such as a Sil-Pad or

thermally conductive epoxy should be used to fill the

gap between the vias and the bottom of the IC.

PCB Design

PCB design is critical to high-frequency switching

regulator performance. Careful component placement

and trace routing are necessary to reduce voltage

spikes and minimize undesirable voltage drops.

Selection of a suitable thermal interface material is

also required for optimum heat dissipation and to

provide lead strain relief.

Lead Strain Relief

Use of a Sil-Pad or a thin layer of thermally conductive

epoxy will raise the bottom of the IC from the PCB

surface so that a slight bend can be added to the leads

of the IC for strain relief.

PCB Plane Allocation

Four layers of two ounce copper are recommended.

Layer 2 should be a dedicated ground plane with all

critical component ground connections made with vias

to this layer. Layer 3 should be a dedicated power

plane split between the input and output power rails.

Layers 1 and 4 should be used primarily for signals,

but can also provide additional power and ground

islands as required.

FN6947.0

December 15, 2009

13

ISL70001SRH

BACKSIDE FINISH

Die Characteristics

Die Dimensions

Silicon

ASSEMBLY RELATED INFORMATION

5720µm x 5830µm (225.2 mils x 229.5 mils)

Thickness: 483µm ± 25.4µm (19.0 mils ± 1 mil)

Substrate Potential

PGND

Interface Materials

GLASSIVATION

ADDITIONAL INFORMATION

Worst Case Current Density

Type: Silicon Oxide and Silicon Nitride

Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm

5

2

< 2 x 10 A/cm

TOP METALLIZATION

Transistor Count

Type: AlCu (0.5%)

Thickness: 2.7µm ±0.4µm

25030

Layout Characteristics

Step and Repeat

SUBSTRATE

Type: Silicon

Isolation: Junction

5720µm x 5830µm

Connect PGND to PGNDx

Metallization Mask Layout

ISL70001SRH

LX1

PGND1

LX2

PVIN2

PVIN3

SYNC PVIN1

PGND2

M/S

ZAP

TDI

LX3

TDO

PGND3

PGND4

PGOOD

SS

LX4

DVDD

PVIN4

PVIN5

LX5

DGND

PGND

AGND

AVDD REF

FB

EN PORSEL

PVIN6

LX6

PGND6

PGND5

FN6947.0

December 15, 2009

14

ISL70001SRH

TABLE 1. LAYOUT X-Y COORDINATES

BOND

WIRES PER

PAD

X

Y

dX

(µm)

dY

(µm)

PAD NAME

PAD NUMBER

(µm)

AVDD

REF

FB

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

1

478

865

263

135

521

135

521

135

521

135

333

135

1

3

1

2

1

1295

1751

2151

2838

3449

4060

4845

5449

4941

4137

3449

2838

2227

1578

962

263

EN

263

PORSEL

PVIN6

LX6

263

188

PGND6

PGND5

LX5

188

925

PVIN5

PVIN4

LX4

1651

2263

2874

3485

4096

4745

5559

5280

4910

4540

4170

3777

3425

2566

1538

1018

654

PGND4

PGND3

LX3

PVIN3

PVIN2

LX2

PGND2

PGND1

LX1

2

PVIN1

SYNC

M/S

3

4

544

5

226

ZAP

6

226

TDI

7

226

TDO

8

226

PGOOD

SS

9

226

10

11

12

13

14

226

DVDD

DGND

PGND

AGND

226

FN6947.0

December 15, 2009

15

ISL70001SRH

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to

web to make sure you have the latest Rev.

DATE

REVISION

CHANGE

12/15/09

FN6947.0

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The

Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell

phones, handheld products, and notebooks. Intersil's product families address power management and analog

signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device

information page on intersil.com: ISL70001SRH

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications

at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by

Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any

patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6947.0

December 15, 2009

16


型号：	ISL70001SRH
厂家：	Intersil
描述：	Radiation Hardened and SEE Hardened 6A Synchronous Buck Regulator with Integrated MOSFETs 抗辐射和SEE硬化6A同步降压型稳压器内置MOSFET 稳压器
文件：	总16页 (文件大小：284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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