ISL75051SRH [INTERSIL]
3A, Rad Hard, Positive, Ultra Low Dropout Regulator; 3A ，抗辐射，积极，超低压差稳压器
| 型号： | ISL75051SRH |
| 厂家： | 
Intersil |
| 描述： | 3A, Rad Hard, Positive, Ultra Low Dropout Regulator |
| 文件： | 总15页 (文件大小：979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3A, Rad Hard, Positive, Ultra Low Dropout Regulator
ISL75051SRH
Features
The ISL75051SRH is a radiation hardened low-voltage,
high-current, single-output LDO specified for up to 3.0A of
continuous output current. These devices operate over an input
voltage range of 2.2V to 6.0V and are capable of providing
output voltages of 0.8V to 5.0V adjustable based on resistor
divider setting. Dropout voltages as low as 65mV can be
realized using the device.
• DLA SMD#5962-11212
• Output Current Up to 3.0A at T = 150°C
J
• Output Accuracy ±1.5% over MIL Temp Range
• Ultra Low Dropout:
- 65mV Typ Dropout at 1.0A
- 225mV Typ Dropout at 3.0A
The OCP pin allows the short circuit output current limit
threshold to be programmed by means of a resistor from the
OCP pin to GND. The OCP setting range is from 0.5A minimum
to 8.5A maximum. The resistor sets the constant current
threshold for the output under fault conditions. The thermal
shutdown disables the output if the device temperature
exceeds the specified value. It subsequently enters an ON/OFF
cycle until the fault is removed. The ENABLE feature allows the
part to be placed into a low current shutdown mode that
typically draws about 1µA. When enabled, the device operates
with a typical low ground current of 11mA, which provides for
operation with low quiescent power consumption.
• Noise of 100µV
from 300Hz to 300kHz
RMS
• SET Mitigation with No Added Filtering/Diodes
• Input Supply Range: 2.2V to 6.0V
• Fast Load Transient Response
• Shutdown Current of 1µA Typ
• Output Adjustable Using External Resistors
• PSRR 66dB Typ @ 1kHz
• Enable and PGood Feature
• Programmable Soft-start/Inrush Current Limiting
• Adjustable Overcurrent Limit from 0.5A to 8.5A
• Over-temperature Shutdown
The device is optimized for fast transient response and single
event effects. This reduces the magnitude of SET seen on the
output. Additional protection diodes and filters are not needed.
The device is stable with tantalum capacitors as low as 47µF
and provides excellent regulation all the way from no load to
full load. Programmable soft-start allows the user to program
the inrush current by means of the decoupling capacitor value
used on the BYP pin.
• Stable with 47µF Min Tantalum Capacitor
• 18 Ld Ceramic Flatpack Package
• Radiation Environment
- High Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)
2
•
- SET/SEL/SEB . . . . . . . . . . . . . . . . . . . . . . . .86 MeV cm /mg
Applications
• LDO Regulator for Space Application
• DSP, FPGA and µP Core Power Supplies
• Post-regulation of Switched Mode Power Supplies
• Down-hole Drilling
0.30
EN
EN
BYP
ADJ
+150°C
ROCP
0.25
0.1uF
OCP
+125°C
ISL75051SRH
VIN
VOUT
0.20
VIN
PG
VOUT
GND
R1
0.15
+25°C
220uF
0.1uF
0.1uF 220uF
2.67k
VIN
0.10
0.05
0.00
4.7n
PG
R2
0.00
0.50
1.00
1.50
2.00
(A)
2.50
3.00
3.50
100pF
I
OUT
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. DROPOUT vs I
OUT
November 4, 2011
FN7610.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL75051SRH
Block Diagram
VIN
CURRENT
LIMIT ADJ
OCP
520MV
POWER
PMOS
REFERENCE
BIAS
BYPASS
ENABLE
VOUT
CURRENT
LIMIT
THERMAL
SHUTDOWN
LEVEL
SHIFT
VADJ
PGOOD
DELAY
450mV
GND
Typical Applications
EN
EN
OCP
VIN
VIN
VIN
10
11
BYP
9
8
511
ADJ
0.2uF
12
13
14
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
GND
7
6
5
4
3
ISL75051SRH
VIN
VIN
VIN
PG
15
16
17
VIN
VOUT
2
1
18
220uF
0.1uF
0.1uF 220uF
2.67k
4.7n
4.32k
2.26k
VIN
100pF
5.49k
PG
FN7610.1
November 4, 2011
2
ISL75051SRH
Pin Configuration
ISL75051SRH
(18LD CDFP)
TOP VIEW
GND
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VADJ
BYP
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
PG
VIN
VIN
VIN
VIN
VIN
VIN
OCP
EN
GND
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
12, 13, 14
15, 16, 17
V
Input supply pins
IN
18
1
PG
V
in regulation signal. Logic low defines when V
OUT
is not in regulation. Must be grounded if not used.
OUT
GND
GND pin
2, 3, 4
5, 6, 7
V
Output voltage pins
OUT
8
9
VADJ
BYP
EN
VADJ pin allows V to be programmed with an external resistor divider.
OUT
To filter the internal reference, connect a 0.1µF capacitor from BYP pin to GND.
V independent chip enable. TTL and CMOS compatible.
IN
10
11
OCP
GND
Allows current limit to be programmed with an external resistor.
The top lid is connected to GND pin of the package.
Top Lid
FN7610.1
November 4, 2011
3
ISL75051SRH
Ordering Information
ORDERING
NUMBER
PART NUMBER
(NOTES 1, 2)
TEMP
RANGE (°C)
PACKAGE
18 Ld CDFP
PKG DWG. #
K18.D
5962R1121201VXC
5962R1121201QXC
5962R1121201V9A
ISL75051SRHX/SAMPLE
ISL75051SRHF/PROTO
ISL75051SRHEVAL1Z
NOTES:
ISL75051SRHVF
ISL75051SRHQF
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
18 Ld CDFP
Die
K18.D
ISL75051SRHVX
ISL75051SRHX/SAMPLE
ISL75051SRHF/PROTO
Evaluation Board
Die Sample
18 Ld CDFP
K18.D
1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISL75051SRH. For more information on MSL please see
Tech Brief TB363.
FN7610.1
November 4, 2011
4
ISL75051SRH
Absolute Maximum Ratings
Thermal Information
V
V
Relative to GND (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7V
Relative to GND (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.7V
Thermal Resistance (Typical)
18 Ld CDFP Package (Notes 5, 6) . . . . . . .
θ
JA (°C/W)
28
θ
JC (°C/W)
IN
OUT
4
PG, EN, OCP/ADJ Relative to GND (Note 3). . . . . . . . . . . . . -0.3 to +6.7VDC
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature (T ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
J
Radiation Information
Max Total Dose
Recommended Operating Conditions (Note 4)
Ambient Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Junction Temperature (T ) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
J
(Dose Rate = 50 - 300radSi/s . . . . . . . . . . . . . . . . . . . . . . . 100 krad (Si)
A
2
SET (V
OUT
< ±5% During Events (Note 7). . . . . . . . . . . . . . 86MeV•cm /mg
2
SEL/B (No Latchup/Burnout. . . . . . . . . . . . . . . . . . . . . . . . 86MeV•cm /mg
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2V to 6.0V
IN
V
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8V to 5.0V
The output capacitance used for SEE testing is 220µF for C and C
200nF for BYPASS
,
OUT
IN
OUT
PG, EN, OCP/ADJ relative to GND . . . . . . . . . . . . . . . . . . . . . . . 0V to +6.0V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions
define limits where specifications are guaranteed.
4. Refer to “Thermal Guidelines” on page 12.
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379
6. For θ , the “case temp” location is the center of the package underside.
JC
2
7. The device can work down to V
= 0.8V; however, the SET performance of < ±5% at LET = 86MeV.cm /mg is guaranteed at V = >1.5V only. SET
OUT
OUT
tests performed with 220µF 10V 25mΩ and 0.1µF CDR04 capacitor on the input and output.
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
= V + 0.4V, V = 1.8V, C = C = 220µF 25mΩ and 0.1µF X7R, T = +25°C, I = 0A. Applications must follow thermal guidelines of
V
IN
OUT OUT IN
OUT
J
L
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
T = T defines guaranteed limits.
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
0.2
(Note 8)
UNITS
%
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
V
Resistor adjust to 0.52V, 1.5V and 1.8V
OUT
OUT
2.2V < V < 3.6V; 0A < I
IN
< 3.0A
-1.5
1.5
LOAD
V
Resistor adjust to 5.0V
OUT
V
+ 0.4V < V < 6.0V; 0A < I
IN
< 3.0A
LOAD
-1.5
0.2
520
520
1.13
1.5
%
OUT
Feedback Pin
V
2.2V < V < 6.0V; I
= 0A
= 0A
514.8
525.2
mV
mV
mV
ADJ
IN
2.2V < V < 6.0V; I
LOAD
LOAD
BYP Pin
V
BYP
IN
DC Input Line Regulation
2.2V < V < 3.6V, V
IN
= 1.5V, +25°C & -55°C
3.5
OUT
(Note 9)
DC Input Line Regulation
DC Input Line Regulation
2.2V < V < 3.6V, V
IN
= 1.5V, +125°C (Note 9)
= 1.8V, +25°C & -55°C
1.13
1.62
8.0
3.5
mV
mV
OUT
2.2V < V < 3.6V, V
IN
OUT
(Note 9)
DC Input Line Regulation
DC Input Line Regulation
DC Output Load Regulation
2.2V < V < 3.6V, V
IN
= 1.8V, +125°C (Note 9)
1.62
12.50
-0.8
10.5
20.0
-0.1
mV
mV
mV
OUT
V
+ 0.4V < V < 6.0V, V = 5.0V (Note 9)
IN OUT
OUT
V
= 1.5V; 0A < I < 3.0A, V = V
+ 0.4V
+ 0.4V
+ 0.4V
-4.0
-4.0
OUT
LOAD
LOAD
LOAD
IN
OUT
OUT
OUT
(Note 9)
DC Output Load Regulation
DC Output Load Regulation
V
= 1.8V; 0A < I
< 3.0A, V = V
IN
-1.2
-6.0
-0.05
-0.05
mV
mV
OUT
(Note 9)
V
= 5.0V; 0A < I
< 3.0A, V = V
IN
-15.0
OUT
(Note 9)
FN7610.1
November 4, 2011
5
ISL75051SRH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
V
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C = C
IN
= 220µF 25mΩ and 0.1µF X7R, T = +25°C, I = 0A. Applications must follow thermal guidelines of
OUT J L
IN
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
T = T defines guaranteed limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
µA
mA
mA
mA
mA
µA
mV
mV
mV
A
Feedback Input Current
Ground Pin Current
V
= 0.5V
1
ADJ
I
I
I
I
V
V
V
V
= 1.5V; I
= 5.0V; I
= 1.5V; I
= 5.0V; I
= 0A, V = 2.2V
IN
11
16
12
Q
Q
Q
Q
OUT
OUT
OUT
OUT
LOAD
LOAD
LOAD
LOAD
Ground Pin Current
= 0A, V = 6.0V
IN
18
Ground Pin Current
= 3.0A, V = 2.2V
IN
11
13
Ground Pin Current
= 3.0A, V = 6.0V
IN
16
18
Ground Pin Current in Shutdown
Dropout Voltage
I
ENABLE Pin = 0V, V = 6.0V
IN
1
10
SHDN
V
V
V
I
I
I
= 1.0A, V
= 2.0A, V
= 3.0A, V
= 2.5V (Note 10)
= 2.5V (Note 10)
= 2.5V (Note 10)
65
100
200
300
DO
DO
DO
LOAD
LOAD
LOAD
OUT
OUT
OUT
Dropout Voltage
140
225
1.1
1.2
5.7
6.2
175
25
Dropout Voltage
Output Short Circuit Current
Output Short Circuit Current
Output Short Circuit Current
Output Short Circuit Current
Thermal Shutdown Temperature
ISCL
ISCL
V
V
V
V
V
V
= 0V, V = 2.2V, R
IN
= 5.11k
= 5.11k
= 511Ω
= 511Ω
OUT
OUT
OUT
OUT
OUT
OUT
SET
SET
SET
SET
= 0V, V = 6.0V, R
IN
A
ISCH
ISCH
TSD
= 0V, V = 2.2V, R
IN
A
= 0V, V = 6.0V, R
IN
A
+ 0.4V < V < 6.0V
IN
°C
°C
Thermal Shutdown Hysteresis
(Rising Threshold)
TSDn
+ 0.4V < V < 6.0V
IN
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
PSRR
V
= 300mV, f = 1kHz, I
= 1.8V
= 3A; V = 2.5V,
LOAD IN
42
66
30
dB
dB
P-P
V
OUT
Input Supply Ripple Rejection
V
= 300mV, f = 100kHz, I
= 1.8V
= 3A; V = 2.5V,
LOAD IN
P-P
V
V
V
OUT
Phase Margin
PM
GM
= 1.8V, C = 220µF Tantalum
70
16
dB
dB
OUT
OUT
L
Gain Margin
= 1.8V, C = 220µF Tantalum
L
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz, BYPASS
100
µV
RMS
LOAD
to GND capacitor = 0.2µF
DEVICE START-UP CHARACTERISTICS: ENABLE PIN
Rising Threshold
2.2V < V < 6.0V
IN
0.6
0.9
0.7
1.2
0.9
1
V
V
Falling Threshold
2.2V < V < 6.0V
IN
0.47
Enable Pin Leakage Current
Enable Pin Propagation Delay
Enable Pin Turn-on Delay
V
V
V
= 6.0V, EN = 6.0V
= 2.2V, EN rise to I
µA
µs
IN
IN
IN
rise
225
300
6
450
OUT
= 2.2V, V
OUT
= 1.8V, I
= 1A, C
= 220µF,
= 47µF,
ms
LOAD
OUT
C
= 0.2µF
BYP
Enable Pin Turn-on Delay
V
C
= 2.2V, V
=1.8V, I
= 1A, C
OUT
50
µs
IN
OUT
= 0.2µF
LOAD
BYP
Hysteresis
Must be independent of V ; 2.2V < V < 6.0V
90
200
318
mV
IN IN
DEVICE START-UP CHARACTERISTICS: PG PIN
V
V
V
Error Flag Rising Threshold
Error Flag Falling Threshold
Error Flag Hysteresis
2.2V < VIN < 6.0V
2.2V < VIN < 6.0V
2.2V < VIN < 6.0V
85
82
90
88
96
93
%
%
OUT
OUT
OUT
2.5
3.2
4.0
%V
OUT
FN7610.1
November 4, 2011
6
ISL75051SRH
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the following specified conditions:
V
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C = C
IN
= 220µF 25mΩ and 0.1µF X7R, T = +25°C, I = 0A. Applications must follow thermal guidelines of
OUT J L
IN
the package to determine worst-case junction temperature. Please refer to “Applications Information” on page 11 of the datasheet and
Tech Brief TB379. Boldface limits apply over the operating temperature range, -55°C to +125°C. Pulse load techniques used by ATE to ensure
T = T defines guaranteed limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
35
(Note 8)
UNITS
mV
Error Flag Low Voltage
Error Flag Low Voltage
Error Flag Leakage Current
NOTES:
I
I
= 1mA
= 6mA
100
400
1
SINK
185
0.01
mV
SINK
V
= 6.0V, PG = 6.0V
µA
IN
8. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Line and Load Regulation done under pulsed condition for T<10ms.
10. Dropout is defined as the difference between the supply V and V
IN
when the supply produces a 2% drop in V
from its nominal value. Data
OUT
OUT,
measured within a 3ms period.
Typical Operating Performance
0.522
1.528
+25°C, V
(mV)
OUT
+25°C, V
-58°C, V
(mV)
(mV)
1.526
1.524
1.522
1.520
1.518
1.516
1.514
1.512
1.510
ADJ
0.521
0.520
0.519
0.518
0.517
0.516
0.515
-58°C, V
(mV)
OUT
ADJ
+128°C, V
(mV)
+128°C, V
(mV)
3.0
OUT
ADJ
V
V
= 2.5V
= 1.5V
V
V
= 2.5V
= 1.5V
IN
IN
OUT
0.5
OUT
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.5
0.0
1.0
1.5
2.0
(A)
2.5
3.0
3.5
I
I
OUT
OUT
FIGURE 3. LOAD REGULATION, V
vs I
FIGURE 4. LOAD REGULATION, V
vs I
ADJ OUT
OUT
OUT
0.5215
2.525
0.5210
0.5205
0.5200
0.5195
0.5190
0.5185
0.5180
0.5175
0.5170
0.5165
0.5160
+25°C, V
-58°C, V
(mV)
(mV)
ADJ
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
-58°C, V
+25°C, V
(mV)
OUT
ADJ
(mV)
OUT
+128°C, V
ADJ
(mV)
3.0
+128°C, V
(mV)
OUT
V
V
= 3.3V
= 2.5V
IN
OUT
V
V
= 3.3V
= 2.5V
IN
OUT
0.0
0.5
1.0
1.5
I
2.0
(A)
2.5
3.0
3.5
0.0
0.5
1.0
1.5
I
2.0
(A)
2.5
3.5
OUT
OUT
FIGURE 5. LOAD REGULATION, V
vs I
FIGURE 6. LOAD REGULATION, V
vs I
ADJ OUT
OUT
OUT
FN7610.1
November 4, 2011
7
ISL75051SRH
Typical Operating Performance (Continued)
0.5215
0.5210
0.5205
0.5200
0.5195
0.5190
0.5185
0.5180
0.5175
0.5170
0.5165
0.5160
4.090
4.085
4.080
4.075
4.070
4.065
4.060
+25°C, V
-58°C, V
(mV)
(mV)
ADJ
+128°C, V
OUT
(mV)
ADJ
+25°C, V
(mV)
+128°C, V
(mV)
OUT
ADJ
-58°C, V
1.5
(mV)
OUT
2.0
V
V
= 5V
V
V
= 5V
IN
OUT
0.5
IN
OUT
= 4V
= 4V
0.0
1.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
(A)
2.5
3.0
3.5
I
(A)
I
OUT
OUT
FIGURE 7. LOAD REGULATION, V
vs I
FIGURE 8. LOAD REGULATION, V
vs I
ADJ OUT
OUT
OUT
0.525
8
R
= 0.511k
OCP
7
6
5
4
3
2
1
0
0.523
0.521
0.519
0.517
0.515
R
R
= 0.681k
= 0.75k
OCP
+25°C, V
(mV)
ADJ
OCP
R
R
= 1.00k
= 2.00k
OCP
R
= 1.47k
OCP
OCP
-58°C, V
(mV)
ADJ
+128°C, V
(mV)
ADJ
R
= 2.61k
R
= 3.83
R
= 5.11k
OCP
OCP
OCP
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
(V)
V
(V)
V
IN
IN
FIGURE 9. V vs V
IN ADJ
OVER TEMPERATURE
FIGURE 10. R
vs OCP AT +25°C, V
= 1.5V
OCP
OUT
8
7
6
5
4
3
2
1
0
8
R
R
= 0.511k
= 0.681k
R
R
= 0.511k
OCP
OCP
7
6
5
4
3
2
1
0
= 0.681k
= 0.75k
= 1.47k
OCP
OCP
OCP
OCP
R
R
R
R
= 1.00k
= 2.00k
R
R
= 1.00k
= 2.00k
R
R
= 0.75k
= 1.47k
OCP
OCP
OCP
OCP
OCP
OCP
R
= 2.61k
R
= 3.83
R
= 5.11k
R = 3.83
OCP
R
= 2.61k
R
= 5.11k
OCP
OCP
OCP
OCP
OCP
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
V
(V)
V
IN
(V)
IN
FIGURE 11. R
vs OCP AT +128°C, V
= 1.5V
FIGURE 12. R
vs OCP AT -58°C, V
= 1.5V
OUT
OCP
OUT
OCP
FN7610.1
November 4, 2011
8
ISL75051SRH
Typical Operating Performance (Continued)
FIGURE 13. TRANSIENT LOAD RESPONSE, V = 3.3V,
IN
FIGURE 14. TRANSIENT LOAD RESPONSE, V = 3.3V,
IN
V
= 2.5V, C
= 47µF, 35mΩ
V
= 2.5V, C
= 220µF, 25mΩ
OUT
OUT
OUT
OUT
FIGURE 15. POWER-ON AND POWER-OFF, EN = 0 TO 1,
FIGURE 16. POWER-ON AND POWER-OFF, EN = 0 TO 1,
+25°C, V = 6V, V
= 0.8V, I
= 0.5A, PGOOD
+25°C, V = 2.2V, V
= 0.8V, I
= 0.5A,
IN
OUT
OUT
IN
OUT
OUT
TURN-ON
PGOOD TURN-ON
FIGURE 17. POWER-ON AND POWER-OFF, EN = 1 TO 0,
FIGURE 18. POWER-ON AND POWER-OFF, EN = 1 TO 0,
+25°C, V = 6V, V
= 0.8V, I
= 0.5A, PGOOD
+25°C, V = 2.2V, V
= 0.8V, I
= 0.5A,
IN
OUT
OUT
IN
OUT
OUT
TURN-OFF
PGOOD TURN-OFF
FN7610.1
November 4, 2011
9
ISL75051SRH
Typical Operating Performance (Continued)
140
120
100
80
>
60
40
20
0
0
50k
100k
150k
200k
250k
300k
FREQUENCY (Hz)
FIGURE 19. NOISE (µV/√Hz O.5)
FIGURE 20. PSRR
FN7610.1
November 4, 2011
10
ISL75051SRH
TABLE 2. TYPICAL GM/PM WITH VARIOUS CAPACITORS
Applications Information
Input Voltage Requirements
CAPACITANCE
ESR
GAIN MARGIN PHASE MARGIN
(µF)
(mΩ)
(dB)
14
16
19
16
10
(°)
55
57
51
69
62
This RH LDO will work from a V in the range of 2.2V to 6.0V. The
IN
47
35
25
6
input supply can have a tolerance of as much as ±10% for
conditions noted in the “Electrical Specifications” table starting
on page 5. Minimum guaranteed input voltage is 2.2V. However,
100
220
220
100
due to the nature of an LDO, V must be some margin higher
IN
25
100
than the output voltage, plus dropout at the maximum rated
current of the application, if active filtering (PSRR) is expected
from V to V . The dropout spec of this family of LDOs has
IN OUT
been generously specified to allow applications to design for
efficient operation.
Type numbers of KEMET capacitors used in the device are shown
in Table 3.
TABLE 3. KEMET CAPACITORS USED IN DEVICE
Adjustable Output Voltage
KEMET TYPE NUMBER
T525D476M016ATE035
T525D107M010ATE025
T530D227M010ATE006
T525D227M010ATE025
T495X107K016ATE100
CAPACITOR DETAILS
47µF, 10V, 35mΩ
100µF, 10V, 25mΩ
220µF, 10V, 6mΩ
220µF, 10V, 25mΩ
100µF, 16V, 100mΩ
The output voltage of the RH LDO can be set to any user
programmable level between 0.8V to 5.0V. This is achieved with
a resistor divider connected between the OUT, ADJ and GND pins.
With the internal reference at 0.52V, the divider ratio should be
fixed such that when the desired VOUT level is reached, the
voltage presented to the ADJ pin is 0.52V. Resistor values for
typical voltages are shown in Table 1.
TABLE 1. RESISTOR VALUES FOR TYPICAL VOLTAGES
V
R
R
OUT
TOP
BOTTOM
4.32k
A typical gain phase plot measured on the ISL75051SRHEVAL1Z
evaluation board for V = 3.3V, V = 1.8V and I = 3A with a
220µF, 10V, 25mΩ capacitor is shown in Figure 21 and is
0.8V
1.5V
1.8V
2.5V
4.0V
5.0V
7.87k
2.26k
1.74k
1.13k
634
IN OUT OUT
4.32k
4.32k
4.32k
4.32k
4.32k
measured at GM = 16.3dB and PM = 69.16°.
60
50
40
180
150
120
90
30
PHASE
20
60
499
10
0
30
0
GAIN
-10
-20
-30
-40
-50
-60
3.3V
-30
-60
-90
-120
-150
-180
Input and Output Capacitor Selection
1.8V
RH operation requires the use of a combination of tantalum and
ceramic capacitors to achieve a good volume-to-capacitance
ratio. The recommended combination is a 220µF, 25mΩ 10V
DSSC 04051-032 rated tantalum capacitor in parallel with a
0.1µF MIL-PRF-49470 CDR04 ceramic capacitor, to be
3.0A
1x220µF
T525D
500
5k
50k
500k
5M
FREQUENCY (Hz)
connected between V to GND pins and V
to GND pins of the
IN OUT
FIGURE 21. TYPICAL GAIN PHASE PLOT
LDO, with PCB traces no longer than 0.5cm.
The stability of the device depends on the capacitance and ESR
of the output capacitor. The usable ESR range for the device is
6mΩ to 100mΩ. At the lower limit of ESR = 6mΩ, the phase
margin is about 51°C. On the high side, an ESR of 100mΩ is
found to limit the gain margin at around 10dB. The typical
GM/PM seen with capacitors are shown in Table 2.
Enable
The device can be enabled by applying a logic high on the EN pin.
The enable threshold is typically 0.9V. A soft-start cycle is
initiated when the device is enabled using this pin. Taking this pin
to logic low disables the device.
EN can be driven from either an open drain or a totem pole logic
drive between EN pin and GND. Assuming an open drain
configuration, M1 will actively pull down the EN line, as shown in
Figure 22, and thereby discharge the input capacitance, shutting
off the device immediately.
FN7610.1
November 4, 2011
11
ISL75051SRH
Current Limit Protection
VIN
The RH LDO incorporates protection against overcurrent due to
any short or overload condition applied to the output pin. The
current limit circuit becomes a constant current source when the
output current exceeds the current limit threshold, which can be
adjusted by means of a resistor connected between the OCP pin
R1
10k
INT EN GATE
EN PIN
INT EN BUS
and GND. If the short or overload condition is removed from V
,
OUT
then the output returns to normal voltage mode regulation. OCP
can be calculated with Equation 2:
M1
EN
(EQ. 2)
OCP = 9.5 • EXP(–0.6 • (ROCP ⁄ (1 + 0.1ROCP)))
0
where OCP = Overcurrent Threshold in amps, and ROCP = OCP
resistor in kΩ.
FIGURE 22. ENABLE
Power Good
In the event of an overload condition based on the set OCP limit,
the die temperature may exceed the internal over-temperature
limit, and the LDO begins to cycle on and off due to the fault
condition (Figure 24). However, thermal cycling may never occur
if the heatsink used for the package can keep the die
The Power-Good pin is asserted high when the voltage on the ADJ
pin crosses the rising threshold of 0.9 x V typ. On the falling
ADJ
threshold, Power-Good is asserted low when the voltage on the
ADJ pin crosses the falling threshold of 0.88 x V . The
power-good output is an open-drain output rated for a continuous
sink current of 1mA.
ADJ
temperature below the limits specified for thermal shutdown.
8
7
6
5
4
Soft-start
Soft-start is achieved by means of the charging time constant of
the BYP pin. The capacitor value on the pin determines the time
constant and can be calculated using Equation 1:
3
2
1
0
OCP = +25°C
T
= 0.00577xC
S
(EQ. 1)
S
where T = soft-start time in ms, and C = BYPASS capacitor in
nF.
S
S
0
1
2
3
4
5
6
The BYPASS capacitor, C1, charges with a 90µA source current
and provides an EA reference, -IN, with an SS ramp. V , in turn,
ROCP (kΩ)
OUT
follows this ramp. The ramp rate can be calculated based on the
C1 value. For conditions in which C1 is opened, or for small
values of C1, the ramp is provided by C2 = 50pF, with a source of
0.5µA. Connecting C1 min = 0.1µF to the BYPASS pin is
recommended for normal operation.
FIGURE 24. OCP vs ROCP OVER TEMP
Thermal Guidelines
If the die temperature exceeds typically +175°C, then the LDO
output shuts down to zero until the die temperature cools to
ADJ PIN
typically +155°C. The level of power combined with the thermal
VIN
VIN
impedance of the package (θ of 4°C/W for the 18 Ld CDFP
JC
I1
90µAdc
I2
package) determines whether the junction temperature exceeds
the thermal shutdown temperature specified in the “Electrical
Specifications” table.
0.5µAdc
U1
VIN
75051_PMOS
+IN
-IN
-IN
BYPASS
EXT PIN
INT SS NODE
OUT
M1
The device should be mounted on a high effective thermal
conductivity PCB with thermal vias, per JESD51-7 and JESD51-5.
Place a silpad between package base and PCB copper plane. The
VIN and VOUT ratios should be selected to ensure that dissipation
VOUT
ISL75051SRH EA
C1
0.1µF
C2
50pF
0
0
for the selected VIN range keeps T within the recommended
J
operating level of 150°C for normal operation.
FIGURE 23. SOFT-START
FN7610.1
November 4, 2011
12
ISL75051SRH
BACKSIDE FINISH
Weight Characteristics
Weight of Packaged Device
Silicon
PROCESS
K18.D: 1.07 Grams typical with leads clipped
0.6µM BiCMOS Junction Isolated
Die Characteristics
ASSEMBLY RELATED INFORMATION
Die Dimensions
Substrate Potential
4555µm x 4555µm (179.3 mils x 179.3 mils)
Thickness: 304.8µm ± 25.4µm (12.0 mils ± 1 mil)
Unbiased
ADDITIONAL INFORMATION
Worst Case Current Density
Interface Materials
5
2
GLASSIVATION
< 2 x 10 A/cm
Type: Silicon Oxide and Silicon Nitride
Thickness: 0.3µm ± 0.03µm to 1.2µm ± 0.12µm
Transistor Count
2932
TOP METALLIZATION
Layout Characteristics
Step and Repeat
Type: AlCu (99.5%/0.5%)
Thickness: 2.7µm ±0.4µm
BACKSIDE METALLIZATION
4555µm x 4555µm
None
Metallization Mask Layout
SUBSTRATE
Type: Silicon
PAD X Y COORDINATES
PAD NAME X µm Y µm
1
GND
0
0
2
GND
-393
0
3
VOUT -711 -710
VOUT -711 -1858
VOUT -711 -2964
ADJ -1680 -3070
BYP -1621 -3879
4
5
6
7
8
EN
2164 -3879
9
OCP 2222 -3131
10
11
12
13
VIN
VIN
VIN
PG
1078 -2965
1078 -1853
1078 -711
420
-25
FN7610.1
November 4, 2011
13
ISL75051SRH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7610.1
CHANGE
November 4, 2011
Removed “Coming Soon” from ISL75051SRHVF, ISL75051SRHQF, ISL75051SRHVX and
ISL75051SRHX/SAMPLE in “Ordering Information” table on page 4.
September 30, 2011
FN7610.0
Initial Release
Products
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FN7610.1
November 4, 2011
14
ISL75051SRH
Package Outline Drawing
K18.D
18 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 3/11
0.015 (0.381)
0.005 (0.127)
PIN NO. 1
ID OPTIONAL
1
2
0.040 (1.016 BSC)
0.476 (12.09)
0.456 (11.58)
PIN NO. 1
ID AREA
0.005 (0.127)
MIN
4
0.020 (0.508)
0.013 (0.330)
TOP VIEW
0.122 (3.10)
0.100 (2.54)
0.010 (0.25)
0.004 (0.10)
0.038 (0.97)
0.026 (0.66)
6
0.397 (10.084)
0.377 (9.576)
-D-
-H-
-C-
0.350 (8.89)
0.250 (6.35)
0.283 (7.19)
MIN
0.03 (0.76) MIN
SEATING AND
BASE PLANE
SIDE VIEW
NOTES:
Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
1.
0.007 (0.178)
0.004 (0.102)
LEAD FINISH
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
0.010 (0.254)
0.004 (0.102)
BASE
METAL
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
0.017 (0.432)
0.013 (0.330)
4. Measure dimension at all four corners.
0.0015 (0.04)
MAX
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
0.020 (0.508)
0.013 (0.330)
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
3
SECTION A-A
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Dimensions = INCH (mm). Controlling dimension: INCH.
FN7610.1
November 4, 2011
15
相关型号：
ISL76120ARTZ
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RENESAS
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