ISL76683EVAL1Z [INTERSIL]
Light-to-Digital Output Sensor with Gain Selection,Interrupt Function and I2C Interface;
| 型号： | ISL76683EVAL1Z |
| 厂家： | 
Intersil |
| 描述： | Light-to-Digital Output Sensor with Gain Selection,Interrupt Function and I2C Interface |
| 文件： | 总17页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Light-to-Digital Output Sensor with Gain Selection,
2
Interrupt Function and I C Interface
ISL76683
Features
2
The ISL76683 is an integrated light sensor with an internal
integrating ADC intended for automotive applications. The ADC
provides 16-bit resolution and is capable of rejecting 50Hz and
• Range select via I C
- Range 1 = 0 lux to 1000 lux
- Range 2 = 0 lux to 4000 lux
- Range 3 = 0 lux to 16,000 lux
- Range 4 = 0 lux to 64,000 lux
2
60Hz flicker caused by artificial light sources. The I C interface
provides four user programmable lux sensitivity ranges for
optimized counts/lux in a variety of lighting conditions. In
2
addition, the I C interface provides multi-function control of the
• Human eye response (540nm peak sensitivity)
• Temperature compensated
sensor and remote monitoring capabilities.
In normal operation, power consumption is less than 300µA.
Furthermore, a software power-down mode controlled via the I C
• 16-bit resolution
2
• Adjustable sensitivity: up to 65 counts per lux
• User-programmable upper and lower threshold interrupt
• Simple output code, directly proportional to lux
• IR + UV rejection
interface reduces power consumption to less than 1µA.
The ISL76683 supports twin (upper & lower) user programmed
thresholds and provides a hardware interrupt that remains
2
asserted low until the host clears it via the I C control interface.
Designed to operate on supplies from 2.5V to 3.3V, the ISL76683 is
qualified to AEC Q100 and specified for operation over the -40°C to
+105°C (grade 2) ambient temperature range. To achieve this, the
ISL76683 is packaged in a special extended temperature clear
package.
• 50Hz/60Hz rejection
• 2.5V to 3.3V supply
• 6 Ld ODFN (2.1mmx2mm)
• AEC-Q100 qualified
• Pb-free (RoHS compliant)
Related Literature
AN1657, “ISL76683 Light-to-Digital Output Sensor Evaluation
Hardware/Software User Guide”
Applications
• Automotive ambient light sensing
• Backlight control
• Lighting controls
VDD
1
PHOTODIODE 1
COMMAND
REGISTER
INTEGRATING
ADC
DATA
REGISTER
MUX
5
6
SCL
SDA
PHOTODIODE 2
IREF
2
I C
EXT
TIMING
FOSC
INT
16
2
INTERRUPT
4
INT
COUNTER
3
2
REXT
GND
ISL76683
FIGURE 1. BLOCK DIAGRAM
March 24, 2014
FN7697.7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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1
ISL76683
Pin Configuration
Pin Descriptions
ISL76683
(6 LD ODFN)
TOP VIEW
VDD
GND
1
2
3
6
5
4
SDA
SCL
INT
THERMAL
PAD
REXT
PIN NUMBER
PIN NAME
DESCRIPTION
1
2
3
4
5
6
VDD
Positive supply; connect this pin to a regulated 2.5V to 3.3V supply
GND
Ground pin. The thermal pad is connected to the GND pin
REXT
INT
External resistor pin for ADC reference; connect this pin to ground through a (nominal) 100kΩ resistor
Interrupt pin; LO for interrupt/alarming. The INT pin is an open drain.
2
2
SCL
I C serial clock
The I C bus lines can be pulled above VDD, 5.5V max.
2
SDA
I C serial data
Ordering Information
PACKAGE
PART NUMBER
(Notes 1, 2, 3)
TEMP RANGE
(°C)
Tape & Reel
(Pb-free)
PKG.
DWG. #
ISL76683AROZ-T7
ISL76683AROZ-T7A
ISL76683EVAL1Z
NOTES:
-40 to +105
-40 to +105
6 Ld ODFN
6 Ld ODFN
L6.2x2.1
L6.2x2.1
Evaluation Board
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL76683. For more information on MSL please see techbrief TB477.
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ISL76683
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V
, Supply Voltage between VDD and GND . . . . . . . . . . . . . . . . . . . . .3.6V
Thermal Resistance (Typical)
6 Ld ODFN Package (Notes 4, 5) . . . . . . . .
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+105°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
JA (°C/W)
88
θ
JC (°C/W)
7.94
DD
2
I C Bus Pin Voltage (SCL, SDA). . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to 5.5V
2
I C Bus Pin Current (SCL, SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA
INT, R
ESD Rating
Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2V to V
EXT
DD
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD78B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
JA
Tech Brief TB379.
5. For θ , “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
JC
Electrical Specifications V = 3V, T = +25°C, R = 100kΩ 1% tolerance, unless otherwise specified, Internal Timing Mode Operation
DD
A
EXT
(see “Principles of Operation” on page 6).
MIN
MAX
PARAMETER
DESCRIPTION
Power Supply Range
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
V
V
2.25
3.3
0.33
1
DD
I
Supply Current
0.29
0.1
mA
DD
I
Supply Current Disabled
Software disabled, -40°C to +85°C
µA
DD1
Software disabled, -40°C to +105°C, V = 3.3V
DD
0.1
8
µA
f
f
Internal Oscillator Frequency
Internal Oscillator Frequency
Gain/Range = 1 or 2
Gain/Range = 3 or 4
290
580
1
327
655
360
720
400
5
kHz
OSC1
kHz
OSC2
2
2
FI C
I C Clock Rate
kHz
DATA0
DATA1
DATA2
Diode1 Dark ADC Code
Full Scale ADC Code
E = 0 lux, Mode1, Gain/Range = 1
Counts
Counts
Counts
65535
24440
Diode1 ADC Code Gain/Range = 1
Accuracy
Mode1
Mode2
Mode1
Mode2
Mode1
Mode2
Mode1
Mode2
E = 300 lux, fluorescent light,
Gain/Range = 1
(Note 7)
15760
20200
2020
5050
505
DATA3
DATA4
DATA5
DATA6
DATA5
DATA6
DATA6
Diode2 ADC Code Gain/Range = 1
Accuracy
Counts
Counts
Counts
Counts
Counts
Counts
Counts
Diode1 ADC Code Gain/Range = 2
Accuracy
E = 300 lux, fluorescent light,
Gain/Range = 2
(Note 7)
Diode2 ADC Code Gain/Range = 2
Accuracy
Diode1 ADC Code Gain/Range = 3
Accuracy
E = 300 lux, fluorescent light,
Gain/Range = 3
(Note 7)
1262
126
Diode2 ADC Code Gain/Range = 3
Accuracy
Diode1 ADC Code Gain/Range = 4
Accuracy
E = 300 lux, fluorescent light,
Gain/Range = 4
(Note 7)
316
Diode2 ADC Code Gain/Range = 4
Accuracy
32
V
Voltage of REXT Pin
-40°C to +85°C
-40°C to +105°C
(Note 8)
0.485
0.51
0.535
0.545
V
V
V
V
REF
V
SCL and SDA Threshold LO
SCL and SDA Threshold HI
1.05
1.95
TL
V
(Note 8)
TH
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ISL76683
Electrical Specifications V = 3V, T = +25°C, R = 100kΩ 1% tolerance, unless otherwise specified, Internal Timing Mode Operation
DD
A
EXT
(see “Principles of Operation” on page 6). (Continued)
MIN
MAX
PARAMETER
DESCRIPTION
SDA Current Sinking Capability
INT Current Sinking Capability
TEST CONDITIONS
(Note 6)
TYP
5
(Note 6)
UNITS
mA
I
3
3
SDA
I
5
mA
INT
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. Fluorescent light is substituted by a white LED during production.
8. The voltage threshold levels of the SDA and SCL pins are VDD dependent: V = 0.35*V . V = 0.65*V
TL DD TH
.
DD
Typical Performance Curves (R = 100kΩ)
EXT
100
90
RADIATION PATTERN
0º
ISL76683 D1
80
10º
10º
20º
20º
70
60
50
40
LUMINOSITY
30º
30º
ANGLE
40º
40º
50º
60º
50º
60º
ISL76683 D2
30
20
10
0
70º
80º
90º
70º
80º
90º
300
400
500
600
700
800
900
1k
0.2
0.4
0.6
0.8
1.0
WAVELENGTH (nm)
RELATIVE SENSITIVITY
FIGURE 2. SPECTRAL RESPONSE
FIGURE 3. RADIATION PATTERN
320
10
8
T
= +27°C
T = +27°C
A
COMMAND = 00H
0 lux
A
COMMAND = 00H
306
292
278
264
250
5000 lux
6
4
200 lux
RANGE 2
2
0
2.0
2.3
2.6
2.9
3.2
3.5
3.8
2.0
2.3
2.6
2.9
3.2
3.5
3.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 4. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 5. OUTPUT CODE FOR 0 LUX vs SUPPLY VOLTAGE
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ISL76683
Typical Performance Curves (R = 100kΩ) (Continued)
EXT
1.015
1.010
1.005
1.000
0.995
0.990
320.0
319.5
319.0
318.5
318.0
T
= +27°C
T
= +27°C
A
A
COMMAND = 00H
5000 lux
200 lux
2.0
2.3
2.6
2.9
3.2
3.5
3.8
2.0
2.3
2.6
2.9
3.2
3.5
3.8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
FIGURE 6. OUTPUT CODE vs SUPPLY VOLTAGE
FIGURE 7. OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE
10
330
320
310
300
290
280
270
260
V
= 3V
DD
V
- 3V
DD
COMMAND = 00H
0 LUX
8
6
4
2
RANGE2
0
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 8. SUPPLY CURRENT vs TEMPERATURE
FIGURE 9. OUTPUT CODE FOR 0 LUX vs TEMPERATURE
330
1.10
V
= 3V
DD
COMMAND = 00H
V
= 3V
DD
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
329
328
327
326
325
5000 LUX
RANGE 3
200 LUX
RANGE 1
-60
-40
-20
0
20
40
60
80
100 120
-60
-40
-20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. OUTPUT CODE vs TEMPERATURE
FIGURE 11. OSCILLATOR FREQUENCY vs TEMPERATURE
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ISL76683
Interrupt Function
Principles of Operation
The active low interrupt pin is an open drain pull-down
configuration. The interrupt pin serves as an alarm or monitoring
function to determine whether the ambient light exceeds the
upper threshold or goes below the lower threshold. The user can
also configure the persistency of the interrupt pin. This
eliminates any false triggers, such as noise or sudden spikes in
ambient light conditions. An unexpected camera flash, for
example, can be ignored by setting the persistency to 8
integration cycles.
Photodiodes
The ISL76683 contains two photodiodes. Diode1 is sensitive to
both visible and infrared light, while Diode2 is mostly sensitive to
infrared light. The spectral response of the two diodes are
independent from one another. See Figure 2, “SPECTRAL
RESPONSE,” on page 4 in the “Typical Performance Curves”
section. The photodiodes convert light to current then the diodes’
current outputs are converted to digital by a single built-in
2
integrating type 16-bit Analog-to-Digital Converter (ADC). An I C
2
I C Interface
command mode determines which photodiode will be converted
to a digital signal. Mode1 is Diode1 only. Mode2 is Diode2 only.
Mode3 is a sequential Mode1 and Mode2 with an internal subtract
function (Diode1 - Diode2).
There are eight (8) 8-bit registers available inside the ISL76683. The
command and control registers define the operation of the device.
The command and control registers do not change until the registers
are overwritten. There are two 8-bit registers that set the high and
low interrupt thresholds. There are four 8-bit data Read Only
registers; two bytes for the sensor reading and another two bytes for
the timer counts. The data registers contain the ADC's latest digital
output, and the number of clock cycles in the previous integration
period.
Analog-to-Digital Converter (ADC)
The converter is a charge-balancing integrating type 16-bit ADC.
The chosen method for conversion is best for converting small
current signals in the presence of AC periodic noise. A 100ms
integration time, for instance, highly rejects 50Hz and 60Hz
power line noise simultaneously. See “Integration Time or
Conversion Time” on page 11 and “Noise Rejection” on page 12.
2
The ISL76683’s I C interface slave address is hardwired
internally as 1000100. When 1000100x with x as R or W is sent
after the Start condition, this device compares the first seven bits
of this byte to its address and matches.
The built-in ADC offers the user flexibility in integration time or
conversion time. Two timing modes are available; Internal Timing
Mode and External Timing Mode. In Internal Timing Mode,
integration time is determined by an internal dual speed oscillator
Figure 12 shows a sample one-byte read. Figure 13 shows a
sample one-byte write. Figure 14 shows a sync_iic timing
diagram sample for externally controlled integration time. The
(f
), and the n-bit (n = 4, 8, 12, 16) counter inside the ADC. In
OSC
External Timing Mode, integration time is determined by the time
between two consecutive I C External Timing Mode commands. See
“External Timing Mode” on page 10. A good balancing act of
integration time and resolution depending on the application is
required for optimal results.
2
I C bus master always drives the SCL (clock) line, while either the
2
master or the slave can drive the SDA (data) line. Figure 13
2
shows a sample write. Every I C transaction begins with the
master asserting a start condition (SDA falling while SCL remains
high). The following byte is driven by the master and includes the
slave address and read/write bit. The receiving device is
responsible for pulling SDA low during the acknowledgement
period.
2
The ADC has four I C programmable range selects to
dynamically accommodate various lighting conditions. For very
dim conditions, the ADC can be configured at its lowest range.
For very bright conditions, the ADC can be configured at its
highest range.
2
Every I C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high).
2
For more information about the I C standard, please consult the
2
Philips™ I C specification documents.
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ISL76683
Start
DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0
SDA DRIVEN BY MASTER
W
W
A
A
A
9
REGISTER ADDRESS
R7 R6 R5 R4 R3 R2 R1 R0
SDA DRIVEN BY MASTER
A
A
A
9
STOP
START
DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0
SDA DRIVEN BY MASTER
A
A
A
9
DATA BYTE0
A
NAK
A
STOP
I2C DATA
I2C SDA
In
ISL76683
SDA DRIVEN B03
W
I2C SDA
Out
D7 D6 D5 D4 D3 D2 D1 D0
I2C CLK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
2
FIGURE 12. I C READ TIMING DIAGRAM SAMPLE
Start
DEVICE ADDRESS
W
W
A
A
A
9
REGISTER ADDRESS
R7 R6 R5 R4 R3 R2 R1 R0
SDA DRIVEN BY MASTER
A
A
A
9
FUNCTIONS
A
A
A
9
STOP
I2C DATA
I2C SDA In
A6 A5 A4 A3 A2 A1 A0
SDA DRIVEN BY MASTER
B7 B6 B5 B4 B3 B2 B1 B0
I2C SDA Out
I2C CLK In
SDA DRIVEN BY MASTER
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
2
FIGURE 13. I C WRITE TIMING DIAGRAM SAMPLE
Start
DEVICE ADDRESS
A6 A5 A4 A3 A2 A1 A0
SDA DRIVEN BY MASTER
W
W
A
A
A
9
REGISTER ADDRESS
A Stop
I2C DATA
I2C SDA In
R7 R6 R5 R4 R3 R2 R1 R0
A
A
9
I2C SDA Out
SDA DRIVEN BY MASTER
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
I2C CLK In
2
FIGURE 14. I C sync_iic TIMING DIAGRAM SAMPLE
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ISL76683
Register Set
There are eight registers that are available in the ISL76683. Table 1 summarizes the available registers and their functions.
TABLE 1. REGISTER SET
ADDR
(HEX)
REGISTER
NAME
BIT(S)
7
FUNCTION NAME
Enable
FUNCTIONS/DESCRIPTION
00
Command
0: disable ADC-core
1: enable ADC-core
6
5
ADCPD
0: Normal operation
1: Power-down Mode
Timing_Mode
0: Integration is internally timed
1: Integration is externally sync/controlled by I C host
2
4
Reserved
3:2
Mode<1:0>
Selects ADC work mode
0: Diode1’s current to unsigned 16-bit data
1: Diode2’s current to unsigned 16-bit data
2: Difference between diodes (I1 - I2) to signed 15-bit data
3: reserved
1:0
Width<1:0>
Number of clock cycles; n-bit resolution
16
0: 2 cycles
12
1: 2 cycles
8
2: 2 cycles
4
3: 2 cycles
01
Control
7
6
5
Ext_Mode
Test_Mode
Int_Flag
Always set to logic 0. Factory use only.
Always set to logic 0
0: Interrupt is cleared or not yet triggered
1: Interrupt is triggered
4
Reserved
Always set to logic 0. Factory use only.
3:2
Gain<1:0>
Selects the gain so range is
0: 0 to 1000 lux
1: 0 to 4000 lux
2: 0 to 16000 lux
3: 0 to 64000 lux
1:0
Int_Persist
<1:0>
Interrupt is triggered after
0: 1 integration cycle
1: 4 integration cycles
2: 8 integration cycles
3: 16 integration cycles
02
03
04
05
06
07
Interrupt Threshold
HI
7:0
7:0
7:0
7:0
7:0
7:0
Interrupt Threshold High byte of HI interrupt threshold. Default is 0xFF
HI
Interrupt Threshold
LO
Interrupt Threshold High byte of the LO interrupt threshold. Default is 0x00
LO
LSB_Sensor
MSB_Sensor
LSB_Timer
MSB_Timer
LSB_Sensor
MSB_Sensor
LSB_Timer
MSB_Timer
Read-Only data register that contains the least significant byte of the latest
sensor reading.
Read-Only data register that contains the most significant byte of the latest
sensor reading.
Read-Only data register that contains the least significant byte of the timer
counter value corresponding to the latest sensor reading.
Read-Only data register that contains the most significant byte of the timer
counter value corresponding to the latest sensor reading.
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ISL76683
4. Photodiode Select Mode; Bits 3 and 2. This function controls
TABLE 2. WRITE ONLY REGISTERS
the mux attached to the two photodiodes. At Mode1, the mux
directs the current of Diode1 to the ADC. At Mode2, the mux
directs the current of Diode2 only to the ADC. Mode3 is a
sequential Mode1 and Mode2 with an internal subtract
function (Diode1 - Diode2).
REGISTER
NAME
FUNCTIONS/
DESCRIPTION
ADDRESS
b1xxx_xxxx
sync_iic
clar_int
Writing a logic 1 to this address bit ends
the current ADC-integration and starts
another. Used only with External Timing
Mode.
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BITS 3:2
0:0
MODE
bx1xx_xxxx
Writing a logic 1 to this address bit clears
the interrupt.
MODE1. ADC integrates or converts Diode1 only. Current
is converted to an n-bit unsigned data.*
0:1
1:0
1:1
MODE2. ADC integrates or coverts Diode2 only. Current is
converted to an n-bit unsigned data.*
Command Register 00(hex)
The Read/Write command register has five functions:
MODE3. A sequential MODE1 then MODE2 operation.
The difference current is an (n-1) signed data.*
1. Enable; Bit 7. This function either resets the ADC or enables
the ADC in normal operation. A logic 0 disables ADC to reset
mode. A logic 1 enables ADC to normal operation.
No Operation.
*n = 4, 8, 12,16 depending on the number of clock cycles
function.
TABLE 3. ENABLE
BIT 7
OPERATION
5. Width; Bits 1 and 0. This function determines the number of
clock cycles per conversion. Changing the number of clock
cycles does more than just change the resolution of the
device; it also changes the integration time, which is the
period the device’s analog-to-digital (A/D) converter samples
the photodiode current signal for a lux measurement.
0
1
Disable ADC-Core to Reset-Mode (default)
Enable ADC-Core to Normal Operation
2. ADCPD; Bit 6. This function puts the device in a power-down
mode. A logic 0 puts the device in normal operation. A logic 1
powers down the device.
TABLE 7. WIDTH
TABLE 4. ADCPD
BITS 1:0
0:0
NUMBER OF CLOCK CYCLES
= 65,536
= 4,096
16
12
8
BIT 6
OPERATION
Normal Operation (default)
Power-Down
2
2
2
2
0
1
0:1
1:0
= 256
= 16
4
1:1
For proper shut down operation, it is recommended to disable
ADC first then disable the chip. Specifically, the user should first
send I C command with Bit 7 = 0 and then send I C command
with Bit 6 = 1.
2
2
Control Register 01(hex)
The Read/Write control register has three functions:
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an internal dual
1. Interrupt flag; Bit 5. This is the status bit of the interrupt. The
bit is set to logic high when the interrupt thresholds have been
triggered, and logic low when not yet triggered.
speed oscillator (f
), and the n-bit (n = 4, 8, 12,16) counter
OSC
TABLE 8. INTERRUPT FLAG
inside the ADC. In External Timing Mode, integration time is
determined by the time between two consecutive external-sync
sync_iic pulse commands.
BIT 5
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
0
1
TABLE 5. TIMING MODE
BIT 5
0
OPERATION
Internal Timing Mode. Integration time is internally
timed determined by f
cycles.
, REXT, and number of clock
OSC
1
External Timing Mode. Integration time is externally
timed by the I C host.
2
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ISL76683
2. Range/Gain; Bits 3 and 2. The Full Scale Range can be
adjusted by an external resistor R and/or it can be
cannot provide high-accuracy command-to-command timing,
and the timer counter value can be used to eliminate the
resulting noise.
EXT
2
adjusted via I C using the Gain/Range function. Gain/Range
has four possible values, Range(k) where k is 1 through 4.
Table 9 lists the possible values of Range(k) and the resulting
TABLE 11. DATA REGISTERS
ADDRESS
FSR for some typical value R
resistors.
EXT
TABLE 9. RANGE/GAIN TYPICAL FSR LUX RANGES
(hex)
04
CONTENTS
Least-significant byte of most recent sensor reading.
Most-significant byte of most recent sensor reading.
FSR LUX
RANGE@
FSR LUX
RANGE@
FSR LUX
RANGE@
05
BITS
3:2
RANGE
(k)
06
Least-significant byte of timer counter value corresponding to
most recent sensor reading.
k
1
2
3
4
R
= 100k
R
= 50k
R
= 500k
EXT
EXT
EXT
0:0
0:1
1:0
1:1
973
973
1946
195
07
Most-significant byte of timer counter value corresponding to
most recent sensor reading.
3892
3892
15,568
62,272
7784
778
3114
15,568
62,272
31,136
Calculating Lux
The ISL76683’s output codes, DATA, are directly proportional to lux.
124,544
12,454
3. Interrupt persist; Bits 1 and 0. The interrupt pin and the
interrupt flag is triggered/set when the data sensor reading is
out of the interrupt threshold window after m consecutive
number of integration cycles. The interrupt persist bits
determine m.
(EQ. 1)
E = α × DATA
The proportionality constant α is determined by the Full Scale
Range, FSR, and the n-bit ADC, which is user defined in the
command register. The proportionality constant can also be
viewed as the resolution; The smallest lux measurement the
device can measure is α.
TABLE 10. INTERRUPT PERSIST
FSR
BITS 1:0
0:0
NUMBER OF INTEGRATION CYCLES
------------
(EQ. 2)
α =
n
2
1
4
Full Scale Range, FSR, is determined by the software
0:1
programmable Range/Gain, Range(k), in the command register
and an external scaling resistor R , which is referenced to
1:0
8
EXT
100kΩ.
1:1
16
(EQ. 3)
100kΩ
-----------------
FSR = Range(k) ×
R
EXT
Interrupt Threshold HI Register 02(hex)
The transfer function effectively for each timing mode becomes:
This register sets the HI threshold for the interrupt pin and the
interrupt flag. By default, the Interrupt threshold HI is FF(hex).
The 8-bit data written to the register represents the upper MSB of
a 16-bit value. The LSB is always 00(hex).
INTERNAL TIMING MODE
100kΩ
-----------------
Range(k) ×
(EQ. 4)
R
EXT
----------------------------------------------------
E =
× DATA
× DATA
n
2
Interrupt Threshold LO Register 03(hex)
EXTERNAL TIMING MODE
This register sets the LO threshold for the interrupt pin and the
interrupt flag. By default, the Interrupt threshold LO is 00(hex).
The 8-bit data written to the register represents the upper MSB of
a 16-bit value. The LSB is always 00(hex).
100kΩ
-----------------
Range(k) ×
(EQ. 5)
R
EXT
----------------------------------------------------
E =
COUNTER
n = 4, 8, 12, or 16. This is the number of clock cycles
programmed in the command register.
Sensor Data Register 04(hex) and 05(hex)
When the device is configured to output a 16-bit data, the least
significant byte is accessed at 04(hex), and the most significant
byte can be accessed at 05(hex). The sensor data register is
refreshed after every integration cycle.
Range(k) is the user defined range in the Gain/Range bit in the
command register.
R
is an external scaling resistor hardwired to the REXT pin.
EXT
DATA is the output sensor reading in number of counts available
at the data register.
Timer Data Register 06(hex) and 07(hex)
Note that the timer counter value is only available when using the
External Timing Mode. The 06(hex) and 07(hex) are the LSB and
MSB respectively of a 16-bit timer counter value corresponding to
the most recent sensor reading. Each clock cycle increments the
counter. At the end of each integration period, the value of this
n
2 represents the maximum number of counts possible in
Internal Timing Mode. For the External Timing Mode, the
maximum number of counts is stored in the data register named
COUNTER.
2
counter is made available over the I C. This value can be used to
COUNTER is the number increments accrued for between
integration time for External Timing Mode.
eliminate noise introduced by slight timing errors caused by
imprecise external timing. Microcontrollers, for example, often
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ISL76683
The automatic f
OSC
improvement of signal-to-noise ratio when detecting very low lux
signals.
adjustment feature allows significant
Gain/Range, Range (k)
The Gain/Range can be programmed in the control register to
give Range (k) determining the FSR. Note that Range(k) is not
the FSR (see Equation 3). Range(k) provides four constants
Integration Time or Conversion Time
depending on programmed k that will be scaled by R
(see
EXT
Integration time is the period during which the device’s analog-
to-digital ADC converter samples the photodiode current signal
for a lux measurement. Integration time, in other words, is the
time to complete the conversion of analog photodiode current
into a digital signal (number of counts).
Table 9). Unlike R , Range(k) dynamically adjusts the FSR. This
EXT
function is especially useful when light conditions are varying
drastically while maintaining excellent resolution.
Number of Clock Cycles, n-bit ADC
The number of clock cycles determines “n” in the n-bit ADC; 2 clock
n
Integration time affects the measurement resolution. For better
resolution, use a longer integration time. For short and fast
conversions, use a shorter integration time.
cycles is a n-bit ADC. n is programmable in the command register in
the width function. Depending on the application, a good balance of
speed and resolution has to be considered when deciding for n. For
fast and quick measurement, choose the smallest n = 4. For
maximum resolution without regard of time, choose n = 16.
Table 12 compares the trade-off between integration time and
resolution. See Equations 10 and 11 for the relation between
integration time and n. See Equation 3 for the relation of n and
resolution.
The ISL76683 offers user flexibility in the integration time to
balance resolution, speed and noise rejection. Integration time can
be set internally or externally and can be programmed in the
command register 00(hex) bit 5.
INTEGRATION TIME IN INTERNAL TIMING MODE
This timing mode is programmed in the command register
00(hex) bit 5. Most applications will be using this timing mode.
TABLE 12. RESOLUTION AND INTEGRATION TIME SELECTION
When using the Internal Timing Mode, f
and n-bits resolution
OSC
determine the integration time. t is a function of the number of
RANGE1
RANGE4
f
= 327kHz
f
= 655kHz
int
OSC
OSC
clock cycles and f
.
OSC
RESOLUTION
LUX/COUNT
RESOLUTION
(LUX/COUNT)
n
1
(EQ. 9)
n
16
12
8
t
(ms)
t
(ms)
----------
INT
INT
100
for Internal Timing Mode only
t
= 2
×
int
f
osc
200
0.01
0.24
3.90
62.5
1
12.8
0.8
6.4
0.4
16
n = 4, 8, 12, and 16. n is the number of bits of resolution.
n
250
4000
Therefore, 2 is the number of clock cycles. n can be programmed
at the command register 00(hex) bits 1 and 0.
4
0.05
0.025
NOTE: R
= 100kΩ
EXT
Since f
OSC
is dual speed depending on the Gain/Range bit, t is
int
dual time. The integration time as a function of R
and n is:
EXT
External Scaling Resistor R
The ISL76683 uses an external resistor R
and f
R
n
EXT
EXT
osc
EXT
(EQ. 10)
---------------------------------------------
t
1 = 2
×
int
327kHz × 100kΩ
to fix its internal
determines the
, a dual
oscillator frequency, f
. Consequently, R
OSC EXT
t
is the integration time when the device is configured for
Internal Timing Mode and Gain/Range is set to Range1 or
int1
f
, integration time and the FSR of the device. f
OSC
OSC
speed mode oscillator, is inversely proportional to R . For user
simplicity, the proportionality constant is referenced to fixed
constants 100kΩ and 655kHz:
EXT
Range2.
R
n
EXT
(EQ. 11)
---------------------------------------------
t
2 = 2
×
int
655kHz × 100kΩ
(EQ. 6)
(EQ. 7)
1
2
100kΩ
-- -----------------
× 655kHz
fosc1 =
fosc2 =
×
R
EXT
t
is the integration time when the device is configured for
Internal Timing Mode and Gain/Range is set to Range3 or
Range4.
int2
100kΩ
-----------------
× 655kHz
R
EXT
TABLE 13. INTEGRATION TIMES FOR TYPICAL R
VALUES
EXT
f
1 is oscillator frequency when Range1 or Range2 are set.
OSC
RANGE1
RANGE2
RANGE3
RANGE4
This is nominally 327kHz when R
is 100kΩ.
EXT
R
(kΩ)
EXT
f
2 is the oscillator frequency when Range3 or Range4 are
OSC
n = 16-BIT
100
n = 12-BIT
n = 12-BIT
n = 4
0.013
0.025
0.050
0.125
set. This is nominally 655kHz when R
is 100kΩ.
EXT
50
6.4
13
26
64
3.2
6.5
13
32
When the Range/Gain bits are set to Range1 or Range2, f
runs at half speed compared to when Range/Gain bits are set to
Range3 and Range4.
OSC
100**
200
200
400
(EQ. 8)
1
2
--
1 = (f
f
2)
OSC
OSC
500
1000
*Integration time in milliseconds
**Recommended R resistor value
EXT
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ISL76683
Solution 1
INTEGRATION TIME IN EXTERNAL TIMING MODE
This timing mode is programmed in the command register
00(hex) bit 5. External Timing Mode is recommended when
integration time can be synchronized to an external signal (such
as a PWM) to eliminate noise.
Using Internal Timing Mode
In order to achieve both 60Hz and 50Hz AC noise rejection, the
integration time needs to be adjusted to coincide with an integer
multiple of the AC noise cycle times.
(EQ. 14)
For Mode1 or Mode2 operation, the integration starts when the
t
= i(1 ⁄ 60Hz)= j(1 ⁄ 50Hz)
int
2
sync_iic command is sent over the I C lines. The device needs
two sync_iic commands to complete a photodiode conversion.
The integration then stops when another sync_iic command is
received. Writing a logic 1 to the sync_iic bit ends the current
ADC integration and starts another one.
The first instance of integer values at which t rejects both 60Hz
int
and 50Hz is when i = 6, and j = 5.
t
= 6(1 ⁄ 60Hz)= 5(1 ⁄ 50Hz)
= 100ms
int
int
(EQ. 15)
t
For Mode3, the operation is a sequential Mode1 and Mode2. The
device needs three sync_iic commands to complete two
photodiode measurements. The 1st sync_iic command starts the
conversion of the Diode1. The 2nd sync_iic completes the
conversion of Diode1 and starts the conversion of Diode2. The 3rd
sync_iic pulse ends the conversion of Diode2 and starts over again
to commence conversion of Diode1.
Next, the Gain/Range needs to be determined. Based on the
application condition given, lux(max) = 500 lux, a range of 1000
lux is desirable. This corresponds to a Gain/Range Range1
mode. Also impose a resolution of n = 16-bit. Hence, we choose
Equation 10 to determine R
.
EXT
t
× 327kHz × 100kΩ
int
The integration time, t , is determined by Equation 12:
int
------------------------------------------------------------
R
=
EXT
n
i 2
2
I
C
(EQ. 16)
----------
C
t
=
(EQ. 12)
int
f 2
I
R
= 50kΩ
EXT
2
2
i
f
is the number of I C clock cycles to obtain the t
for Internal Timing Mode and Gain/Range is set to Range3 or Range4 only
I C
int.
2
2
is the I C operating frequency.
I C
The Full Scale Range, FSR, needs to be determined from
Equation 3:
The internal oscillator, f
internal and external timing modes, with the same dependence
, operates identically in both the
OSC
100kΩ
on R . However, in External Timing Mode, the number of clock
-----------------
FSR = 1000 lux
EXT
(EQ. 17)
(EQ. 18)
50kΩ
n
cycles per integration is no longer fixed at 2 . The number of
clock cycles varies with the chosen integration time, and is
limited to 2 = 65,536. In order to avoid erroneous lux readings,
the integration time must be short enough not to allow an
overflow in the counter register.
FSR = 2000 lux
16
The effective transfer function becomes:
data
-------------
16
E =
× 2000 lux
65,535
2
-----------------
t
<
(EQ. 13)
int
f
OSC
TABLE 14. SOLUTION1 SUMMARY TO EXAMPLE DESIGN PROBLEM
f
= 327kHz*100kΩ/R . When Range/Gain is set to
EXT
OSC
DESIGN PARAMETER
VALUE
100ms
Range1 or Range2.
t
int
f
= 655kHz*100kΩ/R . When Range/Gain is set to
OSC
EXT
R
50kΩ
Range3 or Range4.
EXT
Gain/Range Mode
Range1 = 1000 lux
Noise Rejection
FSR
2000 lux
In general, integrating type ADC’s have excellent noise-rejection
characteristics for periodic noise sources whose frequency is an
integer multiple of the integration time. For instance, a 60Hz AC
16
2
# of clock cycles
Transfer Function
DATA
----------------
E =
× 2000 lux
16
unwanted signal’s sum from 0ms to k*16.66ms (k = 1,2...k ) is
i
2
zero. Similarly, setting the device’s integration time to be an
integer multiple of the periodic noise signal greatly improves the
light sensor output signal in the presence of noise.
Solution 2
Using External Timing Mode
From Solution 1, the desired integration time is 100ms. Note
DESIGN EXAMPLE 1
The ISL76683 will be designed in a portable system. The
ambient light conditions that the device will be exposed to is at
most 500 lux, which is a good office lighting. The light source has
a 50/60Hz power line noise, which is not visible by the human
that the R resistor only determines the inter oscillator
frequency when using external timing mode. Instead, the
EXT
integration time is the time between two sync_iic commands
2
2
sent through the I C. The programmer determines how many I C
clock cycles to wait between two external timing commands.
2
eye. The I C clock is 10kHz.
2
2
2
i
= f
t
= number of I C clock cycles
I C
I C* int
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ISL76683
2
i
i
= 10kHz 100ms
*
Flat Window Lens Design
I C
2
2
= 1,000 I C clock cycles. An external sync_iic command sent
A window lens will surely limit the viewing angle of the ISL76683.
The window lens should be placed directly on top of the device.
The thickness of the lens should be kept at minimum to
minimize loss of power due to reflection and also to minimize
loss of loss due to absorption of energy in the plastic material. A
thickness of t = 1mm is recommended for a window lens design.
The bigger the diameter of the window lens, the wider the
viewing angle is of the ISL76683. Table 16 shows the
I C
1,000 cycles after another sync_iic command rejects both 60Hz
and 50Hz AC noise signals.
Next, is to pick an arbitrary R
EXT
Gain/Range Mode. For a maximum 500 lux, Range1 is
adequate. From Equation 3:
= 100kΩ and to choose the
100kΩ
-----------------
FSR = 1000 lux
100kΩ
recommended dimensions of the optical window to ensure both
35° and 45° viewing angle. These dimensions are based on a
window lens thickness of 1.0mm and a refractive index of 1.59.
FSR = 1000 lux
The effective transfer function becomes:
WINDOW LENS
DATA
COUNTER
-------------------------------
E =
× 1000 lux
DATA is the sensor reading data located in data registers 04(hex)
and 05(hex)
t
D
TOTAL
∅
D1
COUNTER is the timer counter value data located in data registers
06(hex) and 07(hex). In this sample problem, COUNTER = 1000.
TABLE 15. SOLUTION 2 SUMMARY TO EXAMPLE DESIGN PROBLEM
DESIGN PARAMETER
VALUE
100ms
ISL76683
D
t
LENS
int
R
100kΩ
EXT
∅ = VIEWING ANGLE
Gain/Range Mode
FSR
Range1 = 1000 lux
1000 lux
FIGURE 15. FLAT WINDOW LENS
# of clock cycles
Transfer Function
COUNTER = 1000
Window with Light Guide Design
DATA
If a smaller window is desired while maintaining a wide effective
viewing angle of the ISL76683, a cylindrical piece of transparent
plastic is needed to trap the light and then focus and guide the
light on to the device. Hence, the name light guide or also known
as light pipe. The pipe should be placed directly on top of the
device with a distance of D1 = 0.5mm to achieve peak
performance. The light pipe should have minimum of 1.5mm in
diameter to ensure that whole area of the sensor will be exposed.
See Figure 16.
-------------------------------
E =
× 1000 lux
COUNTER
IR Rejection
Any filament type light source has a high presence of infrared
component invisible to the human eye. A white fluorescent lamp,
on the other hand has a low IR content. As a result, output
sensitivity may vary depending on the light source. Maximum
attenuation of IR can be achieved by properly scaling the readings
of Diode1 and Diode2. The user obtains data reading from sensor
Diode1 (D1), which is sensitive to visible and IR, then reading from
sensor Diode2 (D2), which is mostly sensitive from IR. The graph in
Figure 2 shows the effective spectral response after applying
Equation 19 of the ISL76683 from 400nm to 1000nm.
Equation 19 describes the method of cancelling IR in internal
timing mode.
TABLE 16. RECOMMENDED DIMENSIONS FOR A FLAT WINDOW
DESIGN
D
@ 35° VIEWING
ANGLE
D
@ 45° VIEWING
ANGLE
LENS
LENS
D
D1
TOTAL
1.5
0.50
1.00
1.50
2.00
2.50
2.25
3.00
3.75
4.30
5.00
3.75
4.75
5.75
6.75
7.75
2.0
2.5
3.0
3.5
(EQ. 19)
D3 = n(D1 – kD2)
Where:
data = lux amount in number of counts less IR presence
D1 = data reading of Diode1
D2 = data reading of Diode2
t = 1
D1
Thickness of lens
Distance between ISL76683 and inner edge of lens
Diameter of lens
Distance constraint between the ISL76683 and lens
outer edge
D
D
LENS
TOTAL
n = 1.85. This is a fudge factor to scale back the sensitivity up to
ensure Equation 4 is valid.
*All dimensions are in mm.
k = 7.5. This is a scaling factor for the IR sensitive Diode2.
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ISL76683
D
LENS
LIGHT PIPE
D
>1.5mm
2
t
D
LENS
D
2
L
ISL76683
FIGURE 16. WINDOW WITH LIGHT GUIDE/PIPE
FIGURE 17. SENSOR LOCATION DRAWING
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ISL76683
Suggested PCB Footprint
Typical Circuit
Footprint pads should be a nominal 1-to-1 correspondence with
package pads. Since ambient light sensor devices do not
dissipate high power, heat dissipation through the exposed pad is
not important; instead, similar to DFN or QFN, the exposed pad
provides robustness in board mount process. Intersil
recommends mounting the exposed pad to the PCB, but this is
not mandatory.
A typical application for the ISL76683 is shown in Figure 18. The
2
ISL76683’s I C address is internally hardwired as 1000100. The
2
device can be tied onto a system’s I C bus together with other
2
I C compliant devices.
Soldering Considerations
Convection heating is recommended for reflow soldering; direct
infrared heating is not recommended. The plastic ODFN package
does not require a custom reflow soldering profile, and is
qualified to +260°C. A standard reflow soldering profile with a
+260°C maximum is recommended.
Layout Considerations
The ISL76683 is relatively insensitive to layout. Like other I C
devices, it is intended to provide excellent performance even in
significantly noisy environments. There are only a few
considerations that will ensure best performance.
2
2
Route the supply and I C traces as far as possible from all
sources of noise. Use two power-supply decoupling capacitors,
4.7µF and 0.1µF, placed close to the device.
1.8V TO 5.5V
2
I C MASTER
R1
R2
R3
10kΩ 10kΩ RES1
MICROCONTROLLER
SDA
SCL
2.5V TO 3.3V
2
2
2
I C SLAVE_1
I C SLAVE_0
I C SLAVE_n
1
2
6
5
4
SDA
SCL
SDA
SCL
VDD
SDA
SCL
INT
GND
REXT
C1
C2
3
4.7µF 0.1µF
R
EXT
ISL76683
100kΩ
FIGURE 18. ISL76683 TYPICAL CIRCUIT
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ISL76683
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7697.7
CHANGE
March 24, 2014
Added AEC-Q100 qualified to features on page 1.
Added Related Literature on page 1.
Added Eval board to ordering information on page 2.
Updated Figure 17 Sensor Location Drawing with Pin 1 Marking.
December 23, 2013
FN7697.6
Page 16
- 2nd line of the disclaimer changed from:
"Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted"
to:
"Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality
systems as noted"
July 22, 2013
FN7697.5
FN7697.4
Removed Confidential Watermark, Updated Product Information verbiage to About Intersil verbiage.
October 30, 2012
Added ISL76683AROZ-T7A to “Ordering Information” on page 2.
Updated “Package Outline Drawing” on page 17. Added "MAX 0.75" dimension to Side View.
July 9, 2012
FN7697.3
In “Control Register 01(hex)” on page 9, removed sentence: “Writing a logic low clears/resets the status bit.”
from “1. Interrupt flag; Bit 5”
March 8, 2011
FN7697.2
FN7697.1
Changed TechBrief reference in ordering information for MSL info from TB363 to TB477.
Initial Release to web.
January 24, 2011
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL76683
Package Outline Drawing
L6.2x2.1
6 LEAD OPTICAL DUAL FLAT NO-LEAD PLASTIC PACKAGE (ODFN)
Rev 3, 5/11
2.10
A
6
B
PIN #1
INDEX AREA
6
1
PIN 1
INDEX AREA
0.65
1.35 1.30 REF
2.00
4
6X 0.30±0.05
(4X)
0.10
0.10 M C A B
0.65
TOP VIEW
6x0.35 ± 0.05
BOTTOM VIEW
2.50
2.10
PACKAGE
OUTLINE
SEE DETAIL "X"
0.10 C
0.65
(4x0.65)
MAX 0.75
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(1.35)
5
C
(6x0.30)
0 . 2 REF
(6x0.20)
0 . 00 MIN.
0 . 05 MAX.
(6x0.55)
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7697.7
March 24, 2014
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