ISL80101IRAJZ [INTERSIL]
High Performance 1A LDO; 高性能1A LDO
| 型号： | ISL80101IRAJZ |
| 厂家： | 
Intersil |
| 描述： | High Performance 1A LDO |
| 文件： | 总15页 (文件大小：539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 1A LDO
ISL80101
Features
• 0.2% initial V
Accuracy
The ISL80101 ia a low-voltage, high-current, single
output LDO specified for 1A output current. This part
operates from input voltages of 2.2V to 6V and is capable
of providing output voltages of 0.8V to 5V on the
OUT
• Designed for 2.2V to 6V Input Supply
• Dropout Typically 130mV at 1A
• Fast Load Transient Response
adjustable V
versions. Fixed output voltage options
OUT
available in 0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V.
Other custom voltage options available upon request.
• Rated Output Current Options of 1A
• Adjustable In-Rush Current Limiting
For applications that demand in-rush current less than
• Fixed and Adjustable V
• 58dB Typical PSRR
Options Available
OUT
current limit or a longer delay for a valid V
, an
OUT
external capacitor on the soft-start pin provides
adjustment. A supply independent ENABLE signal allows
the part to be placed into a low quiescent current
shutdown mode. Sub-micron CMOS process is utilized for
this product family to deliver best in class analog
performance and overall value.
• Output Noise of 100µV
300kHz
between 300Hz to
RMS
• PG Feature
• 1V Enable Input Threshold
• Short-Circuit Current Protection
• 1A Peak Reverse Current
This CMOS LDO will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable leading class
fast load transient response and hence total AC
regulation band for an LDO in this category.
• Over-Temperature Shutdown
• Any Cap Stable with Minimum 10µF Ceramic
• ±1.8% Guaranteed V
Temperature Range from -40°C to +125°C
Accuracy for Junction
OUT
• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5
Applications*(see page 14)
• DSP, FPGA and µP Core Power Supplies
• Noise-Sensitive Instrumentation Systems
• Post Regulation of Switched Mode Power Supplies
• Industrial Systems
• Pb-Free (RoHS Compliant)
• Medical Equipment
• Telecommunications and Networking Equipment
• Servers
• Hard Disk Drives (HD/HDD)
Pin Configuration
ISL80101
(10 LD 3X3 DFN)
TOP VIEW
VOUT
VIN
1
10
9
VOUT
SENSE/ADJ
PG
VIN
2
3
4
5
NC
8
7
ENABLE
SS
GND
6
December 21, 2009
FN6931.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL80101
Pin Descriptions
PIN
NUMBER
PIN NAME
VOUT
DESCRIPTION
1, 2
3
Output voltage pin.
Remote voltage sense for internally fixed V
SENSE/ADJ
PG
options. ADJ pin for externally set V .
OUT
OUT
4
V
in regulation signal. Logic low defines when V
is not in regulation. Pin should be grounded
OUT
OUT
if not used.
5
6
GND
SS
GND pin.
External cap controls the rate of the V
ramp.
OUT
7
ENABLE
DNC
V
independent chip enable. TTL and CMOS compatible.
IN
8
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
9, 10
VIN
Ordering Information
VOUT
PART NUMBER
(Notes 4, 5)
VOLTAGE
(Note 3)
PACKAGE
(Pb-Free)
PART MARKING
TEMP RANGE (°C)
PKG DWG. #
L10.3x3
ISL80101IRAJZ
(Note 1)
DZAB
ADJ
-40 to +125
10 Ld 3x3 DFN
ISL80101IR08Z
DZBB
DZBB
0.8V
0.8V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR08Z-T
(Note 2)
ISL80101IR12Z
DZCB
DZCB
1.2V
1.2V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR12Z-T
(Note 2)
ISL80101IR15Z
DZDB
DZDB
1.5V
1.5V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR15Z-T
(Note 2)
ISL80101IR18Z
(Note 1)
DZEB
DZFB
1.8V
2.5V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR25Z
(Note 1)
ISL80101IR33Z
DZGB
DZGB
3.3V
3.3V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR33Z-T
(Note 2)
ISL80101IR50Z
DZHB
DZHB
5.0V
5.0V
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
ISL80101IR50Z-T
(Note 2)
NOTES:
1. Add “-T” or “TK” for Tape and Reel. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. For other output voltages, contact Intersil Marketing.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101. For more information on MSL please
see techbrief TB363.
FN6931.0
December 21, 2009
2
ISL80101
Absolute Maximum Ratings
Thermal Information
VIN relative to GND (Note 6) . . . . . . . . . . . . -0.3V to +6.5V
VOUT relative to GND (Note 6) . . . . . . . . . . -0.3V to +6.5V
PG, ENABLE, SENSE/ADJ, SS
Thermal Resistance . . . . . . . . . . . . . . . . . . .θJA (°C/W)θJC (°C/W)
10 Ld DFN Package (Notes 7, 8) . .
45
4
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Relative to GND (Note 6) . . . . . . . . . . . . . -0.3V to +6.5V
Recommended Operating Conditions
(Notes 9, 10)
Junction Temperature Range (TJ) (Note 9) . -40°C to +125°C
VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V
VOUT range. . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5V
PG, ENABLE, SENSE/ADJ, SS relative to GND . . . .0V to +6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . .<10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
8. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
9. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage.
Recommended operating conditions define limits where specifications are guaranteed.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
Electrical Specifications Unless otherwise noted, V = V
+ 0.4V, V
= 1.8V, C = C
IN
= 10µF, T = +25°C.
OUT J
IN
OUT
OUT
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 11) TYP (Note 11) UNITS
DC CHARACTERISTICS
DC Ouput Voltage Accuracy
V
V
V
Options: 0.8V, 1.2V, 1.5V and 1.8V
OUT
OUT
2.2V ≤ V < 3.6V; 0A < I
IN
≤ 1A
-1.8
0.2
1.8
%
LOAD
Options: 2.5V, 3.3V and 5.0V
OUT
V
+ 0.4V ≤ V ≤ 6V; 0A < I
IN LOAD
< 1A
-1.8
491
0.2
1.8
%
OUT
Feedback Pin
(ADJ Option Only)
V
ΔV
ΔV
2.2V ≤V ≤ 6V, 0A < I
IN LOAD
< 1A
500
509
mV
ADJ
DC Input Line Regulation
/
/
V
+ 0.5V < V < 5V
OUT IN
1
%
%
OUT
ΔV
IN
DC Output Load Regulation
0A < I
LOAD
< 1A, All voltage options
-1
OUT
OUT
ΔI
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
3
1
5
µA
mA
mA
µA
ADJ
I
I
I
= 0A, 2.2V < V < 6V
IN
Q
LOAD
LOAD
= 1A, 2.2V < V < 6V
IN
5
7
Ground Pin Current in
Shutdown
I
ENABLE Pin = 0.2V, V = 6V
IN
0.2
12
SHDN
Dropout Voltage (Note 12)
V
I
= 1A, V = 2.5V
OUT
130
212
mV
A
DO
LOAD
Output Short Circuit Current
(1A Version)
V
= 0V, 2.2V < V < 6V
1.75
OCP
OUT
IN
Thermal Shutdown
Temperature
2.2V < V < 6V
IN
160
°C
TSD
FN6931.0
December 21, 2009
3
ISL80101
Electrical Specifications Unless otherwise noted, V = V
+ 0.4V, V
= 1.8V, C = C
IN
= 10µF, T = +25°C.
OUT J
IN
OUT
OUT
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to Applications section of the datasheet and Tech Brief TB379.
Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 11) TYP (Note 11) UNITS
Thermal Shutdown
Hysteresis (Rising Threshold)
2.2V < V < 6V
30
°C
TSDn
IN
AC CHARACTERISTICS
Input Supply Ripple
Rejection
PSRR
f = 1kHz, I
= 1A; V = 2.2V
IN
58
72
dB
dB
LOAD
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz
100
µV
LOAD
RMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
2.2V < V < 6V
IN
0.3
10
0.8
80
1
V
Hysteresis
(Rising Threshold)
2.2V < V
OUT
+ 0.4V < 6V
200
mV
Enable Pin Turn-on Delay
Enable Pin Leakage Current
C
V
= 10µF, I
= 1A
LOAD
100
µs
OUT
= 6V, EN = 3V
1
µA
IN
ADJUSTABLE INRUSH CURRENT LIMIT CHARACTERISTICS
Current limit adjust
I
V
= 3.5V, EN = 0V, SS = 1V
0.5
1
1.3
mA
µA
PD
IN
I
-3.3
-2
-0.8
CHG
PG PIN CHARACTERISTICS
V
V
PG Flag Threshold
PG Flag Hysteresis
75
85
4
92
%V
OUT
OUT
OUT
%
mV
µA
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
V
V
= 2.5V, I
= 500µA
= 6V, PG = 6V
100
1
IN
SINK
IN
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
12. Dropout is defined by the difference in supply V and V
IN
when the supply produces a 2% drop in VOUT from its nominal
OUT
value.
FN6931.0
December 21, 2009
4
ISL80101
Typical Application Diagrams
1
2
3
9
V
V
OUT
OUT
2.5V ± 10%
V
V
1.8V ± 1.8%
IN
10
10µF
IN
10µF
SENSE/ADJ
100k
10k
ISL80101
4
7
6
ENABLE
SS
PG
(*NOTE 13)
GND
5
FIXED
FIGURE 1. FIXED TYPICAL APPLICATION DIAGRAM
1
9
1.8V ± 1.8%
2.5V ± 10%
V
V
V
OUT
IN
2
10
V
10µF
OUT
10µF
IN
ISL80101
2.6k
1k
10k
100k
SENSE/ADJ
7
6
ENABLE
SS
4
PG
GND
(*NOTE 13)
5
ADJUSTABLE
FIGURE 2. ADJUSTABLE TYPICAL APPLICATION DIAGRAM
NOTE:
13. Used when large bulk capacitance required on V
for application.
OUT
FN6931.0
December 21, 2009
5
ISL80101
ISL80101 Schematic Block Diagram
VIN
THERMAL
SHUTDOWN
OCL
SS
SS
-
REFERENCE
BIAS
POWER
PMOS
+
VOUT
SENSE
LEVEL
SHIFT
ENABLE
ADJ
PGOOD
-
+
GND
INPUT CAPACITOR
Application Section
Input Voltage Requirements
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 3. Minimum guaranteed input voltage is 2.2V.
minimum capacitor must be connected to V and
Ground pins of the LDO with PCB traces no longer than
0.5cm.
OUT
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +130°C.
The level of power combined with the thermal resistance
of the package (+45°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature specified in the “Electrical Specifications”
table on page 3 (see thermal packaging guidelines).
However, due to the nature of an LDO, V must be some
IN
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
filtering (PSRR) is expected from V to V
. The
IN OUT
Dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
Current Limit Protection
External Capacitor Requirements
GENERAL GUIDELINE
The ISL80101 LDO incorporates protection against
overcurrent due to any short or overload condition
applied to the output pin. The current limit circuit
performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 3. If the short or
External capacitors are required for proper operation.
Careful attention must be paid to layout guidelines and
selection of capacitor type and value to ensure optimal
performance.
overload condition is removed from V
, then the
OUT
OUTPUT CAPACITOR
output returns to normal voltage mode regulation. In the
event of an overload condition on the DFN package the
LDO will begin to cycle on and off due to the die
temperature exceeding thermal fault condition. The
TO220/263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if
the heatsink of this larger package can keep the die
temperature below the specified typical thermal
shutdown temperature.
The required minimum output capacitor is 10µF X5R/X7R
to ensure stable operation. Additional capacitors of any
value in Ceramic, POSCAP or Alum/Tantalum Electrolytic
types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output
voltage tolerances. This minimum capacitor must be
connected to V
traces no longer than 0.5cm.
and Ground pins of the LDO with PCB
OUT
FN6931.0
December 21, 2009
6
ISL80101
Functional Description
Enable Operation
The Enable turn-on threshold is typically 0.8V with a
hysteresis of 80mV. The Enable pin doesn't have an
internal pull-up or pull-down resistor. As a result, this pin
must not be left floating. This pin must be tied to V if it
IN
is not used. A pull-up resistor (typically 1kΩ to 10kΩ) will
be required for applications that use open collector or
open drain outputs to control the Enable pin. The Enable
pin may be connected directly to V for applications that
IN
are always on.
Soft-Start Operation
FIGURE 4. IN-RUSH CURRENT WITH C
= 15nF,
The soft-start circuit controls the rate at which the output
voltage comes up to regulation at power-up or coming
out of a chip disable. A constant current charges an
external soft-start capacitor. The external capacitor
always gets discharged to 0V at start-up of after coming
out of a chip disable. The discharge rate is the RC time
SS
= 1000µF, IN-RUSH CURRENT = 0.5A
C
OUT
constant of an internal resistance and C . The soft-start
SS
function effectively limits the amount of in-rush current
below the programmed current limit during start-up or
an enable sequence to avoid an overcurrent fault
condition. This can be an issue for applications that
require large, external bulk capacitances on V
where
OUT
high levels of charging current can be seen for a
significant period of time. High in-rush currents can
cause V to drop below minimum which could cause
IN
to shutdown. Equation 3 can be used to calculate
V
C
OUT
for a desired in-rush current Where V
is the
SS
output voltage, C
.
OUT
FIGURE 5. IN-RUSH CURRENT WITH C
= 33nF,
SS
= 1000µF, IN-RUSH CURRENT = 0.2A
is the total capacitance on the
OUT
is the desired in-rush current.
C
OUT
output and I
INRUSH
xC x2μA))
Also
(V
The rise time of the regulator output voltage for a given
OUT
OUT
(EQ. 1)
-----------------------------------------------------------
C
=
SS
I
x0.5V
C
value can be calculated using Equation 2.
SS
INRUSH
C
x0.5V
SS
(EQ. 2)
----------------------------
=
t
The following scope in Figure 3 captures the response for
the soft-start function.The output voltage is set to 1.8V.
RAMP
2μA
Power-Good Operation
The PGOOD circuit monitors V
and signals a fault
OUT
condition when V
is below 85% of the nominal output
OUT
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
be pulled up to a voltage source greater than V . During
IN
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
FIGURE 3. IN-RUSH CURRENT WITH NO C
,
SS
C
= 1000µF, IN-RUSH CURRENT = 1.8A
OUT
FN6931.0
December 21, 2009
7
ISL80101
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
resistance (θ ) for the DFN package with Equation 5:
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
JA
(EQ. 7)
P
= (T
– T ) ⁄ θ
J(MAX) A JA
D(MAX)
and 5V. An external resistor divider, R and R , is used to
1
2
set the output voltage as shown in Equation 3. The
Substitute P for P
and the maximum ambient
operating temperature can be found by solving for T
D
D(MAX)
recommended value for R is 500Ω to 1kΩ. R is then
2
1
A
chosen according to Equation 4:
using Equation 8:
R
⎛
⎜
⎝
⎞
1
(EQ. 3)
(EQ. 4)
------
V
= 0.5V ×
+ 1
⎟
(EQ. 8)
OUT
T
= T
– P
× θ
D(MAX) JA
R
2
A
JMAX
⎠
Heatsinking The DFN Package
V
OUT
0.5V
⎛
⎝
⎞
---------------
R
= R
×
– 1
1
2
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 6
⎠
Power Dissipation
shows a curve for the θ of the DFN package for
JA
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 5:
different copper area sizes.
46
44
42
40
38
36
34
(EQ. 5)
P
= (V – V
) × I
+ V × I
OUT IN GND
D
IN
OUT
The maximum allowed junction temperature, T
J(MAX)
and the maximum expected ambient temperature,
will determine the maximum allowed junction
T
A(MAX)
temperature rise (ΔT ) as shown in Equation 6:
2
4
6
8
10 12 14 16 18 20 22 24
2
J
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
(EQ. 6)
FIGURE 6. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB
WITH THERMAL VIAS θ vs EPAD-MOUNT
ΔT = T
– T
A(MAX)
J
J(MAX)
JA
COPPER LAND AREA ON PCB
FN6931.0
December 21, 2009
8
ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A.
OUT
J
L
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.2
0.6
0
+125°C
+25°C
-40°C
-0.6
-1.2
-1.8
-50 -25
0
25
50
75
100 125 150
0
1
2
3
4
5
6
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 8. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 7. OUTPUT VOLTAGE vs TEMPERATURE
1.8
1.2
5
4
3
2
1
0
0.6
0
+25°C
-40°C
-0.6
-1.2
-1.8
+125°C
0.25
OUTPUT CURRENT (mA)
0
0.50
0.75
1.00
2
3
4
5
6
INPUT VOLTAGE (V)
FIGURE 9. OUTPUT VOLTAGE vs OUTPUT CURRENT
FIGURE 10. GROUND CURRENT vs SUPPLY VOLTAGE
3.50
5.0
4.5
4.0
3.5
3.0
3.25
+125°C
3.00
2.75
2.50
2.25
2.00
1.75
1.50
-40°C
+25°C
V
= 6V
IN
2.5
2.0
1.5
1.0
0.5
0
0
0.25
0.50
0.75
1.00
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OUTPUT CURRENT (A)
FIGURE 11. GROUND CURRENT vs OUTPUT CURRENT
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
FN6931.0
December 21, 2009
9
ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C = 10µF, T = +25°C, I = 0A. (Continued)
IN OUT J L
OUT
200
190
180
170
160
150
140
130
120
110
100
90
200
190
180
170
160
150
140
130
120
110
100
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
V
= 2.5
V
= 2.5
OUT
0.8
OUT
10
10
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
0.2
0.4
0.6
1.0
OUTPUT CURRENT (A)
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
FIGURE 16. POWER-UP (V
= 2.2V)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
IN
FIGURE 17. POWER-DOWN (V
= 2.2V)
FIGURE 18. ENABLE START-UP
IN
FN6931.0
December 21, 2009
10
ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
J
L
300
250
200
150
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
FIGURE 19. ENABLE SHUTDOWN
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
3.5
2.5
300
250
200
150
100
50
2.0
6V
2.2V
1.5
1.0
0.5
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
FIGURE 21. START-UP TIME vs TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
FIGURE 24. CURRENT LIMIT RESPONSE
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
FN6931.0
December 21, 2009
11
ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C = 10µF, T = +25°C, I = 0A. (Continued)
IN OUT J L
FIGURE 26. LOAD TRANSIENT 0A TO 1A,
= 100µF CERAMIC
FIGURE 25. LOAD TRANSIENT 0A TO 1A,
= 10µF CERAMIC
C
C
OUT
OUT
FIGURE 28. LOAD TRANSIENT 10mA TO 1A,
= 100µF CERAMIC
FIGURE 27. LOAD TRANSIENT 10mA TO 1A,
= 10µF CERAMIC
C
C
OUT
OUT
90
80
70
60
50
40
30
20
10
0
2.2V
2V
2.5V
I
= 1A
100
OUT
10
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 29. I
TRANSIENT
FIGURE 30. PSRR vs V
IN
LINE
FN6931.0
December 21, 2009
12
ISL80101
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C = 10µF, T = +25°C, I = 0A. (Continued)
IN OUT J L
OUT
90
80
70
60
50
40
30
20
10
0
90
80
70
1A
60
100µF
50
40
30
20
10
47µF
10µF
100mA
I
= 1A
100
OUT
0
10
100
1k
10k
100k
1M
10
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 32. PSRR vs LOAD
FIGURE 31. PSRR vs C
OUT
10
1
0.1
0.01
I
LOAD
0.001
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 33. SPECTRAL NOISE DENSITY vs FREQUENCY
FN6931.0
December 21, 2009
13
ISL80101
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
12/21/09
FN6931.0
Initial Release to web
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80101
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6931.0
December 21, 2009
14
ISL80101
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
1
2
6
PIN 1
INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
10x 0.35
4
TOP VIEW
BOTTOM VIEW
C A B
M
0.10
(4X)
0.415
0.23
PACKAGE
OUTLINE
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
5
0.20 REF
0.05
C
1.60
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6931.0
December 21, 2009
15
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