ISL80103IR15Z-T [INTERSIL]
High Performance 2A and 3A LDOs; 高性能2A及3A的LDO
| 型号： | ISL80103IR15Z-T |
| 厂家： | 
Intersil |
| 描述： | High Performance 2A and 3A LDOs |
| 文件： | 总16页 (文件大小：618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 2A and 3A LDOs
ISL80102, ISL80103
Features
• 0.5% initial V
Accuracy
The ISL80102 and ISL80103 are low voltage,
OUT
high-current, single output LDOs specified for 2A and 3A
output current, respectively. These parts operate from
input voltages of 2.2V to 6V and are capable of providing
• Designed for 2.2V to 6V Input Supply
• ±1.8% Guaranteed V Accuracy for Junction
OUT
Temperature Range from -40°C to +125°C
• 185mV Dropout @ 3A, 125mV Dropout @ 2A
• Fast Load Transient Response
output voltages of 0.8V to 5V on the adjustable V
OUT
versions. Fixed output voltage options available in 0.8V,
1.2V, 1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom
voltage options available upon request.
• Rated Output Current Options of 2A and 3A
• Adjustable In-Rush Current Limiting
For applications that demand in-rush current less than
current limit, an external capacitor on the in-rush set pin
provides adjustment. The ENABLE feature allows the part
to be placed into a low quiescent current shutdown
mode. Sub-micron CMOS process is utilized for this
product family to deliver the best in class analog
performance and overall value.
• Fixed and Adjustable V
• 65dB Typical PSRR
Options Available
OUT
• Output Noise of 100µV
300kHz
between 300Hz to
RMS
• PG Feature
• 900mV Enable Input Threshold
• Short-Circuit Current Protection
• 1A Peak Reverse Current
These CMOS LDOs will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable a leading
class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
• Over-Temperature Shutdown
• Any Cap Stable with Minimum 10µF Ceramic
• Available in a 10 Ld DFN Package and soon to follow
TO220-5, TO263-5 and SOT223-5 (1A and 2A
versions)
Pin Configuration
• Pb-Free (RoHS Compliant)
ISL80102, ISL80103
(10 LD 3X3 DFN)
TOP VIEW
Applications*(see page 15)
• DSP, FPGA and µP Core Power Supplies
• Noise-Sensitive Instrumentation Systems
• Post Regulation of Switched Mode Power Supplies
• Industrial Systems
V
V
V
V
1
2
3
4
5
10
9
OUT
OUT
IN
IN
SENSE/ADJ
PG
DNC
8
7
ENABLE
SS
• Medical Equipment
GND
6
• Telecommunications and Networking Equipment
• Servers
• Hard Disk Drives (HD/HDD)
September 30, 2009
FN6660.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
3
V
Output voltage pin.
OUT
SENSE/ADJ
Remote voltage sense for internally fixed V
options. ADJ pin for externally set
OUT
V
.
OUT
4
PG
V
in regulation signal. Logic low defines when V
is not in regulation. Must be
OUT
OUT
grounded if not used.
5
6
GND
SS
GND pin.
External cap controls in-rush current.
7
ENABLE
DNC
V
independent chip enable. TTL and CMOS compatible.
IN
8
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
9, 10
EPAD
V
IN
Must be soldered directly to GND plane
Block Diagram
VIN
IL/10,000
M3
R4
M5
M4
10µA
10µA
M1
POWER PMOS
IL
VOUT
SNS
+
-
LEVEL
SHIFT
R8
R9
R1
R7
EN
EN
-
500mV
+
R2
R4
EN
ADJ
PG
+
-
EN
-
EN
SS
M7
+
-
M2
500mV
+
+
-
V TO I
R3
485mV
GND
FN6660.0
September 30, 2009
2
ISL80102, ISL80103
Typical Applications
1
9
V
V
OUT
OUT
2.5V ± 10%
V
V
1.8V ± 1.8%
IN
2
3
10
10µF
10µF
IN
SENSE/ADJ
100k
10k
ISL80102
ISL80103
4
7
6
ENABLE
SS
PG
(*Note 12)
GND
5
FIXED
FIGURE 1.
1
2
9
2.5V ± 10%
V
V
V
1.8V ± 1.8%
IN
OUT
10
ISL80102
ISL80103
10µF
V
10µF
OUT
IN
2.6k
1k
100k
10k
SENSE/ADJ
7
6
ENABLE
SS
4
PG
GND
(*NOTE 12)
5
ADJUSTABLE
FIGURE 2.
FN6660.0
September 30, 2009
3
ISL80102, ISL80103
Ordering Information
PART
MARKING
V
VOLTAGE
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
OUT
(Note 4)
PART NUMBER
ISL80102IRAJZ
(Notes 1, 3)
DZJA
ADJ
0.8V
1.2V
1.5V
1.8V
2.5V
3.3V
5.0V
ADJ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
ISL80102IR08Z
(Notes 1, 3)
DZKA
DZLA
DZMA
DZNA
DZPA
DZRA
DZSA
DZAA
DZBA
DZCA
DZDA
DZDA
DZEA
DZFA
DZGA
DZGA
DZHA
DZHA
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
ISL80102IR12Z
(Notes 1, 3)
ISL80102IR15Z
(Notes 1, 3)
ISL80102IR18Z
(Notes 1, 3)
ISL80102IR25Z
(Notes 1, 3)
ISL80102IR33Z
(Notes 1, 3)
ISL80102IR50Z
(Notes 1, 3)
ISL80103IRAJZ
(Notes 1, 3)
ISL80103IR08Z
(Notes 1, 3)
0.8V
1.2V
1.5V
1.5V
1.8V
2.5V
3.3V
3.3V
5.0V
5.0V
ISL80103IR12Z
(Notes 1, 3)
ISL80103IR15Z
(Note 3)
ISL80103IR15Z-T
(Notes 2, 3)
10 Ld 3x3 DFN
Tape and Reel
ISL80103IR18Z
(Notes 1, 3)
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
ISL80103IR25Z
(Notes 1, 3)
ISL80103IR33Z
(Note 3)
ISL80103IR33Z-T
(Notes 2, 3)
10 Ld 3x3 DFN
Tape and Reel
ISL80103IR50Z
(Note 3)
10 Ld 3x3 DFN
ISL80103IR50Z-T
(Notes 2, 3)
10 Ld 3x3 DFN
Tape and Reel
NOTES:
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For other output voltages, contact Intersil Marketing.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on
MSL please see techbrief TB363.
FN6660.0
September 30, 2009
4
ISL80102, ISL80103
Absolute Maximum Ratings (Note 8)
Thermal Information
V
V
relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
θ
JA (°C/W) θJC (°C/W)
45
IN
relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
OUT
10 Ld 3x3 DFN Package (Notes 6, 7)
4
PG, ENABLE, SENSE/ADJ, SS
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Recommended Operating Conditions
Junction Temperature Range (T ) . . . . . . . -40°C to +125°C
J
VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V
V
range . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5V
OUT
PG, ENABLE, SENSE/ADJ, SS relative to GND . . . . . 0V to 6V
PG sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
6. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
7. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
8. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified
conditions: V = V
+ 0.4V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A
IN OUT
OUT
IN
OUT J L
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Application Section” on page 7 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 9) TYP (Note 9) UNITS
DC CHARACTERISTICS
DC Output Voltage
Accuracy
V
V
Options: 0.8V, 1.2V, 1.5V and 1.8V
OUT
OUT
2.2V < V < 3.6V; 0A < I
< 3A
-1.8
0.5
1.8
%
IN LOAD
V
V
Options: 2.5V, 3.3V and 5.0V
OUT
OUT
+ 0.4V < V < 6V; 0A < I
IN LOAD
< 3A
-1.8
491
0.5
-1.8
509
%
Feedback Pin (ADJ option
only)
V
2.2V < V < 6V, 0A < I
IN LOAD
< 3A
500
mV
FB
/ΔV
DC Input Line Regulation
ΔV
V
V
+ 0.4V < V < 3.6V, V
= 1.8V
= 2.5V
0.1
0.1
0.4
0.8
%
%
OUT
IN
OUT
OUT
IN OUT
+ 0.4V < V < 6V, V
IN OUT
DC Output Load Regulation ΔV
/ΔI
0A < I
< 3A, All voltage options
< 2A, All voltage options
-0.8
-0.6
%
OUT
OU
LOAD
LOAD
T
0A < I
%
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
7.5
8.5
0.4
3.3
120
81
1
9
µA
mA
mA
µA
µA
mV
mV
A
ADJ
I
I
I
= 0A, 2.2V < V < 6V
IN
Q
LOAD
LOAD
= 3A, 2.2V < V < 6V
IN
12
Ground Pin Current in
Shutdown
I
ENABLE Pin = 0.2V, V = 5V
IN
SHDN
ENABLE Pin = 0.2V, V = 6V
IN
16
Dropout Voltage (Note 10)
V
I
I
= 3A, V
= 2A, V
= 2.5V
= 2.5V
185
125
DO
LOAD
LOAD
OUT
OUT
Output Short Circuit
Current (3A Version)
ISC
V
V
V
= 0V, V
+ 0.4V < V < 6V
IN
5.0
OUT
OUT
OUT
OUT
Output Short Circuit
Current (2A Version)
= 0V, V
+ 0.4V < V < 6V
IN
2.8
A
OUT
Thermal Shutdown
Temperature
+ 0.4V < V < 6V
IN
160
°C
TSD
FN6660.0
September 30, 2009
5
ISL80102, ISL80103
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified
conditions: V = V
+ 0.4V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A
IN OUT
OUT
IN
OUT J L
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Application Section” on page 7 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse
load techniques used by ATE to ensure T = T defines established limits. (Continued)
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
+ 0.4V < V < 6V
(Note 9) TYP (Note 9) UNITS
Thermal Shutdown
Hysteresis (Rising
Threshold)
V
15
°C
dB
TSDn
OUT
IN
AC CHARACTERISTICS
Input Supply Ripple
Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V = 2.2V
IN
55
62
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz
100
µV
LOAD
RMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
2.2V < V < 6V
IN
0.3
0.8
0.95
V
Hysteresis (rising
threshold)
Must be independent of V , 2.2V < V < 6V
IN IN
135
mV
Enable Pin Turn-on Delay
C
V
= 10µF, I
= 1A
150
µs
OUT
LOAD
Enable Pin Leakage Current
SOFT START CHARACTERISTICS
= 6V, EN = 3V
1
µA
IN
In-rush Current Limit
Adjust
R
323
-4.5
Ω
PD
I
-7
-2
µA
CHG
PG PIN CHARACTERISTICS
V
V
PG Flag Threshold
PG Flag Hysteresis
75
84
4
92
%V
OUT
OUT
OUT
%
mV
µA
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
I
= 500µA
47
100
1
SINK
V
= 6V, PG = 6V
0.05
IN
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
10. Dropout is defined by the difference in supply V and V
IN
when the supply produces a 2% drop in V
from its nominal
OUT
OUT
value.
11. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
12. Minimum cap on V and V
IN OUT
required for stability.
13. Used when large bulk capacitance required on V
for application.
OUT
FN6660.0
September 30, 2009
6
ISL80102, ISL80103
circuit performs as a constant current source when the
output current exceeds the current limit threshold noted
in the “Electrical Specifications” table on page 5. If the
Application Section
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 5. Minimum guaranteed input voltage is 2.2V.
short or overload condition is removed from V
, then
OUT
the output returns to normal voltage mode regulation. In
the event of an overload condition on the DFN package
the LDO will begin to cycle on and off due to the die
temperature exceeding thermal fault condition. The
TO220/263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if
the heatsink of this larger package can keep the die
temperature below the specified typical thermal
shutdown temperature.
However, due to the nature of an LDO, V must be some
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
IN
filtering (PSRR) is expected from V to V
. The
IN OUT
Dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
Functional Description
Enable Operation
The Enable turn-on threshold is typically 770mV with a
hysteresis of 135mV. The Enable pin doesn't have an
internal pull-up or pull-down resistor. As a result, this pin
External Capacitor Requirements
GENERAL GUIDELINE
must not be left floating. This pin must be tied to V if it
IN
External capacitors are required for proper operation.
Careful attention must be paid to layout guidelines and
selection of capacitor type and value to ensure optimal
performance.
is not used. A 1kΩ to 10kΩ pull-up resistor will be
required for applications that use open collector or open
drain outputs to control the Enable pin. The Enable pin
may be connected directly to V for applications that are
IN
always on.
OUTPUT CAPACITOR
Soft-Start Operation
The required minimum output capacitor is 10µF X5R/X7R
to ensure stable operation. Lower cost Y5V and Z5U type
ceramic capacitors are acceptable if the size of the
capacitor is larger to compensate for the significantly
lower tolerance over X5R/X7R types (approximately 2x).
Additional capacitors of any value in Ceramic, POSCAP or
Alum/Tantalum Electrolytic types may be placed in
parallel to improve PSRR at higher frequencies and/or
load transient AC output voltage tolerances. This
The soft start circuit controls the rate at which the output
voltage comes up to regulation at power-up or coming
out of a chip disable. A constant current charges an
external soft start capacitor. The external capacitor
always gets discharged to 0V at start-up of after coming
out of a chip disable. The discharge rate is the RC time
constant of R
and C . The soft-start function
PD
SS
effectively limits the amount of in-rush current below the
programmed current limit during start-up or an enable
sequence to avoid an overcurrent fault condition. This
can be an issue for applications that require large,
minimum capacitor must be connected to V
and
OUT
Ground pins of the LDO with PCB traces no longer than
0.5cm.
external bulk capacitances on V
charging current can be seen for a significant period of
time. High in-rush currents can cause V to drop below
where high levels of
OUT
INPUT CAPACITOR
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
minimum capacitor must be connected to V
Ground pins of the LDO with PCB traces no longer than
0.5cm.
IN
to shutdown. Figure 3
minimum which could cause V
shows the relationship between in-rush current and C
OUT
and
OUT
SS
with a C
of 1000µF.
OUT
5.0
Thermal Fault Protection
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +145°C.
The level of power combined with the thermal impedance
of the package (+50°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature specified in the “Electrical Specifications”
table on page 5 (see thermal packaging guidelines).
Current Limit Protection
0
20
40
Css (nF)
60
80
100
The ISL80102/3 family of LDOs incorporates protection
against overcurrent due to any short or overload
condition applied to the output pin. The current limit
FIGURE 3. IN-RUSH CURRENT vs SOFT-START
CAPACITANCE
FN6660.0
September 30, 2009
7
ISL80102, ISL80103
The maximum allowed junction temperature, T
J(MAX)
Power-Good Operation
The PGOOD circuit monitors V
and the maximum expected ambient temperature,
will determine the maximum allowed junction
and signals a fault
OUT
T
A(MAX)
temperature rise (ΔT ) as shown in Equation 4:
condition when V
is below 84% of the nominal output
OUT
J
voltage. The PGOOD flag is an open-drain NMOS that can
sink 10mA during a fault condition. The PGOOD pin
requires an external pull up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
(EQ. 4)
ΔT = T
– T
A(MAX)
J
J(MAX)
be pulled up to a voltage source greater than V . During
IN
To calculate the maximum ambient operating
temperature, use the junction-to-ambient thermal
a fault condition, the PGOOD output is pulled low. The
PGOOD fault can be caused by the current limit fault or
low input voltage. The PGOOD does not function during
thermal shutdown and when the part is disabled.
resistance (θ ) for the DFN package with Equation 5:
JA
(EQ. 5)
P
= (T
– T ) ⁄ θ
J(MAX) A JA
D(MAX)
Output Voltage Selection
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
and 5V. An external resistor divider, R and R , is used to
Substitute P for P
and the maximum ambient
operating temperature can be found by solving for T
D
D(MAX)
A
using Equation 6:
(EQ. 6)
1
2
T
= T
– P
× θ
D(MAX) JA
A
JMAX
set the output voltage as shown in Equation 1. The
recommended value for R is 500Ω to 1kΩ. R is then
chosen according to Equation 2:
2
1
Heatsinking The DFN Package
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 4
R
⎛
⎜
⎝
⎞
1
(EQ. 1)
(EQ. 2)
------
V
= 0.5V ×
+ 1
⎟
OUT
R
2
⎠
shows a curve for the θ of the DFN package for
JA
different copper area sizes.
V
OUT
0.5V
⎛
⎝
⎞
46
---------------
R
= R
×
2
– 1
1
⎠
44
42
40
38
36
34
Power Dissipation
The junction temperature must not exceed the range
specified in the Recommended Operating Conditions. The
power dissipation can be calculated by using Equation 3:
2
4
6
8
10 12 14 16 18 20 22 24
2
(EQ. 3)
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
P
= (V – V
) × I
+ V × I
GND
D
IN
OUT
OUT
IN
FIGURE 4. 3mmx3mm-10 Pin DFN ON 4-LAYER PCB
WITH THERMAL VIAS θ vs EPAD-MOUNT
JA
COPPER LAND AREA ON PCB
FN6660.0
September 30, 2009
8
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A.
OUT
J
L
1.8
1.2
0.6
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+125°C
+25°C
-40°C
-0.6
-1.2
-1.8
0
1
2
3
4
5
6
-50
-25
0
25
50
75
100 125 150
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 6. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 5. OUTPUT VOLTAGE vs TEMPERATURE
1.8
1.2
9
8
7
6
5
4
3
2
1
0
0.6
+25°C
0.0
-0.6
-40°C
-1.2
+125°C
-1.8
0
0.5
1.0
1.5
2.0
2.5
3.0
2
3
4
5
6
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE
FIGURE 7. OUTPUT VOLTAGE vs OUTPUT CURRENT
12.0
11.5
9.1
8.9
11.0
10.5
10.0
9.5
-40°C
8.7
-40°C
8.5
8.3
+25°C
8.1
9.0
+125°C
7.9
7.7
7.5
+125°C
1.0
8.5
+25°C
2.0
8.0
7.5
0
0.5
1.5
2.0
2.5
3.0
0.8
1.4
2.6
3.2
3.8
4.4
5.0
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
FIGURE 10. GROUND CURRENT vs OUTPUT VOLTAGE
FIGURE 9. GROUND CURRENT vs OUTPUT CURRENT
FN6660.0
September 30, 2009
9
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
OUT
IN
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
10
9
8
7
6
5
4
3
2
V
= 5V
IN
V
= 6V
IN
1
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. SHUTDOWN CURRENT vs TEMPERATURE
FIGURE 11. SHUTDOWN CURRENT vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
2A
3A
40
30
20
10
1A
0
0
0.5
1.0
1.5
2.0
2.5
3.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OUTPUT CURRENT (A)
FIGURE 13. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 14. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
V
(1V/DIV)
IN
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TIME (10ms/DIV)
JUNCTION TEMPERATURE (°C)
FIGURE 16. POWER-UP (V
= 2.2V)
FIGURE 15. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
IN
FN6660.0
September 30, 2009
10
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
EN (1V/DIV)
V
(1V/DIV)
IN
SS (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
V
(1V/DIV)
OUT
OUT
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (10ms/DIV)
FIGURE 18. ENABLE START-UP
FIGURE 17. POWER-DOWN (V
= 2.2V)
IN
300
250
200
150
100
50
EN (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
TIME (5ms/DIV)
INPUT VOLTAGE (V)
FIGURE 19. ENABLE SHUTDOWN
FIGURE 20. START-UP TIME vs SUPPLY VOLTAGE
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
300
250
200
150
100
50
ISL80103
ISL80102
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 21. START-UP TIME vs TEMPERATURE
FIGURE 22. CURRENT LIMIT vs TEMPERATURE
FN6660.0
September 30, 2009
11
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
ISL80102
VOUT (1V/DIV)
IOUT (1A/DIV)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
TIME (10ms/DIV)
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80102)
FIGURE 23. CURRENT LIMIT vs SUPPLY VOLTAGE
V
(1V/DIV)
OUT
V
(1V/DIV)
OUT
I
(1A/DIV)
OUT
I
(2A/DIV)
OUT
TIME (100ms/DIV)
TIME (20ms/DIV)
FIGURE 25. THERMAL CYCLING (ISL80102)
FIGURE 26. CURRENT LIMIT RESPONSE (ISL80103)
EN (1V/DIV)
V
(1V/DIV)
OUT
I
(2A/DIV)
(1V/DIV)
OUT
I
(2A/DIV)
OUT
V
OUT
TIME (1ms/DIV)
TIME (50ms/DIV)
FIGURE 28. IN-RUSH CURRENT WITH NO
SOFT-START CAPACITOR, C
FIGURE 27. THERMAL CYCLING (ISL80103)
= 1000µF
OUT
FN6660.0
September 30, 2009
12
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
EN (1V/DIV)
EN (1V/DIV)
I
(2A/DIV)
(1V/DIV)
I
(2A/DIV)
OUT
OUT
V
(1V/DIV)
V
OUT
OUT
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE 29. IN-RUSH WITH 22nF SOFT-START
CAPACITOR, C = 1000µF
FIGURE 30. IN-RUSH WITH 47nF SOFT-START
CAPACITOR, C = 1000µF
OUT
OUT
V
(50mV/DIV)
V
(50mV/DIV)
OUT
OUT
3A
3A
0A
0A
I
(2A/DIV)
I
(2A/DIV)
OUT
OUT
TIME (100µs/DIV)
TIME (100µs/DIV)
FIGURE 31. LOAD TRANSIENT 0A TO 3A,
= 10µF CERAMIC
FIGURE 32. LOAD TRANSIENT 0A TO 3A,
= 10µF CERAMIC + 100µF OSCON
C
C
OUT
OUT
V
(50mV/DIV)
(2A/DIV)
OUT
V
(50mV/DIV)
(2A/DIV)
OUT
I
3A
OUT
3A
I
OUT
1A
1A
TIME (100µs/DIV)
TIME (100µs/DIV)
FIGURE 33. LOAD TRANSIENT 1A TO 3A,
FIGURE 34. LOAD TRANSIENT 1A TO 3A,
= 10µF CERAMIC + 100µF OSCON
C
= 10µF CERAMIC
C
OUT
OUT
FN6660.0
September 30, 2009
13
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
3.2V
2.2V
80
70
60
50
40
30
20
10
0
100mA
1A
V
(1V/DIV)
IN
V
(10mV/DIV)
OUT
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
TIME (200µs/DIV)
FIGURE 35. LINE TRANSIENT
FIGURE 36. PSRR vs LOAD
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
100µF
2.5V
2.2V
2V
47µF
10µF
I
= 1A
100
L
I
= 100mA
L
10
100
1k
10k
100k
1M
10
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 38. PSRR vs V
IN
FIGURE 37. PSRR vs C
OUT
10
1
0.1
0.01
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 39. SPECTRAL NOISE DENSITY vs FREQUENCY
FN6660.0
September 30, 2009
14
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
09/30/09
FN6660.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80102, ISL80103
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6660.0
September 30, 2009
15
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
1
2
6
PIN 1
INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
10x 0.35
4
TOP VIEW
BOTTOM VIEW
C A B
M
0.10
(4X)
0.415
0.23
PACKAGE
OUTLINE
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
5
0.20 REF
0.05
C
1.60
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6660.0
September 30, 2009
16
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