ISL8018EVAL3Z [INTERSIL]
8A Low Quiescent Current High Efficiency Synchronous Buck Regulator;
| 型号： | ISL8018EVAL3Z |
| 厂家： | 
Intersil |
| 描述： | 8A Low Quiescent Current High Efficiency Synchronous Buck Regulator |
| 文件： | 总21页 (文件大小：843K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
8A Low Quiescent Current High Efficiency Synchronous
Buck Regulator
ISL8018
Features
The ISL8018 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 8A continuous
output current from a 2.7V to 5.5V input supply. The output
• High efficiency synchronous buck regulator with up to 97%
efficiency
• ±10% output voltage margining
• Adjustable current limit
voltage is adjustable from 0.6V to V . With an adjustable current
limit, reverse current protection, prebias start and
IN
over-temperature protection, the ISL8018 offers a highly robust
power solution. It uses current control architecture to deliver fast
transient response and excellent loop stability.
• Start-up with prebiased output
• Internal soft-start - 1ms or adjustable, internal/external
compensation
The ISL8018 integrates a pair of low ON-resistance P-channel
and N-channel internal MOSFETs to maximize efficiency and
minimize external component count. 100% duty-cycle operation
allows less than 250mV dropout at 8A output current. Adjustable
frequency and synchronization allow the ISL8018 to be used in
applications requiring low noise.
• Soft-stop output discharge during disabled
• Adjustable frequency from 500kHz to 4MHz - default at 1MHz
• External synchronization up to 4MHz - master to slave phase
shifting capability
• Peak current limiting, hiccup mode short-circuit protection and
over-temperature protection
The ISL8018 can be configured for discontinuous or forced
continuous operation at light load. Forced continuous operation
reduces noise and RF interference while discontinuous mode
provides high efficiency by reducing switching losses at light loads.
Applications
• DC/DC POL modules
The ISL8018 is offered in a space saving 20 Ld 3x4 QFN lead free
package with exposed pad lead frames for excellent thermal
performance. The complete converter occupies less than
• µC/µP, FPGA and DSP power
• Plug-in DC/DC modules for routers and switchers
• Portable instruments
2
96.8mm area.
• Test and measurement systems
• Li-ion battery powered devices
See Ordering Information on page 2 for more detail.
Related Literature
• UG052 “ISL8018DEMO1Z Demonstration Board User Guide”
• UG053 “ISL8018EVAL3Z Evaluation Board User Guide”
100
95
3.3V
OUT
PFM
90
85
80
75
70
3.3V
OUT
PWM
0
1
2
3
4
5
6
7
8
I
(A)
OUT
FIGURE 1. EFFICIENCY T = +25°C V = 5V
IN
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL8018
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
OUTPUT VOLTAGE
(V)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
PART MARKING
ISL8018IRAJZ
018A
Adjustable
-40 to +85
20 Ld 3x4 QFN
L20.3x4
ISL8018EVAL3Z
ISL8018DEMO1Z
NOTES:
Evaluation Board
Demonstration Board
1. Add “-T” suffix for 6k units or “-T7A” suffix for 250 units Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8018. For more information on MSL please see techbrief TB363.
Pin Configuration
ISL8018
(20 LD QFN)
TOP VIEW
20
18
19
17
1
2
3
4
5
COMP
16
PGND
PHASE
PHASE
PHASE
VIN
15 SS
ISET
14
13
PAD
VSET
FS
12
11
VIN
EN
6
10
8
7
9
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ISL8018
Pin Descriptions
PIN
1, 19, 20
2, 3, 4
5, 6, 7
8
SYMBOL
PGND
PHASE
VIN
DESCRIPTION
Power ground.
Switching node connection. Connect to one terminal of the inductor.
Input supply voltage. Connect two 22µF ceramic capacitors to power ground.
PG
Power-good is an open-drain output. Use 10kΩ to 100kΩ pull-up resistor connected between VIN and
PG. At power-up or EN HI, PG rising edge is delayed by 1ms from the output reaching regulation.
9
SYNCOUT
SYNCIN
This pin outputs a 250µA current source that is turned on at the rising edge of the internal clock or
SYNCIN. When SYNCOUT voltage reaches 0.8V, a reset circuit will activate and discharge SYNCOUT to
0V. SYNCOUT is held at 0V in PFM light load to reduce quiescent current.
10
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or
ground for PFM mode. Connect to an external function generator for synchronization with the positive
edge trigger. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state if SYNCIN
is floating.
11
12
EN
FS
Regulator enable pin. Enables the output when driven to high. Shuts down the chip and discharges the
output capacitor when driven to low.
This pin sets the oscillator switching frequency, using a resistor, R , from the FS pin to GND. The
FS
frequency of operation may be programmed between 500kHz to 4MHz. The default frequency is 1MHz
and configured for internal compensation if FS is connected to VIN.
13
14
VSET
ISET
VSET is the output margining setting of the regulators. Connect to SGND for -10%, keep it floating for
no margining and connect to VIN for +10%.
ISET is the peak output current limit and skip current limit setting of the regulators. Connect to SGND
for 3A, to VIN for 5A and keep it floating for 8A.
15
SS
SS is used to adjust the soft-start time. Set to SGND for internal 1ms rise time. Connect a capacitor
from SS to SGND to adjust the soft-start time. Do not use more than 33nF per IC.
16, 17
COMP, VFB
The feedback network of the regulator, VFB, is the negative input to the transconductance error
amplifier. COMP is the output of the amplifier if the FS resistor is used. If internal compensation is used
(FS = VIN), the comp pin should be tied to SGND. The output voltage is set by an external resistor divider
connected to VFB. With a properly selected divider, the output voltage can be set to any voltage
between VIN and the 0.6V reference. While internal compensation offers a solution for many typical
applications, an external compensation network may offer improved performance for some designs.
In addition to regulation, VFB is also used to determine the state of PG.
18
SGND
EPAD
Signal ground.
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many
vias as possible under the pad connecting to the system GND plane for optimal thermal performance.
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ISL8018
Typical Application Diagrams
OUTPUT
1.8V/8A
L
1µH
INPUT
2.7V TO 5.5V
VIN
EN
PHASE
C
2
2x47µF
ISL8018
C
1
2x22µF
R
1
100k
R
200k
C *
3
15pF
2
PGND
SGND
PG
R
3
SYNCIN
100k
SYNCOUT
FS
VIN
VFB
COMP
SS
ISET
* C is optional. Recommend
3
putting a placeholder for it. Check
loop analysis first before use.
VSET
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE CHIP 8A
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ISL8018
Block Diagram
COMP
55pF
FS
SYNCIN
SYNCOUT
SS
SOFT-
SHUTDOWN
START
SHUTDOWN
168k
250µA
VDD
+
+
VIN
EN
OSCILLATOR
VREF
BANDGAP
+
EAMP
COMP
-
P
-
PWM/PFM
LOGIC
PHASE
PGND
VSET
VFB
CONTROLLER
PROTECTION
HS DRIVER
3pF
LS
DRIVER
N
+
SLOPE
COMP
6k
+
-
0.8V
-
CSA
+
OV
+
OCP
-
-
0.85*VREF
ISET
ISET
THRESHOLD
+
UV
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
-
SCP
+
0.1V
100
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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ISL8018
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, ISET, PG, SYNCOUT, SYNCIN VFB, VSET . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Thermal Resistance (Typical)
3x4 QFN Package (Notes 4, 5) . . . . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
42
(°C/W)
5
JA
JC
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . .1.5V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . .100mA at +85°C
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 8A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: T = -40°C to +85°C, V = 3.6V, EN = V , unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across
A
IN
IN
A
the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
INPUT SUPPLY
Undervoltage Lockout Threshold
V
V
Rising, no load
2.5
2.4
70
2.7
V
V
IN
UVLO
Falling, no load
2.2
Quiescent Supply Current
I
SYNCIN = GND, no load at the output
µA
µA
VIN
SYNCIN = GND, no load at the output and no
switches switching
70
95
15
SYNCIN = VIN, f
output
= 1MHz, no load at the
8
5
mA
µA
SW
Shutdown Supply Current
OUTPUT REGULATION
Reference Voltage
I
SYNCIN = GND, V = 5.5V, EN = low
IN
9.5
SD
V
V
V
V
V
V
= V
IN
0.651
0.594
0.531
9.5
0.660
0.600
0.540
10
0.669
0.606
0.549
10.5
V
V
REF
SET
SET
SET
SET
SET
= FLOAT
= SGND
V
Output Voltage Margining
V
= V , percent of output changed
IN
%
VFB
= SGND, percent of output changed
-10.5
-10
-9.5
%
VFB Bias Current
I
I
VFB = 0.75V
0.1
µA
µA
%/V
ms
µA
VFB
Fixed Output VFB Bias Current
Line Regulation
V
V
= FLOAT, VFB = 10% above output
6
VFB
SET
= V + 0.5V to 5.5V (minimal 2.7V)
0.2
IN
O
Soft-Start Ramp Time Cycle
Soft-Start Charging Current
OVERCURRENT PROTECTION
Current Limit Blanking Time
SS = SGND
= 0.1V
1
ISS
V
1.4
1.8
2.2
SS
t
17
8
Clock
pulses
OCON
Overcurrent and Auto Restart Period
t
SS cycle
OCOFF
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ISL8018
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: T = -40°C to +85°C, V = 3.6V, EN = V , unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across
A
IN
IN
A
the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
IPLIMIT
TEST CONDITIONS
(Note 6)
TYP
12.8
8.8
(Note 6)
UNIT
A
Positive Peak Current Limit
I
I
I
I
I
I
= FLOAT
9.7
6.7
4
15.8
10.9
7.2
SET
SET
SET
SET
SET
SET
= V
A
IN
= SGND
= FLOAT
5.6
A
Peak Skip Limit
I
2.18
1.08
2.8
3.78
2.3
A
SKIP
= V
1.66
1.05
A
IN
= SGND
A
Zero Cross Threshold
-300
300
mA
A
Negative Current Limit
COMPENSATION
INLIMIT
-4.25
-3
-1.75
Error Amplifier Transconductance
FS = V
IN
100
200
0.11
µA/V
µA/V
Ω
FS with resistor
Transresistance
RT
PHASE
P-Channel MOSFET ON-Resistance
V
V
V
V
= 5V, I = 200mA
31
44
45
55
35
50
mΩ
mΩ
mΩ
mΩ
%
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 5V, I = 200mA
19
O
= 2.7V, I = 200mA
25
O
PHASE Maximum Duty Cycle
PHASE Minimum On-Time
OSCILLATOR
100
SYNCIN = High
140
ns
Nominal Switching Frequency
f
FS = V
800
440
1000
520
3700
0.75
0.15
3.6
1200
600
kHz
kHz
kHz
V
SW
IN
FS with RS = 402kΩ
FS with RS = 42.4kΩ
3200
0.70
4200
0.80
SYNCIN Logic Low to High Transition Range
SYNCIN Hysteresis
V
SYNCIN Logic Input Leakage Current
SYNCOUT Charging Current
V
= 3.6V
5
µA
µA
µA
V
IN
PWM
PFM
210
250
0
290
ISO
SYNCOUT Voltage Low
PG
0.3
Output Low Voltage
0.3
2
V
ms
µA
V
Delay Time (Rising Edge)
PG Pin Leakage Current
OVP PG Rising Threshold
UVP PG Rising Threshold
UVP PG Hysteresis
0.5
80
1
0.01
0.80
85
5
0.1
90
%
%
PGOOD Delay Time (Falling Edge)
7
µs
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ISL8018
Analog Specifications All parameter limits are established across the recommended operating conditions and are measured at the
following conditions: T = -40°C to +85°C, V = 3.6V, EN = V , unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across
A
IN
IN
A
the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNIT
ISET, VSET
Logic Input Low
0.4
0.8
V
V
Logic Input Float
Logic Input High
0.5
0.9
V
Logic Input Leakage Current
EN
0.1
1
0.4
1
µA
Logic Input Low
V
Logic Input High
0.9
V
EN Logic Input Leakage Current
Thermal Shutdown
Thermal Shutdown Hysteresis
NOTE:
0.1
150
25
µA
°C
°C
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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ISL8018
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = 3.3V,
A
IN
SYNCIN = V , L = 1µH, C = 2x22µF, C = 4x22µF, V
= 1.8V, I = 0A to 8A.
OUT
IN
1
2
OUT
100
100
90
80
70
60
50
40
2.5V
2.5V
OUT
OUT
90
80
70
60
50
40
1.2V
1.2V
OUT
OUT
1.5V
1.5V
OUT
OUT
1.8V
OUT
1.8V
OUT
0
1
2
3
4
5
6
7
8
0
1
2
3
4
I
5
6
7
8
(A)
I
(A)
OUT
OUT
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3V PWM)
IN
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3V PFM)
IN
100
100
90
80
70
60
50
40
3.3V
OUT
3.3V
OUT
2.5V
2.5V
OUT
OUT
90
80
70
60
50
40
1.2V
OUT
1.2V
OUT
1.5V
1.5V
OUT
OUT
1.8V
1.8V
OUT
OUT
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
I
(A)
I
(A)
OUT
OUT
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5V PWM)
IN
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5V PFM)
IN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.815
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.775
0A LOAD
5V PWM MODE
IN
3.3V PWM MODE
IN
4A LOAD
8A LOAD
2.5 2.8
3.1
3.4
3.7
4.0
(A)
4.3
4.6
4.9
5.2
5.5
0
1
2
3
4
5
6
7
8
I
(A)
I
OUT
OUT
FIGURE 8. POWER DISSIPATION vs LOAD (1MHz, V
OUT
= 1.8V)
FIGURE 9. V
REGULATION vs V (PWM V = 1.8V)
IN OUT
OUT
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ISL8018
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = 3.3V,
A
IN
SYNCIN = V , L = 1µH, C = 2x22µF, C = 4x22µF, V
= 1.8V, I
OUT
= 0A to 8A. (Continued)
IN
1
2
OUT
1.847
1.839
1.831
1.823
1.815
1.807
1.799
1.791
1.783
1.775
1.230
0A LOAD
1.224
1.218
1.212
1.206
1.200
1.194
1.188
1.182
3.3V PFM MODE
IN
5V PFM MODE
IN
3.3V PWM MODE
IN
4A LOAD
5V PWM MODE
IN
8A LOAD
4.0 4.3
(A)
2.5
2.8
3.1
3.4
3.7
4.6
4.9
5.2
5.5
0
1
2
3
4
5
6
7
8
8
8
I
I
(A)
OUT
OUT
FIGURE 10. V
OUT
REGULATION vs V (PFM V
IN
= 1.8V)
FIGURE 11. V
REGULATION vs LOAD (1MHz, V
= 1.2V)
OUT
OUT
OUT
1.527
1.521
1.515
1.509
1.503
1.497
1.491
1.485
1.479
1.829
3.3V PFM MODE
IN
3.3V PFM MODE
IN
1.822
1.815
1.808
1.801
1.794
1.787
1.780
1.773
5V PFM MODE
IN
5V PFM MODE
IN
3.3V PWM MODE
IN
3.3V PWM MODE
IN
5V PWM MODE
5V PWM MODE
IN
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
I
(A)
I
(A)
OUT
OUT
FIGURE 12. V
REGULATION vs LOAD (1MHz, V
= 1.5V)
FIGURE 13. V
REGULATION vs LOAD (1MHz, V
= 1.8V)
OUT
OUT
OUT
OUT
2.532
3.36
5V PFM MODE
IN
3.3V PFM MODE
IN
2.524
2.516
2.508
2.500
2.492
2.484
2.476
2.468
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
5V PFM MODE
IN
5V PWM MODE
IN
3.3V PWM MODE
IN
5V PWM MODE
IN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
I
(A)
I
(A)
OUT
OUT
FIGURE 14. V
OUT
REGULATION vs LOAD (1MHz, V
= 2.5V)
FIGURE 15. V
OUT
REGULATION vs LOAD (1MHz, V
= 3.3V)
OUT
OUT
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ISL8018
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = 3.3V,
A
IN
SYNCIN = V , L = 1µH, C = 2x22µF, C = 4x22µF, V
= 1.8V, I = 0A to 8A. (Continued)
OUT
IN
1
2
OUT
PHASE 2V/DIV
PHASE 2V/DIV
V
RIPPLE 20mV/DIV
OUT
V
RIPPLE 20mV/DIV
IL 1A/DIV
OUT
IL 1A/DIV
500ns/DIV
2µs/DIV
FIGURE 16. STEADY STATE OPERATION AT NO LOAD (PWM)
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PFM)
PHASE 2V/DIV
V
RIPPLE 50mV/DIV
OUT
IL 2A/DIV
V
RIPPLE 20mV/DIV
OUT
IL 2A/DIV
500ns/DIV
1ms/DIV
FIGURE 18. STEADY STATE OPERATION WITH FULL LOAD
FIGURE 19. LOAD TRANSIENT (PWM)
V
RIPPLE 50mV/DIV
OUT
EN 2V/DIV
V
1V/DIV
OUT
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
1ms/DIV
5ms/DIV
FIGURE 20. LOAD TRANSIENT (PFM)
FIGURE 21. SOFT-START WITH NO LOAD (PWM)
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ISL8018
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = 3.3V,
A
IN
SYNCIN = V , L = 1µH, C = 2x22µF, C = 4x22µF, V
= 1.8V, I
OUT
= 0A to 8A. (Continued)
IN
1
2
OUT
EN 5V/DIV
V
1V/DIV
OUT
EN 2V/DIV
V
1V/DIV
OUT
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
5ms/DIV
5ms/DIV
FIGURE 22. SOFT-START AT NO LOAD (PFM)
FIGURE 23. SOFT-START WITH PREBIASED 1V
EN 2V/DIV
1V/DIV
V
OUT
EN 2V/DIV
1V/DIV
V
OUT
IL 2A/DIV
PG 5V/DIV
IL 2A/DIV
PG 5V/DIV
5ms/DIV
500µs/DIV
FIGURE 24. SOFT-START AT FULL LOAD
FIGURE 25. SOFT-DISCHARGE SHUTDOWN
PHASE 5V/DIV
PHASE 5V/DIV
IL 2A/DIV
V
RIPPLE 20mV/DIV
IL 1A/DIV
OUT
V
RIPPLE 20mV/DIV
OUT
SYNC 5V/DIV
200ns/DIV
SYNC 5V/DIV
200ns/DIV
FIGURE 26. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
FIGURE 27. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
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ISL8018
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = 3.3V,
A
IN
SYNCIN = V , L = 1µH, C = 2x22µF, C = 4x22µF, V
= 1.8V, I = 0A to 8A. (Continued)
OUT
IN
1
2
OUT
PHASE 5V/DIV
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
IL 2A/DIV
OUT
V
RIPPLE 20mV/DIV
IL 0.2A/DIV
OUT
SYNC 5V/DIV
SYNC 5V/DIV
100ns/DIV
100ns/DIV
FIGURE 28. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
FIGURE 29. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH
FREQUENCY = 4MHz
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
OUT
V
1V/DIV
OUT
IL 5A/DIV
IL 5A/DIV
PG 5V/DIV
PG 5V/DIV
10µs/DIV
2ms/DIV
FIGURE 30. OUTPUT SHORT-CIRCUIT
FIGURE 31. OUTPUT SHORT-CIRCUIT RECOVERY
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ISL8018
with the 55pF and 168kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 2.4V.
Theory of Operation
The ISL8018 is a step-down switching regulator optimized for
battery-powered handheld applications. The regulator operates at
1MHz fixed default switching frequency when FS is connected to
VIN. By connecting a resistor from FS to SGND, the operating
frequency may be adjusted from 500kHz to 4MHz. Unless forced
and PWM is chosen (SYNCIN pulled HI), the regulator will allow
PFM operation and reduce switching frequency at light loading to
maximize efficiency. In this condition, no load quiescent is typically
70µA.
V
EAMP
V
CSA
DUTY
CYCLE
I
L
PWM Control Scheme
V
OUT
Pulling the SYNCIN high (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8018 employs the
current-mode Pulse Width Modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. Figure 3
shows the block diagram. The current loop consists of the oscillator,
the PWM comparator, current sensing circuit and the slope
compensation for the current loop stability. The slope compensation
is 360mV/Ts. Current sense resistance, Rt, is typically 0.11V/A. The
control reference for the current loop comes from the error
amplifier's (EAMP) output.
FIGURE 32. PWM OPERATION WAVEFORMS
Skip Mode
Pulling the SYNCIN pin LO (<0.4V) forces the converter into PFM
mode. The ISL8018 enters a pulse-skipping mode at light load to
minimize the switching loss by reducing the switching frequency.
Figure 33 illustrates the Skip mode operation. A zero-cross
sensing circuit shown in Figure 3 monitors the N-FET current for
zero crossing. When 8 consecutive cycles of the inductor current
crossing zero are detected, the regulator enters the Skip mode.
During the eight detecting cycles, the current in the inductor is
allowed to become negative. The counter is reset to zero when
the current in any cycle does not cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA and the slope compensation
reaches the control reference of the current loop, the PWM
comparator EAMP output sends a signal to the PWM logic to turn
off the P-FET and turn on the N-channel MOSFET. The N-FET stays
on until the end of the PWM cycle. Figure 32 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output.
Once the Skip mode is entered, the pulse modulation starts being
controlled by the skip comparator shown in Figure 33. Each pulse
cycle is still synchronized by the PWM clock. The P-FET is turned on
at the clock's rising edge and turned off when the output is higher
than 1.5% of the nominal regulation or when its current reaches
the peak skip current limit value. Then the inductor current is
discharging to 0A and stays at zero. The internal clock is disabled.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage drops to
the nominal voltage, the P-FET will be turned on again at the rising
edge of the internal clock as it repeats the previous operations.
The output voltage is regulated by controlling the V
EAMP
voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
PWM
0.8V
PFM
PWM
SYNCOUT
CLOCK
8 CYCLES
PFM CURRENT LIMIT
LOAD CURRENT
I
L
0
NOMINAL +1.5%
V
OUT
NOMINAL -1.5%
NOMINAL
FIGURE 33. SKIP MODE OPERATION WAVEFORMS
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ISL8018
Frequency Adjust
The frequency of operation is fixed at 1MHz and internal
PHASE1
CLOCK1
compensation when FS is tied to VIN. Adjustable frequency ranges
from 500kHz to 4MHz via a simple resistor connecting FS to SGND
according to Equation 1:
3
0.8V
220 10
0.75V
------------------------------
(EQ. 1)
R k =
– 14
SYNCIN_S
T
f
kHz
OSC
SYNCOUT_M
w/Cap
Figure 34 is a graph of the measured Frequency vs RT for a VIN of
2.7V and 5.5V.
20nsDELAY
PHASE2
4200
3500
2800
2100
FIGURE 35. SYNCHRONIZATION WAVEFORMS
Figure 36 is a graph of the master to slave phase shift vs SYNCOUT
capacitance for 1MHz switching operation.
300
250
200
V
= 5.5V
IN
1400
V
= 2.7V
70
IN
700
0
150
0
140
210
280
350
420
PHASE SHIFT
MEASUREMENT
RT (kΩ)
100
FIGURE 34. FREQUENCY vs RT
50
0
PHASE SHIFT
CALCULATION
Synchronization Control
The ISL8018 can be synchronized from 500kHz to 4MHz by an
external signal applied to the SYNCIN pin. SYNCIN frequency should
be greater than 50% of internal clock frequency. The rising edge on
the SYNCIN triggers the rising edge of the PHASE pulse. Make sure
that the minimum on time of the PHASE node is greater than
140ns.
0
40
80
120
(pF)
160
200
240
C
13
FIGURE 36. PHASE SHIFT vs CAPACITANCE
Overcurrent Protection
SYNCOUT is a 250µA current pulse signal that is triggered on the
rising edge of the clock or SYNCIN signal (whichever is greater in
frequency). This drives other ISL8018s and avoids system beat
frequency effects. See Figure 35 for more detail. The current
pulse is terminated and SYNCOUT is discharged to 0V after 0.8V
threshold is reached. SYNCOUT is 0V if the regulator operates at
light PFM load.
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in Figure 3 on page 5.
The current sensing circuit has a gain of 0.11V/A, from the P-FET
current to the CSA output. When the CSA output reaches a
threshold set by ISET, the OCP comparator is tripped to turn off the
P-FET immediately. See “Analog Specifications” on page 6 of the
OCP threshold for various ISET configurations. The overcurrent
function protects the switching converter from a shorted output by
monitoring the current flowing through the upper MOSFET.
To implement time shifting between the master circuit to the
slave, it is recommended to add a capacitor, C as shown in
13
Figure 3 on page 5. The time delay from SYNCOUT_Master to
SYNCIN_Slave as shown in Figure 3 on page 5 is calculated in pF
using Equation 2:
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the overcurrent fault counter is set to 1. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC fault counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shut down under an
overcurrent fault condition. An overcurrent fault condition will
result in the regulator attempting to restart in a hiccup mode
within the delay of eight soft-start periods. At the end of the eight
soft-start wait period, the fault counters are reset and soft-start is
attempted again. If the overcurrent condition goes away during
the delay of eight soft-start periods, the output will resume back
into regulation point after hiccup mode expires. When an
C
pF = 0.333 t – 20ns
(EQ. 2)
13
Where t is the desired time shift between the master and the
slave circuits in ns. Care must be taken to include PCB parasitic
capacitance of ~3pF to 10pF.
The maximum should be limited to 1/f -100ns to insure that
SW
SYNCOUT has enough time to discharge before the next cycle
starts.
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ISL8018
overcurrent condition happens at low V , it is recommended to
IN
18
15
12
9
add more input capacitance, so the valley of V is always above
IN
UVLO to maintain normal operation.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side N-FET, as shown in
Figure 3 on page 5. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.
The 100Ω in parallel to the N-FET will activate discharging the
output into regulation. The control will begin to switch when output
is within regulation. The regulator will be in PFM for 20µs before
switching to PWM if necessary.
SS (ms)
MEASUREMENT
6
SS (ms)
CALCULATION
3
0
0
8
16
24
(nF)
32
40
48
C
SS
PG
PG is an open-drain output of a window comparator that
FIGURE 37. SOFT-START TIME vs C
SS
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within
nominal regulation voltage set by VFB. When VFB drops 15%
below or raises 0.8V above the nominal regulation voltage, the
ISL8018 pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
Enable
The enable (EN) input allows the user to control the turning on or
off of the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference and then the soft start-up
begins.
output voltages, connect an external pull-up resistor, R , between
PG and VIN. A 100kΩ resistor works well in most applications.
Discharge Mode (Soft-Stop)
1
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch. The discharge mode is disabled if SS is tied to an external
capacitor.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 31mΩ and the
ON-resistance for the N-FET is typically 19mΩ.
Soft Start-Up
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz so that the output can start up smoothly at light load
condition. During soft-start, the IC operates in the Skip mode to
support prebiased output condition.
100% Duty Cycle
The ISL8018 features 100% duty cycle operation to maximize
the battery life. When the battery voltage drops to a level that the
ISL8018 can no longer maintain the regulation at the output, the
regulator completely turns on the P-FET. The maximum dropout
voltage under the 100% duty cycle operation is the product of the
load current and the ON-resistance of the P-FET.
Tie SS to SGND for an internal soft-start of approximately 1ms.
Connect a capacitor from SS to SGND to adjust the soft-start
time. This capacitor, along with an internal 1.8µA current source
Thermal Shutdown
sets the soft-start interval of the converter, t
.
SS
The ISL8018 has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the ISL8018 resumes
operation by stepping through the soft-start.
C
F = 3.33 t s
SS
(EQ. 3)
SS
C
must be less than 33nF to insure proper soft-start reset after
SS
fault condition. For proper use, do not prebias output voltage
more than regulation point.
Figure 37 is a comparison between measured and calculated
output soft-start time versus C capacitance.
SS
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ISL8018
The ISL8018 uses an internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R.
Power Derating Characteristics
To prevent the regulator from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 4:
For high or low output voltage applications, use external
compensation for better phase margin.
(EQ. 4)
T
= PD
JA
RISE
Output Voltage Selection
Where PD is the power dissipated by the regulator and θ is the
thermal resistance from the junction of the die to the ambient
JA
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier (refer to Figure 2 on page 4).
temperature. The junction temperature, T , is given by
J
Equation 5:
(EQ. 5)
T
= T + T
RISE
The output voltage programming resistor, R , will depend on the
2
J
A
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩ, as shown in Equation 7.
Where T is the ambient temperature. For the TQFN package, the
A
θ
is 42 (°C/W).
JA
V
O
VFB
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
-----------
– 1
(EQ. 7)
R
= R
2
3
If the output voltage desired is 0.6V, then R is left unpopulated
3
8
and R is shorted. There is a leakage current from VIN to
2
PHASE. It is recommended to preload the output with 10µA
3.3V
minimum. Capacitance, C , may be added to improve transient
3
6
performance. A good starting point for C can be determined by
choosing a value that provides an 80kHz corner frequency
3
1.8V
with R .
0.6V
2
4
VSET marginally adjusts VFB according to the “Analog
Specifications” on page 6.
2
0
Figure 39 is the recommended minimum output voltage setting
vs operational frequency in order to avoid the minimum on-time
specification.
50
60
70
80
90
100
110
120
130
3.0
2.5
TEMPERATURE (°C)
FIGURE 38. DERATING CURVE vs TEMPERATURE
V
= 5V
IN
2.0
1.5
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL8018
1.0
0.5
0.0
typically uses a 1µH output inductor. The higher or lower inductor
value can be used to optimize the total converter system
performance. For example, for higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current
approximately 30% of the maximum output current for optimized
performance. The inductor ripple current can be expressed as
shown in Equation 6:
V
= 3.3V
3.0
IN
0.5
1.0
1.5
2.0
2.5
3.5
4.0
FREQUENCY (MHz)
FIGURE 39. MINIMUM V
OUT
vs FREQUENCY
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and a filtering function to
prevent the switching current flowing back to the battery rail. At
least two 22µF X5R or X7R ceramic capacitors are a good
starting point for the input capacitor selection.
V
O
---------
V
1 –
O
V
IN
(EQ. 6)
--------------------------------------
I =
L f
SW
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8018 protects the typical
peak current of 12A. The saturation current needs be over 16A
for maximum output current application.
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ISL8018
Figure 41 shows the type II compensator and its transfer function
is expressed as shown in Equation 8:
Loop Compensation Design
When there is an external resistor connected from FS to SGND,
the COMP pin is active for external loop compensation. The
ISL8018 uses constant frequency peak current mode control
architecture to achieve fast loop transient response. An accurate
current sensing pilot device in parallel with the upper MOSFET is
used for peak current control signal and overcurrent protection.
The inductor is not considered as a state variable since its peak
current is constant and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 40 shows the
small signal model of the synchronous buck regulator.
S
S
------------
------------
1 +
1 +
ˆ
GM R
v
comp
3
cz1
cz2
---------------- -------------------------------------------------------- --------------------------------------------------------------
A S=
=
v
ˆ
C + C R + R
S
S
v
6
7
2
3
FB
-------------
-------------
S 1 +
1 +
cp1
cp2
(EQ. 8)
Where
C
+ C
R + R
2
1
1
6
7
3
--------------
--------------
----------------------
----------------------
=
,
=
=
cp2
=
cz1
cz2
cp1
R C
R C
R C C
C R R
3 2
6
6
2
3
6
6
7
3
Compensator design goal:
High DC gain
Choose loop bandwidth f less than 100kHz
c
^
^
L
R
^
P
LP
I
I
v
L
IN
o
Gain margin: >10dB
Phase margin: >40°
^
d
V
^
^
IN
1:D
d
V
IN
I
L
Rc
Co
+
R
T
The compensator design procedure is as follows:
Ro
The loop gain at crossover frequency of f has a unity gain.
c
Therefore, the compensator resistance R is determined by
6
Equation 9.
T (S)
i
^
d
2f V C R
o o t
3
c
K
(EQ. 9)
---------------------------------
= 5.7610 f V C
c o o
R
=
6
GM V
F
FB
m
Where GM is the sum of the transconductance, g , of the voltage
m
H (S)
+
error amplifier in each phase. Compensator capacitor C is then
e
6
T (S)
V
given by Equation 10.
^
V
COMP
R C
V C
o o
I R
o 6
R C
-Av(S)
o
o
1
c
o
(EQ. 10)
-------------- --------------
,C = max(--------------,---------------)
7
C
=
=
6
R
R
f R
6
6
s 6
FIGURE 40. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 10. An optional zero can boost the phase margin. CZ2
Vo
is a zero due to R and C .
2
3
R
C
3
Put compensator zero 2 to 5 times f .
c
2
V
1
FB
(EQ. 11)
---------------
C =
-
V
3
COMP
f R
c
2
R
3
GM
V
REF
+
Example: V = 5V, V = 1.8V, I = 8A, f = 1MHz, R = 200kΩ,
IN sw
O
O
2
R = 100kΩ, C = 4x22µF/3mΩ, L = 1µH, f = 100kHz, then
3
o
c
R
6
compensator resistance R :
C
6
7
3
C
(EQ. 12)
6
R
= 5.7610 100kHz 1.8V 88F = 91.2k
6
1.8V 88F
8A 90.9k
(EQ. 13)
(EQ. 14)
-------------------------------
= 217pF
C
C
=
6
7
FIGURE 41. TYPE II COMPENSATOR
3m 88F
1
= max(--------------------------------,-------------------------------------------------) = (2.9pF, 3.5pF)
90.9k 1MHz90.9k
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ISL8018
It is also acceptable to use the closest standard values for C and
PCB Layout Recommendation
6
C . There is approximately 3pF parasitic capacitance from V
7
COMP
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8018, the power
loop is composed of the output inductor L’s, the output capacitor
COUT, the PHASE’s pins and the PGND pin. It is necessary to make
the power loop as small as possible and the connecting traces
among them should be direct, short and wide. The switching
node of the converter, the PHASE pins and the traces connected
to the node are very noisy, so keep the voltage feedback trace
away from these noisy traces. The input capacitor should be
placed as close as possible to the VIN pin and the ground of the
input and output capacitors should be connected as close as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
to GND. Therefore, C is optional. Use C = 220pF and C = OPEN.
7
6
7
1
(EQ. 15)
-----------------------------------------------
= 16pF
C
=
3
100kHz 200k
Use C = 15pF. Note that C may increase the loop bandwidth
3
3
from previous estimated value. Figure 42 on page 19 shows the
simulated voltage loop gain. It is shown that it has a 125kHz loop
bandwidth with a 45° phase margin and 10dB gain margin. It
may be more desirable to achieve an increased phase margin.
This can be accomplished by lowering R by 20% to 30%.
6
80
60
40
20
0
-20
-40
-60
100
1k
10k
100k
1M
FREQUENCY (Hz)
150
100
50
0
-50
-100
-150
-200
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 42. SIMULATED LOOP GAIN
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ISL8018
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7889.0
CHANGE
September 30, 2015
Initial Release.
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FN7889.0
September 30, 2015
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20
ISL8018
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
0.10 M
C
C
A
B
3.00
A
M
0.05
0.50
16X
20X 0.25 +0.05
6
B
4
-0.07
PIN 1 INDEX AREA
(C 0.40)
17
20
A
16
1
6
PIN 1
INDEX AREA
4.00
+0.10
2.65
-0.15
11
6
0.15
(4X)
A
10
7
VIEW "A-A"
1.65 +0.10
-0.15
TOP VIEW
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
C
0.10
0.9± 0.10
SEATING PLANE
0.08
C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
5
0.2 REF
C
(20 x 0.60)
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7889.0
September 30, 2015
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21
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