ISL8033AIRZ [INTERSIL]
Dual 3A Low Quiescent Current High Efficiency Synchronous Buck Regulator; 双路3A低静态电流高效率同步降压型稳压器
| 型号： | ISL8033AIRZ |
| 厂家： | 
Intersil |
| 描述： | Dual 3A Low Quiescent Current High Efficiency Synchronous Buck Regulator |
| 文件： | 总17页 (文件大小：1831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 3A Low Quiescent Current High Efficiency
Synchronous Buck Regulator
ISL8033, ISL8033A
Features
• Dual 3A High Efficiency Synchronous Buck Regulator
with up to 95% Efficiency
• 2% Output Accuracy Over-Temperature/Load/Line
• Internal Digital Soft-Start - 1.5ms
• External Synchronization up to 6MHz (ISL8033)
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
ISL8033 is a dual integrated power controller rated for
3A per channel with a 1MHz step-down regulator that is
ideal for any low power low-voltage applications. The
ISL8033A offers 2.5MHz operation for smaller more
compacted design. The channels are 180° out-of-phase
for input RMS current and EMI reduction. It is optimized
for generating low output voltages down to 0.8V each.
The supply voltage range is from 2.85V to 6V, allowing
for the use of a single Li+ cell, three NiMH cells or a
regulated 5V input. It has a guaranteed minimum output
current of 3A each when ISET is connected to VDD. The
output current of each output is selectable by setting
ISET pin.
• Adjustable Peak Overload Current
• Negative Current Protection
• Pb-Free (RoHS Compliant)
The ISL8033, ISL8033A includes a pair of low
ON-resistance P-Channel and N-Channel internal
MOSFETs to maximize efficiency and minimize external
component count. 100% duty-cycle operation allows less
than 250mV dropout voltage at 3A.
Applications*(see page 16)
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Power Devices
• Bar Code Readers
The ISL8033, ISL8033A offers an independent 1ms
Power-Good (PG) timer at power-up. When shutdown,
ISL8033, ISL8033A discharges the output capacitor.
Other features include internal digital soft-start, enable
for power sequence, controllable soft-stop output
discharge during disabled, start-up with pre-biased
output, 100% maximum duty cycle for lowest dropout,
100% duty cycle operation for smooth transition, less
than 8µA logic controlled shutdown current,
independent enable, overcurrent protection, and
thermal shutdown.
The ISL8033, ISL8033A is offered in a 24 Ld 4mmx4mm
QFN package with 1mm maximum height. The complete
2
converter occupies less than 5.46cm area.
Efficiency vs Load
100
90
80
3.3V
OUT
70
60
50
40
V
= 5V
IN
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
OUT
October 21, 2010
FN6854.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8033, ISL8033A
Typical Application Circuit
L1
1.5µH
OUTPUT1
1.8V/3A
INPUT 2.85V TO 6V
VIN1, 2
LX1
C2
2x22µF
VDD
ISET
C1
2x22µF
C3
12pF
PGND
FB1
R2
ISL8033
124k
EN1
R3
100k
PG1
SGND
LX2
L2
1.5µH
SYNC
OUTPUT2
1.8V/3A
C4
2x22µF
EN2
PG2
C5
PGND
FB2
12pF
R5
124k
R6
100k
SGND
FIGURE 1. TYPICAL APPLICATION DIAGRAM - DUAL INDEPENDENT OUTPUTS
TABLE 1. ISL8033 COMPONENT VALUE SELECTION
V
0.8V
2x22µF
2x22µF
12pF
1.2V
2x22µF
2x22µF
12pF
1.5V
2x22µF
2x22µF
12pF
1.8V
2x22µF
2x22µF
12pF
2.5V
2x22µF
2x22µF
12pF
3.3V
2x22µF
2x22µF
12pF
OUT
C1
C2 (or C4)
C3 (or C5)
L1 (or L2)
R2 (or R5)
R3 (or R6)
1.0µH~2.2µH
0
1.0µH~2.2µH
50k
1.0µH~2.2µH
87.5k
1.0µH~3.3µH
124k
1.0µH~3.3µH
212.5k
1.0µH~4.7µH
312.5k
100k
100k
100k
100k
100k
100k
TABLE 2. ISL8033A COMPONENT VALUE SELECTION
V
0.8V
2x22µF
2x22µF
12pF
1.2V
2x22µF
2x22µF
12pF
1.5V
2x22µF
2x22µF
12pF
1.8V
2x22µF
2x22µF
12pF
2.5V
2x22µF
2x22µF
12pF
3.3V
2x22µF
2x22µF
12pF
OUT
C1
C2 (or C4)
C3 (or C5)
L1 (or L2)
R2 (or R5)
R3 (or R6)
0.47~1.5µH
0
0.47~1.5µH
50k
0.47~1.5µH
87.5k
0.47~1.5µH
124k
1.0~2.2µH
212.5k
100k
1.0~3.3µH
312.5k
100k
100k
100k
100k
100k
NOTE: The minimum output capacitor value is given for different output voltage to make sure the whole converter system is
stable. Output capacitance should increase to support faster load transient requirement.
TABLE 3. SUMMARY OF DIFFERENCES
PART NUMBER
ISL8033
SWITCHING FREQUENCY
Internally fixed switching frequency F
Internally fixed switching frequency F
= 1MHz
SW
ISL8033A
= 2.5MHz
SW
FN6854.1
October 21, 2010
2
ISL8033, ISL8033A
Block Diagram
27pF
390k
0.3pF
SHUTDOWN
SOFT-
START
SHUTDOWN
VIN
EN1
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
+
0.8V
BANDGAP
+
EAMP
LX1
COMP
3pF
PGND
SLOPE
COMP
+
FB1
+
CSA1
SCP
+
0.5V
1.6k
0.864V
+
+
OSCILLATOR
VIN
1M
0.736V
PG1
SYNC
ISET
1ms
DELAY
SGND
SHUTDOWN
THERMAL
SHUTDOWN
OCP
THRESHOLD
LOGIC
SOFT-
27pF
390k
START
0.3pF
SHUTDOWN
SHUTDOWN
BANDGAP
VIN
EN2
+
0.8V
+
EAMP
PWM
LOGIC
CONTROLLER
PROTECTION
DRIVER
COMP
LX2
3pF
PGND
SLOPE
COMP
+
+
FB2
CSA2
SCP
+
0.5V
1.6k
0.864V
+
+
VIN
0.736V
1M
PG2
1ms
DELAY
SGND
FN6854.1
October 21, 2010
3
ISL8033, ISL8033A
Pin Configuration
ISL8033, ISL8033A
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
LX2
VIN2
VIN2
EN2
LX1
18
17
16
15
14
13
1
2
3
4
5
6
VIN1
VIN1
VDD
ISET
EN1
25
PD
PG2
FB2
7
8
9
10 11 12
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 24
22, 23
4
LX2
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
PGND2
EN2
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the
VOUT2 and discharge output capacitor when driven to low. Do not leave this pin floating.
5
6
PG2
FB2
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT2 voltage.
The feedback network of the Channel 2 regulator. FB2 is the negative input to the
transconductance error amplifier. The output voltage is set by an external resistor divider
connected to FB2. With a properly selected divider, the output voltage can be set to any voltage
between the power rail (reduced by converter losses) and the 0.8V reference. There is an internal
compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB2 to monitor
the Channel 2 regulator output voltage.
7, 8
9
NC
No connect pins. Please tie to GROUND.
FB1
The feedback network of the Channel 1 regulator. FB1 is the negative input to the
transconductance error amplifier. The output voltage is set by an external resistor divider
connected to FB1. With a properly selected divider, the output voltage can be set to any voltage
between the power rail (reduced by converter losses) and the 0.8V reference. There is an
internal compensation to meet a typical application.
In addition, the regulator power-good and undervoltage protection circuitry use FB1 to monitor
the Channel 1 regulator output voltage.
10
11
SGND
PG1
System ground. Make a single point connection from these pins to PGND.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
VOUT1 voltage.
12
13
SYNC
EN1
Connect to logic high or input voltage VIN. Connect to an external function generator for external
Synchronization. Negative edge trigger. Do not leave this pin floating. Do not tie this pin low
(or to SGND).
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the
VOUT1 and discharge output capacitor when driven to low. Do not leave this pin floating.
FN6854.1
October 21, 2010
4
ISL8033, ISL8033A
Pin Descriptions(Continued)
PIN NUMBER
SYMBOL
DESCRIPTION
14
ISET
ISET is the output current limit setting of the regulators. See the “Electrical Specifications” table
on page 6 for settings.
15
VDD
PGND1
LX1
Input supply voltage for the logic. Connect VIN pin.
20, 21
18, 19
Negative supply for the power stage of Channel 1.
Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.
Input supply voltage. Connect a 22µF ceramic capacitor to power-ground per channel.
2, 3,
16, 17
VIN2,
VIN1
25
PD
The exposed pad must be connected to the PGND pin for proper electrical performance. Add as
much vias as possible under this pad for optimal thermal performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL8033IRZ*
80 33IRZ
80 33AIRZ
-40 to +85
-40 to +85
24 Ld 4x4 QFN
24 Ld 4x4 QFN
L24.4x4D
L24.4x4D
ISL8033AIRZ*
NOTES:
1. Add “-T” suffix for tape and reel.Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8033, ISL8033A. For more information on MSL,
please see Technical Brief TB363.
FN6854.1
October 21, 2010
5
ISL8033, ISL8033A
Absolute Maximum Ratings (Reference to SGND)
Thermal Information
VIN1,VIN2, VDD. . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms)
LX1, LX2. . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
EN1, EN2, PG1, PG2, SYNC, ISET. . . . . . . . . -0.3V to +6.5V
FB1, FB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
NC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Ratings
Human Body Model (Tested per JESD22-A114) . . . . . . 4kV
Charged Device Model (Tested per JESD22-C101E) . . . 2kV
Machine Model (Tested per JESD22-A115) . . . . . . . . 0.3kV
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . 100mA
Thermal Resistance (Typical)
θ
(°C/W) θ (°C/W)
JC
JA
4x4 QFN Package (Notes 4, 5). . .
36
2
Junction Temperature Range . . . . . . . . . . -55°C to +150°C
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . -40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . 2.85V to 6V
Load Current Range per Channel. . . . . . . . . . . . . . 0A to 3A
Junction Temperature Range . . . . . . . . . . -55°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions:
T = -40°C to +85°C, V = 3.6V, EN1 = EN2 = VDD, L = 1.5µH, C1 = C2 = C4 = 2x22µF, I
OUT1
= I = 0A to 3A. Typical
OUT2
A
IN
values are at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
A
MIN
MAX
PARAMETER
INPUT SUPPLY
SYMBOL
TEST CONDITIONS
(Note 7) TYP (Note 7)
UNITS
VIN Undervoltage Lockout Threshold
V
Rising
2.5
2.85
V
UVLO
Hysteresis
50
100
mV
Quiescent Supply Current
I
SYNC = VDD, EN1 = EN2 = VDD,
15
30
8
40
70
20
mA
mA
µA
VDD
F = 1MHz, no load at the output
S
SYNC = VDD, EN1 = EN2 = VDD,
F = 2.5MHz, no load at the output
S
Shutdown Supply Current
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
I
VDD = 6V, EN1 = EN2 = SGND
SD
V
0.790 0.8 0.810
V
FB
I
VFB = 0.75V
0.1
2
µA
FB
Load Regulation
SYNC = VDD, output load from 0A to 3A
VIN = VO + 0.5V to 6V (minimal 2.85V)
mV/A
%/V
ms
Line Regulation
0.1
1.5
Soft-Start Ramp Time Cycle
COMPENSATION
Error Amplifier Trans-Conductance
Trans-Resistance
20
µA/V
RT
0.18
0.2
0.22
Ω
OVERCURRENT PROTECTION
Dynamic Current Limit ON-time
Dynamic Current Limit OFF-time
Positive Peak Overcurrent Limit
t
17
8
Clock pulses
OCON
t
SS cycle
OCOFF
I
I
I
I
I
I
ISET = VDD
ISET = Float
ISET = GND
4.1
4.1
4.1
2.7
2.7
2.7
4.8
4.8
4.8
3.3
3.3
3.3
5.5
5.5
5.5
3.9
3.9
3.9
A
A
A
A
A
A
poc1
poc2
poc1
poc2
poc1
poc2
FN6854.1
October 21, 2010
6
ISL8033, ISL8033A
Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions:
T = -40°C to +85°C, V = 3.6V, EN1 = EN2 = VDD, L = 1.5µH, C1 = C2 = C4 = 2x22µF, I
OUT1
= I = 0A to 3A. Typical
OUT2
A
IN
values are at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 7) TYP (Note 7)
UNITS
Negative Peak Overcurrent Limit
I
-3.5
-3.5
-2.5
-2.5
-1.5
-1.5
A
A
noc1
noc2
I
LX1, LX2
P-Channel MOSFET ON-Resistance
VIN = 6V, I = 200mA
50
70
75
100
75
mΩ
mΩ
mΩ
mΩ
%
O
VIN = 2.85V, I = 200mA
O
N-Channel MOSFET ON-Resistance
VIN = 6V, I = 200mA
50
O
VIN = 2.85V, I = 200mA
O
70
100
LX_ Maximum Duty Cycle
PWM Switching Frequency
100
1.1
2.5
F
ISL8033
0.88
2.15
2.64
1.32
2.85
6
MHz
MHz
MHz
°
S
ISL8033A
Synchronization Range
F
ISL8033 (Note 6)
Rising edge to rising edge timing
SYNC = High (forced PWM mode)
EN = LOW
SYNC
Channel 1 to Channel 2 Phase Shift
LX Minimum On-Time
180
140
120
1
ns
Soft Discharge Resistance
LX Leakage Current
R
80
100
0.1
Ω
DIS
Pulled up to 6V
µA
PG1, PG2
Output Low Voltage
Sinking 1mA, VFB = 0.7V
0.3
0.1
V
PG_ Pin Leakage Current
Internal PGOOD Low Rising Threshold
Internal PGOOD Low Falling Threshold
Delay Time (Rising Edge)
PG = VIN = 6V
0.01
92
88
1
µA
%
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
89.5
85
94.5
91
%
ms
µs
Internal PGOOD Delay Time (Falling
Edge)
7
10
EN1, EN2, SYNC
Logic Input Low
0.4
V
Logic Input High
1.5
V
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
I
Pulled up to 6V
Pulled up to 6V
0.1
0.1
150
25
1
1
µA
µA
°C
°C
SYNC
I
EN
Thermal Shutdown Hysteresis
NOTES:
6. The operational frequency per switching channel will be half of the SYNC frequency.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
FN6854.1
October 21, 2010
7
ISL8033, ISL8033A
Typical Operating Performance ISL8033
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = L2 = 1.5µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
= 1.8V, I = I
OUT1 OUT2
= 0A to 3A.
OUT1
100
OUT2
100
90
90
80
70
60
2.5V
1.8V
OUT
1.2V
2.5V
OUT
1.8V
OUT
1.2V
80
OUT
1.5V
OUT
1.5V
OUT
OUT
OUT
3.3V
OUT
70
60
50
40
50
40
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
OUT
OUT
FIGURE 2. EFFICIENCY, T = +25°C V
A
= 3.3V
FIGURE 3. EFFICIENCY, T = +25°C, V
= 5V
IN
IN
A
1.2
1.0
1.210
1.205
5V
IN
3.3V
0.8
0.6
0.4
0.2
0
IN
1.200
1.195
1.190
1.185
1.180
5V
IN
3.3V
2.0
IN
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.5
3.0
I
OUT
IOUT (A)
FIGURE 4. POWER DISSIPATION, T = +25°C
FIGURE 5. LOAD REGULATION, V
= 1.2V
OUT
A
V
= 1.8V
T
= +25°C
OUT
A
1.500
1.495
1.490
1.485
1.480
1.475
1.470
1.800
1.795
1.790
1.785
1.780
1.775
1.770
5V
IN
5V
IN
3.3V
IN
3.3V
IN
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
OUT
OUT
FIGURE 6. LOAD REGULATION, V
= 1.5V
FIGURE 7. LOAD REGULATION, V
= 1.8V
OUT
OUT
T
= +25°C
T
= +25°C
A
A
FN6854.1
October 21, 2010
8
ISL8033, ISL8033A
Typical Operating Performance ISL8033
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = L2 = 1.5µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
= 1.8V, I
= I = 0A to 3A. (Continued)
OUT2
OUT1
OUT2
OUT1
2.490
2.485
2.480
2.475
2.470
2.465
2.460
3.270
3.265
3.260
3.255
3.250
3.245
3.240
5V
IN
5V
IN
3.3V
IN
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
I
I
(A)
OUT
OUT
FIGURE 8. LOAD REGULATION, V
= 2.5V
FIGURE 9. LOAD REGULATION, V
= 3.3V
OUT
OUT
T
= +25°C
T
= +25°C
A
A
LX1 2V/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
IL1 0.5A/DIV
OUT1
V
RIPPLE 20mV/DIV
IL2 0.5A/DIV
.
OUT2
FIGURE 10. STEADY STATE OPERATION AT NO LOAD
CHANNEL 1 (PWM)
FIGURE 11. STEADY STATE OPERATION AT NO LOAD
CHANNEL 2 (PWM)
LX1 2V/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
OUT2
V
RIPPLE 20mV/DIV
IL1 2A/DIV
OUT1
IL2 2A/DIV
FIGURE 12. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 1
FIGURE 13. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 2
FN6854.1
October 21, 2010
9
ISL8033, ISL8033A
Typical Operating Performance ISL8033
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = L2 = 1.5µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
OUT2
= 1.8V, I
OUT1
= I
OUT2
= 0A to 3A. (Continued)
OUT1
LX1 2V/DIV
V
RIPPLE 50mV/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT1
LX2 2V/DIV
IL1 2A/DIV
V
RIPPLE 20mV/DIV
OUT2
FIGURE 14. STEADY STATE OPERATION WITH FULL
LOADS AT BOTH CHANNELS
FIGURE 15. LOAD TRANSIENT CHANNEL 1 (PWM)
EN1 2V/DIV
V
RIPPLE 50mV/DIV
OUT2
V
0.5V/DIV
OUT1
IL1 0.5A/DIV
PG 5V/DIV
IL2 2A/DIV
FIGURE 16. LOAD TRANSIENT CHANNEL 2 (PWM)
FIGURE 17. SOFT-START WITH NO LOAD CHANNEL 1
EN2 2V/DIV
EN1 2V/DIV
0.5V/DIV
V
OUT1
IL1 1A/DIV
V
1V/DIV
OUT2
IL2 0.5A/DIV
PG 2V/DIV
PG 5V/DIV
FIGURE 18. SOFT-START WITH NO LOAD CHANNEL 2
FIGURE 19. SOFT-START AT FULL LOAD CHANNEL 1
FN6854.1
October 21, 2010
10
ISL8033, ISL8033A
Typical Operating Performance ISL8033
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = L2 = 1.5µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
OUT2
= 1.8V, I
OUT1
= I
OUT2
= 0A to 3A. (Continued)
OUT1
EN2 2V/DIV
EN1 2V/DIV
V
1V/DIV
OUT2
V
0.5V/DIV
OUT1
IL2 1A/DIV
PG 2V/DIV
IL1 0.5A/DIV
PG 5V/DIV
FIGURE 20. SOFT-START AT FULL LOAD CHANNEL 2
FIGURE 21. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
LX1 2V/DIV
EN2 2V/DIV
V
1V/DIV
OUT2
SYNCH 5V/DIV
IL2 0.5A/DIV
PG 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
IL1 0.2A/DIV
FIGURE 22. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 23. CHANNEL 1 STEADY STATE OPERATION AT
NO LOAD WITH FREQUENCY = 6MHz
LX2 2V/DIV
LX1 2V/DIV
SYNCH 5V/DIV
SYNCH 5V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
IL2 0.2A/DIV
OUT2
IL1 2A/DIV
FIGURE 24. CHANNEL 2 STEADY STATE OPERATION AT
NO LOAD WITH FREQUENCY = 6MHz
FIGURE 25. CHANNEL 1 STEADY STATE OPERATION AT
FULL LOAD WITH FREQUENCY = 6MHz
FN6854.1
October 21, 2010
11
ISL8033, ISL8033A
Typical Operating Performance ISL8033
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = L2 = 1.5µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
OUT2
= 1.8V, I
OUT1
= I = 0A to 3A. (Continued)
OUT2
OUT1
LX2 2V/DIV
LX1 2V/DIV
IL1 2A/DIV
SYNCH 5V/DIV
RIPPLE 20mV/DIV
V
OUT2
V
0.5V/DIV
OUT1
IL2 2A/DIV
PG 5V/DIV
FIGURE 26. CHANNEL 2 STEADY STATE OPERATION AT
FULL LOAD WITH FREQUENCY = 6MHz
FIGURE 27. OUTPUT SHORT CIRCUIT CHANNEL 1
LX2 2V/DIV
LX1 2V/DIV
V
0.5V/DIV
IL2 2A/DIV
OUT1
IL1 2A/DIV
V
1V/DIV
OUT2
PG 5V/DIV
PG 5V/DIV
FIGURE 28. OUTPUT SHORT CIRCUIT RECOVERY
CHANNEL 1
FIGURE 29. OUTPUT SHORT CIRCUIT CHANNEL 2
LX2 2V/DIV
V
1V/DIV
OUT2
IL2 2A/DIV
PG 5V/DIV
FIGURE 30. OUTPUT SHORT CIRCUIT RECOVERY CHANNEL 2
FN6854.1
October 21, 2010
12
ISL8033, ISL8033A
Typical Operating Performance ISL8033A
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = 0.68µH, L2 = 1µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
OUT2
= 1.8V, I
OUT1
= I
OUT2
= 0A to 3A.
OUT1
100
90
100
2.5V
OUT
3.3V
OUT
2.5V
OUT
90
80
70
60
50
40
80
1.2V
OUT
1.5V
OUT
1.5V
OUT
1.8V
OUT
1.2V
OUT
1.8V
70
OUT
60
50
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 31. EFFICIENCY vs LOAD, 1MHz 3.3V
CH1 +25°C
DUAL
FIGURE 32. EFFICIENCY vs LOAD, 1MHz 5V , DUAL
IN
IN
CH1 +25°C
LX2 2V/DIV
LX1 2V/DIV
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
IL2 0.2A/DIV
OUT2
IL1 0.2A/DIV
FIGURE 33. STEADY STATE OPERATION AT NO LOAD
CHANNEL 1
FIGURE 34. STEADY STATE OPERATION AT NO LOAD
CHANNEL 2
LX1 2V/DIV
LX2 2V/DIV
V
RIPPLE 20mV/DIV
IL1 0.2A/DIV
V
RIPPLE 20mV/DIV
IL2 0.2A/DIV
OUT1
OUT2
FIGURE 35. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 1
FIGURE 36. STEADY STATE OPERATION WITH FULL
LOAD CHANNEL 2
FN6854.1
October 21, 2010
13
ISL8033, ISL8033A
Typical Operating Performance ISL8033A
Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V , L1 = 0.68µH, L2 = 1µH, C1 = C2 = C4 = 2x22µF,
A
IN
IN
V
= 1.2V, V
OUT2
= 1.8V, I
OUT1
= I = 0A to 3A. (Continued)
OUT2
OUT1
V
RIPPLE 50mV/DIV
OUT1
V
RIPPLE 50mV/DIV
OUT2
IL1 2A/DIV
IL2 2A/DIV
FIGURE 37. LOAD TRANSIENT CHANNEL 1
FIGURE 38. LOAD TRANSIENT CHANNEL 2
P-MOSFET and to turn on the N-channel MOSFET. The
N-MOSFET stays on until the end of the PWM cycle.
Figure 39 shows the typical operating waveforms during
the PWM operation. The dotted lines illustrate the sum
of the compensation ramp and the current-sense
amplifier CSA_ output.
Theory of Operation
The ISL8033 is a dual 3A step-down switching regulator
optimized for battery-powered or mobile applications.
The regulator operates at 1MHz fixed switching
frequency under heavy load condition. The ISL8033A
operates at 2.5MHz to allow small external inductor and
capacitors to be used for minimal printed-circuit board
(PCB) area. The two channels are 180° out-of-phase
operation. The supply current is typically only 8µA when
the regulator is shutdown.
The output voltage is regulated by controlling the
reference voltage to the current loop. The bandgap
circuit outputs a 0.8V reference voltage to the voltage
control loop. The feedback signal comes from the VFB
pin. The soft-start block only affects the operation during
the start-up and will be discussed separately. The error
amplifier is a transconductance amplifier that converts
the voltage error signal to a current output. The voltage
loop is internally compensated with the 27pF and 390kΩ
RC network. The maximum EAMP voltage output is
precisely clamped to the bandgap voltage (1.172V).
PWM Control Scheme
Pulling the SYNC pin HI (>1.5V) forces the converter into
PWM mode in the next switching cycle regardless of
output current. Each of the channels of the ISL8033,
ISL8033A employ the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting, as shown
in the “Theory of Operation” on page 14. The current
loop consists of the oscillator, the PWM comparator
COMP, current sensing circuit, and the slope
compensation for the current loop stability. The current
sensing circuit consists of the resistance of the P-channel
MOSFET when it is turned on and the current sense
amplifier CSA1. The gain for the current sensing circuit is
typically 0.20V/A. The control reference for the current
loops comes from the error amplifier EAMP of the voltage
loop.
VEAMP
VCSA1
Duty
Cycle
IL
The PWM operation is initialized by the clock from the
oscillator. The P-channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the
MOSFET starts to ramp-up. When the sum of the
current amplifier CSA1 (or CSA2 on Channel 2) and the
compensation slope (0.46V/µs) reaches the control
reference of the current loop, the PWM comparator
COMP sends a signal to the PWM logic to turn off the
VOUT
FIGURE 39. PWM OPERATION WAVEFORMS
FN6854.1
October 21, 2010
14
ISL8033, ISL8033A
Synchronization Control (ISL8033)
Enable
The frequency of operation can be synchronized up to 6MHz
by an external signal applied to the SYNC pin. The 1st
falling edge on the SYNC triggered the rising edge of the
PWM ON pulse of Channel 1. The 2nd falling edge of the
SYNC triggers the rising edge of the PWM ON pulse of the
Channel 2. This process alternates indefinitely allowing
180° output phase operation between the two channels.
The enable (EN) input allows the user to control the
turning on or off the regulator for purposes such as
power-up sequencing. When the regulator is enabled,
there is typically a 600µs delay for waking up the
bandgap reference and then the soft-start-up will begin.
Soft Start-Up
The soft start-up eliminates the inrush current during the
start-up. The soft-start block outputs a ramp reference to
both the voltage loop and the current loop. The two
ramps limit the inductor current rising 1/2 speed as well
as the output voltage speed so that the output voltage
rises in a controlled fashion. At the very beginning of the
start-up, the output voltage is less than 0.5V; hence the
PWM operating frequency is 1/2 of the normal frequency.
Overcurrent Protection
CAS1 and CSA2 are used to monitor Output 1 and
Output 2 channels respectively. The overcurrent
protection is realized by monitoring the CSA output with
the OCP threshold logic, as shown in Figure 39. The
current sensing circuit has a gain of 0.20V/A, from the
P-MOSFET current to the CSA output. When the CSA1
output reaches the threshold set by ISET, the OCP
comparator is tripped to turn off the P-MOSFET
immediately. The overcurrent function protects the
switching converter from a shorted output by
monitoring the current flowing through the upper
MOSFETs.
When the IC ramps up at start-up, it can’t sink current
even at PWM mode.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, or the
output undervoltage fault latch is set, its output
discharges to PGND through an internal 100Ω switch.
Upon detection of overcurrent condition, the upper
MOSFET will be immediately turned off and will not be
turned on again until the next switching cycle. Upon
detection of the initial overcurrent condition, the
Overcurrent Fault Counter is set to 1 and the Overcurrent
Condition Flag is set from LOW to HIGH. If, on the
subsequent cycle, another overcurrent condition is
detected, the OC Fault Counter will be incremented. If
there are 17 sequential OC fault detections, the regulator
will be shutdown under an Overcurrent Fault Condition.
An Overcurrent Fault Condition will result in the regulator
attempting to restart in a hiccup mode with the delay
between restarts being 4 soft-start periods. At the end of
the fourth soft-start wait period, the fault counters are
reset and soft-start is attempted again. If the
Power MOSFETs
The power MOSFETs are optimize for best efficiency. The
ON-resistance for the P-MOSFET is typically 50mΩ and
the ON-resistance for the N-MOSFET is typical 50mΩ.
100% Duty Cycle
The ISL8033 features 100% duty cycle operation to
maximize the battery life. When the battery voltage
drops to a level that the ISL8033, ISL8033A can no
longer maintain the regulation at the output, the
regulator completely turns on the P-MOSFET. The
maximum drop-out voltage under the 100% duty-cycle
operation is the product of the load current and the
ON-resistance of the P-MOSFET.
overcurrent condition goes away prior to the OC Fault
Counter reaching a count of four, the Overcurrent
Condition Flag will set back to LOW.
Thermal Shutdown
The ISL8033, ISL8033A has built-in thermal protection.
When the internal temperature reaches +150°C, the
regulator is completely shutdown. As the temperature
drops to +125°C, the ISL8033, ISL8033A resumes
operation by stepping through a soft start-up.
If the negative output current reaches -2.5A, the part
enters Negative Overcurrent Protection. At this point, all
switching stops and the part enters tri-state mode while
the pull-down FET is discharging the output until it
reaches normal regulation voltage, then the IC restarts.
Applications Information
PG
Output Inductor and Capacitor Selection
There are two independent power-good signals. PG1
monitors the Output Channel 1 and PG2 monitors the
Output Channel 2. When powering up, the open-collector
To consider steady state and transient operation,
ISL8033 typically uses a 1.5µH output inductor. Higher or
lower inductor value can be used to optimize the total
converter system performance. For example, for a higher
output voltage 3.3V application, in order to decrease the
inductor current ripple and output voltage ripple, the
output inductor value can be increased. The inductor
ripple current can be expressed in Equation 1:
Power-On Reset output holds low for about 1ms after V
reaches the preset voltage. The PG_ output also serves
O
as a 1ms delayed Power-Good signal.
UVLO
When the input voltage is below the undervoltage lock
out (UVLO) threshold, the regulator is disabled.
V
⎛
⎞
⎟
⎠
O
---------
V
• 1 –
⎜
(EQ. 1)
O
V
⎝
IN
--------------------------------------
ΔI =
L • f
S
FN6854.1
October 21, 2010
15
ISL8033, ISL8033A
The inductor’s saturation current rating needs be at least
Input Capacitor Selection
larger than the peak current. The ISL8033, ISL8033A
protects the typical peak current 4.8A. The saturation
current needs be over 4.8A for maximum output current
application.
The main functions for the input capacitor is to provide
decoupling of the parasitic inductance and to provide
filtering function to prevent the switching current flowing
back to the battery rail. One 22µF X5R or X7R ceramic
capacitor is a good starting point for the input capacitor
selection per channel.
ISL8033, ISL8033A uses an internal compensation
network and the output capacitor value is dependent on
the output voltage. The ceramic capacitor is
recommended to be X5R or X7R. The recommended
minimum output capacitor values for the ISL8033,
ISL8033A are shown in Tables 1 and 2 on page 2.
PCB Layout Recommendation
The PCB layout is a very important converter design step
to make sure the designed converter works well. For
ISL8033, the power loop is composed of the output
Output Voltage Selection
inductor L’s, the output capacitor C
and C , the
OUT1
OUT2
LX’s pins, and the SGND pin. It is necessary to make the
power loop as small as possible and the connecting
traces among them should be direct, short and wide. The
switching node of the converter, the LX_ pins, and the
traces connected to the node are very noisy, so keep the
voltage feedback trace away from these noisy traces. The
input capacitor should be placed as closely as possible to
the VIN pin . Also, the ground of the input and output
capacitors should be connected as closely as possible.
The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to
the thermal pad is preferable. In addition, a solid ground
plane is helpful for better EMI performance. It is
The output voltage of the regulator can be programmed
via an external resistor divider, which is used to scale the
output voltage relative to the internal reference voltage
and feed it back to the inverting input of the error
amplifier. Refer to Figure 1.
The output voltage programming resistor, R (or R in
2
5
Channel 2), will depend on the desired output voltage of
the regulator. The value for the feedback resistor is
typically between 0Ω and 750kΩ. Let R = 124kΩ, then
2
R will be:
3
R x0.8V
2
(EQ. 2)
----------------------------------
=
R
3
V
– 0.8V
OUT
recommended to add at least 5 vias ground connection
within the pad for the best thermal relief.
For better performance, add 12pF in parallel to R . If the
2
output voltage desired is 0.8V, then leave R
unpopulated and short R .
3
2
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest revision.
DATE
10/12/10
9/29/10
REVISION
FN6854.1
FN6854.0
CHANGE
In Table 3 on page 2, corrected F
Initial Release.
for ISL8033 from 1Hz to 1MHz
SW
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL8033, ISL8033A
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6854.1
October 21, 2010
16
ISL8033, ISL8033A
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 50 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 50 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6854.1
October 21, 2010
17
相关型号：
©2020 ICPDF网 联系我们和版权申明