ISL8036A [RENESAS]
Dual 3A 1MHz/2.5MHz High Efficiency Synchronous Buck Regulator;
| 型号： | ISL8036A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Dual 3A 1MHz/2.5MHz High Efficiency Synchronous Buck Regulator |
| 文件： | 总26页 (文件大小：3229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8036, ISL8036A
Dual 3A 1MHz/2.5MHz High Efficiency Synchronous Buck Regulator
FN6853
Rev 3.00
August 17, 2012
ISL8036, ISL8036A are integrated power controllers rated for
Features
dual 3A output current or current sharing operation with a
• 3A High Efficiency Synchronous Buck Regulator with up to
95% Efficiency
1MHz (ISL8036)/2.5MHz (ISL8036A) step-down regulator,
which is ideal for any low power low-voltage applications. The
channels are 180° out-of-phase for input RMS current and EMI
reduction. It is optimized for generating low output voltages
down to 0.8V each. The supply voltage range is from 2.8V to
6V, allowing for the use of a single Li+ cell, three NiMH cells or
a regulated 5V input. The two channels are 180° out-of-phase,
and each one has a guaranteed minimum output current of
3A. They can be combined to form a single 6A output in the
current sharing mode. While in current sharing, the interleaved
PWM signals reduce input and output ripple.
• 2% Output Accuracy Over-Temperature/Load/Line
• Internal Digital Soft-Start - 1.5ms
• 6A Current Sharing Mode Operation
• External Synchronization up to 6MHz
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
• Reverse Overcurrent Protection
The ISL8036, ISL8036A includes a pair of low ON-resistance
P-channel and N-channel internal MOSFETs to maximize
efficiency and minimize external component count. 100%
duty-cycle operation allows less than 250mV dropout voltage
at 3A each.
Applications
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Test and Measurement Systems
• Li-ion Battery Power Devices
• Bar Code Reader
The ISL8036, ISL8036A offers an independent 1ms
Power-good (PG) timer at power-up. When shutdown, ISL8036,
ISL8036A discharges the output capacitor. Other features
include internal digital soft-start, enable for power sequence,
overcurrent protection, and thermal shutdown.
The ISL8036, ISL8036A is offered in a 24 Ld 4mmx4mm QFN
package with 1mm maximum height. The complete converter
occupies less than 1.5cm area.
Related Literature
• AN1616, “ISL8036CRSHEVAL1Z Current Sharing 6A Low
Quiescent Current High Efficiency Synchronous Buck
Regulator”
2
• AN1617, “ISL8036DUALEVAL1Z Dual 3A Low Quiescent
Current High Efficiency Synchronous Buck Regulator”
• AN1615, “ISL8036ACRSHEVAL1Z Current Sharing 6A Low
Quiescent Current High Efficiency Synchronous Buck
Regulator”
• AN1618, “ISL8036ADUALEVAL1Z Dual 3A Low Quiescent
Current High Efficiency Synchronous Buck Regulator”
100
90
80
70
60
50
40
3.3V
- PWM
OUT
0
1
2
3
4
5
6
OUTPUT LOAD (A)
FIGURE 1. EFFICIENCY vs LOAD, 1MHz 5V PWM, T = +25°C
IN
A
FN6853 Rev 3.00
August 17, 2012
Page 1 of 26
ISL8036, ISL8036A
Typical Applications
L1
1.5µH
OUTPUT1
1.8V/6A
INPUT 2.8V TO 6V
VIN1, 2
LX1
PGND
FB1
C2
2x22µF
VDD
EN1
C1
C3
2x22µF
12pF
R2
124k
ISL8036,
ISL8036A
EN2
R3
100k
PG1
SGND
LX2
L2
1.5µH
SYNC
PG2
SS
C4
2x22µF
PGND
C5
22nF
FB2
COMP
C6
150pF
R6
50k
SGND
FIGURE 2. TYPICAL APPLICATION DIAGRAM - SINGLE 6A
L1
1.5µH
OUTPUT1
1.8V/3A
INPUT 2.7V TO 6V
VIN
LX1
C2
2x22µF
C3
12pF
VDD
SS
C1
2x22µF
PGND
FB1
R2
124k
ISL8036,
ISL8036A
EN1
R3
100k
PG1
SGND
LX2
L2
1.5µH
SYN C
OUTPUT2
1.8V/3A
C4
2x22µF
EN2
PG2
C5
12pF
PGND
FB2
R5
124k
R6
100k
COMP
SGND
FIGURE 3. TYPICAL APPLICATION DIAGRAM - DUAL 3A OUTPUTS
FN6853 Rev 3.00
August 17, 2012
Page 2 of 26
ISL8036, ISL8036A
TABLE 1. COMPONENT VALUE SELECTION FOR DUAL OPERATION
V
0.8V
2x22µF
2X22µF
1.0~2.2µH
0
1.2V
2x22µF
2X22µF
1.0~2.2µH
50k
1.5V
2x22µF
2X22µF
1.0~2.2µH
87.5k
1.8V
2x22µF
2X22µF
1.0~3.3µH
124k
2.5V
2x22µF
2X22µF
1.0~3.3µH
212.5k
100k
3.3V
2x22µF
2X22µF
1.0~4.7µH
312.5k
100k
OUT
C1
C2 (or C4)
L1 (or L2)*
R2 (or R5)
R3 (or R6)
100k
100k
100k
100k
*For ISL8036A, the values used for L1 (or L2) are half the values specified above for each V
.
OUT
TABLE 2. COMPONENT VALUE SELECTION FOR CURRENT SHARING OPERATION
V
0.8V
2x22µF
2X22µF
1.0~2.2µH
0
1.2V
2x22µF
2X22µF
1.0~2.2µH
50k
1.5V
2x22µF
2X22µF
1.0~2.2µH
87.5k
1.8V
2x22µF
2X22µF
1.0~3.3µH
124k
2.5V
2x22µF
2X22µF
1.0~3.3µH
212.5k
100k
3.3V
2x22µF
2X22µF
1.0~4.7µH
312.5k
100k
OUT
C1
C2 (or C4)
L1 (or L2)*
R2
R3
100k
100k
100k
100k
R6
30k
33k
31k
30k
29k
28k
C6
250pF
180pF
150pF
150pF
150pF
150pF
*For ISL8036A, the values used for L1 (or L2) are half the values specified above for each V
NOTE: C5 value (22nF) is given by Equation 1 corresponding to the desired soft-start time.
.
OUT
TABLE 3. SUMMARY OF DIFFERENCES
SWITCHING FREQUENCY
PART NUMBER
ISL8036
Internally fixed switching frequency F
= 1MHz
SW
SW
ISL8036A
Internally fixed switching frequency F
= 2.5MHz
FN6853 Rev 3.00
August 17, 2012
Page 3 of 26
ISL8036, ISL8036A
Block Diagram
COMP
27pF
390k
0.3pF
SS
SHUTDOWN
SOFT-
START
T
SHUTDOWN
VIN1
EN1
PWM
LOGIC
0.8V
+
BANDGAP
+
EAMP
LX1
COMP
CONTROLLER
PROTECTION
DRIVER
3pF
PGND
SLOPE
COMP
+
+
FB1
CSA1
1.6k
SCP
0.5V
+
0.864V
+
+
OSCILLATOR
VIN1
0.736V
1M
PG1
SYNC
1ms
DELAY
SGND
SHUTDOWN
THERMAL
SHUTDOWN
OCP
THRESHOLD
LOGIC
27pF
390k
SS
SOFT-
START
0.3pF
SHUTDOW N
SHUTDOWN
BANDGAP
VIN2
EN2
0.8V
+
+
EAMP
COMP
PWM
LOGIC
LX2
CONTROLLER
PROTECTION
DRIVER
3pF
PGND
SLOPE
COMP
+
+
FB2
CSA2
SCP
1.6k
0.5V
+
0.864V
+
+
VIN2
0.736V
1M
PG2
1ms
DELAY
SGND
FN6853 Rev 3.00
August 17, 2012
Page 4 of 26
ISL8036, ISL8036A
Pin Configuration
ISL8036, ISL8036A
(24 LD QFN)
TOP VIEW
24 23 22 21 20 19
LX2
VIN2
VIN2
EN2
PG2
FB2
LX1
VIN1
VIN1
VDD
SS
18
17
16
15
14
13
1
2
3
4
5
6
25
PAD
EN1
7
8
9
10 11 12
Pin Descriptions
PIN
NUMBER
1, 24
22, 23
4
SYMBOL
LX2
DESCRIPTION
Switching node connection for Channel 2. Connect to one terminal of inductor for VOUT2.
Negative supply for the power stage of Channel 2.
PGND2
EN2
Regulator Channel 2 enable pin. Enable the output, VOUT2, when driven to high. Shutdown the VOUT2 and discharge
output capacitor when driven to low. Do not leave this pin floating.
5
6
7
PG2
FB2
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT2 voltage.
The feedback network of the Channel 2 regulator. To be connected to FB1 (current sharing)
COMP
An additional external network across COMP and SGND is required to improve the loop compensation of the amplifier
channel parallel operation. The soft-start pin should be tied to the external capacitor. COMP pin is NC in dual mode
operation, using internal compensation. If SS pin is tied to CSS (without connection to VIN), external compensation is
automtaically used. Connect an external R,C network on COMP pin for parallel mode operation.
8
9
NC
No connect pin; please tie to GND.
FB1
The feedback network of the Channel 1 regulator. FB1 is the negative input to the transconductance error amplifier.
The output voltage is set by an external resistor divider connected to FB1. With a properly selected divider, the output
voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.8V reference. There
is an internal compensation to meet a typical application. In addition, the regulator power-good and undervoltage
protection circuitry use FB1 to monitor the Channel 1 regulator output voltage.
10
11
12
SGND
PG1
System ground.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the VOUT1 voltage.
SYNC
Connect to logic high or input voltage VIN . Connect to an external function generator for external Synchronization.
Negative edge trigger. Do not leave this pin floating. Do not tie this pin low (or to SGND).
13
EN1
Regulator Channel 1 enable pin. Enable the output, VOUT1, when driven to high. Shutdown the VOUT1 and discharge
output capacitor when driven to low. Do not leave this pin floating.
FN6853 Rev 3.00
August 17, 2012
Page 5 of 26
ISL8036, ISL8036A
Pin Descriptions(Continued)
PIN
NUMBER
SYMBOL
SS
DESCRIPTION
14
SS is used to adjust the soft-start time. When SS pin is tied to VIN, SS time is 1.5ms. SS pin is tied to VIN only in dual
mode operation. SS pin is tied to CSS only in parallel mode operation, using only external compensation. Connect a
capacitor from SS to SGND to adjust the soft-start time (current sharing). C should not be larger than 33nF. This
SS
capacitor, along with an internal 5µA current source sets the soft-start interval of the converter, t
(EQ. 1)
.
SS
C
F = 6.25 t s
SS
SS
15
VDD
PGND1
LX1
Input supply voltage for the logic. VDD to be at the same potential as VIN +0.3/-0.5V.
Negative supply for the power stage of Channel 1.
20, 21
18, 19
Switching node connection for Channel 1. Connect to one terminal of inductor for VOUT1.
Input supply voltage. Connect 22µF ceramic capacitor to power ground per channel.
16, 17
2, 3
VIN1,
VIN2
25
PAD
The exposed pad must be connected to the SGND pin for proper electrical performance. Add as much vias as possible
for optimal thermal performance.
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL8036IRZ
80 36IRZ
-40 to +85
-40 to +85
-40 to +85
-40 to +85
24 Ld 4x4 QFN
L24.4x4D
ISL8036IRZ-T (Note 1)
ISL8036AIRZ
80 36IRZ
24 Ld 4x4 QFN
24 Ld 4x4 QFN
24 Ld 4x4 QFN
L24.4x4D
L24.4x4D
L24.4x4D
80 36AIRZ
ISL8036AIRZ-T (Note 1)
ISL8036CRSHEVAL1Z
ISL8036DUALEVAL1Z
ISL8036ACRSHEVAL1Z
ISL8036ADUALEVAL1Z
NOTES:
80 36AIRZ
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus
anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8036, ISL8036A. For more information on MSL, please see Technical
Brief TB363.
FN6853 Rev 3.00
August 17, 2012
Page 6 of 26
ISL8036, ISL8036A
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ISL8036 Typical Operating Performance for Dual PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ISL8036A Typical Operating Performance for Dual PWM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
ISL8036 Typical Operating Performance for Current Sharing PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ISL8036A Typical Operating Performance for Current Sharing PWM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Output Current Sharing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Soft-start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power MOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PCB Layout Recommendation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
FN6853 Rev 3.00
August 17, 2012
Page 7 of 26
ISL8036, ISL8036A
Absolute Maximum Ratings (Reference to SGND)
Thermal Information
VIN1, VIN2, VDD . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V (DC) or 7V (20ms)
LX1, LX2 . . . . . . . . . . . . . -3V/(10ns)/-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V(20ms)/8.5V(10ns)
EN1, EN2, PG1, PG2, SYNC, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
FB1, FB2, COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
NC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
ESD Ratings
Thermal Resistance (Typical)
JA (°C/W)
36
JC (°C/W)
24 Ld 4x4 QFN (Notes 4, 5). . . . . . . . . . .
2
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 4kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 300V
Latch Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.85V to 6V
Load Current Range per Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions:
T = -40°C to +85°C, V = 3.6V, EN1 = EN2 = VDD, L = 1.5µH, C1 = C2 = C4 = 2x22µF, I
= I = 0A to 3A, unless otherwise noted. Typical values
OUT1 OUT2
A
IN
are at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
A
MIN
MAX
PARAMETER
INPUT SUPPLY
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
VIN Undervoltage Lockout Threshold
V
Rising
2.5
100
15
2.85
40
V
UVLO
Hysteresis
50
mV
mA
Quiescent Supply Current
I
SYNC = VDD, EN1 = EN2 = VDD,
F = 1MHz, no load at the output
VDD
S
F
= 2.5MHz, no load at the output
30
8
70
20
mA
µA
S
Shutdown Supply Current
OUTPUT REGULATION
FB1, FB2 Regulation Voltage
FB1, FB2 Bias Current
Load Regulation
I
V
= 6V, EN1 = EN2 = SGND
DD
SD
V
0.790
0.8
0.1
2
0.810
V
µA
FB
I
VFB = 0.75V
FB
SYNC = VDD, output load from 0A to 6A
mV/A
%/V
ms
Line Regulation
V
= V + 0.5V to 6V (minimal 2.85V)
0.1
1.5
5
IN
O
Soft-start Ramp Time Cycle
Soft-start Charging Current
COMPENSATION
SS = VDD
I
4
6
µA
SS
Error Amplifier Trans-Conductance
SS = VDD
20
100
0.2
µA/V
µA/V
Ω
SS with Capacitor
Trans-resistance
RT
0.180
-0.03
0.220
+0.03
Trans-resistance Matching
OVERCURRENT PROTECTION
Dynamic Current Limit ON-time
Dynamic Current Limit OFF-time
Positive Peak Overcurrent Limit
RT_match
Ω
t
17
8
Clock pulses
OCON
t
SS cycle
OCOFF
I
I
I
I
4.1
4.1
4.8
4.8
-2.5
-2.5
5.5
5.5
A
A
A
A
poc1
poc2
noc1
noc2
Negative Peak Overcurrent Limit
-3.5
-3.5
-1.5
-1.5
FN6853 Rev 3.00
August 17, 2012
Page 8 of 26
ISL8036, ISL8036A
Electrical Specifications Unless otherwise noted, the typical specifications are measured at the following conditions:
T = -40°C to +85°C, V = 3.6V, EN1 = EN2 = VDD, L = 1.5µH, C1 = C2 = C4 = 2x22µF, I
= I = 0A to 3A, unless otherwise noted. Typical values
OUT1 OUT2
A
IN
are at T = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
LX1, LX2
P-Channel MOSFET ON-Resistance
V
V
V
V
= 6V, I = 200mA
50
70
75
100
75
mΩ
mΩ
mΩ
mΩ
%
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 6V, I = 200mA
50
O
= 2.7V, I = 200mA
70
100
O
LX_ Maximum Duty Cycle
PWM Switching Frequency
100
1.1
2.5
F
ISL8036
0.88
2.15
2.64
1.32
2.85
6
MHz
MHz
MHz
°
S
ISL8036A
Synchronization Frequency Range
Channel 1 to Channel 2 Phase Shift
LX Minimum On Time
F
ISL8036 (Note 7)
Rising edge to rising edge timing
SYNC = High (PWM mode)
EN = LOW
SYNC
180
140
120
1
ns
Soft Discharge Resistance
LX Leakage Current
R
80
100
0.1
Ω
DIS
Pulled up to 6V
µA
PG1, PG2
Output Low Voltage
Sinking 1mA, VFB = 0.7V
0.3
0.1
V
µA
%
PG Pin Leakage Current
PG = V = 6V
IN
0.01
92
88
1
Internal PGOOD Low Rising Threshold
Internal PGOOD Low Falling Threshold
Delay Time (Rising Edge)
Percentage of nominal regulation voltage
Percentage of nominal regulation voltage
Time from VOUT_ reached regulation
89.5
85
94.5
91
%
ms
µs
Internal PGOOD Delay Time
(Falling Edge)
7
10
EN1, EN2, SYNC
Logic Input Low
0.4
V
Logic Input High
1.5
V
SYNC Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
I
Pulled up to 6V
Pulled up to 6V
0.1
0.1
150
25
1
1
µA
µA
°C
°C
SYNC
I
EN
Thermal Shutdown Hysteresis
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
7. The operational frequency per switching channel will be half of the SYNC frequency.
FN6853 Rev 3.00
August 17, 2012
Page 9 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, F = 1MHz.
SW
OUT1
OUT2
OUT2
100
100
90
80
90
2.5V
1.8V
OUT
2.5V
OUT
1.8V
OUT
OUT
80
70
60
50
40
OUT
1.5V
1.2V
1.2V
OUT
OUT
1.5V
OUT
OUT
3.3V
70
60
50
40
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
0.0
0.5
1.0
1.5
(A)
2.0
2.5
3.0
I
I
OUT
OUT
FIGURE 4. EFFICIENCY, V = 3.3V, T = +25°C
FIGURE 5. EFFICIENCY, V = 5V, T = +25°C
IN
A
IN
A
1.810
1.805
1.800
1.795
1.790
1.785
1.780
1.2
1.0
0.8
0.6
0.4
0.2
0
3.3V
IN
5V
5V
IN
IN
3.3V
IN
2.7V
1.0
IN
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.5
2.0
2.5
3.0
I
OUT
(A)
OUTPUT LOAD (A)
FIGURE 6. POWER DISSIPATION, V
OUT
= 1.8V, T = +25°C
FIGURE 7. V
REGULATION vs LOAD, 1.8V, T = +25°C
OUT A
A
1.810
LX1 2V/DIV
1.805
1.800
1.795
1.790
1.785
1.780
VOUT RIPPLE 20mV/DIV
0A LOAD
IL1 0.5A/DIV
2A LOAD
4.0
3A LOAD
3.0
2.5
3.5
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 8. OUTPUT VOLTAGE REGULATION vs V , 1.8V, T = +25°C
IN
FIGURE 9. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
A
FN6853 Rev 3.00
August 17, 2012
Page 10 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, F
= 1MHz. (Continued)
SW
OUT1
OUT2
LX2 2V/DIV
LX1 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT2 RIPPLE 20mV/DIV
IL1 2A/DIV
IL2 0.5A/DIV
FIGURE 11. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1
FIGURE 10. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
LX2 2V/DIV
VOUT RIPPLE 50mV/DIV
IL1 2A/DIV
VOUT RIPPLE 20mV/DIV
IL2 2A/DIV
FIGURE 12. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2
FIGURE 13. LOAD TRANSIENT CHANNEL 1
EN1 2V/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT 1V/DIV
IL1 0.5A/DIV
IL2 2A/DIV
PG1 5V/DIV
FIGURE 15. SOFT-START WITH NO LOAD CHANNEL 1
FIGURE 14. LOAD TRANSIENT CHANNEL 2
FN6853 Rev 3.00
August 17, 2012
Page 11 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, F
= 1MHz. (Continued)
SW
OUT1
OUT2
EN2 2V/DIV
EN1 2V/DIV
VOUT1 1V/DIV
IL1 2A/DIV
VOUT2 0.5V/DIV
IL2 0.5A/DIV
PG2 5V/DIV
PG1 5V/DIV
FIGURE 17. SOFT-START AT FULL LOAD CHANNEL 1
FIGURE 16. SOFT-START WITH NO LOAD CHANNEL 2
EN1 5V/DIV
EN2 2V/DIV
VOUT2 0.5V/DIV
IL2 2A/DIV
PG2 5V/DIV
VOUT1 0.5V/DIV
IL1 0.5A/DIV
PG1 5V/DIV
FIGURE 18. SOFT-START AT FULL LOAD CHANNEL 2
FIGURE 19. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
LX1 2V/DIV
EN2 2V/DIV
SYNCH 5V/DIV
VOUT2 0.5V/DIV
IL2 0.5A/DIV
VOUT1 RIPPLE 20mV/DIV
PG2 5V/DIV
IL1 1A/DIV
FIGURE 20. SOFT-DISCHARGE SHUTDOWN CHANNEL 2
FIGURE 21. STEADY STATE OPERATION CHANNEL 1 AT NO LOAD
WITH F
= 2.4MHz
SW
FN6853 Rev 3.00
August 17, 2012
Page 12 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, F = 1MHz. (Continued)
SW
OUT1
OUT2
LX2 2V/DIV
LX1 2V/DIV
SYNCH 5V/DIV
SYNCH 5V/DIV
VOUT1 RIPPLE 20mV/DIV
IL1 2A/DIV
VOUT2 RIPPLE 20mV/DIV
IL2 1A/DIV
FIGURE 22. STEADY STATE OPERATION CHANNEL 2 AT NO LOAD
WITH F = 2.4MHz
FIGURE 23. STEADY STATE OPERATION CHANNEL 1 AT FULL LOAD
WITH F = 2.4MHz
SW
SW
LX2 2V/DIV
LX1 2V/DIV
SYNCH 5V/DIV
SYNCH 5V/DIV
VOUT2 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
IL2 2A/DIV
IL1 2A/DIV
FIGURE 25. STEADY STATE OPERATION CHANNEL 1 AT NO LOAD
WITH F = 6MHz
FIGURE 24. STEADY STATE OPERATION CHANNEL 2 AT FULL LOAD
WITH F = 2.4MHz
SW
SW
LX2 2V/DIV
PHASE1 5V/DIV
VOUT1 1V/DIV
PG1 5V/DIV
SYNCH 5V/DIV
VOUT2 RIPPLE 20mV/DIV
IL2 2A/DIV
IL1 1A/DIV
FIGURE 26. STEADY STATE OPERATION CHANNEL 2 AT NO LOAD
WITH F = 5MHz
FIGURE 27. OUTPUT SHORT CIRCUIT CHANNEL 1
SW
FN6853 Rev 3.00
August 17, 2012
Page 13 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, F = 1MHz. (Continued)
SW
OUT1
OUT2
PHASE1 5V/DIV
PHASE2 5V/DIV
VOUT1 1V/DIV
IL1 1A/DIV
VOUT2 0.5V/DIV
IL2 1A/DIV
PG2 5V/DIV
PG1 5V/DIV
FIGURE 28. OUTPUT SHORT CIRCUIT RECOVERY (FROM HICCUP)
CHANNEL 1
FIGURE 29. OUTPUT SHORT CIRCUIT CHANNEL 2
PHASE2 5V/DIV
VOUT2 1V/DIV
IL2 1A/DIV
PG2 5V/DIV
FIGURE 30. OUTPUT SHORT CIRCUIT RECOVERY (FROM HICCUP) CHANNEL 2
FN6853 Rev 3.00
August 17, 2012
Page 14 of 26
ISL8036, ISL8036A
ISL8036A Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I
= 0A to 3A, L1 = L2 = 0.6µH,
OUT1
OUT2
F
= 2.5MHz.
SW
100
90
80
70
60
50
100
2.5V
OUT
3.3V
OUT
2.5V
OUT
90
80
70
60
50
1.2V
OUT
1.5V
1.5V
OUT
1.8V
OUT
OUT
1.2V
1.8V
OUT
OUT
40
0.0
40
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 32. EFFICIENCY vs LOAD, 5V DUAL CHANNEL 1,
IN
FIGURE 31. EFFICIENCY vs LOAD, 3.3V DUAL CHANNEL 1,
IN
T
= +25°C
T
= +25°C
A
A
1.50
1.25
1.00
0.75
0.50
0.25
1.810
1.805
1.800
1.795
1.790
1.785
1.780
2.7V
IN
3.3V
IN
5V
IN
3.3V
IN
2.7V
2.0
IN
5V
IN
0.00
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.5
3.0
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 33. POWER DISSIPATION vs LOAD, 1.8V
OUT
DUAL CHANNEL 1,
FIGURE 34. V
OUT
REGULATION vs LOAD, 1.8V
OUT
DUAL CHANNEL 1,
T
= +25°C
T = +25°C
A
A
1.810
1.805
1.800
1.795
1.790
1.785
1.780
LX1 2V/DIV
VOUT RIPPLE 20mV/DIV
IL1 0.5A/DIV
3A LOAD
3.0
1.5A LOAD
4.0
0A LOAD
5.0
2.5
3.5
4.5
5.5
INPUT VOLTAGE (V)
FIGURE 35. V
OUT
REGULATION vs V , 1.8V
IN OUT
DUAL CHANNEL 1,
FIGURE 36. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
T
= +25°C
A
FN6853 Rev 3.00
August 17, 2012
Page 15 of 26
ISL8036, ISL8036A
ISL8036A Typical Operating Performance for Dual PWM Operation
Unless otherwise noted, operating conditions are: V
= 1.8V; V
OUT2
= 0.8V; I
OUT1
= 0A to 3A; I = 0A to 3A, L1 = L2 = 0.6µH,
OUT2
OUT1
F
= 2.5MHz. (Continued)
SW
LX1 2V/DIV
LX1 1V/DIV
IL1 0.5A/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL1 2A/DIV
FIGURE 37. STEADY STATE OPERATION AT NO LOAD CHANNEL 2
FIGURE 38. STEADY STATE OPERATION AT FULL LOAD CHANNEL 1
LX1 1V/DIV
VOUT1 RIPPLE 50mV/DIV
IL1 2A/DIV
VOUT RIPPLE 20mV/DIV
IL1 2A/DIV
FIGURE 39. STEADY STATE OPERATION AT FULL LOAD CHANNEL 2
FIGURE 40. LOAD TRANSIENT CHANNEL 1
VOUT1 RIPPLE 50mV/DIV
IL1 2A/DIV
FIGURE 41. LOAD TRANSIENT CHANNEL 2
FN6853 Rev 3.00
August 17, 2012
Page 16 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Current Sharing PWM
Operation
Unless otherwise noted, operating conditions are: V
= 1.8V, I
+ I
= 0A to 6A, F
= 1MHz.
SW
OUT
OUT1 OUT2
100
100
90
80
70
60
50
40
90
2.5V
OUT
2.5V
OUT
80
70
60
50
40
1.5V
OUT
1.5V
1.8V
OUT
OUT
1.8V
OUT
1.2V
OUT
1.2V
OUT
3.3V
OUT
0
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 43. EFFICIENCY vs LOAD, V = 5V, T = +25°C
IN
FIGURE 42. EFFICIENCY vs LOAD, V = 3.3V, T = +25°C
A
IN
A
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.820
1.815
1.810
1.805
1.800
1.795
1.790
2.7V
IN
5V
IN
3.3V
IN
5V
IN
3.3V
5
IN
2.7V
IN
0
1
2
3
4
5
6
0
1
2
3
4
6
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 45. V
REGULATION vs LOAD, 1.8V, T = +25°C
A
FIGURE 44. POWER DISSIPATION vs LOAD, 1.8V, T = +25°C
A
OUT
1.820
1.815
1.810
1.805
1.815
3.3V
IN
5V
IN
1.810
1.805
1.800
1.795
1.790
1.785
5V
IN
3.3V
IN
2.7V
1.800
1.795
1.790
IN
2.7V
IN
1
0
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 46. V
OUT
REGULATION vs LOAD, 1.8V, T = -40°C
A
FIGURE 47. V
OUT
REGULATION vs LOAD, 1.8V, T = +85°C
A
FN6853 Rev 3.00
August 17, 2012
Page 17 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Current Sharing PWM
Operation
Unless otherwise noted, operating conditions are: V
= 1.8V, I
+ I
= 0A to 6A, F
= 1MHz. (Continued)
SW
OUT
OUT1 OUT2
1.820
LX1 2V/DIV
1.815
1.810
1.805
4A
0A
VOUT RIPPLE 20mV/DIV
1.800
IL1 0.5A/DIV
1.795
1.790
6A
2.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT VOLTAGE (V)
FIGURE 49. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
FIGURE 48. OUTPUT VOLTAGE REGULATION vs V , T = +25°C
IN
A
LX2 2V/DIV
LX1 2V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL1 2A/DIV
IL2 2A/DIV
FIGURE 51. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 2
FIGURE 50. STEADY STATE OPERATION WITH FULL LOAD CHANNEL 1
LX1 5V/DIV
LX1 5V/DIV
LX2 5V/DIV
LX2 5V/DIV
IL1 1A/DIV
IL2 1A/DIV
IL1 1A/DIV
IL2 1A/DIV
FIGURE 52. STEADY STATE OPERATION AT NO LOAD CHANNEL 1
AND 2
FIGURE 53. STEADY STATE OPERATION AT FULL LOAD CHANNEL 1
AND 2
FN6853 Rev 3.00
August 17, 2012
Page 18 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Current Sharing PWM
Operation
Unless otherwise noted, operating conditions are: V
= 1.8V, I
+ I
= 0A to 6A, F
= 1MHz. (Continued)
SW
OUT
OUT1 OUT2
EN1 2V/DIV
VOUT RIPPLE 50mV/DIV
VOUT 1V/DIV
IL1 0.5A/DIV
PG1 5V/DIV
IL1 2A/DIV
FIGURE 54. LOAD TRANSIENT CHANNEL 1
FIGURE 55. SOFT-START WITH NO LOAD CHANNEL 1
EN1 2V/DIV
EN1 5V/DIV
VOUT 1V/DIV
IL1 2A/DIV
PG1 5V/DIV
VOUT 0.5V/DIV
IL1 0.5A/DIV
PG1 5V/DIV
FIGURE 57. SOFT-DISCHARGE SHUTDOWN CHANNEL 1
FIGURE 56. SOFT-START AT FULL LOAD CHANNEL 1
LX1 2V/DIV
SYNC 5V/DIV
LX1 2V/DIV
SYNC 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL1 2A/DIV
IL1 1A/DIV
FIGURE 59. STEADY STATE OPERATION CH1 AT FULL LOAD WITH
= 3MHz
FIGURE 58. STEADY STATE OPERATION CH1 AT NO LOAD WITH
= 3MHz
F
F
SW
SW
FN6853 Rev 3.00
August 17, 2012
Page 19 of 26
ISL8036, ISL8036A
ISL8036 Typical Operating Performance for Current Sharing PWM
Operation
Unless otherwise noted, operating conditions are: V
OUT
= 1.8V, I
+ I
= 0A to 6A, F
= 1MHz. (Continued)
SW
OUT1 OUT2
LX1 2V/DIV
LX1 2V/DIV
SYNC 5V/DIV
SYNC 5V/DIV
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
IL1 1A/DIV
IL1 2A/DIV
FIGURE 60. STEADY STATE OPERATION CH1 AT NO LOAD WITH
FIGURE 61. STEADY STATE OPERATION CH1 AT FULL LOAD WITH
= 6MHz
F
= 6MHz
F
SW
SW
PHASE1 5V/DIV
PHASE1 5V/DIV
VOUT 1V/DIV
IL1 1A/DIV
VOUT 1V/DIV
PG1 5V/DIV
IL1 1A/DIV
PG1 5V/DIV
FIGURE 63. OUTPUT SHORT CIRCUIT RECOVERY (FROM HICCUP)
CHANNEL 1
FIGURE 62. OUTPUT SHORT CIRCUIT CHANNEL 1
FN6853 Rev 3.00
August 17, 2012
Page 20 of 26
ISL8036, ISL8036A
ISL8036A Typical Operating Performance for Current Sharing PWM
Operation
Unless otherwise noted, operating conditions are: V
OUT
= 1.8V, I
+ I
= 0A to 6A, L1 = L2 = 0.6µH, F
= 2.5MHz.
SW
OUT1 OUT2
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV
LX1 5V/DIV
LX1 5V/DIV
LX2 5V/DIV
LX2 5V/DIV
FIGURE 64. STEADY STATE OPERATION AT NO LOAD
FIGURE 65. STEADY STATE OPERATION AT FULL 6A LOAD
FN6853 Rev 3.00
August 17, 2012
Page 21 of 26
ISL8036, ISL8036A
Synchronization Control
Theory of Operation
The frequency of operation can be synchronized up to 6MHz by
an external signal applied to the SYNC pin. The 1st falling edge
on the SYNC triggered the rising edge of the PWM ON pulse of
Channel 1. The 2nd falling edge of the SYNC triggers the rising
edge of the PWM ON pulse of the Channel 2. This process
alternate indefinitely allowing 180° output phase operation
between the two channels.
The ISL8036, ISL8036A is a dual 3A or current sharing 6A
step-down switching regulator optimized for battery-powered or
mobile applications. The regulator operates at 1MHz (ISL8036) or
2.5MHz (ISL8036A) fixed switching frequency under heavy load
condition. The two channels are 180° out-of-phase operation. The
supply current is typically only 8µA when the regulator is shutdown.
PWM Control Scheme
Output Current Sharing
Pulling the SYNC pin HI (>1.5V) forces the converter into PWM mode
in the next switching cycle regardless of output current. Each of the
channels of the ISL8036, ISL8036A employ the current-mode
pulse-width modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting, as shown in the “Block
Diagram” on page 4 with waveforms in Figure 66. The current loop
consists of the oscillator, the PWM comparator COMP, current
sensing circuit, and the slope compensation for the current loop
stability. The current sensing circuit consists of the resistance of the
P-channel MOSFET when it is turned on and the current sense
amplifier CSA1. The gain for the current sensing circuit is typically
0.2V/A. The control reference for the current loops comes from the
error amplifier EAMP of the voltage loop.
The ISL8036, ISL8036A dual outputs are paralleled for
multi-phase operation in order to support a 6A output. Connect
the FBs together and connect all the COMPs together. Channel 1
and Channel 2 will be 180° out-of-phase. In parallel configuration,
external soft-start should be used to ensure proper full loading
start-up. Before using full load in current sharing mode, PWM
mode should be enabled. Likewise, multiple regulators can be
paralleled by connecting the FBs, COMPs, and SS for higher
current capability. External compensation is required.
Overcurrent Protection
CAS1 and CSA2 are used to monitor Output 1 and Output 2
channels respectively. The overcurrent protection is realized by
monitoring the CSA output with the OCP threshold logic, as
shown in Figure 4. The current sensing circuit has a gain of
0.2V/A, from the P-MOSFET current to the CSA_ output. When
the CSA1 output reaches the threshold, the OCP comparator is
tripped to turn off the P-MOSFET immediately. The overcurrent
function protects the switching converter from a shorted output by
monitoring the current flowing through the upper MOSFETs.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier CSA1 (or CSA2 on Channel 2) and the
compensation slope (0.46V/µs) reaches the control reference of
the current loop, the PWM comparator COMP sends a signal to the
PWM logic to turn off the P-MOSFET and to turn on the N-channel
MOSFET. The N-MOSFET stays on until the end of the PWM cycle.
Figure 66 shows the typical operating waveforms during the PWM
operation. The dotted lines illustrate the sum of the compensation
ramp and the current-sense amplifier CSA_ output.
Upon detection of overcurrent condition, the upper MOSFET will
be immediately turned off and will not be turned on again until
the next switching cycle. Upon detection of the initial overcurrent
condition, the Overcurrent Fault Counter is set to 1 and the
Overcurrent Condition Flag is set from LOW to HIGH. If, on the
subsequent cycle, another overcurrent condition is detected, the
OC Fault Counter will be incremented. If there are 17 sequential
OC fault detections, the regulator will be shutdown under an
Overcurrent Fault Condition. An Overcurrent Fault Condition will
result with the regulator attempting to restart in a hiccup mode
with the delay between restarts being 8 soft-start periods. At the
end of the eighth soft-start wait period, the fault counters are
reset and soft-start is attempted again. If the overcurrent
condition goes away prior to the OC Fault Counter reaching a
count of four, the Overcurrent Condition Flag will set back to LOW.
VEAMP
VCSA1
Duty
Cycle
IL
VOUT
If the negative output current reaches -2.5A, the part enters
Negative Overcurrent Protection. At this point, all switching stops
and the part enters tri-state mode while the pull-down FET is
discharging the output until it reaches normal regulation voltage,
then the IC restarts.
FIGURE 66. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a 0.8V
reference voltage to the voltage control loop. The feedback signal
comes from the VFB pin. The soft-start block only affects the
operation during the start-up and will be discussed separately.
The error amplifier is a transconductance amplifier that converts
the voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 390kΩ RC network.
The maximum EAMP voltage output is precisely clamped to the
bandgap voltage (1.172V).
PG
There are two independent power-good signals. PG1 monitors
the Output Channel 1 and PG2 monitors the Output Channel 2.
When powering up, the open-collector Power-on Reset output
holds low for about 1ms after V reaches the preset voltage. The
O
PG_ output also serves as a 1ms delayed Power-Good signal.
FN6853 Rev 3.00
August 17, 2012
Page 22 of 26
ISL8036, ISL8036A
output voltage ripple, the output inductor value can be increased.
The inductor ripple current can be expressed in Equation 2:
UVLO
When the input voltage is below the undervoltage lock out (UVLO)
threshold, the regulator is disabled.
V
O
---------
V
1 –
(EQ. 2)
O
V
IN
Enable
--------------------------------------
I =
L f
S
The enable (EN) input allows the user to control the turning on or
off the regulator for purposes such as power-up sequencing.
When the regulator is enabled, there is typically a 600µs delay
for waking up the bandgap reference. Then the soft start-up
begins.
The inductor’s saturation current rating needs be at least larger than
the peak current. The ISL8036, ISL8036A protects the typical peak
current 4.8A. The saturation current needs be over 4.8A for maximum
output current application.
ISL8036, ISL8036A uses an internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R. The
recommended minimum output capacitor values for the ISL8036,
ISL8036A are shown in Table 4.
Soft-start-up
The soft-start-up eliminates the inrush current during the
start-up. The soft-start block outputs a ramp reference to both
the voltage loop and the current loop. The two ramps limit the
inductor current rising speed as well as the output voltage speed
so that the output voltage rises in a controlled fashion. At the
very beginning of the start-up, the output voltage is less than
0.5V; hence the PWM operating frequency is 1/2 of the normal
frequency.
TABLE 4. OUTPUT CAPACITOR VALUE vs V
OUT
ISL8036, ISL8036A
V
C
L
OUT
OUT
(V)
0.8
1.2
1.6
1.8
2.5
3.3
3.6
(µF)
2 x 22
2 x 22
2 x 22
2 x 22
2 x 22
2 x 6.8
10
(µH)
1.0~2.2
1.0~2.2
1.0~2.2
1.0~3.3
1.0~3.3
1.0~4.7
1.0~4.7
When the IC ramps up at start-up, it can't sink current even at
PWM mode, behaving like in diode emulated mode for the
soft-start time.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs, or the output
undervoltage fault latch is set, its output discharges to PGND
through an internal 100 switch.
Power MOSFETs
In Table 4, the minimum output capacitor value is given for
different output voltages to make sure the whole converter
system is stable.
The power MOSFETs are optimize for best efficiency. The
ON-resistance for the P-MOSFET is typically 50m and the
ON-resistance for the N-MOSFET is typical 50m.
Output Voltage Selection
100% Duty Cycle
The output voltage of the regulator can be programmed via an
external resistor divider, which is used to scale the output voltage
relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 2.
The ISL8036, ISL8036A features 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to a
level that the ISL8036, ISL8036A can no longer maintain the
regulation at the output, the regulator completely turns on the
P-MOSFET. The maximum drop-out voltage under the 100%
duty-cycle operation is the product of the load current and the
ON-resistance of the P-MOSFET.
The output voltage programming resistor, R (or R in
2
5
Channel 2), will depend on the desired output voltage of the
regulator. The value for the feedback resistor is typically between
0 and 750k. Let R = 124k, then R will be:
2
3
Thermal Shutdown
R x0.8V
2
(EQ. 3)
----------------------------------
=
3
The ISL8036, ISL8036A has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is completely
shutdown. As the temperature drops to +125°C, the ISL8036,
ISL8036A resumes operation by stepping through a soft start-up.
R
V
– 0.8V
OUT
For better performance, add 12pF in parallel with R If the
2
output voltage desired is 0.8V, then leave R unpopulated and
3
short R .
2
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operation, ISL8036,
ISL8036A typically uses a 1.5µH output inductor. Higher or lower
inductor value can be used to optimize the total converter system
performance. For example, for a higher output voltage 3.3V
application, in order to decrease the inductor current ripple and
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. One 22µF X5R or X7R ceramic capacitor is a good
starting point for the input capacitor selection per channel.
FN6853 Rev 3.00
August 17, 2012
Page 23 of 26
ISL8036, ISL8036A
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For ISL8036, ISL8036A,
the power loop is composed of the output inductor L’s, the output
capacitor C
and C , the LX’s pins, and the PGND pin. It is
OUT1
OUT2
necessary to make the power loop as small as possible and the
connecting traces among them should be direct, short and wide.
The switching node of the converter, the LX_ pins, and the traces
connected to the node are very noisy, so keep the voltage
feedback trace away from these noisy traces. The FB network
should be as close as possible to its FB pin. SGND should have one
single connection to PGND. The input capacitor should be placed
as closely as possible to the VIN pin. Also, the ground of the input
and output capacitors should be connected as closely as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least 5 vias ground connection within the pad for the best
thermal relief.
© Copyright Intersil Americas LLC 2010-2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6853 Rev 3.00
August 17, 2012
Page 24 of 26
ISL8036, ISL8036A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
July 18, 2012
FN6853.3 page 5
Comments added, COMP pin:
COMP pin is NC in dual mode operation, using internal compensation. If SS pin is tied to CSS (without VIN connection),
external compensation is automatically used. Connect an external R,C network on COMP pin for parallel mode
operation.
Comments added, SS pin:
When SS pin is tied to VIN, SS time is 1.5ms. SS pin is tied to VIN only in dual mode operation.
SS pin is tied to CSS only in parallel mode operation, using only external compensation.
page 6 Ordering Information table, added evals:
ISL8036ACRSHEVAL1Z, ISL8036ADUALEVAL1Z, ISL8036CRSHEVAL1Z, ISL8036DUALEVAL1Z
page 15
Figure 33 title correction: "1.8VIN" on the title of these is changed to "1.8VOUT".
Figure 34 title correction: "1.8VIN" on the title of these is changed to "1.8VOUT"
Figure 35 title correction: "1.8VIN" on the title of these is changed to "1.8VOUT"
page 18, Figure 48, deleted "1.8V" in the title since the condition is mentioned in the page header.
page 22
Line 4 in Overcurrent Protection paragraph, instead of "Figure 66" changed to "Figure 4".
"with the delay between restarts being 4 soft-start periods" changed to "with the delay between restarts being 8
soft-start periods".
"end of the fourth soft-start wait period" to "end of the eighth soft-start wait period"
October 14, 2011 FN6853.2 Added “Related Literature” on page 1.
In the “Absolute Maximum Ratings” on page 8, changed:
“LX1, LX2....-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)”
to:
“LX1, LX2....-3V/(10ns)/-1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)/8.5V(10ns)”
October 12, 2010 FN6853.1 In Table 3 on page 3, corrected F
September 28, 2010 FN6853.0 Initial release.
for ISL8036 from 1Hz to 1MHz.
SW
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL8036, ISL8036A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
FN6853 Rev 3.00
August 17, 2012
Page 25 of 26
ISL8036, ISL8036A
Package Outline Drawing
L24.4x4D
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 10/06
4X
2.5
4.00
A
20X
0.50
PIN #1 CORNER
(C 0 . 25)
B
19
24
PIN 1
INDEX AREA
1
18
2 . 50 ± 0 . 15
13
0.15
(4X)
12
24X 0 . 4 ± 0 . 1
7
0.10 M C
A B
TOP VIEW
+ 0 . 07
24X 0 . 23
4
- 0 . 05
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3 . 8 TYP )
SEATING PLANE
0.08
SIDE VIEW
C
(
2 . 50 )
( 20X 0 . 5 )
5
C
0 . 2 REF
( 24X 0 . 25 )
0 . 00 MIN.
0 . 05 MAX.
( 24X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6853 Rev 3.00
August 17, 2012
Page 26 of 26
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