ISL84051IBZ_技术文档

ISL84051, ISL84052, ISL84053

®

Data Sheet

March 15, 2007

FN6047.7

Low Voltage, Single and Dual Supply,

8 to 1 Multiplexer, Dual 4 to 1 Multiplexer

and a Triple SPDT Analog Switch

Features

• Drop-in Replacements for MAX4051/A, MAX4052/A and

MAX4053/A

The Intersil ISL84051, ISL84052, ISL84053 devices are

precision, bidirectional, analog switches configured as a

8-Channel multiplexer/demultiplexer (ISL84051), a dual

differential 4-Channel multiplexer/demultiplexer (ISL84052)

and a triple single pole/double throw (SPDT) switch

(ISL84053) designed to operate from a single +2V to +12V

supply or from a ±2V to ±6V supply. All devices have an inhibit

pin to simultaneously open all signal paths.

• Pin Compatible with MAX4581, MAX4582, MAX4583 and

with Industry Standard 74HC4051, 74HC4052 and

74HC4053

• ON Resistance (r ) Max, V = ±5V . . . . . . . . . . . . 100Ω

ON

S

• ON Resistance (r ) Max, V = +3V. . . . . . . . . . . . 525Ω

ON

S

• r

ON

Matching Between Channels . . . . . . . . . . . . . . . . . . <6Ω

• Low Charge Injection . . . . . . . . . . . . . . . . . . . . . 10pC (Max)

• Single Supply Operation. . . . . . . . . . . . . . . . . . . +2V to +12V

• Dual Supply Operation . . . . . . . . . . . . . . . . . . . . . . ±2V to ±6

ON resistance is 60Ω with a ±5V supply and 125Ω with a

single +5V supply. Each switch can handle rail to rail analog

signals. The off-leakage current is only 0.1nA at +25°C or

5nA at +85°C with a ±5V supply.

• Fast Switching Action (V = +5V)

S

All digital inputs have 0.8V to 2.4V logic thresholds, ensuring

TTL/CMOS logic compatibility when using a single +3.3V

and +5V supply or dual ±5V supplies.

- t

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90ns

ON

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60ns

OFF

• Guaranteed Max Off-leakage @ V = ±5V. . . . . . . . . . 5nA

S

The ISL84051 is a 8 to 1 multiplexer device. The ISL84052 is

a dual 4 to 1 multiplexer device. The ISL84053 is a committed

triple SPDT, which is perfect for use in 2-to-1 multiplexer

applications.

• Guaranteed Break-Before-Make

• TTL, CMOS Compatible

• Pb-Free Plus Anneal Available (RoHS Compliant)

Table 1 summarizes the performance of this family.

Applications

TABLE 1. FEATURES AT A GLANCE

• Portable Equipment

ISL84051

ISL84052

ISL84053

• Communications Systems

- Radios

DUAL

4:1 Mux

TRIPLE

SPDT

CONFIGURATION

±5V r

8:1 Mux

60Ω

- Telecom Infrastructure

- ADSL, VDSL Modems

60Ω

50ns/40ns

125Ω

60Ω

50ns/40ns

125Ω

ON

±5V t /t

50ns/40ns

125Ω

ON OFF

• Test Equipment

5V r

ON

- Medical Ultrasound

- Magnetic Resonance Image

- CT and PET Scanners (MRI)

- ATE

5V t /t

90ns/60ns

250Ω

90ns/60ns

250Ω

90ns/60ns

250Ω

ON OFF

3V r

ON

3V t /t

180ns/100ns 180ns/100ns 180ns/100ns

ON OFF

Packages

- Electrocardiograph

16 Ld SOIC,

16 Ld SSOP

16 Ld TSSOP 16 Ld TSSOP

16 Ld SOIC, 16 Ld SOIC,

16 Ld SSOP 16 Ld SSOP

• Audio and Video Signal Routing

• Various Circuits

- +3V/+5V DACs and ADCs

- Sample and Hold Circuits

- Operational Amplifier Gain Switching Networks

- High Frequency Analog Switching

- High Speed Multiplexing

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

• Application Note AN557 “Recommended Test Procedures

for Analog Switches”

- Integrator Reset Circuits

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL84051, ISL84052, ISL84053

Pinouts

ISL84051

(16 LD SOIC, SSOP, TSSOP)

TOP VIEW

ISL84052

(16 LD SOIC, SSOP, TSSOP)

TOP VIEW

NO1

NO3

COM

NO7

NO5

INH

1

2

3

4

5

6

7

8

16 V+

NO0B

1

2

3

4

5

6

7

8

16 V+

15 NO2

14 NO4

13 NO0

12 NO6

11 ADDC

10 ADDB

NO1B

COMB

NO3B

NO2B

INH

15 NO1A

14 NO2A

13 COMA

12 NO0A

11 NO3A

10 ADDB

LOGIC

V-

LOGIC

9

ADDA

GND

9

ADDA

GND

ISL84053

(16 LD SOIC, SSOP)

TOP VIEW

NOB

NCB

NOA

COMA

NCA

INH

1

2

3

4

5

6

7

8

16 V+

15 COMB

14 COMC

13 NOC

12 NCC

11 ADDC

10 ADDB

V-

9

ADDA

GND

NOTE:

1. Switches Shown for Logic “0” Inputs.

FN6047.7

March 15, 2007

2

ISL84051, ISL84052, ISL84053

Ordering Information

Truth Tables

TEMP.

ISL84051

PART

NUMBER

PART

MARKING

RANGE

(°C)

PKG.

DWG. #

SWITCH

ON

PACKAGE

INH

1

ADDC

ADDB

ADDA

ISL84051IB* 84051IB

-40 to +85 16 Ld SOIC M16.15

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

None

NO0

NO1

NO2

NO3

NO4

NO5

NO6

NO7

ISL84051IBZ* 84051IBZ

(Note)

-40 to +85 16 Ld SOIC M16.15

(Pb-free)

0

ISL84051IA* 84051 IA

-40 to +85 16 Ld SSOP M16.15A

0

ISL84051IAZ* 84051 IAZ

(Note)

-40 to +85 16 Ld SSOP M16.15A

(Pb-free)

0

ISL84051IVZ* 84051 IVZ

(Note)

-40 to +85 16 Ld TSSOP M16.173

(Pb-free)

0

ISL84052IB* 84052IB

-40 to +85 16 Ld SOIC M16.15

0

ISL84052IBZ* 84052IBZ

(Note)

-40 to +85 16 Ld SOIC M16.15

(Pb-free)

0

ISL84052IA* 84052 IA

-40 to +85 16 Ld SSOP M16.15A

ISL84052IAZ* 84052 IAZ

(Note)

-40 to +85 16 Ld SSOP M16.15A

(Pb-free)

ISL84052

ISL84052IVZ* 84052IVZ

(Note)

-40 to +85 16 Ld TSSOP M16.173

(Pb-free)

INH

1

ADDB

ADDA

SWITCH ON

None

ISL84053IB* 84053IB

-40 to +85 16 Ld SOIC M16.15

X

0

1

X

0

1

0

1

ISL84053IBZ* 84053IBZ

(Note)

-40 to +85 16 Ld SOIC M16.15

(Pb-free)

0

NO0

ISL84053IA* 84053 IA

-40 to +85 16 Ld SSOP M16.15A

0

NO1

ISL84053IAZ* 84053 IAZ

(Note)

-40 to +85 16 Ld SSOP M16.15A

(Pb-free)

0

NO2

0

NO3

*Add “-T” suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

ISL84053

INH

ADD

X

ADD

A

SWITCH ON

C

B

1

0

X

0

X

0

None

X

NC

NO

NC

NO

A

B

C

X

1

Pin Description

0

X

V+

V-

FUNCTION

1

Positive Power Supply Input

X

NC

NO

Negative Power Supply Input. Connect to GND for

Single Supply Configurations.

1

X

NOTE: Logic “0” ≤0.8V. Logic “1” ≥2.4V, with V+ between 2.7V and

10V. X = Don’t Care.

GND

INH

Ground Connection

Digital Control Input. Connect to GND for Normal

Operation. Connect to V+ to turn all switches off.

COM

NO

Analog Switch Common Pin

Analog Switch Normally Open Pin

Analog Switch Normally Closed Pin

Address Input Pin

NC

ADD

FN6047.7

March 15, 2007

3

ISL84051, ISL84052, ISL84053

Absolute Maximum Ratings

Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V

V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 15V

V- to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15V to 0.3V

Input Voltages

Thermal Resistance (Typical, Note 3)

θ

(°C/W)

JA

16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .

16 Ld SSOP Package . . . . . . . . . . . . . . . . . . . . . . .

16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .

115

160

150

INH, NO, NC, ADD (Note 2). . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)

Output Voltages

COM (Note 2). . . . . . . . . . . . . . . . . . . ((V-) - 0.3) to ((V+) + 0.3V)

Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . ±30mA

Peak Current NO, NC, or COM

Maximum Junction Temperature (Plastic Package). . . . . . . +150°C

Maximum Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C

(Lead Tips Only)

(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . ±100mA

ESD Rating

HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >2kV

Operating Conditions

Temperature Range

ISL8405XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. Signals on NC, NO, COM, ADD, or INH exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current

ratings.

3. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

Electrical Specifications - 5V Supply

Test Conditions: V

Unless Otherwise Specified

= ±4.5V to ±5.5V, GND = 0V, V

INH

= 2.4V, V

= 0.8V (Note 4),

INL

SUPPLY

TEMP

(°C)

MIN

(NOTE 5)

MAX

(NOTE 5) UNITS

PARAMETER

TEST CONDITIONS

TYP

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

V-

-

V+

100

125

6

V

ON Resistance, r

V

= ±5V, I

= 1mA, V

or V

= ±3V,

60

Ω

ON

S

COM

NO

NC

(See Figure 5)

-

Ω

r

Matching Between Channels,

V

= ±5V, I

= 1mA, V

or V

= ±3V, (Note 6)

= ±3V, 0V,

-

Ω

ON

Δr

S

COM

NO

NC

ON

-

12

10

15

0.1

5

Ω

r

Flatness, r

FLAT(ON)

= 1mA, V

or V

-

Ω

ON

NO

NC

(Note 7)

-

Ω

NO or NC OFF Leakage Current,

or I

V

= ±5.5V, V

COM

= ±4.5V, V

or V

= ±4.5V,

-0.1

-5

0.002

nA

S

NO

NC

I

(Note 8)

NO(OFF)

NC(OFF)

-

COM OFF Leakage Current,

, (ISL84051)

V

= ±5.5V, V

-0.1

-5

0.002

0.1

5

S

COM

I

(Note 8)

COM(OFF)

-

COM OFF Leakage Current,

, (ISL84052, ISL84053)

V

= ±5.5V, V

-0.1

-2.5

-0.1

-5

0.002

0.1

2.5

0.1

5

S

I

(Note 8)

COM(OFF)

-

COM ON Leakage Current,

, (ISL84051)

V

= ±5.5V, V

= V

or V

= ±4.5V,

0.002

S

NO

NC

I

(Note 8)

COM(ON)

-

0.002

-

COM ON Leakage Current,

, (ISL84052, ISL84053)

V

= ±5.5V, V

or V

= ±4.5V, (Note 8)

-0.1

-2.5

0.1

2.5

S

NC

I

COM(ON)

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V , V

Full

2.4

-

0.8

1

V

INH ADDH

Input Voltage Low, V , V

INL ADDL

Input Current, I

, I , I

,

V

= ±5.5V, V

S

, V

INH ADD

= 0V or V+

-1

0.03

µA

INH INL ADDH

I

ADDL

FN6047.7

March 15, 2007

4

ISL84051, ISL84052, ISL84053

Electrical Specifications - 5V Supply

Test Conditions: V

Unless Otherwise Specified (Continued)

= ±4.5V to ±5.5V, GND = 0V, V

INH

= 2.4V, V

= 0.8V (Note 4),

INL

SUPPLY

TEMP

(°C)

MIN

(NOTE 5)

MAX

(NOTE 5) UNITS

PARAMETER

TEST CONDITIONS

TYP

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

V

C

= ±4.5V, V

or V

= ±3V, R = 300Ω,

+25

Full

+25

Full

+25

-

50

-

175

225

150

200

250

ns

ON

S

NO

NC

L

= 35pF, V = 0 to 3, (See Figure 1)

L

IN

Inhibit Turn-OFF Time, t

V

C

= ±4.5V, V

or V

= ±3V, R = 300Ω,

40

-

OFF

S

NO

NC

L

= 35pF, V = 0 to 3, (See Figure 1)

L

IN

Address Transition Time, t

Break-Before-Make Time, t

Charge Injection, Q

V

C

= ±4.5V, V

or V

= ±3V, R = 300Ω,

75

TRANS

S

NO

NC

L

= 35pF, V = 0 to 3, (See Figure 1)

L

IN

V

C

= ±5.5V, V

or V

= 3V, R = 300Ω,

+25

2

10

-

ns

BBM

S

NO

NC

L

= 35pF, V = 0 to 3V, (See Figure 3)

L

IN

C

= 1.0nF, V = 0V, R = 0Ω, (See Figure 2)

+25

-

2

3

10

-

pC

pF

dB

L

G

NO/NC OFF Capacitance, C

OFF

f = 1MHz, V

or V

NC

= V

= 0V, (See Figure 7)

COM

NO

COM OFF Capacitance, C

f = 1MHz, V

(See Figure 7)

or V

= V

= 0V,

ISL84051

ISL84052

ISL84053

ISL84051

ISL84052

ISL84053

21

12

9

-

OFF

NO

NC

COM

-

COM ON Capacitance, C

OFF Isolation

f = 1MHz, V

or V

= V

= 0V,

26

18

14

<90

< -90

-

COM(ON)

NO

(See Figure 7)

NC

COM

-

R

V

= 50Ω, C = 15pF, f = 100kHz,

-

L

or V

= 1V

, (See Figures 4 and 6)

NO

NC

RMS

Crosstalk, (Note 9) (ISL84052,

ISL84053 Only)

-

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

+25

Full

25

±2

-1

-

0.1

-

±6

1

V

Positive Supply Current, I+

Negative Supply Current, I-

NOTES:

V

Off

= ±5.5V, V

, V

INH ADD

= 0V or V+, Switch On or

µA

S

-10

-1

10

1

0.1

-

Full

-10

10

4. V = Input voltage to perform proper function.

IN

5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.

6. Δr = r (MAX) - r (MIN).

ON

7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.

8. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at +25°C.

9. Between any two switches.

FN6047.7

March 15, 2007

5

ISL84051, ISL84052, ISL84053

Electrical Specifications: 5V Supply

Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V

Unless Otherwise Specified

= 2.4V, V

= 0.8V (Note 4),

INL

INH

TEMP

(°C)

MIN

(NOTE 5)

MAX

(NOTE 5) UNITS

PARAMETER

TEST CONDITIONS

TYP

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

0

-

V+

225

280

1

V

ON Resistance, r

V+ = 5V, I

= 1.0mA, V

or V = 3.5V,

NC

125

Ω

ON

COM

(See Figure 5)

NO

-

Ω

NO or NC OFF Leakage Current,

or I

V+ = 5.5V, V

(Note 8)

= 0V, 4.5V, V

or V

= 4.5V, 0V,

-1

-10

-1

-10

-1

-5

-1

-10

0.002

nA

COM

NO

NC

I

NO(OFF)

NC(OFF)

-

10

1

COM OFF Leakage Current,

, (ISL84051)

V+ = 5.5V, V

(Note 8)

0.002

I

COM(OFF)

-

10

1

COM OFF Leakage Current,

V+ = 5.5V, V

0.002

NO

I

, (ISL84052, ISL84053) (Note 8)

COM(OFF)

-

0.002

-

5

COM ON Leakage Current,

V+ = 5.5V, V

= V

or V

4.5V, (Note 8)

1

NO

NC =

I

COM(ON)

10

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V , V

Full

2.4

-

0.8

1

V

INH ADDH

Input Voltage Low, V , V

INL ADDL

, I , I

Input Current, I

INH INL ADDH

,

V+ = 5.5V, V

, V

INH ADD

= 0V or V+

-1

0.03

µA

I

ADDL

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

V+ = 4.5V, V

or V

= 3V, R = 300Ω, C = 35pF,

+25

Full

+25

Full

+25

-

90

-

200

275

125

175

-

ns

ON

NO

NC

L

V

= 0 to 3V, (See Figure 1)

IN

Inhibit Turn-OFF Time, t

OFF

V+ = 4.5V, V

or V

= 3V, R = 300Ω, C = 35pF,

60

-

NO

NC

L

V

= 0V to 3V, (See Figure 1)

IN

Break-Before-Make Time, t

V+ = 5.5V, V

or V

= 3V, R = 300Ω, C = 35pF,

30

BBM

NO

NC

L

V

C

R

= 0V to 3V, (See Figure 3)

IN

Charge Injection, Q

OFF Isolation

= 1.0nF, V = 0V, R = 0Ω, (See Figure 2)

+25

-

2

10

-

pC

dB

L

G

= 50Ω, C = 15pF, f = 100kHz,

<90

<-90

L

V

or V

= 1V

, (See Figures 4 and 6)

NO

NC

RMS

Crosstalk, (Note 9) (ISL84052,

ISL840533 Only)

-

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

+25

Full

2

-

12

1

V

Positive Supply Current, I+

V+ = 5.5V, V- = 0V, V

Switch On or Off

, V

INH ADD

= 0V or V+,

-1

µA

-10

10

FN6047.7

March 15, 2007

6

ISL84051, ISL84052, ISL84053

Electrical Specifications: 3.3V Supply

Test Conditions: V+ = +3.0V to +3.6V, V- = GND = 0V, V

Unless Otherwise Specified

= 2.4V, V

= 0.8V (Note 4),

INL

INH

TEMP

(°C)

MIN

(NOTE 5)

MAX

(NOTE 5) UNITS

PARAMETER

TEST CONDITIONS

TYP

ANALOG SWITCH CHARACTERISTICS

Analog Signal Range, V

ANALOG

Full

+25

Full

+25

Full

+25

Full

+25

Full

+25

Full

0

-

V+

525

700

1

V

ON Resistance, r

V+ = 3V, I

= 1.0mA, V

or V = 1.5V

NC

250

Ω

ON

COM

NO

-

Ω

NO or NC OFF Leakage Current,

or I

V+ = 3.6V, V

(Note 8)

= 0V, 3V, V

or V

= 3V, 0V,

-1

-10

-1

-10

-1

-5

-1

-10

0.002

nA

COM

NO

NC

I

NO(OFF)

NC(OFF)

-

10

1

COM OFF Leakage Current,

, (ISL84051)

V+ = 3.6V, V

(Note 8)

or V

= 3V, 0V,

0.002

I

COM(OFF)

-

10

1

COM OFF Leakage Current,

V+ = 3.6V, V

0.002

I

, (ISL84052, ISL84053) (Note 8)

COM(OFF)

-

0.002

-

5

COM ON Leakage Current,

V+ = 3.6V, V

= V

or V

3V, (Note 8)

NC =

1

NO

I

COM(ON)

10

DIGITAL INPUT CHARACTERISTICS

Input Voltage High, V , V

Full

2.4

-

0.8

1

V

INH ADDH

Input Voltage Low, V , V

INL ADDL

, I , I

Input Current, I

INH INL ADDH

,

V+ = 3.6V, V

, V

INH ADD

= 0V or V+

-1

0.03

µA

I

ADDL

DYNAMIC CHARACTERISTICS

Inhibit Turn-ON Time, t

V+ = 3V, V

NO

or V

= 1.5V, R = 300Ω, C = 35pF,

+25

Full

+25

Full

+25

-

180

-

600

700

300

400

-

ns

ON

NC

= 0 to 3V, (See Figure 1)

L

V

IN

Inhibit Turn-OFF Time, t

OFF

V+ = 3V, V

NO

or V

= 1.5V, R = 300Ω, C = 35pF,

100

-

NC

= 0 to 3V, (See Figure 1)

L

V

IN

Break-Before-Make Time, t

V+ = 3.6V, V

or V

= 1.5V, R = 300Ω, C = 35pF,

90

BBM

NO

NC

L

V

C

R

= 0 to 3V, (See Figure 3)

IN

Charge Injection, Q

OFF Isolation

= 1.0nF, V = 0V, R = 0Ω, (See Figure 2)

+25

-

1

10

-

pC

dB

L

G

= 50Ω, C = 15pF, f = 100kHz,

<90

<-90

L

V

or V

= 1V

, (See Figures 4 and 6)

NO

NC

RMS

Crosstalk, (Note 9) (ISL84052,

ISL84053 Only)

-

POWER SUPPLY CHARACTERISTICS

Power Supply Range

Full

+25

Full

2

-

12

1

V

Positive Supply Current, I+

V+ = 3.6V, V- = 0V, V

Switch On or Off

, V

INH ADD

= 0V or V+,

-1

µA

-10

10

FN6047.7

March 15, 2007

7

ISL84051, ISL84052, ISL84053

Test Circuits and Waveforms

V+

V-

C

V+

NO0

ISL84051

V

OUT

COM

NO1-NO7

INH

ADDA-C

GND

C

35pF

L

R

300Ω

LOGIC

INPUT

L

V+

C

V-

C

3V

t < 20ns

r

t < 20ns

f

LOGIC

INPUT

50%

V+

NO0

ISL84052

0V

V

OUT

COM

NO1-NO3

INH

t

ON

V

ADDA-B

GND

C

L

35pF

R

300Ω

LOGIC

INPUT

OUT

L

90%

SWITCH

OUTPUT

0V

t

OFF

V+

C

V-

Logic input waveform is inverted for switches that have the opposite

logic sense.

C

V+

NC

X

ISL84053

COM

V

OUT

NO

X

INH

ADD

GND

X

C

35pF

L

R

300Ω

L

LOGIC

INPUT

Repeat test for other switches. C includes fixture and stray

L

capacitance.

R

L

+ r

ON

-----------------------

L

V

= V

OUT

(NO or NC)

R

FIGURE 1B. INHIBIT t /t

ON OFF

TEST CIRCUIT

FIGURE 1A. INHIBIT t /t

ON OFF

MEASUREMENT POINTS

FIGURE 1. SWITCHING TIMES

FN6047.7

March 15, 2007

8

ISL84051, ISL84052, ISL84053

Test Circuits and Waveforms (Continued)

V+

V-

C

V+

NO0

NO7

ISL84051

COM

V

V-

OUT

C

NO1-NO6

ADDA-C

INH

GND

C

35pF

L

R

300Ω

L

LOGIC

INPUT

V+

V-

C

3V

0V

t < 20ns

r

t < 20ns

f

LOGIC

INPUT

50%

V+

NO0

ISL84052

COM

V

OUT

t

V-

NO3

TRANS

C

NO1-NO2

V

ADDA-B

OUT

INH

VNOX

0V

GND

C

35pF

90%

L

R

300Ω

L

LOGIC

INPUT

SWITCH

OUTPUT

10%

VNOX

V+

V-

C

t

TRANS

Logic input waveform is inverted for switches that have the opposite

logic sense.

V+

NC

ISL84053

COM

X

V

OUT

V-

NO

X

C

ADD

X

INH

GND

C

35pF

L

R

300Ω

LOGIC

INPUT

L

Repeat test for other switches. C includes fixture and stray

L

capacitance.

R

L

+ r

ON

-----------------------

L

V

= V

OUT

(NO or NC)

R

FIGURE 1D. ADDRESS t

TEST CIRCUIT

TRANS

FIGURE 1C. ADDRESS t

MEASUREMENT POINTS

TRANS

FIGURE 1. SWITCHING TIMES (Continued)

FN6047.7

March 15, 2007

9

ISL84051, ISL84052, ISL84053

Test Circuits and Waveforms (Continued)

V+

V-

C

3V

0V

V

R

OUT

OFF

G

LOGIC

INPUT

COM

INH

ON

NO or NC

ADDX

0Ω

SWITCH

OUTPUT

V

GND

G

ΔV

OUT

C

L

1nF

V

OUT

LOGIC

INPUT

Q = ΔV

x C

L

OUT

Repeat test for other switches.

FIGURE 2B. Q TEST CIRCUIT

FIGURE 2A. Q MEASUREMENT POINTS

FIGURE 2. CHARGE INJECTION

V+

V-

C

V

OUT

NO0-NO7

ADDA-C

COM

V+

C

L

R

L

300Ω

35pF

ISL84051

LOGIC

INPUT

INH

GND

t < 20ns

r

V+

C

V-

t < 20ns

f

3V

0V

C

LOGIC

INPUT

V

OUT

NO0-NO3

ADDA-B

COM

V+

C

L

R

L

300Ω

80%

35pF

SWITCH

OUTPUT

V

ISL84052

OUT

LOGIC

INPUT

0V

t

BBM

INH

GND

V+

C

V-

C

V

OUT

NO

X

V+

COM

X

C

L

35pF

R

L

300Ω

NC

X

ISL84053

ADD

X

INH

GND

LOGIC

INPUT

Repeat test for other switches. C includes fixture and stray

L

capacitance.

FIGURE 3B. t

TEST CIRCUIT

BBM

FIGURE 3A. t

BBM

MEASUREMENT POINTS

FIGURE 3. BREAK-BEFORE-MAKE TIME

FN6047.7

March 15, 2007

10

ISL84051, ISL84052, ISL84053

Test Circuits and Waveforms (Continued)

V+

V-

V+

V-

C

r

= V /1mA

1

ON

SIGNAL

GENERATOR

NO or NC

V

NX

0V or V+

1mA

0V or V+

V

1

ADDX

INH

COM

ANALYZER

COM

INH

GND

R

L

FIGURE 5. r

TEST CIRCUIT

FIGURE 4. OFF ISOLATION TEST CIRCUIT

ON

V+

V-

V+

C

V-

C

SIGNAL

GENERATOR

50Ω

NO or NC

COM

A

ISL84052

AND

ISL84053

0V or V+

ADDX

IMPEDANCE

ANALYZER

0V or V+

NO or NC

NC

COM

B

GND

INH

ANALYZER

COM

B

INH

GND

R

L

FIGURE 7. CAPACITANCE TEST CIRCUIT

FIGURE 6. CROSSTALK TEST CIRCUIT

FN6047.7

March 15, 2007

11

ISL84051, ISL84052, ISL84053

Power-Supply Considerations

Detailed Description

The ISL8405X construction is typical of most CMOS analog

switches, in that they have three supply pins: V+, V-, and

GND. V+ and V- drive the internal CMOS switches and set

their analog voltage limits, so there are no connections

between the analog signal path and GND. Unlike switches

with a 13V maximum supply voltage, the ISL8405X 15V

maximum supply voltage provides plenty of room for the

10% tolerance of 12V supplies (±6V or 12V single supply),

as well as room for overshoot and noise spikes.

The ISL84051, ISL84052, ISL84053 analog switches offer

precise switching capability from a bipolar ±2V to ±6V or a

single 2V to 12V supply with low on-resistance (60Ω) and

high speed operation (t

= 50ns, t = 40ns). The devices

ON

OFF

are especially well suited to portable battery powered

equipment thanks to the low operating supply voltage (2V),

low power consumption (3μW), low leakage currents (5nA

max). High frequency applications also benefit from the wide

bandwidth, and the very high off isolation and crosstalk

rejection.

This family of switches performs equally well when operated

with bipolar or single voltage supplies. The minimum

recommended supply voltage is 2V or ±2V. It is important to

note that the input signal range, switching times, and on-

resistance degrade at lower supply voltages. Refer to the

Electrical Specification tables and “Typical Performance

Curves TA = +25°C, Unless Otherwise Specified” on

page 13 for details.

Supply Sequencing And Overvoltage Protection

With any CMOS device, proper power supply sequencing is

required to protect the device from excessive input currents

which might permanently damage the IC. All I/O pins contain

ESD protection diodes from the pin to V+ and to V- (see

Figure 8). To prevent forward biasing these diodes, V+ and

V- must be applied before any input signals, and input signal

voltages must remain between V+ and V-. If these conditions

cannot be guaranteed, then one of the following two

protection methods should be employed.

V+ and GND power the internal logic (thus setting the digital

switching point) and level shifters. The level shifters convert

the logic levels to switched V+ and V- signals to drive the

analog switch gate terminals.

Logic inputs can easily be protected by adding a 1kΩ

resistor in series with the input (see Figure 8). The resistor

limits the input current below the threshold that produces

permanent damage, and the sub-microamp input current

produces an insignificant voltage drop during normal

operation.

Logic-Level Thresholds

V+ and GND power the internal logic stages, so V- has no

affect on logic thresholds. This switch family is TTL

compatible (0.8V and 2.4V) over a V+ supply range of 2.7V

to 10V. At 12V the V level is about 3.5V. This is still below

IH

the CMOS guaranteed high output minimum level of 4V, but

noise margin is reduced. For best results with a 12V supply,

This method is not applicable for the signal path inputs.

Adding a series resistor to the switch input defeats the

use a logic family that provides a V

greater than 4V.

purpose of using a low r

switch, so two small signal

OH

ON

diodes can be added in series with the supply pins to provide

overvoltage protection for all pins (see Figure 8). These

additional diodes limit the analog signal from 1V below V+ to

1V above V-. The low leakage current performance is

unaffected by this approach, but the switch resistance may

increase, especially at low supply voltages.

The digital input stages draw supply current whenever the

digital input voltage is not at one of the supply rails. Driving

the digital input signals from GND to V+ with a fast transition

time minimizes power dissipation.

High-Frequency Performance

In 50Ω systems, signal response is reasonably flat even past

100MHz (see Figure 17). Figure 17 also illustrates that the

frequency response is very consistent over varying analog

signal levels.

OPTIONAL

PROTECTION

OPTIONAL PROTECTION

DIODE

RESISTOR

FOR LOGIC

INPUTS

V+

An OFF switch acts like a capacitor and passes higher

frequencies with less attenuation, resulting in signal feed

through from a switch’s input to its output. Off Isolation is the

resistance to this feed through, while Crosstalk indicates the

amount of feed through from one switch to another.

Figure 18 details the high off isolation and crosstalk rejection

provided by this family. At 10MHz, off isolation is about 55dB

in 50Ω systems, decreasing approximately 20dB per decade

as frequency increases. Higher load impedances decrease

off isolation and crosstalk rejection due to the voltage divider

action of the switch OFF impedance and the load

impedance.

1kΩ

LOGIC

V

NO OR NC

COM

V-

OPTIONAL PROTECTION

DIODE

FIGURE 8. INPUT OVERVOLTAGE PROTECTION

FN6047.7

March 15, 2007

12

ISL84051, ISL84052, ISL84053

V+ or V- and the analog signal. This means their leakages

Leakage Considerations

will vary as the signal varies. The difference in the two diode

leakages to the V+ and V- pins constitutes the analog-signal-

path leakage current. All analog leakage current flows

between each pin and one of the supply terminals, not to the

other switch terminal. This is why both sides of a given

switch can show leakage currents of the same or opposite

polarity. There is no connection between the analog signal

paths and GND.

Reverse ESD protection diodes are internally connected

between each analog-signal pin and both V+ and V-. One

of these diodes conducts if any analog signal exceeds V+

or V-.

Virtually all the analog leakage current comes from the ESD

diodes to V+ or V-. Although the ESD diodes on a given

signal pin are identical and therefore fairly well balanced,

they are reverse biased differently. Each is biased by either

Typical Performance Curves T = +25°C, Unless Otherwise Specified

A

225

200

70

60

50

40

30

V

= (V+) - 1V

I

= 1mA

V- = -5V

COM

= 1mA

COM

I

COM

175

150

+85°C

+25°C

-40°C

125

100

+25°C

-40°C

V+ = 2.7V

V- = 0V

75

160

140

120

100

80

20

400

V- = 0V

+85°C

+25°C

-40°C

300

200

100

0

V+ = 3.3V

V- = 0V

60

100

90

80

70

60

50

40

+85°C

V+ = 5V

V- = 0V

+25°C

+85°C

1

+25°C

-40°C

0

2

3

4

5

3

4

5

6

7

8

9

10

11

12

2

V

(V)

COM

V+ (V)

FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE

FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE

2

1

120

110

100

90

80

70

V

= ±2V

S

I

= 1mA

COM

+85°C

+25°C

-40°C

60

50

90

80

70

60

50

40

30

0

V

= ±3V

S

+85°C

V+ = 5V

V- = 0V

+25°C

-40°C

-1

V

= ±5V

S

60

50

40

30

20

-2

-3

V

= ±5V

S

+85°C

+25°C

-40°C

-4

-5

-2.5

0

2.5

5

-5

-3

-2

-1

0

1

2

3

4

5

V

(V)

COM

V

(V)

COM

FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE

FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE

FN6047.7

March 15, 2007

13

ISL84051, ISL84052, ISL84053

Typical Performance Curves T = +25°C, Unless Otherwise Specified (Continued)

A

200

150

100

50

500

400

300

200

100

V = (V+) - 1V

COM

V- = -5V

V

= (V+) - 1V

V- = -5V

-40°C

+25°C

COM

-40°C

+25°C

+85°C

+25°C

+85°C

-40°C

0

-40°C

0

100

250

V- = 0V

80

60

40

20

0

200

150

100

50

+85°C

+25°C

-40°C

3

-40°C

3

0

2

4

5

6

7

8

9

10

11

12

2

4

5

6

7

8

9

10

11

12

V+ (V)

FIGURE 13. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE

FIGURE 14. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE

250

300

V

= (V+) - 1V

V

= (V+) - 1V

COM

V- = 0V

250

200

150

100

50

200

150

100

50

+25°C

+85°C

7

-40°C

0

2

3

4

5

6

2

3

4

5

6

8

9

10

11

12

13

V± (V)

V+ (V)

FIGURE 15. ADDRESS TRANS TIME vs SINGLE SUPPLY

VOLTAGE

FIGURE 16. ADDRESS TRANS TIME vs DUAL SUPPLY

VOLTAGE

-10

10

20

30

40

50

60

70

80

90

V

= ±5V

V+ = 3V to 12V or

S

V

= 0.2V

to 5V

P-P P-P

IN

-20

-30

-40

-50

-60

-70

-80

-90

V

R

= ±2V to ±5V

= 50Ω

S

L

3

0

ISL84053

GAIN

ISL84051

ISL84052

-3

ISL84053

0

ISOLATION

PHASE

45

90

ISL84051

ISL84052

CROSSTALK

135

180

-100

-110

100

110

R

= 50Ω

L

1M

10M

100M

600M

1k

10k

100k

1M

10M

100M 500M

FREQUENCY (Hz)

FIGURE 18. CROSSTALK AND OFF ISOLATION

FIGURE 17. FREQUENCY RESPONSE

FN6047.7

March 15, 2007

14

ISL84051, ISL84052, ISL84053

Die Characteristics

SUBSTRATE POTENTIAL (POWERED UP):

V-

TRANSISTOR COUNT:

ISL84051: 193

ISL84052: 193

ISL84053: 193

PROCESS:

Si Gate CMOS

FN6047.7

March 15, 2007

15

ISL84051, ISL84052, ISL84053

Small Outline Plastic Packages (SOIC)

M16.15 (JEDEC MS-012-AC ISSUE C)

N

16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

0.0688

0.0098

0.020

MIN

1.35

0.10

0.33

0.19

9.80

3.80

MAX

1.75

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

-

1

2

3

0.25

-

L

0.51

9

SEATING PLANE

A

0.0075

0.3859

0.1497

0.0098

0.3937

0.1574

0.25

-

-A-

10.00

4.00

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

16

7

0°

8°

0°

8°

-

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above

the seating plane, shall not exceed a maximum value of 0.61mm

(0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions are

not necessarily exact.

FN6047.7

March 15, 2007

16

ISL84051, ISL84052, ISL84053

Thin Shrink Small Outline Plastic Packages (TSSOP)

M16.173

N

16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

E

INCHES

MIN

MILLIMETERS

E1

-B-

GAUGE

PLANE

SYMBOL

MAX

0.043

0.006

0.037

0.012

0.008

0.201

0.177

MIN

-

MAX

1.10

0.15

0.95

0.30

0.20

5.10

4.50

NOTES

A

A1

A2

b

-

0.002

0.033

0.0075

0.0035

0.193

0.169

0.05

0.85

0.19

0.09

4.90

4.30

-

1

2

3

-

L

0.25

0.010

0.05(0.002)

SEATING PLANE

A

9

-A-

c

-

D

3

-C-

E1

e

4

α

0.026 BSC

0.65 BSC

-

A2

e

A1

c

E

0.246

0.020

0.256

0.028

6.25

0.50

6.50

0.70

-

b

0.10(0.004)

L

6

0.10(0.004) M

C

A M B S

N

16

7

o

0

8

0

8

-

α

NOTES:

Rev. 1 2/02

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AB, Issue E.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.15mm (0.006

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are not necessarily exact. (Angles in degrees)

FN6047.7

March 15, 2007

17

ISL84051, ISL84052, ISL84053

Shrink Small Outline Plastic Packages (SSOP)

Quarter Size Outline Plastic Packages (QSOP)

M16.15A

N

16 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE

(0.150” WIDE BODY)

INDEX

M

B

0.25(0.010)

H

AREA

E

INCHES

MILLIMETERS

GAUGE

PLANE

-B-

SYMBOL

MIN

MAX

MIN

1.55

0.102

1.40

0.20

0.191

4.80

3.81

MAX

1.73

0.249

1.55

0.31

0.249

4.98

3.99

NOTES

A

A1

A2

B

0.061

0.004

0.055

0.008

0.0075

0.189

0.150

0.068

0.0098

0.061

0.012

0.0098

0.196

0.157

-

1

2

3

-

L

-

0.25

0.010

SEATING PLANE

A

9

-A-

D

h x 45°

C

D

E

-

3

-C-

4

α

A2

e

A1

e

0.025 BSC

0.635 BSC

-

C

B

H

h

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

-

0.10(0.004)

M

S

B

0.17(0.007)

C

A

5

L

6

NOTES:

N

α

16

7

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

0°

8°

0°

8°

-

Rev. 2 6/04

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “B” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.10mm (0.004 inch) total in excess

of “B” dimension at maximum material condition.

10. Controlling dimension: INCHES. Converted millimeter dimen-

sions are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6047.7

March 15, 2007

18


型号：	ISL84051IBZ
厂家：	Intersil
描述：	Low Voltage, Single and Dual Supply, 8 to 1 Multiplexer, Dual 4 to 1 Multiplexer and a Triple SPDT Analog Switch 低电压，单电源和双电源， 8到1多路复用器，双4：1多路复用器和一个三SPDT模拟开关复用器开关光电二极管
文件：	总18页 (文件大小：442K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL84051IBZ [INTERSIL]

相关型号：

ISL84051IVZ

ISL84051IVZ

ISL84051IVZ-T

ISL84051IVZ-T

ISL84051_07

ISL84051_0710

ISL84052

ISL84052IA

ISL84052IA-T

ISL84052IAZ

ISL84052IAZ

ISL84052IAZ-T