ISL870XEVAL1 [INTERSIL]
Adjustable Quad Sequencer; 可调式四序
| 型号： | ISL870XEVAL1 |
| 厂家： | 
Intersil |
| 描述： | Adjustable Quad Sequencer |
| 文件： | 总13页 (文件大小：290K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL8700, ISL8701, ISL8702
®
Data Sheet
March 21, 2008
FN9250.2
Adjustable Quad Sequencer
Features
The ISL8700, ISL8701, ISL8702 family of ICs provide four
delay adjustable sequenced outputs while monitoring an
input voltage all with a minimum of external components.
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
High performance DSP, FPGA, µP and various subsystems
require input power sequencing for proper functionality at
initial power-up and the ISL870x provides this function while
monitoring the distributed voltage for over and undervoltage
compliance.
• Undervoltage and Overvoltage Adjustable Delay to Auto
Start Sequence
• I/O Options
ENABLE (ISL8700, ISL8702) and ENABLE# (ISL8701)
SEQ_EN (ISL8702)
The ISL8700 and ISL8701 operate over the +2.5V to +24V
nominal voltage range, whereas the ISL8702 operates over
the +2.5V to +12V nominal voltage range. All three have a
user adjustable time from UV and OV voltage compliance to
sequencing start via an external capacitor when in auto start
mode and adjustable time delay to subsequent ENABLE
output signal via external resistors.
• Voltage Compliance Fault Output
• Pb-Free (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
Additionally, the ISL8702 provides an input for sequencing
on and off operation (SEQ_EN) and for voltage window
compliance reporting (FAULT) over the +2.5V to +12V
voltage range.
2.5V TO 24V (2.5V TO 12V FOR ISL8702)
EN
Easily daisy chained for more than 4 sequenced signals.
DC/DC
DC/DC
DC/DC
DC/DC
Vo1
VIN
Ru
Altogether, the ISL870x provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
SEQ_EN*
EN
EN
EN
UV
Vo2
Vo3
Vo4
Rm
Rl
Ordering Information
FAULT*
OV
PARTNUMBER
(Note)
PART
TEMP.
PACKAGE PKG.
GND TB TC TD TIME
MARKING RANGE (°C) (Pb-free) DWG. #
ISL 8700IBZ -40 to +85 14 Ld SOIC M14.15
ISL 8701IBZ -40 to +85 14 Ld SOIC M14.15
ISL 8702IBZ -40 to +85 14 Ld SOIC M14.15
ISL8700IBZ*
ISL8701IBZ*
ISL8702IBZ*
* SEQ_EN and FAULT are not available on ISL8700 and ISL8701
FIGURE 1. ISL870x IMPLEMENTATION
ISL870xEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8700, ISL8701, ISL8702
Pinouts
ISL8700
(14 LD SOIC)
TOP VIEW
ISL8701
(14 LD SOIC)
TOP VIEW
ISL8702
(14 LD SOIC)
TOP VIEW
ENABLE_D
VIN
TD
ENABLE#_D
ENABLE#_C
ENABLE#_B
ENABLE#_A
OV
VIN
TD
ENABLE_D
ENABLE_C
ENABLE_B
ENABLE_A
OV
VIN
1
2
3
4
5
6
14
13
12
11
10
9
1
2
3
4
5
6
14
13
12
11
10
9
1
2
3
4
5
6
14
13
12
11
10
9
ENABLE_C
ENABLE_B
ENABLE_A
OV
TD
TC
TC
TC
TB
TB
TB
TIME
NC
NC
TIME
NC
NC
TIME
SEQ_EN
FAULT
UV
UV
UV
GND
GND
GND
7
8
7
8
7
8
FN9250.2
March 21, 2008
2
ISL8700, ISL8701, ISL8702
Absolute Maximum Ratings
Thermal Information
ISL8700, ISL8701 V , ENABLE(#), FAULT . . . . . . . . 27V, to -0.3V
IN
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
JA
110
ISL8702 V , ENABLE(#), FAULT . . . . . . . . . . . . . . . . 14V, to -0.3V
IN
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V +0.3V, to -0.3V
IN
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 2.5V to 24V
ISL8702 Supply Voltage Range (Nominal) . . . . . . . . . . 2.5V to 12V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Nominal V = 2.5V to +24V, T = T = -40°C to +85°C, Unless Otherwise Specified.
IN
A
J
ISL8702 V = 2.5V to +12V
IN
PARAMETER
UV AND OV INPUTS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
V
1.16
1.21
1.10
104
10
1.28
V
V
UVRvth
V
1.06
1.18
UVFvth
V
V
- V
UVFvth
-
-
-
-
mV
nA
UVhys
UVRvth
UV/OV Input Current
I
UV
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current
TIME Pin Threshold
I
-
2.6
2.0
30
-
µA
V
TIME
V
1.9
2.25
TIME_VTH
VINSEQpd
Time from V Valid to ENABLE_A
IN
t
SEQ_EN = high, C
SEQ_EN = high, C
SEQ_EN = high, C
= open
= 10nF
= 500nF
-
-
µs
ms
ms
µs
Ω
TIME
TIME
TIME
t
t
-
7.7
435
-
-
VINSEQpd_10
VINSEQpd500
-
-
-
Time from V Invalid to Shutdown
IN
t
UV or OV to simultaneous shutdown
1
shutdown
ENABLE Output Resistance
ENABLE Output Low
R
I
I
= 1mA
= 1mA
-
100
0.1
15
-
EN
ENABLE
ENABLE
Vol
-
-
V
ENABLE Pull-Down Current
Delay to Subsequent ENABLE Turn-On/Off
I
ENABLE = 1V
10
155
3.5
-
-
240
6
mA
ms
ms
ms
pulld
t
R
R
R
= 120kΩ
= 3kΩ
= 0Ω
195
4.7
0.5
del_120
TX
TX
TX
t
del_3
del_0
t
-
SEQUENCE ENABLE AND FAULT I/O
V
V
Valid to FAULT Low
t
15
-
30
0.5
15
50
µs
µs
mA
V
IN
IN
FLTL
Invalid to FAULT High
t
-
-
FLTH
FAULT Pull-down Current
FAULT = 1V
10
-
SEQ_EN Pull-up Voltage
V
SEQ_EN open
V
-
SEQ
IN
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
Vil
SEQ_EN
-
-
-
0.3
-
V
Vih
1.2
-
V
SEQ_EN
SEQ_EN_ENA
t
SEQ_EN low to ENABLE_A low
0.2
1
µs
FN9250.2
March 21, 2008
3
ISL8700, ISL8701, ISL8702
Electrical Specifications Nominal V = 2.5V to +24V, T = T = -40°C to +85°C, Unless Otherwise Specified.
IN
A
J
ISL8702 V = 2.5V to +12V (Continued)
IN
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS
IC Supply Current
I
V
V
V
V
= 2.2V
-
-
-
-
191
246
286
2.08
-
400
-
µA
µA
µA
V
VIN_2.2V
IN
IN
IN
IN
I
= 12V
VIN_12V
VIN_24V
I
= 24V
V
Power On Reset
V
low to high
2.5
IN
IN_POR
Pin Descriptions
PIN NUMBER
ISL8700 ISL8701 ISL8702
PIN NAME
FUNCTION DESCRIPTION
NA
1
NA
2
NA
ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output to
sequence off for the ISL8701. Tracks V upon bias.
IN
1
1
ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to
sequence off for the ISL8700, ISL8702. Pulls low with V < 1V.
IN
NA
2
NA
2
ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced off after
ENABLE#_D for the ISL8701. Tracks V upon bias.
IN
NA
3
ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced off after
ENABLE_D for the ISL8700, ISL8702. Pulls low with V < 1V.
IN
NA
3
NA
3
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced off after
ENABLE#_C for the ISL8701. Tracks V upon bias.
IN
NA
4
ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced off after
ENABLE_C for the ISL8700, ISL8702. Pulls low with V < 1V.
IN
NA
4
NA
4
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced off after
ENABLE#_B for the ISL8701. Tracks V upon bias.
IN
NA
5
ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and sequenced off after
ENABLE_B for the ISL8700, ISL8702. Pulls low with V < 1V.
IN
5
5
OV
UV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be immediately
pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull
ups.
6
6
6
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be immediately
pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled high via external pull
ups.
7
7
7
8
GND
IC ground.
NA
NA
FAULT
The V voltage when not within the desired UV to OV window will cause FAULT to be released to be
IN
pulled high to a voltage equal to or less than V via an external resistor.
IN
NA
NA
10
NA
NA
10
9
SEQ_EN
SEQ_EN#
TIME
This pin provides a sequence on signal input with a high input. Internally pulled high to V .
IN
NA
10
This pin provides a sequence on signal input with a low input. Internally pulled high to V .
IN
This pin provides a 2.6µA current output so that an adjustable V valid to sequencing on and off start
IN
delay period is created with a capacitor to ground.
11
12
13
14
11
12
13
14
11
12
13
14
TB
TC
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_A being active
to ENABLE _B being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_B being active
to ENABLE _C being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_C being active
to ENABLE _D being active on turn-on and also going inactive on turn-off via the SEQ_IN input.
V
IC Bias Pin Nominally 2.5V to 24V (2.5V to 12V for ISL8702). This pin requires a 1µF decoupling
IN
capacitor close to IC pin.
FN9250.2
March 21, 2008
4
ISL8700, ISL8701, ISL8702
Functional Block Diagram
VIN (2.2V MIN TO 27V MAX, 2.5V TO 12V FOR ISL8702)
VIN
VREF
1.17V
VOLTAGE
REFERENCE
VREG
3.5V
SEQ_EN
INTERNAL VOLTAGE
REGULATOR
+
UV
eo
-
ENABLE_A
ENABLE_B
ENABLE_C
2.0V VIN POR
+
LOGIC
OV
-
FAULT
30µs
GND
TIME
V
TIME_VTH
ENABLE_D
PROGRAMMABLE
DELAY TIMER
VIN
2.6µA
TB
TC
TD
resistor or a pull-up in a DC/DC convertor enable input, for
example. Conversely, ENABLE#_A output will be pulled low at
this time on an ISL8701. The time delay generated by the
external capacitor is to assure continued voltage compliance
within the programmed limits, as during this time any OV or UV
condition will halt the start-up process. TIME capacitor is
Functional Description
The ISL870x family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 2.5V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870x initiate the pre-programmed A-B-C-D sequence of the
ENABLE (ISL8700, ISL8702) or ENABLE# (ISL8701) outputs.
Although this IC has a bias range of 2.5V to 24V (12V for
ISL8702) it can monitor any voltage >1.22V via the external
divider if a suitable bias voltage is otherwise provided.
discharged once V
TIME_VTH
is met.
Once ENABLE_A is active (either released high on the
ISL8700, ISL8702 or pulled low on the ISL8701), a counter is
started and using the resistor on TB as a timing component, a
delay is generated before ENABLE_B is activated. At this time,
the counter is restarted using the resistor on TC as its timing
component for a separate timed delay until ENABLE_C is
activated. This process is repeated for the resistor on TD to
complete the A-B-C-D sequencing order of the ENABLE or
ENABLE# outputs. At any time during sequencing if an OV or
UV event is registered, all four ENABLE outputs will
During initial bias voltage (V ) application, the ISL8700,
IN
ISL8702 ENABLE outputs are held low once V = 1V whereas
the ISL8701 ENABLE# outputs follow the rising V . Once
IN
IN
V
> the V
power-on reset threshold (POR) of 2.0V, V
IN
is constantly monitored for compliance via the input voltage
BIAS
IN
resistor divider and the voltages on the UV and OV pins and
reported by the FAULT output. Internally, voltage regulators
generate 3.5V and 1.17V ±5% voltage rails for internal usage
immediately return to their reset state; low for ISL8700,
ISL8702 and high for ISL8701. C
is immediately
TIME
once V > POR. Once UV > 1.22V and with the SEQ_EN pin
IN
discharged after initial ramp-up thus waiting for subsequent
voltage compliance to restart. Once sequencing is complete,
any subsequently registered UV or OV event will trigger an
immediate and simultaneous reset of all ENABLE or ENABLE#
outputs.
high or open, the auto sequence of the four ENABLE
(ENABLE#) outputs begins as the TIME pin charges its external
capacitor with a 2.6µA current source. The voltage on TIME is
compared to the internal reference (V
input and when greater than V
TIME_VTH
) comparator
the ISL8700, ISL8702
TIME_VTH
ENABLE_A is released to go high via an external pull-up
FN9250.2
March 21, 2008
5
ISL8700, ISL8701, ISL8702
On the ISL8702, enabling of on or off sequencing can also be
The following is a practical example worked out. For detailed
equations on how to perform this operation for a given supply
requirement, please refer to the next section.
signaled via the SEQ_EN input pin once voltage compliance is
met. Initially the SEQ_EN pin should be held low and released
when sequence start is desired. The on sequence of the
ENABLE outputs is as previously described. The off sequence
feature is only available on the variants having the SEQ_EN or
the SEQ_EN# inputs, this being the ISL8702. The sequence is
D off, then C off, then B off and finally A off. Once SEQ_EN
(SEQ_EN#) is signaled low (high) the TIME cap is charged to
2V once again. Once this Vth is reached ENABLE_D
transitions to its reset state and CTIM is discharged. A delay
and subsequent sequence off is then determined by TD resistor
to ENABLE_C. Likewise, a delay to ENABLE_B and then
ENABLE_A turn-off is determined by TC and TB resistor values
respectively.
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, I = divider
r
current
4. (R + R ) x I = 1.1V @ UV and R x I = 1.2V @ OV
m
l
r
l
r
5. R + R = 1.1V/Ir @ UV = R + R = 1.1V/(10.8V/100kΩ)
m
l
m
l
= 10.370kΩ
6. R = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
l
7. R = 10.370kΩ - 9.242kΩ = 1.128kΩ
m
With the ISL8700, ISL8701, a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
8. R = 100kΩ - 10.370kΩ = 89.630kΩ
u
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors values.
In our example with the closest standard values of
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
R = 90.9kΩ, R = 1.13kΩ and R = 9.31kΩ, the nominal UV
u
m
l
falling and OV rising will be at 10.9V and 13.3V respectively.
An Advanced Tutorial on Setting UV and OV
Levels
Programming the Undervoltage and Overvoltage
Limits
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870x than the earlier text.
When choosing resistors for the divider, remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ to 1000kΩ range is
advisable with high precision resistors being used to reduce
monitoring error. Although for the ISL870x two dividers of two
resistors each can be employed to separately monitor the OV
The following equation set can alternatively be used to work
out ideal values for a 3 resistor divider string of R , R and
u
m
R . These equations assume that V
is the center point
l
REF
between V
and V
UVFvth
(i.e. (V
UVRvth
+ V )/2
UVRvth
UVFvth
is the load current in the resistor string
= 1.17V), I
load
and UV levels for the V voltage which will be discussed here
IN
(i.e. V /(R + R + R )), V is the nominal input voltage
IN IN
u
m
l
using a single three resistor string for monitoring the V
IN
voltage, referencing Figure 1. In the three resistor divider string
with R (upper), R (middle) and R (lower), the ratios of each
and V is the acceptable voltage tolerance, such that the
tol
UV and OV thresholds are centered at V ± V . The actual
IN tol
u
m
l
acceptable voltage window will also be affected by the
hysteresis at the UV and OV pins. This hysteresis is
amplified by the resistor string such that the hysteresis at the
top of the string is calculated in Equation 1:
in combination to the other two is balanced to achieve the
desired UV and OV trip levels. Although this IC has a bias
range of 2.5V to 24V (12V for ISL8702), it can monitor any
voltage >1.22V.
(EQ. 1)
Vhys = V
× V
⁄ V
OUT REF
UVhys
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (ground connected) resistor.
This means that the V ± V thresholds will exhibit
IN tol
hysteresis resulting in thresholds of V + V ± V /2 and
IN tol hys
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
V
- V ± V /2.
tol hys
IN
There is a window between the V rising UV threshold and
IN
the V falling OV threshold where the input level is
guaranteed not to be detected as a fault. This window exists
IN
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
between the limits V ± (V - V /2). There is an
IN tol hys
extension of this window in each direction up to
V
± (V + V /2), where the voltage may or may not be
tol hys
IN
FN9250.2
March 21, 2008
6
ISL8700, ISL8701, ISL8702
detected as a fault, depending on the direction from which it
Programming the ENABLE Output Delays
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For
The delay timing between the four sequenced ENABLE outputs
are programmed with four external passive components. The
example, if V is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If V
IN IN
delay from a valid V (ISL8700 and ISL8701) to ENABLE_A
IN
must remain within 12V ± 1.5V, V = 1.5 - 1.03/2 = 0.99V.
tol
and SEQ_EN being valid (ISL8702) to ENABLE_A is
This will give a window of 12 ±0.48V where the system is
guaranteed not to be in fault and a limit of 12 ±1.5V beyond
which the system is guaranteed to be in fault.
determined by the value of the capacitor on the TIME pin to
GND. The external TIME pin capacitor is charged with a 2.6µA
current source. Once the voltage on TIME is charged up to the
internal reference voltage, (VTIME_VTH) the ENABLE_A output
is released out of its reset state. The capacitor value for a
It is wise to check both these voltages for if the latter is made
too tight, the former will cease to exist. This point comes
desired delay (±10%) to ENABLE_A once V and SEQ_EN
IN
when V < V /2 and results from the fact that the
tol hys
where applicable has been satisfied is determined by using
Equation 5:
acceptable window for the OV pin no longer aligns with the
acceptable window for the UV pin. In this case, the
application will have to be changed such that UV and OV are
provided separate resistor strings. In this case the UV and
OV thresholds can be individually controlled by adjusting the
relevant divider.
(EQ. 5)
C
= t
⁄ 770kΩ
VINSEQpd
TIME
Once ENABLE_A reaches V , the TIME pin is pulled
TIME_VTH
low in preparation for a sequenced off signal via SEQ_EN. At
this time, the sequencing of the subsequent outputs is started.
ENABLE_B is released out of reset after a programmable time,
then ENABLE_C, then ENABLE _D, all with their own
programmed delay times.
The previous example will give voltage thresholds:
with V rising
IN
UVr = V – V + V
hys
⁄ 2 = 11.5Vand
⁄ 2 = 13.5V
IN
tol
(EQ. 2)
OVr = V + V + V
IN
tol
hys
The subsequent delay times are programmed with a single
external resistor for each ENABLE output providing maximum
flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
values determine the charge and discharge rate of an internal
capacitor comprising an RC time constant for an oscillator
whose output is fed into a counter generating the timing delay
to ENABLE output sequencing.
with V falling
IN
OVf = V + V – V
⁄ 2 = 12.5Vand
⁄ 2 = 10.5V
IN
tol
hys
(EQ. 3)
UVf = V – V – V
IN
tol
hys
So with a single three resistor string, the resistor values can
be calculated using Equation 4:
R
R
R
= (V
⁄ I
)(1 – V ⁄ V
)
IN
I
REF load
tol
(EQ. 4)
The R value for a given delay time is defined as Equation 6:
TX
= 2(V
= (1 ⁄ I
× V ) ⁄ (V × I
)
load
m
u
REF
load
tol
IN
t
) × (V – V
)(1 + V ⁄ V )
IN
del
(EQ. 6)
IN
REF
tol
--------------------
R
=
TX
1667nF
For the above example with Vtol = 0.99V, assuming a 100µA
Iload at V = 12V:
IN
R = 10.7kΩ
l
R
= 1.9kΩ
m
R = 107.3kΩ
u
FN9250.2
March 21, 2008
7
ISL8700, ISL8701, ISL8702
FAULT
SEQ_EN
TIME
A
B
C
D
D
C
B
A
ENABLE OUTPUTS
FIGURE 2. ISL8702 OPERATIONAL DIAGRAM
OVERVOLTAGE
LIMIT
t
FLTH
t
<t
FLTH
FLTL
UNDERVOLTAGE
LIMIT
t
FLTL
t
MONITORED VOLTAGE
FLTH
RAMPING UP AND DOWN
FAULT OUTPUT
FIGURE 3. ISL8702 FAULT OPERATIONAL DIAGRAM
Typical Performance Curves
1.208
1.207
1.206
1.205
310
290
270
250
V
= 24V
IN
V
= 2.5V
1.204
1.203
1.202
1.201
1.200
1.199
1.198
IN
V
= 12V
IN
V
= 12V
230
210
190
170
150
IN
V
= 2.5V
25
IN
V
= 24V
IN
-40
-10
0
60
85
100
-40
-10
0
25
60
85
100
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 4. UV/OV RISING THRESHOLD
FIGURE 5. V CURRENT
IN
FN9250.2
March 21, 2008
8
ISL8700, ISL8701, ISL8702
bound conditions by being released to pull high to the VHI
voltage as shown in Figures 6 and 7.
Applications Usage
Using the ISL870xEVAL1 Platform
Once the voltage monitoring FAULT is resolved and where
applicable, the SEQ_EN(#) is satisfied, sequencing of the
ENABLE_X(#) outputs begins. When sequence enabled the
ENABLE_A, ENABLE_B, ENABLE_C and lastly
ENABLE_D are asserted in that order and when SEQ_EN is
disabled, the order is reversed. See Figures 8 and 9
demonstrating the sequenced enabling and disabling of the
ENABLE outputs. The timing between ENABLE outputs is
set by the resistor values on the TB, TC, TD pins as shown.
Figure 10 illustrates the timing from either SEQ_EN and/or
VMONITOR being valid to ENABLE_A being asserted with a
10nF TIME capacitor. Figure 11 shows that ENABLE_X
The ISL870xEVAL1 platform is the primary evaluation board
for this family of sequencers. See Figure 15 for a photograph
and schematic.The evaluation board is shipped with an
ISL8702 mounted in the left position and with the other
device variants loosely packed. In the following discussion,
test points names are bold on initial occurrence for
identification.
The V test point is the chip bias and can be biased from
IN
2.5V to 24V. The VHI test point is for the ENABLE and
FAULT pull-up voltage which are limited to a maximum of
24V independent of V . The UV/OV resistor divider is set so
IN
that a nominal 12V on the VMONITOR test point is compliant
outputs are pulled low even before V = 1V. This is critical
IN
and with a rising OV set at 13.2V and a falling UV set at
to ensure that a false enable is not signaled. Figure 12
shows the time from SEQ_EN transition with the voltage
ramping across the TIME capacitor to TIME Vth being met.
This results in the immediate pull down of the TIME pin and
simultaneous ENABLE_A enabling. Figure 13 illustrates the
immunity of the UV and OV inputs to transients.
10.7V. These three test points (V ,VHI and VMONITOR)
IN
are brought out separately for maximum flexibility in
evaluation.
VMONITOR ramping up and down through the UV and OV
levels will result in the FAULT output signaling the out of
VMON FALLING
VMON RISING
VMON > OV
LEVEL
VMON > OV
LEVEL
VMON > UV
LEVEL
VMON > UV
LEVEL
FAULT OUTPUT
FAULT OUTPUT
FIGURE 6. VMONITOR RISING TO FAULT
FIGURE 7. VMONITOR FALLING TO FAULT
FN9250.2
March 21, 2008
9
ISL8700, ISL8701, ISL8702
R
= 3k
TB
DELAY = 5ms
R
= 3k
TB
DELAY = 5ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
FIGURE 9. ENABLE_X TO ENABLE_X DISABLING
FIGURE 8. ENABLE_X TO ENABLE_X ENABLING
V
RISING
IN
C
= 10nF
TIME
DELAY = 8.5ms
ENABLE OUTPUTS TRACKS V TO < 0.8V
IN
1V/DIV
10ms/DIV
FIGURE 10. V /SEQ_EN VALID TO ENABLE_A
IN
FIGURE 11. ENABLE AS V RISES
IN
VMONITOR OV
VMONITOR UV
SEQ_EN
ENABLE_A
TIME
0.5V/DIV
FAULT = LOW
8µs/DIV
FIGURE 12. SEQ_EN TO ENABLE_A
FIGURE 13. OV AND UV TRANSIENT IMMUNITY
FN9250.2
March 21, 2008
10
ISL8700, ISL8701, ISL8702
Application Concerns and Recommendations
When designing the ISL8700 family of products into
applications with low supply voltages such as 3.3V,
additional filtering to help reduce system noise on the
voltage supply input is necessary to ensure proper voltage
sequencing operation. It is important that the
PIN 4
GND
GND
user-programmed UV threshold is set sufficiently above (i.e.
PIN 5
>200mV) the ISL8700 IC’s internal POR level, V
,
IN_POR
over the entire operating temperature range. Best design
practices include proper decoupling on the supply input (i.e.
at least 1µF) as well as an RC filter that can adequately
suppress noise on the supply in the user’s application,
whereby the resistor should be kept < 13Ω to reduce voltage
loss to the already low biased VIN pin.
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700, ISL8702 parts due to the
ENABLE_A and OV pins being adjacent. This coupling can
be reduced by adding a ground trace between UV and the
ENABLE/FAULT signals, as shown in Figure 14. The PCB
traces on OV and UV should be kept as small as practical
and the ENABLE_X and FAULT traces should ideally not be
routed under/over the OV/UV traces on different PCB layers
unless there is a ground or power plane in between. Other
methods that can be used to eliminate this issue are by
reducing the value of the resistors in the network connected
FIGURE 14. LAYOUT DETAIL OF GND BETWEEN PINS 4 AND 5
to UV and OV (R , R , R in Figure 15) or by adding small
2
3
5
decoupling capacitors to OV and UV (C and C in
2
7
Figure 15). Both these methods act to reduce the AC
impedance at the nodes, although the latter method acts to
filter the signals, which will also cause an increase in the
time that a UV/OV fault takes to be detected.
When the ISL870x is implemented on a hot swappable card
that is plugged into an always powered passive back plane,
an RC filter is required on the V pin to prevent a high dv/dt
IN
transient. With the already existing 1µF decoupling capacitor,
the addition of a small series R (<13Ω) to provide a time
constant >50µs is all that is necessary.
Only the ISL8702 has a V limitation of 14V maximum.
IN
FN9250.2
March 21, 2008
11
ISL8700, ISL8701, ISL8702
.
PULL-UP
RESISTORS
TIMING
COMPONENTS
UV/OV SET
RESISTORS
FIGURE 15. ISL870xEVAL1 PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL
TABLE 1. ISL870xEVAL1 LEFT CHANNEL COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
ISL8702, Quad Under/Overvoltage Sequencer
UV Resistor for Divider String
COMPONENT DESCRIPTION
U1
R3
R2
R5
C1
R1
R9
R7
Intersil, ISL8702, Quad Undervoltage, Overvoltage Sequencer
1.1kΩ 1%, 0603
88.7kΩ 1%, 0603
9.1kΩ 1%, 0603
0.01µF, 0603
VMONITOR Resistor for Divider String
OV Resistor for Divider String
C
R
R
R
Sets Delay from Sequence Start to First ENABLE
TIME
Sets Delay from Third to Fourth ENABLE
Sets Delay from First to Second ENABLE
Sets Delay from Second to Third ENABLE
120kΩ 1%, 0603
3.01kΩ 1%, 0603
51kΩ 1%, 0603
4kΩ 10%, 0402
TD
TB
TC
R4, R6, R8, R10, ENABLE_X(#) and FAULT Pull-up Resistors
R11
C3
Decoupling Capacitor
1µF, 0603
FN9250.2
March 21, 2008
12
ISL8700, ISL8701, ISL8702
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9250.2
March 21, 2008
13
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