ISL8723 [INTERSIL]

Power Sequencing Controllers; 电源排序控制器


型号：	ISL8723
厂家：	Intersil
描述：	Power Sequencing Controllers 电源排序控制器控制器
文件：	总15页 (文件大小：276K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL8723, ISL8724

Data Sheet

December 21, 2006

FN6413.0

Power Sequencing Controllers

Features

The Intersil ISL8723 and ISL8724 are 4 channel sequencers

controlling the on and off sequence of voltages with under

voltage supply fault protection and a “sequence completed”

signal (RESET#). For larger systems, more than 4 voltages

can be sequenced by a simple connection of multiple IC's.

These sequencers use an integrated charge pump to drive 4

external low-cost N-channel MOSFET switch gates above

the IC bias voltage by 5.3V. These IC's can be biased from

and control any supply from 2.5V to 5V and additionally

monitor any voltage above 0.7V. Individual product

descriptions are below.

• Enables arbitrary turn-on and turn-off sequencing of up to

four power supplies (0.7V to 5V)

• Operates from 2.5V to 5V supply voltage

• Supplies V

+5.3V of charge pumped gate drive

• Adjustable voltage slew rate for each rail

• Multiple sequencers can be easily daisy-chained to

sequence an infinite number of independent voltages

• Glitch immunity

• Under voltage lockout for each monitored supply voltage

• 30µA Sleep State (ISL8723)

The four channel ISL8723 (ENABLE input), ISL8724

(ENABLE# input) offer the designer 4 voltage control when it

is required that all four rails are in minimal compliance prior

to turn on and that compliance must be maintained during

operation. The ISL8723 has a low power standby mode

when it is disabled suitable for battery powered applications.

• Active high (ISL8723) or low (ISL8724) ENABLE# input

• Pb-free plus anneal available (RoHS compliant) QFN

Package

Applications

External resistors provide flexible voltage threshold

programming of monitored voltages. Delay and sequencing

timing are programmable by external capacitors for both

ramp up and ramp down.

• Graphics cards

• FPGA/ASIC/microprocessor/PowerPC supply sequencing

• Network Routers

• Telecommunications Systems

Ordering Information

Pinout

TEMP.

RANGE

(°C)

PART

MARKING

PKG.

ISL8723, ISL8724

(24 LD QFN)

TOP VIEW

PART NUMBER

PACKAGE DWG. #

ISL8723IRZ (Note) 8723IRZ

ISL8724IRZ (Note) 8724IRZ

ISL8723IRZ-T (Note) 8723IRZ

ISL8724IRZ-T (Note) 8724IRZ

-40 to +85 24 Ld 4x4 QFN L24.4x4

(Pb-free)

L24.4x4

-40 to +85 24 Ld 4x4 QFN L24.4x4

(Pb-free)

Tape & Reel

L24.4x4

24 23 22 21 20 19

ENABLE/

ISL8723EVAL1

Evaluation Platform

18 DLY_OFF_A

ENABLE#

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100% matte

tin plate termination finish, which are RoHS compliant and compatible with

both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed

the Pb-free requirements of IPC/JEDEC J STD-020.

GATE_A

UVLO_C

DLY_OFF_C

DLY_OFF_D

GATE_B

DLY_ON_C

DLY_ON_D

4mmx4mm

14 UVLO_D

GATE_C

13 DLY_OFF_B

10 11 12

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL8723, ISL8724

AIN

AOUT

BOUT

BIN

CIN

COUT

DOUT

DIN

VDD

ENABLE

UVLO_A

UVLO_B

UVLO_C

UVLO_D

SYSRST#

RESET#

GROUND

FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE

Pin Descriptions

PIN NAME

VDD

FUNCTION

Chip Bias

Bias Return

DESCRIPTION

Bias IC from nominal 2.5V to 5V

IC ground

GND

ENABLE/

ENABLE#

Input to start on/off Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is

sequencing.

disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE#.

RESET#

RESET# Output

RESET# provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization

of output voltages. RESET# will assert low upon any UVLO not being satisfied or ENABLE/ENABLE#

being deasserted. The RESET# output is an open drain N-channel FET and is guaranteed to be in the

correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.

UVLO_A

UVLO_B

UVLO_C

UVLO_D

Under Voltage Lock These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and

Out/Monitoring

Input

are filtered to ignore short (<7µs) transients below programmed UVLO level.

DLY_ON_A Gate On Delay

Allows for programming the delay and sequence for V

turn-on using a capacitor to ground. Each

OUT

Timer Output

cap is charged with 1µA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current

DLY_ON_B

source providing delayed enhancement of the associated FETs GATE to turn-on.

DLY_ON_C

DLY_ON_D

DLY_OFF_A Gate Off Delay

Allows for programming the delay and sequence for V

capacitor to ground. Each cap is charged with a 1µA internal current source to an internal reference

voltage causing the corresponding gate to be pulled down thus turning-off the FET.

turn-off through ENABLE/ENABLE# via a

OUT

Timer Output

DLY_OFF_B

DLY_OFF_C

DLY_OFF_D

GATE_A

GATE_B

GATE_C

GATE_D

FET Gate Drive

Output

Drives the external FETs with a 10µA current source to soft start ramp into the load. During sequence

off, 10µA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will

sink ~75mA to ensure a rapid turn-off.

FN6413.0

December 21, 2006

ISL8723, ISL8724

Pin Descriptions (Continued)

PIN NAME

FUNCTION

DESCRIPTION

SYSRST# System Reset I/O

As an input, allows for immediate and unconditional latch-off of all GATE outputs when driven low. This pin

can also be used to initiate the programmed sequence with ‘zero’ wait (no 10ms stabilization delay) from

input signal on this pin being driven high to first GATE.

As an output when there is a UV condition this pin pulls low. If common to other SYSRST# pins in a multiple

IC configuration it will cause immediate and unconditional latch-off of all other GATEs on all other ISL872x

sequencers.

This pin is released to go high once all UVLO and enable conditions are satisfied and is pulled low

concurrent with the last GATE being turned off after EN disabled.

9,11, No Connect No Connect

No Connect

FN6413.0

December 21, 2006

ISL8723, ISL8724

Absolute Maximum Ratings

Thermal Information

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

Thermal Resistance (Typical, Notes 1, 2)

4 x 4 QFN Package . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

(°C/W)

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +6V

UVLO, ENABLE, ENABLE#, SYSRST# . . . . . . -0.3V to V

RESET#, DLY_ON, DLYOFF. . . . . . . . . . . . . . . -0.3V to V

+0.3V

Operating Conditions

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . +2.5V to +5.0V

Temperature Range (T ) . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

2. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

3. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications

PARAMETER

= 3.3V to +5V, T = T = -40°C to +85°C, Unless Otherwise Specified.

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UVLO

Undervoltage Lockout Falling Threshold

Undervoltage Lockout Hysteresis

Undervoltage Lockout Threshold Range

Undervoltage Lockout Delay

Transient Filter Duration

= T = +25°C

619

631

647

μs

UVLOvth

UVLOhys

604

656

RUVLOvth

TUVLOdel

tFIL

Max V

- Min V

UVLOvth

ENABLE satisfied

, UVLO, ENABLE glitch filter

DELAY ON/OFF

Delay Charging Current

DLY_ichg

DLY_ichg_r

DLY_Vth

= 0V

0.9

1.115

0.05

1.32

μA

DLY

Delay Charging Current Range

Delay Threshold Voltage

DLY_ichg(max) - DLY_ichg(min)

0.01

1.273

1.21

ENABLE/ENABLE#, RESET# AND SYSRST# I/O

ENABLE Threshold

Measured at V

= 5V

1.28

1.35

ENh

ENABLE# Threshold

0.5 V

ENABLE/ENABLE# Hysteresis

ENABLE/ENABLE# Lockout Delay

ENABLE/ENABLE# Input Capacitance

RESET# Pull-up Voltage

0.1

0.2

ENh - ENl

TdelEN_LO

Cin_en

UVLO satisfied, EN to DLY_ON

Vpu_rst

RESET# Pull-Down Current

RESET# Delay after GATE High

RESET# Output Low

= 5V, RST = 0.1V

RSTpd5

GATE = V +5V

160

RSTdel

Measured at V

= 5V, 1mA

0.1

RSTl

sourcing current

RESET Output Capacitance

SYSRST# Pull-up Voltage

SYSRST# Pull-up Current

SYSRST# Pull Down Current

SYSRST# Low Output Voltage

Cout_rst

Vpu_srst

Ipu_srst

Ipu_5

-0.5V

= 3.3V, SYSRST# = 0.5V

= 5V

μA

2.7

Vol_srst

= 5V, I

OUT

= 100μA

0.1

FN6413.0

December 21, 2006

ISL8723, ISL8724

Electrical Specifications

PARAMETER

= 3.3V to +5V, T = T = -40°C to +85°C, Unless Otherwise Specified. (Continued)

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SYSRST# Output Capacitance

SYSRST# Low to GATE Turn-off

SYSRST# High to GATE Turn-on

GATE

Cout_srst

GATE = 80% of V +5V

delSYS_G_1

delSYS_G_2

GATE = 50% of V +5V

0.4

GATE Turn-On Current

GATE Turn-Off Current

GATE Current Range

GATE Pull-Down High Current

GATE High Voltage

GATE = 0V

8.3

10.2

-10.2

0.6

12.5

-8.3

μA

GATEon

GATE = V , Disabled

-12.5

GATEoff_l

Within IC I

max-min

GATE_range

GATE

GATE = V , UVLO = 0V

GATEoff_h

= 5V

+5.3V

V +5.6V

GATEh5

GATE Low Voltage

Gate Low Voltage, V

= 1V

0.01

0.1

GATEl

BIAS

IC Supply Current

= 5V, Enabled and static

0.27

0.31

μA

VDD_5V

ISL8723 Stand By IC Supply Current

Power On Reset

= 5V, ENABLE = 0V

rising

VDD_sb

_POR

2.2

2.41

GATEs are pulled low with ~75mA. Normal shutdown mode

is entered when no UVLO is violated and the ENABLE is

deasserted. When ENABLE is deasserted, RESET# is

asserted and pulled low. Next, all four shutdown ramp caps

on the DLY_OFF pins are charged with a 1μA source and

when any ramp-cap reaches DLY_Vth, a latch is set and a

10μA current is sunk on the respective GATE pin to turn off

its external MOSFET. When the falling GATE voltage is

approximately 1.5V, the GATE is pulled down the rest of the

way at a higher current level to ensure a hard turn-off. Each

individual external FET is thus turned off removing the

voltages from the load in the programmed sequence. The

SYSRST# will pull low concurrent with the last GATE being

pulled low.

ISL8723, ISL8724 Descriptions and

Operation

The ISL8723 and ISL8724 sequencers are quad voltage

sequencing controllers designed for use in multiple-voltage

systems requiring power sequencing of various supply

voltages. Individual voltage rails are gated on and off by

external N-Channel MOSFETs, the gates of which are

driven by an internal charge pump to ~VDD +5.6V (VQP) in

a user programmed sequence.

With the ISL8723 the ENABLE must be asserted high and

all four voltages to be sequenced must be above their

respective user programmed Under Voltage Lock Out

(UVLO) levels before programmed output turn on

sequencing can begin. Sequencing and delay

The ISL8723 and ISL8724 have the same functionality

except for the complimentary ENABLE active polarity with

the ISL8724 having an ENABLE# input. Additionally the

ISL8723 also has a low power sleep state when disabled.

determination is accomplished by the choice of external

cap values on the DLY_ON and DLY_OFF pins. The

SYSRST# goes high once all 4 UVLO inputs and ENABLE

are satisfied. Once all 4 UVLO inputs and ENABLE are

satisfied for 10ms, the four DLY_ON caps are

simultaneously charged with 1μA current sources to the

DLY_Vth level of 1.28V. As each DLY_ON pin reaches the

DLY_Vth level its associated GATE will then turn-on with a

10μA source current to the VQP voltage of VDD+5.6V.

Thus all four GATEs will sequentially turn on. Once at

DLY_Vth the DLY_ON pins will discharge to be ready when

next needed. After the entire turn on sequence has been

completed and all GATEs have reached the charge

pumped voltage (VQP), a 160ms delay is started to ensure

stability after which the RESET# output will be released to

go high. Subsequent to turn-on, if any input falls below its

Upon bias the SYSRST# and RESET# pins are held low

before bias voltage = 1V.

The SYSRST# has both an input and output function. As an

output the SYSRST# pin is useful when implementing

multiple sequencers in a design needing simultaneous

shutdown as with a kill switch across all sequencers. Once

any UVLO is unsatisfied for longer than T

the related

FIL

SYSRST# will pull low and pull all other SYSRST# pins low

that are on a common connection thus unconditionally

shutting down all outputs across multiple sequencers. As

an input, if it is pulled low all GATEs will be unconditionally

shut off and RESET# pulled low, see Figure 17. This pin

can also be used as a ‘no wait’ enabling input, if all inputs

(ENABLE and UVLO) are satisfied it does not wait through

UVLO point for longer than the glitch filter period, T

(~7μs) this is considered a fault. RESET#, SYSRST# and

all GATEs are simultaneously pulled low. In this mode the

FIL

FN6413.0

December 21, 2006

ISL8723, ISL8724

the ~10ms enable delay to initiate DLY_ON cap charging

when released to go high. This feature can be used where

4 voltages can be monitored in addition to a on-off switch

position or, in the case of the ISL8724 a present pin pull

down.

Restart of the turn on sequence is automatic once all

requirements are met. This allows for no interaction

between the sequencer and a controller IC if so desired.

If no capacitors are connected between DLY_ON or

DLY_OFF pins and ground then all such related GATEs

start to turn on immediately after the 10ms (T

)

UVLOdel

ENABLE stabilization time out has expired and the GATEs

start to immediately turn off when ENABLE is deasserted.

Table 1 illustrates the nominal time delay from the start of

charging to the 1.27V reference for various capacitor

values on the DLY_X pins. This table does not include the

10ms of enable lock out delay during a start up sequence

but represents the time from the end of the enable lock out

delay to the start of GATE transition. There is no enable

lock out delay for a sequence off, so this table illustrates

the delay to GATE transition from a disable signal.

TABLE 1.

NOMINAL DELAY TO SEQUENCING THRESHOLD

DLY PIN CAPACITANCE

TIME (ms)

0.02

Open

100pF

1000pF

0.01μF

0.1μF

1μF

0.135

1.35

13.5

135

1350

NOTE: Nom. T

= dly_cap (µF) X 1.35MΩ

DEL_SEQ

Figure 2 illustrates the turn-on and Figure 3 the nominal turnoff

timing diagrams of the ISL8723 and ISL8724 product.

Note the delay and flexible sequencing possibilities. Multiple

series, parallel or adjustable capacitors can be used to easily

fine tune timing between that offered by standard value

capacitors.

FN6413.0

December 21, 2006

ISL8723, ISL8724

UVLOVth

<tFIL

UVLO_A

UVLO_B

UVLO_C

UVLOVth

UVLO_D

UVLOdel

ENABLE# (ISL8724)

ENABLE (ISL8723)

DLY_Vth

DLYON_B

DLYON_D

DLY_Vth

DLYON_A

DLYON_C

DLY_Vth

QPUMP

GATE_B

GATE_D

GATE_C

GATE_A

-1V

QPUMP

RSTdel

RESET#

SYSRST#

FIGURE 2. ISL8723, ISL8724 TURN-ON AND GLITCH RESPONSE TIMING DIAGRAM

UVLO_X>VUVLOVth

ENABLE(ISL8723)

ENABLE# (ISL8724)

DLYOFF_A

DLY_Vth

DLYOFF_B

DLYOFF_C

DLY_Vth

DLYOFF_D

GATE_C

GATE_D

GATE_A

GATE_B

RESET#

SYSRST#

FIGURE 3. ISL8723, ISL8724 TURN-OFF TIMING DIAGRAM

FN6413.0

December 21, 2006

ISL8723, ISL8724

Typical Performance Curves

0.30

0.25

650

= 5V

645

640

635

630

625

620

615

610

0.20

0.15

0.10

0.05

0.00

= 3.3V

ISL8723 DISABLED

-40

-20

100

125

-40

-20

100

125

TEMPERATURE (°C)

FIGURE 4. BIAS CURRENT

FIGURE 5. UVLO THRESHOLD VOLTAGE

1.29

1.28

1.27

1.26

1.25

1.24

1.23

1.020

1.000

0.980

0.960

0.940

0.920

DLY_OFF Vth

DLY_ON Vth

DLY_ON

DLY_OFF

-40

-20

-40

-20

100 125

TEMPERATURE (°C)

FIGURE 6. DLY THRESHOLD VOLTAGE

FIGURE 7. DLY CHARGE CURRENT

1.29

1.28

1.27

1.26

1.25

1.24

1.23

6.0

5.8

5.6

5.4

5.2

5.0

4.8

DLY_OFF Vth

DLY_ON Vth

= 5V

= 2.5V

-40

-20

100

125

-40

-20

TEMPERATURE (°C)

FIGURE 8. BIAS POWER ON RESET

FIGURE 9. CHARGE PUMP VOLTAGE

FN6413.0

December 21, 2006

ISL8723, ISL8724

Typical Performance Curves (Continued)

100

10.3

10.2

10.1

10.0

9.9

I_GATE_ON

I_GATE_OFF

9.8

9.7

9.6

9.5

9.4

-40

-20

100

125

-20

100

125

TEMPERATURE (°C)

FIGURE 10. GATE TURN-OFF/ON (DIS)CHARGE CURRENT

FIGURE 11. FAULT GATE TURN-OFF SINK CURRENT

VOUT voltage for a single channel being turned on and off

respectively.

Using the ISL8723EVAL1 Platform

The ISL8723EVAL1 platform allows evaluation of the

ISL8723, easily providing access to the critical nodes, see

Figure 21 for schematic and Figure 22 for a photograph of

the evaluation platform.

RESET# and SYSRST# functionality and relationships are

shown in Figures 16 through 20.

Figure 16 illustrates that with a rising VDD, EN tied to VDD,

and all UVLO configured to be satisfied, both the RESET#

and SYSRST# are held low before VDD = 1V. SYSRST# is

released to go high once the last UVLO is satisfied and

RESET# is released to go high at T_RSTdelafter the last GATE

is high.

The board has a SMD layout with a ISL8723 illustrating the

possible small implementation size for a typical four rail

sequencing application. There are bias and function labeled

test points to give access to the IC pins for evaluation.

Remember that significant current or capacitive loading of

particular I/O pins will affect functionality and performance.

Figure 17 shows GATE and RESET# response to SYSRST#

being pulled low.

The default configuration of the ISL8723EVAL1 circuit was

built around the following design assumptions:

Figure 18 shows EN high to SYSRST# delay with all UVLO

inputs satisfied.

1. Using the ISL8723IR

2. The four supplies being sequenced are 5V (IN_A), 3.3V

(IN_B), 2.5V (IN_D) and 1.5V (IN_C), the UVLO levels

are ~80% of nominal voltages. Resistors chosen such

that the total resistance of each divider is ~ 10k using

standard value resistors to approximate 80% of

nominal voltage supply = 0.63V on UVLO input.

Figure 19 shows RESET# and SYSRST# delay to EN pulled

low.

Figure 20 shows ~8µs of glitch filter duration, tFIL during

which the RESET# and SYSRST# do not react.

3. The desired order turn-on sequence is 5V first, then 3.3V

about 12ms later then the 2.5V supply about 19ms later

and lastly the 1.5V supply about 40ms later.

4. The desired turn-off sequence is first the 2.5V, the 3.3V

12ms later, then the 1.5V supply about 36ms later and

lastly the 5V supply about 72ms after that.

5. LED off indicates sequence has completed and RESET

has released and pulled high.

All scope shots are taken from ISL8723EVAL1 board.

Figures 12 and 13 illustrate the desired turn-on and turn-off

sequences respectively. The sequencing order and delay

between voltages sequencing is set by external capacitance

values so other than that illustrated can be accomplished.

Figures 14 and 15 illustrate the timing relationships between

the EN input, RESET#, DLY and GATE outputs and the

FN6413.0

December 21, 2006

ISL8723, ISL8724

Typical Performance Waveforms

ENABLE

RESET#

ENABLE

RESET#

SYSRST#

I/O = 5V/DIV

SYSRST#

I/O = 5V/DIV

5VOUT

3.3VOUT

2.5VOUT

1.5VOUT

2.5VOUT

VOUT = 2V/DIV

20ms/DIV

40ms/DIV

FIGURE 13. ISL8723 SEQUENCED TURN-OFF

FIGURE 12. ISL8723 SEQUENCED TURN-ON

EN 5V/DIV

GATE 2V/DIV

delENLO

DLY_Vth

DLY_ON 0.5V/DIV

DLY_OFF 0.5V/DIV

GATE 2V/DIV

3.3VO 2V/DIV

4ms/DIV

3.3VO 2V/DIV

10ms/DIV

FIGURE 14. ISL8723 3.3V TURN-ON

FIGURE 15. ISL8723 3.3V TURN-OFF

GATE

VDD

SYSRST#

RESET#

FIGURE 16. SYSRST# and RESET# vs VDD (EN = VDD, 4

UVLO > UVLO Vth)

FIGURE 17. SYSRST# LOW to GATE and RESET# LOW

FN6413.0

December 21, 2006

ISL8723, ISL8724

Typical Performance Waveforms (Continued)

SYSRST#

ENABLE

SYSRST#

RESET#

ENABLE

FIGURE 18. 4 UVLOs VALID, ENABLE HIGH to SYSRST HIGH

FIGURE 19. ENABLE LOW to RESET# and SYSRST LOW

UVLO

RESET#

SYSRST#

FIGURE 20. UVLO INVALID to RESET# and SYSRST$# LOW

FN6413.0

December 21, 2006

ISL8723, ISL8724

+3.3V

1.5V

+2.5V

+5V

1μF

DLY_ON_B

ENABLE

0.01μF

DLY_ON_D

DLY_ON_C

DLY_ON_A

0.022μF

0.068μF

6.98K

8.45K

4.99K

7.681K

OPEN

UVLO_B

UVLO_C

UVLO_D

DLY_OFF_C

DLY_OFF_D

DLY_OFF_B

DLY_OFF_A

0.047μF

OPEN

0.01μF

UVLO_A

0.1μF

5 6 FDS6990S

Q1A

ISL8723IR

R12

2.26K

4.99K

3.01K

R11

1.47K

GATE_A

GATE_B

GATE_D

GATE_C

8 FDS6990S

Q1B

SYSRST

FDS6990S

Q2A

9,11

FDS6990S

Q2B

750

7 8

RESET

GND

R14

R10

10 R13

FIGURE 21. ISL8723EVAL1 BOARD SCHEMATIC

FIGURE 22. EVAL BOARD PHOTOGRAPH

FN6413.0

December 21, 2006

ISL8723, ISL8724

TABLE 2. ISL872XSEQEVAL1 BOARD COMPONENT LISTING

COMPONENT

DESIGNATOR

COMPONENT FUNCTION

ISL8723, 4 Supply Sequencer

COMPONENT DESCRIPTION

Q1, Q2

Intersil, ISL8723IR 4 Supply Sequencer

FDS6990S or equiv, Dual N-Channel MOSFET

8.45kΩ 1%, 0402

Voltage Rail Switches

5V to UVLO_A Resistor for Divider String

UVLO_A to GND Resistor for Divider String

3.3V to UVLO_B Resistor for Divider String

UVLO_B to GND Resistor for Divider String

2.5V to UVLO_D Resistor for Divider String

UVLO_D to GND Resistor for Divider String

1.5V to UVLO_C Resistor for Divider String

UVLO_D to GND Resistor for Divider String

RESET LED Current Limiting Resistor

5V turn-on Delay Cap. A (~10ms)

5V turn-off Delay Cap. A (~140ms)

3.3V turn-on Delay Cap.B (~13ms)

3.3V turn-off Delay Cap. B (~13ms)

2.5V turn-on Delay Cap.D (~25ms)

2.5V turn-off Delay Cap. D (0ms)

1.5V turn-on Delay Cap. C (~100ms)

1.5V turn-off Delay Cap. C (~60ms)

Decoupling Capacitor

R11

1.47kΩ 1%, 0402

7.68kΩ 1%, 0402

R12

2.26kΩ 1%, 0402

6.98kΩ 1%, 0402

3.01kΩ 1%, 0402

4.99kΩ 1%, 0402

750Ω 10%, 0805

DNP, 0402

0.1μF 10%, 6.3V, 0402

0.01μF 10%, 6.3V, 0402

0.022μF 10%, 6.3V, 0402

DNP, 0402

0.068μF 10%, 6.3V, 0402

0.047μF 10%, 6.3V, 0402

1μF, 0805

RESET Indicating LED

0805, SMD LEDs Red

10Ω 20%, 3W Carbon

5V Load Resistor

R10

R13

R14

3.3V Load Resistor

2.5V Load Resistor

1.5V Load Resistor

Test Points Labeled as to Function

FN6413.0

December 21, 2006

ISL8723, ISL8724

Application Implementations

HIGH = POWER GOOD

Multiple Sequencer Implementations

In order to control the sequencing of more than 4 voltages in

applications where the integrity of these critical voltages

must be assured prior to sequencing, several of the ISL8723

or ISL8724 devices can configured together to accomplish

this.

SYSRST#

ISL872X

UVLO

ENABLE

ENABLE#

RESET#

Figure 23 shows a typical multi sequencer implementation,

note the common SYSRST# signal that asserts once all

monitored voltages are valid allowing the sequence to

initiate. The sequencing is straight forward across multiple

sequencers as all DLY_ON capacitors will simultaneously

start charging once all monitored voltages area valid and

~10ms after the common ENABLE input signal is delivered.

This allows the choice of capacitors to be related to each

other no different than using a single sequencer. When the

common enabling signal is deasserted this configuration will

then execute the turn-off sequence across all sequencers as

programmed by the DLY_OFF capacitor values.

SYSRST#

ISL872X

UVLO

POWER

SUPPLY

ENABLE#

RESET#

With all the SYSRST# pins bused together once the on

sequence is complete simultaneous shutdown upon any

UVLO input failure is assured as the SYSRST# output will

pull low, simultaneously turning off all GATE outputs.

HIGH = SEQUENCE COMPLETED

FIGURE 23. MULTIPLE ISL872X CONFIGURATION

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6413.0

December 21, 2006

ISL8723, ISL8724

Package Outline Drawing

L24.4x4

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

2.5

4.00

20X

0.50

PIN #1 CORNER

(C 0 . 25)

PIN 1

INDEX AREA

2 . 10 ± 0 . 15

0.15

(4X)

24X 0 . 4 ± 0 . 1

0.10 M C

A B

TOP VIEW

+ 0 . 07

24X 0 . 23

- 0 . 05

BOTTOM VIEW

SEE DETAIL "X"

0.10

0 . 90 ± 0 . 1

BASE PLANE

( 3 . 8 TYP )

SEATING PLANE

0.08

SIDE VIEW

(

2 . 10 )

( 20X 0 . 5 )

0 . 2 REF

( 24X 0 . 25 )

( 24X 0 . 6 )

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6413.0

December 21, 2006

ISL8723 [INTERSIL]

相关型号：

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SI9130_11

SI9137

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