ISL88042IRTHFZ-TK_技术文档

ISL88042

®

Data Sheet

July 26, 2010

FN6655.2

Quadruple Voltage Monitor

Features

The ISL88042 is a Quadruple voltage-monitoring supervisor

combining competitive reset threshold accuracy and low

power consumption. This device combines popular functions

such as Power-On Reset, Undervoltage Supply Supervision,

reset signaling and Manual Reset. Monitoring four different

supplies in a 8 Ld 2x3 TDFN package, the ISL88042 devices

can help to lower system cost, reduce board space

requirements, and increase the reliability of multi-voltage

systems.

• Quadruple Voltage Monitoring

• Fixed-Voltage Options Allow Precise Monitoring of +5.0V

and +3.3V Power Supplies

• Two Adjustable Voltage Inputs Monitor Voltages > 0.6V

• 95ms Nominal Reset Pulse Width

• Manual Reset Capability

• Reset Signals Valid Down to V

= 1V

DD

Low V

detection circuitry protects the user’s system from

• Immune to Power-Supply Transients

• Low 22µA Maximum Supply Current at 5V

• Pb-Free (RoHS Compliant)

DD

low voltage conditions, resetting the system when V

or

DD

any of the other monitored power supply voltages fall below

their respective minimum voltage thresholds. The reset

signal remains asserted until all of these voltages return to

proper operating levels and stabilize.

Applications

• Telecom and Datacom Systems

• Routers and Servers

Two of the four voltage monitors have preset thresholds for

either dual 3.3V or one each for one 5V and one 3.3V

supplies. Users can adjust the threshold voltages of the third

and fourth voltage monitors in order to meet specific system

level requirements.

• Access Concentrators

• Cable/Satellite Applications

• Desktop and Notebook Computer Systems

• Data Storage Equipment

• Set-Top Boxes

Pinout

ISL88042

(8 LD TDFN)

TOP VIEW

• Industrial Equipment

1

2

3

4

8

7

6

5

MR

RST

V

• Multi-Voltage Systems

EPAD

(GND)

V

DD

DDA

V2MON

V4MON

V3MON

GND

Ordering Information

PACKAGE

PART NUMBER

(Notes 1, 2)

PART

MARKING

V

(V)

V

(V)

TEMP RANGE

(°C)

Tape & Reel

(Pb-free)

PKG.

DWG. #

TH1

TH2

ISL88042IRTHFZ-T

ISL88042IRTHFZ-TK

ISL88042IRTEEZ-T

ISL88042IRTEEZ-TK

ISL88042IRTJJZ-T

ISL88042IRTJJZ-TK

NOTES:

4P6

4.60

2.87

2.78

3.09

2.95

2.86

-40 to +85

8 Ld TDFN

L8.2x3A

8 Ld TDFN

L8.2x3A

2P9

2P8

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products

are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL88042

Pin Descriptions

ISL88042

PIN NUMBER

PIN NAME

FUNCTION

1

2

3

4

5

6

7

8

MR

Active-Low open drain manual reset input with internal pull-up resistor

Chip Bias Input and primary integrated preset undervoltage monitor

Secondary integrated preset undervoltage monitor input

Ground

V

DD

V2MON

GND

V3MON

V4MON

Adjustable undervoltage monitor input

V

Must be tied to V

for proper operation

DD

DDA

RST

Active-low open drain reset output

Functional Block Diagram

V

DD

MR

PB

POR

¬

V

REF

RST

t

POR

V2MON

V4MON

V3MON

¬

V

REF

GND

¬

FN6655.2

July 26, 2010

2

ISL88042

Absolute Maximum Ratings

Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Voltage on VDD with Respect to GND. . . . . . . . . . . . . .-1.0V to +7V

Voltage on V3MON, V4MON . . . . . . . . . . . . . . . . . . . . . . -1.0V to 3V

Voltage on Any Other Pin. . . . . . . . . . . . . . . . . -1.0V to VDD + 0.3V

DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Thermal Resistance (Typical)

θ

(°C/W)

60

θ

(°C/W)

8

JA

JC

8 Ld TDFN Package (Notes 3, 4). . . . .

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Operating Temperature Range (Industrial) . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

3. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

4. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Over the recommended operating conditions, unless otherwise specified.

MIN

MAX

SYMBOL

PARAMETER

Supply Voltage Range

Supply Current

TEST CONDITIONS

(Note 5)

TYP

(Note 5)

UNITS

V

2.0

5.5

22

8

DD

DD1

DD2

DDA

I

V

= 5.0V

DD

14

5.5

19

µA

DD

V2MON Input Current

V2MON = 3.3V

µA

I

V3MON, V4MON Input Current

V3MON, V4MON = 1.0V

100

nA

VOLTAGE THRESHOLDS

Fixed Voltage Trip Point for V

V

ISL88042IRTHFZ

ISL88042IRTEEZ

ISL88042IRTJJZ

4.370

2.734

2.647

4.600

2.872

2.780

92

4.830

3.010

2.914

V

TH1

DD

V

Hysteresis of V

TH1

V

= 4.60V

= 2.87V

= 2.78V

mV

V

TH1HYST

TH1

58

V

Fixed Voltage Trip Point for V2MON

ISL88042IRTHFZ

ISL88042IRTEEZ

ISL88042IRTJJZ

2.936

2.815

2.725

3.090

2.957

2.860

61

3.245

3.099

3.000

TH2

V

Hysteresis of V

TH2

V

= 3.09V

= 2.96V

= 2.86V

mV

TH2HYST

TH2

60

V

ISL88042IRTHFZ, ISL88042IRTEEZ

Adj. Reset Threshold Voltage

for V3MON, V4MON

TH

0.572

0.554

0.600

0.630

0.610

V

REF

ISL88042IRTJJZ Adj. Reset Threshold Voltage V for V3MON, V4MON

TH

0.581

12

V

Hysteresis Voltage

mV

REFHYST

RESET

V

Reset Output Voltage Low

V

≥ 3.3V, Sinking 2.5mA

0.05

6

0.40

V

OL

DD

< 3.3V, Sinking 1.5mA

t

V

to Reset Asserted Delay

TH

µs

ms

RPD

t

POR Timeout Delay

V3MON, V4MON < 3V

40

95

150

POR

FN6655.2

July 26, 2010

3

ISL88042

Electrical Specifications Over the recommended operating conditions, unless otherwise specified. (Continued)

MIN

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 5)

TYP

(Note 5)

UNITS

MANUAL RESET

V

MR Input Voltage Low

0.8

V

MRL

V

MR Input Voltage High

MR Minimum Pulse Width

Internal Pull-Up Resistor

V

- 0.6

MRH

DD

t

550

ns

kΩ

MR

R

10

PU

NOTE:

5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

.

Pin Descriptions

RST

V

DD

RST

The RST output is an open drain output, which is asserted

low whenever the following occurs:

V2MON

V4MON

MR

PB

1. The device is initially powered up to 1V or

ISL88042

RESET

SIGNAL

V3MON

2. V , V2MON, V3MON or V4MON fall below their

DD

minimum voltage sense level.

MR

The MR input is an active low debounced input to which a

user can connect a push-button to add manual reset

capability or use a signal to pull low. MR has an internal

pull-up resistor.

GND

FIGURE 1. TYPICAL APPLICATION DIAGRAM

V

DD

The V

Principles of Operation

pin is the IC power supply terminal. The voltage at

DD

this pin is compared against an internal factory-programmed

voltage trip point, V . RST is first asserted low when the

The ISL88042 device provides those functions needed for

monitoring critical voltages, such as power-supply and battery

functions in microprocessor systems. It provides such features

as Power-On Reset control, supply voltage supervision, and

Manual Reset Assertion. The integration of all these features

along with competitive reset threshold accuracy and low power

consumption, makes the ISL88042 device suitable for a wide

variety of applications needing multi-voltage monitoring. See

Figure 1 for the “Typical Application Diagram”.

TH1

device is initially powered and V

< 1V and then at any

DD

falls below V

time thereafter when V

designed with hysteresis to help prevent chattering due to

noise and is immune to brief power-supply transients.

. The device is

DD

TH1

V2MON

The V2MON input is the second preset monitored voltage

that causes the RST output to go low when the voltage on

V2MON falls below V

Low Voltage Monitoring

.

TH2

During normal operation, the ISL88042 monitors the voltage

V3MON, and V4MON

levels of V , V2MON, V3MON and V4MON. If the voltage on

DD

The VxMON inputs provide monitoring and UV compliance

of three additional voltages through resistor dividers. A reset

is issued on the ISL88042 if the voltage on any VxMON falls

any of these four inputs falls below their respective voltage trip

points, a reset is asserted (RST = low) to prevent the

microprocessor from operating during a power failure or

brownout condition. This reset signal remains low until the

voltages exceeds the voltage threshold settings for the reset

below the internal V

of 0.6V.

REF

time delay period t

.

POR

The ISL88042 allows users to customize the minimum voltage

sense level for two of the four monitored voltages. For example,

the user can adjust the voltage input trip point (V

) for the

TRIP

V3MON and V4MON inputs. To do this, connect an external

resistor divider network to the VxMON pin in order to set the trip

FN6655.2

July 26, 2010

4

ISL88042

point to some other voltage above 600mV according to

Equation 1:

The reset signal remains active until V

DD

minimum voltage sense level for time period t

rises above the

. This

POR

ensures that the supply voltage has stabilized to sufficient

operating levels.

(EQ. 1)

V

= 0.6V × R + R /R

1 2 2

TRIP

Manual Reset

Power-On Reset (POR)

The manual-reset input (MR) allows the user to trigger a reset

by using a push-button switch or by signaling the input low. The

MR input is an active low debounced input. Reset is asserted if

the MR pin is pulled low to less than 100mV for the minimum

MR pulse width or longer while the push-button is closed. After

Applying power to the ISL88042 activates a POR circuit, which

makes the reset pin(s) active (i.e. RST goes high while RST

goes low). These signals provide several benefits:

• They prevent the system microprocessor from starting to

operate with insufficient voltage.

MR is released, the reset output remains asserted low for t

(200ms) and then is released.

POR

• They prevent the processor from operating prior to

stabilization of the oscillator.

Figures 2 and 3 illustrate the ISL88042’s operation.

• They ensure that the monitored device is held out of

operation until internal registers are properly loaded.

• They allow time for an FPGA to download its configuration

prior to initialization of the circuit.

V

TH1/ TH2

V

DD /

V2MON

1V

>t

MR

t

POR

RPD

t

POR

RST

>t

MD

FIGURE 2. POWER SUPPLY MONITORING DIAGRAM

VXMON

V

TH

t

POR

RPD

RST

FIGURE 3. VOLTAGE MONITORING DIAGRAM

FN6655.2

July 26, 2010

5

ISL88042

Special Application Considerations

The ISL88042EVAL1Z and Applications

Using good decoupling practices on bias and other

monitoring inputs will prevent transients (i.e. due to switching

noises and short duration droops in the supply voltage) from

causing unwanted resets.

The ISL88042EVAL1Z supports all variants of the ISL88042

devices, enabling evaluation of basic functional operation and

common application implementations. Figure 10 illustrates the

ISL88042EVAL1Z in schematic and photographic forms. The

ISL88042EVAL1Z is populated with the ISL88042IRTEEZ

In unusually noisy environments or situations where

unwanted signals may be injected into the adjustable VMON

inputs, lowering the node impedance and/or positioning a

small valued filter capacitor as close to the pin as possible

can increase noise immunity.

(V

V

and V2MON V = 2.90V).

TH2

DD TH1

With adequate bias on the two preset and the two adjustable

monitor inputs the RST output will release to pull high

indicating that all supplies are compliant for a minimum of

t

. For the ISL88042EVAL1Z as shipped, the V

and

POR

DD

Although the internal ISL88042 threshold references are

guaranteed over the full temp range, accuracy errors due to

external component tolerances and distribution losses will

occur. High tolerance resistors and layout for extreme

accuracy and critical performance must be considered.

V2MON nominal thresholds are as previously noted with the

voltage thresholds being monitored by V3MON and V4MON

being left open for programming via the non populated

resistor dividers.

Typical Performance Curves

610

4.60

4.59

4.58

3.20

3.15

ISL88042IRTHF VDD

605

ISL88042IRTHF ISL88042IRTEE V4MON

3.10

3.05

600

ISL88042IRTHF V2MON

ISL88042IRTEE V2MON

595

3.00

2.95

2.90

2.85

2.80

4.57

4.56

ISL88042IRTHF ISL88042IRTEE V3MON

590

ISL88042IRTJJ V4MON

585

ISL88042IRTEE VDD

4.55

4.54

4.53

580

ISL88042IRTJJ V2MON

ISL88042IRTJJ VDD

ISL88042IRTJJ V3MON

575

2.75

2.70

570

-40

-20

0

25

50

85

100

125

-40

-20

0

25

50

85

100

125

TEMPERATURE (°)

TEMPERATURE (°C)

FIGURE 4. VDD and V2MON Vth vs TEMPERATURE

FIGURE 5. V3MON and V4MON Vth vs TEMPERATURE

120

115

110

105

100

95

16

14

VDD = 5V

12

10

8

6

90

4

V2MON = 3.3V

85

2

0

80

-40

-20

0

25

50

85

100 125

-40

-20

0

25

50

85

100 125

TEMPERATURE (°C)

FIGURE 7. BIAS CURRENT vs TEMPERATURE

FIGURE 6. t

por

vs TEMPERATURE

FN6655.2

July 26, 2010

6

ISL88042

Typical Performance Curves

RST

1V/DIV

RST

1V/DIV

t

= 4.3µs

RPD

t

= 94ms

POR

VMON = 0.5V/DIV

20ms/DIV

1µs/DI

FIGURE 9. ISL88042 t

FIGURE 8. ISL88042 t

POR

RPD

VDD

U1

MR

RST

VDD

RST

MRST

C1

VDD

V4MON

V4

V3

OPEN

V2MON

R5

A

V2MON

V4MON

V3MON

OPEN R3

AGND

GND

OPEN

A

V3MON

ISL88042

A

FIGURE 10. ISL88042EVAL1Z SCHEMATIC AND PHOTOGRAPH

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6655.2

July 26, 2010

7

ISL88042

Package Outline Drawing

L8.2x3A

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE WITH E-PAD

Rev 1, 06/09

6

0.25

2.00

PIN #1 INDEX AREA

A

B

0.50

6

PIN 1

INDEX AREA

(4X)

0.15

(8x0.40)

1.65 +0.1/ -0.15

BOTTOM VIEW

TOP VIEW

(8x0.25)

PACKAGE

OUTLINE

(6x0.50)

SEE DETAIL "X"

C

BASE PLANE

SEATING PLANE

0.08 C

0.05

SIDE VIEW

5

0.20 REF

(8x0.40)

(8x0.20)

C

1.65

2.00

0.05

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.20mm and 0.32mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 indentifier may be

either a mold or mark feature.

FN6655.2

July 26, 2010

8


型号：	ISL88042IRTHFZ-TK
厂家：	Intersil
描述：	Quadruple Voltage Monitor 四电压监控器光电二极管监控
文件：	总8页 (文件大小：296K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL88042IRTHFZ-TK [INTERSIL]

相关型号：

ISL88042IRTJJZ-T

ISL88042IRTJJZ-TK

ISL8840A

ISL8840AABZ

ISL8840AAUZ

ISL8840AAUZ

ISL8840AMBEP

ISL8840AMBEPZ

ISL8840AMBEPZ

ISL8840AMBZ

ISL8840AMBZ

ISL8840AMUZ