ISL8840AMBEPZ [RENESAS]

SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8;


型号：	ISL8840AMBEPZ
厂家：	RENESAS TECHNOLOGY CORP
描述：	SWITCHING CONTROLLER, 2000kHz SWITCHING FREQ-MAX, PDSO8, ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8 开关光电二极管
文件：	总10页 (文件大小：192K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ,

ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Data Sheet

September 29, 2008

FN6792.0

High Performance Industry Standard

Single-Ended Current Mode PWM

Controller

Features

• Full Mil-Temp Electrical Performance from -55°C to +125°C

• Controlled Baseline with One Wafer Fabrication Site and

One Assembly/Test Site

The ISL884xAMBEPZ is a high performance drop-in

replacement for the popular 28C4x and 18C4x PWM

controllers suitable for a wide range of power conversion

applications including boost, flyback, and isolated output

configurations. Its fast signal propagation and output

switching characteristics make this an ideal product for

existing and new designs.

• Full Homogenous Lot Processing in Wafer Fab

• No Combination of Wafer Fabrication Lots in Assembly

• Full Traceability Through Assembly and Test by

Date/Trace Code Assignment

• Enhanced Process Change Notification

• Enhanced Obsolescence Management

• Eliminates Need for Up-Screening a COTS Component

• 1A MOSFET Gate Driver

Features include 30V operation, low operating current, 90µA

start-up current, adjustable operating frequency to 2MHz,

and high peak current drive capability with 20ns rise and fall

times.

RISING UVLO

(V)

MAX. DUTY CYCLE

(%)

• 90µA Start-up Current, 125µA Maximum

• 35ns Propagation Delay Current Sense to Output

• Fast Transient Response with Peak Current Mode Control

• 30V Operation

PART NUMBER

ISL8840AMBEPZ

ISL8841AMBEPZ

ISL8842AMBEPZ

ISL8843AMBEPZ

ISL8844AMBEPZ

ISL8845AMBEPZ

7.0

100

14.4

8.4

100

• Adjustable Switching Frequency to 2MHz

• 20ns Rise and Fall Times with 1nF Output Load

14.4

8.4

• Trimmed Timing Capacitor Discharge Current for Accurate

Deadtime/Maximum Duty Cycle Control

• 1.5MHz Bandwidth Error Amplifier

Pinout

• Tight Tolerance Voltage Reference Over Line, Load and

Temperature

ISL884XAMBEPZ

(8 LD SOIC)

TOP VIEW

• ±3% Current Limit Threshold

• Pb-Free (RoHS Compliant)

COMP

VREF

VDD

OUT

GND

Applications

• Isolated Flyback and Forward Regulators

• Boost Regulators

RTCT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Ordering Information

PART NUMBER

(Notes 1, 2)

PART

MARKING

TEMP RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

ISL8840AMBEPZ

8840A MBEPZ

-55 to +125

8 Ld SOIC

M8.15

ISL8841AMBEPZ

ISL8842AMBEPZ

ISL8843AMBEPZ

ISL8844AMBEPZ

ISL8845AMBEPZ

NOTES:

8841A MBEPZ

8842A MBEPZ

8843A MBEPZ

8844A MBEPZ

8845A MBEPZ

8 Ld SOIC

M8.15

1. Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-

020.

FN6792.0

September 29, 2008

Functional Block Diagram

VREF

REF

5.00V

START/STOP

UV COMPARATOR

ENABLE

VREF FAULT

VREF

UV COMPARATOR

GND

4.65V 4.80V

2.5V

A = 0.5

PWM

COMPARATOR

100mV

ONLY

ISL8841AMBEPZ/

ISL8844AMBEPZ/

ISL8845AMBEPZ

1.1V

CLAMP

VF TOTAL = 1.15V

ERROR

AMPLIFIER

COMP

OUT

36k

RESET

DOMINANT

VREF

100k

2.9V

1.0V

150k

OSCILLATOR

COMPARATOR

<10ns

RTCT

CLOCK

8.4mA

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . GND -0.3V to +30V

Thermal Resistance (Note 4)

(°C/W)

100

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V

+ 0.3V

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Operating Conditions

Supply Voltage Range (Note 3) . . . . . . . . . . . . . . . . . . . . . 9V to 30V

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. All voltages are with respect to GND.

4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Technical Brief TB379 for details.

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3.

= 15V, R = 10kΩ, C = 3.3nF, T = -55 to +125°C, Typical values are at T = +25°C. Parameters with MIN

t t A A

and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

UNDERVOLTAGE LOCKOUT

START Threshold (ISL8840AMBEPZ,

ISL8841AMBEPZ)

6.5

8.0

7.0

8.4

7.5

9.0

START Threshold (ISL8843AMBEPZ,

ISL8845AMBEPZ)

START Threshold (ISL8842AMBEPZ,

ISL8844AMBEPZ)

(Note 7)

13.3

6.1

14.3

6.6

15.3

6.9

STOP Threshold (ISL8840AMBEPZ,

ISL8841AMBEPZ)

STOP Threshold (ISL8843AMBEPZ,

ISL8845AMBEPZ)

7.3

7.6

8.0

STOP Threshold (ISL8842AMBEPZ,

ISL8844AMBEPZ)

8.0

8.8

9.6

Hysteresis (ISL8840AMBEPZ, ISL8841AMBEPZ)

Hysteresis (ISL8843AMBEPZ, ISL8845AMBEPZ)

Hysteresis (ISL8842AMBEPZ, ISL8844AMBEPZ)

0.4

0.8

5.4

Start-up Current, I

< START Threshold

125

4.0

5.5

µA

Operating Current, I

(Note 5)

2.9

4.75

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy

Includes 1nF GATE loading

Over line (V

= 12V to 30V), load,

4.900

5.000

5.050

temperature

Long Term Stability

Current Limit, Sourcing

Current Limit, Sinking

CURRENT SENSE

Input Bias Current

CS Offset Voltage

= +125°C, 1000 hours (Note 6)

-20

= 1V

-1.0

1.0

105

1.30

1.03

µA

= 0V (Note 6)

100

1.15

1.00

COMP to PWM Comparator Offset Voltage

Input Signal, Maximum

0.80

0.97

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 3.

= 15V, R = 10kΩ, C = 3.3nF, T = -55 to +125°C, Typical values are at T = +25°C. Parameters with MIN

t t A A

and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested (Continued)

PARAMETER

/ΔV

TEST CONDITIONS

MIN

2.5

TYP

3.0

MAX

3.5

UNITS

V/V

Gain, A

= ΔV

0 < V < 910mV, V = 0V

CS FB

COMP

CS to OUT Delay

ERROR AMPLIFIER

Open Loop Voltage Gain

Unity Gain Bandwidth

Reference Voltage

FB Input Bias Current

COMP Sink Current

COMP Source Current

COMP VOH

(Note 6)

1.0

MHz

1.5

= V

2.460

-1.0

1.0

2.500

2.535

COMP

= 0V

-0.2

1.0

µA

= 1.5V, V = 2.7V

COMP

= 1.5V, V = 2.3V

-0.4

4.80

0.4

VREF

1.0

= 2.3V

COMP VOL

= 2.7V

PSRR

Frequency = 120Hz, V

30V (Note 6)

= 12V to

OSCILLATOR

Frequency Accuracy

Initial, T = +25°C

0.2

1.0

kHz

Frequency Variation with V

Temperature Stability

= +25°C, (f

- f

)/f

30V 10V 30V

(Note 6)

Amplitude, Peak-to-Peak

Static Test

RTCT = 2.0V

1.75

1.0

8.0

RTCT Discharge Voltage (Valley Voltage)

Discharge Current

OUTPUT

6.2

8.5

Gate VOH

- OUT, I

OUT

= -200mA

= 200mA

1.0

2.0

Gate VOL

OUT - GND, I

OUT

Peak Output Current

Rise Time

= 1nF (Note 6)

OUT

1.2

Fall Time

GATE VOL UVLO Clamp Voltage

PWM

= 5V, I = 1mA

LOAD

Maximum Duty Cycle

(ISL8840AMBEPZ, ISL8842AMBEPZ,

ISL8843AMBEPZ)

COMP = VREF

COMP = GND

94.0

47.0

96.0

48.0

Maximum Duty Cycle

(ISL8841AMBEPZ, ISL8844AMBEPZ,

ISL8845AMBEPZ)

Minimum Duty Cycle

NOTES:

5. This is the V

current consumed when the device is active but not switching. Does not include gate drive current.

6. Limits established by characterization and are not production tested.

7. Adjust V

above the start threshold and then lower to 15V.

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Typical Performance Curves

1.01

1.001

1.000

0.999

1.00

0.998

0.997

0.996

0.995

0.99

0.98

-60 -40 -20

20 40 60 80 100 120 140

-60 -40 -20

20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 1. FREQUENCY vs TEMPERATURE

FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

1.001

1.000

0.998

0.997

0.996

100pF

100

220pF

330pF

470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

R (kΩ)

100

-60 -40 -20

20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN

FIGURE 3. EA REFERENCE vs TEMPERATURE

COMP - COMP is the output of the error amplifier and the

input of the PWM comparator. The control loop frequency

compensation network is connected between the COMP and

FB pins.

Pin Descriptions

RTCT - This is the oscillator timing control pin. The

operational frequency and maximum duty cycle are set by

connecting a resistor, R , between V

and this pin and a

REF

timing capacitor, C , from this pin to GND. The oscillator

produces a sawtooth waveform with a programmable

FB - The output voltage feedback is connected to the

inverting input of the error amplifier through this pin. The

non-inverting input of the error amplifier is internally tied to a

reference voltage.

frequency range up to 2.0MHz. The charge time, t , the

discharge time, t , the switching frequency, f, and the

maximum duty cycle, D

following equations:

, can be approximated from the

MAX

CS - This is the current sense input to the PWM comparator.

The range of the input signal is nominally 0V to 1.0V and has

an internal offset of 100mV.

(EQ. 1)

≈ 0.533 ⋅ R ⋅ C

GND - GND is the power and small signal reference ground

for all functions.

0.008 ⋅ R – 3.83

⎛

⎞

⎟

⎠

(EQ. 2)

------------------------------------------

≈ –R ⋅ C ⋅ In

⎜

⎝

0.008 ⋅ R – 1.71

OUT - This is the drive output to the power switching device.

It is a high current output capable of driving the gate of a

power MOSFET with peak currents of 1.0A. This GATE

f = 1 ⁄ (t + t

)

(EQ. 3)

(EQ. 4)

output is actively held low when V

threshold.

is below the UVLO

D = t ⋅ f

The formulae have increased error at higher frequencies due

to propagation delays. Figure 4 may be used as a guideline

in selecting the capacitor and resistor values required for a

given frequency.

- V is the power connection for the device. The total

supply current will depend on the load applied to OUT. Total

current is the sum of the operating current and the

average output current. Knowing the operating frequency, f,

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

and the MOSFET gate charge, Qg, the average output

current can be calculated from Equation 5:

affects COMP. During power-down, diode D quickly

discharges C so that the soft-start circuit is properly

initialized prior to the next power-on sequence.

(EQ. 5)

= Qg × f

OUT

Gate Drive

To optimize noise immunity, bypass V

to GND with a

and GND pins as

The ISL884xAMBEPZ is capable of sourcing and sinking 1A

peak current. To limit the peak current through the IC, an

optional external resistor may be placed between the

totem-pole output of the IC (OUT pin) and the gate of the

MOSFET. This small series resistor also damps any

oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board and the FET’s input

capacitance.

ceramic capacitor as close to the V

possible.

VREF - The 5.00V reference voltage output. +1.0/-1.5%

tolerance over line, load and operating temperature. Bypass

to GND with a 0.1µF to 3.3µF capacitor to filter this output as

needed.

Functional Description

Slope Compensation

Features

For applications where the maximum duty cycle is less than

50%, slope compensation may be used to improve noise

immunity, particularly at lighter loads. The amount of slope

compensation required for noise immunity is determined

empirically, but is generally about 10% of the full scale

current feedback signal. For applications where the duty

cycle is greater than 50%, slope compensation is required to

prevent instability.

The ISL884xAMBEPZ current mode PWM makes an ideal

choice for low-cost flyback and forward topology

applications. With its greatly improved performance over

industry standard parts, it is the obvious choice for new

designs or existing designs which require updating.

Oscillator

The ISL884xAMBEPZ has a sawtooth oscillator with a

programmable frequency range to 2MHz, which can be

Slope compensation may be accomplished by summing an

external ramp with the current feedback signal or by

subtracting the external ramp from the voltage feedback

error signal. Adding the external ramp to the current

feedback signal is the more popular method.

programmed with a resistor from V

and a capacitor to

REF

GND on the RTCT pin. (Please refer to Figure 4 for the

resistor and capacitance required for a given frequency.)

Soft-Start Operation

From the small signal current-mode model [1] it can be

shown that the naturally-sampled modulator gain, Fm,

without slope compensation, is in Equation 6.

Soft-start must be implemented externally. One method,

illustrated in Figure 5, clamps the voltage on COMP.

-----------------

Fm =

(EQ. 6)

S t

n SW

VREF

where S is the slope of the sawtooth signal and t is the

duration of the half-cycle. When an external ramp is added,

the modulator gain becomes Equation 7:

COMP

GND

(EQ. 7)

------------------------------------

--------------------------

Fm =

(S + S )t

m Snt

where S is slope of the external ramp and

------

= 1 +

(EQ. 8)

FIGURE 5. SOFT-START

The criteria for determining the correct amount of external

ramp can be determined by appropriately setting the

damping factor of the double-pole located at the switching

frequency. The double-pole will be critically damped if the

Q-factor is set to 1, over-damped for Q < 1, and

under-damped for Q > 1. An under-damped condition may

result in current loop instability.

The COMP pin is clamped to the voltage on capacitor C

plus a base-emitter junction by transistor Q . C is charged

from VREF through resistor R and the base current of Q1.

At power-up C is fully discharged, COMP is at ~0.7V, and

the duty cycle is zero. As C charges, the voltage on COMP

increases, and the duty cycle increases in proportion to the

voltage on C . When COMP reaches the steady state

(EQ. 9)

operating point, the control loop takes over and soft-start is

-------------------------------------------------

Q =

π(m (1 – D) – 0.5)

complete. C continues to charge up to V

and no longer

REF

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

where D is the percent of on-time during a switching cycle.

Setting Q = 1 and solving for S yields Equation 10:

R C signal. A typical application sums the buffered R C

t t t t

signal with the current sense feedback and applies the result

to the CS pin, as shown in Figure 6.

⎛⎛

⎝⎝

⎞

– 1

(EQ. 10)

-------------

= S

+ 0.5

⎠

1 – D

Since S and S are the on time slopes of the current ramp

VREF

and the external ramp, respectively, they can be multiplied

by t to obtain the voltage change that occurs during t

ON ON

⎛⎛

⎝⎝

⎞

– 1

-------------

= V

+ 0.5

(EQ. 11)

⎠

1 – D

where V is the change in the current feedback signal (ΔI)

RTCT

during the on-time and V is the voltage that must be added

by the external ramp.

For a flyback converter, V can be solved for in terms of

input voltage, current transducer components, and primary

inductance, yielding

FIGURE 6. SLOPE COMPENSATION

D ⋅ t

⋅ V ⋅ R

IN CS

Assuming the designer has selected values for the RC filter

⎛⎛

⎞

– 1

-------------------------------------------------- --

-------------

+ 0.5

⎝⎝

⎠

1 – D

(R and C ) placed on the CS pin, the value of R required

(EQ. 12)

to add the appropriate external ramp can be found by

superposition.

where R is the current sense resistor, f

frequency, L is the primary inductance, V is the minimum

input voltage, and D is the maximum duty cycle.

is the switching

2.05D ⋅ R

---------------------------

(EQ. 16)

+ R

The current sense signal at the end of the on-time for CCM

operation is:

The factor of 2.05 in Equation 16 arises from the peak

amplitude of the sawtooth waveform on R C minus a

base-emitter junction drop. That voltage multiplied by the

maximum duty cycle is the voltage source for the slope

compensation. Rearranging to solve for R yields:

(1 – D) ⋅ V ⋅ f

⋅ R

⎛

⎜

⎝

⎞

⎟

⎠

------------------------

---------------------------------------------

(EQ. 13)

(2.05D – V ) ⋅ R

where V

is the voltage across the current sense resistor,

L is the secondary winding inductance, and I is the output

---------------------------------------------

(EQ. 17)

current at current limit. Equation 13 assumes the voltage

drop across the output rectifier is negligible.

The value of R

rescaled so that the current sense signal presented at the

determined in Equation 15 must be

Since the peak current limit threshold is 1.00V, the total

current feedback signal plus the external ramp voltage must

sum to this value when the output load is at the current limit

threshold.

CS pin is that predicted by Equation 13. The divider created

by R and R makes this necessary.

+ R

--------------------

R′

⋅ R

(EQ. 18)

+ V

= 1

(EQ. 14)

Example:

= 12V

= 48V

Substituting Equations 12 and 13 into Equation 14 and

solving for R

yields Equation 15:

L = 800µH

----------------------------------------------------------------------------------------------------------------------------------------------------

⎛

+ 0.5

⎞

⎟

Ns/Np = 10

D ⋅ f ⋅ V

(1 – D) ⋅ V ⋅ f

O sw

⎛

⎞

⎟

⎠

⎜

------------------------------- -----------------

------

-------------------------------------------

⋅

–1

⋅ I

⎜

⎝

⎟

⎠

1 – D

⎝

L = 8.0µH

= 200mA

(EQ. 15)

Switching Frequency, f

= 200kHz

Adding slope compensation is accomplished in the

Duty Cycle, D = 28.6%

ISL884xAMBEPZ using an external buffer transistor and the

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

R = 499Ω

Fault Conditions

A Fault condition occurs if V

Fault is detected, OUT is disabled. When V

4.80V, the Fault condition clears, and OUT is enabled.

falls below 4.65V. When a

REF

Solve for the current sense resistor, R , using Equation 15.

exceeds

REF

= 295mΩ

Determine the amount of voltage, V , that must be added to

the current feedback signal using Equation 12.

Ground Plane Requirements

Careful layout is essential for satisfactory operation of the

device. A good ground plane must be employed. A unique

section of the ground plane must be designated for high di/dt

currents associated with the output stage. V

bypassed directly to GND with good high frequency

capacitors.

V = 92.4mV

Using Equation 17, solve for the summing resistor, R , from

CT to CS.

should be

R = 2.67kΩ

Determine the new value of R

(R’ ) using Equation 18.

References

R’

= 350mΩ

[1] Ridley, R., “A New Continuous-Time Model for Current

Mode Control”, IEEE Transactions on Power

Electronics, Vol. 6, No. 2, April 1991.

Additional slope compensation may be considered for

design margin. The previous discussion determines the

minimum external ramp that is required. The buffer transistor

used to create the external ramp from R C should have a

sufficiently high gain (>200) so as to minimize the required

base current. Whatever base current is required reduces the

charging current into R C and will reduce the oscillator

frequency.

FN6792.0

September 29, 2008

ISL8840AMBEPZ, ISL8841AMBEPZ, ISL8842AMBEPZ, ISL8843AMBEPZ, ISL8844AMBEPZ, ISL8845AMBEPZ

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

B M

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

0.0532

0.0040

0.013

0.0688

0.0098

0.020

SEATING PLANE

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-A-

h x 45°

-C-

0.050 BSC

1.27 BSC

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.10(0.004)

0.25(0.010) M

A M B S

NOTES:

0°

8°

0°

8°

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6792.0

September 29, 2008

ISL8840AMBEPZ [RENESAS]

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