ISL8841AABZ_技术文档

ISL8840A, ISL8841A, ISL8842A,

ISL8843A, ISL8844A, ISL8845A

®

Data Sheet

April 18, 2007

FN6320.3

High Performance Industry Standard

Single-Ended Current Mode PWM

Controller

Features

• 1A MOSFET gate driver

• 90μA start-up current, 125μA maximum

The ISL884xA is a high performance drop-in replacement for

the popular 28C4x and 18C4x PWM controllers suitable for a

wide range of power conversion applications including

boost, flyback, and isolated output configurations. Its fast

signal propagation and output switching characteristics

make this an ideal product for existing and new designs.

• 35ns propagation delay current sense to output

• Fast transient response with peak current mode control

• 30V operation

• Adjustable switching frequency to 2MHz

• 20ns rise and fall times with 1nF output load

Features include 30V operation, low operating current, 90μA

start-up current, adjustable operating frequency to 2MHz,

and high peak current drive capability with 20ns rise and fall

times.

• Trimmed timing capacitor discharge current for accurate

deadtime/maximum duty cycle control

• 1.5MHz bandwidth error amplifier

PART NUMBER

ISL8840A

ISL8841A

ISL8842A

ISL8843A

ISL8844A

ISL8845A

RISING UVLO

7.0

MAX. DUTY CYCLE

• Tight tolerance voltage reference over line, load and

temperature

100%

50%

7.0

• ±3% current limit threshold

14.4V

8.4V

100%

50%

• Pb-free plus anneal available and ELV, WEEE, RoHS

Compliant

14.4V

8.4V

Applications

50%

• Telecom and datacom power

• Wireless base station power

• File server power

Pinout

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

(8 LD SOIC, MSOP)

• Industrial power systems

• PC power supplies

TOP VIEW

COMP

FB

1

2

3

4

8

7

VREF

VDD

OUT

GND

• Isolated buck and flyback regulators

• Boost regulators

CS

6

5

RTCT

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Ordering Information (Continued)

Ordering Information

PART

NUMBER*

PART

TEMP.

PACKAGE PKG.

PART

NUMBER*

PART

TEMP.

PACKAGE PKG.

MARKING RANGE (°C) (Pb-free) DWG. #

ISL8843AMBZ 8843 AMBZ

(See Note)

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

ISL8840AABZ 8840 AABZ

(See Note)

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

-55 to +125 8 Ld SOIC M8.15

-55 to +125 8 Ld MSOP M8.118

-40 to +105 8 Ld SOIC M8.15

-40 to +105 8 Ld MSOP M8.118

ISL8843AMUZ 43AMZ

(See Note)

ISL8840AAUZ 40AAZ

(See Note)

ISL8844AABZ 8844 AABZ

(See Note)

ISL8840AMBZ 8840 AMBZ

(See Note)

ISL8844AAUZ 44AAZ

(See Note)

ISL8840AMUZ 40AMZ

(See Note)

ISL8844AMBZ 8844 AMBZ

(See Note)

ISL8841AABZ 8841 AABZ

(See Note)

ISL8844AMUZ 44AMZ

(See Note)

ISL8841AAUZ 41AAZ

(See Note)

ISL8845AABZ 8845 AABZ

(See Note)

ISL8841AMBZ 8841 AMBZ

(See Note)

ISL8845AAUZ 45AAZ

(See Note)

ISL8841AMUZ 41AMZ

(See Note)

ISL8845AMBZ 8845 AMBZ

(See Note)

ISL8842AABZ 8842 AABZ

(See Note)

ISL8845AMUZ 45AMZ

(See Note)

ISL8842AAUZ 42AAZ

(See Note)

*Add “-T” suffix for tape and reel.

ISL8842AMBZ 8842 AMBZ

(See Note)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free

material sets; molding compounds/die attach materials and 100%

matte tin plate termination finish, which are RoHS compliant and

compatible with both SnPb and Pb-free soldering operations. Intersil

Pb-free products are MSL classified at Pb-free peak reflow

temperatures that meet or exceed the Pb-free requirements of

IPC/JEDEC J STD-020.

ISL8842AMUZ 42AMZ

(See Note)

ISL8843AABZ 8843 AABZ

(See Note)

ISL8843AAUZ 43AAZ

(See Note)

FN6320.3

April 18, 2007

2

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . GND -0.3V to +30V

Thermal Resistance (Typical, Note 1)

θ

(°C/W)

JA

DD

OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to V

+ 0.3V

DD

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . .-55°C to +150°C

Maximum Storage Temperature Range. . . . . . . . . .-65°C to +150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C

(SOIC, MSOP - Lead Tips Only)

100

130

Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 6.0V

Peak GATE Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1A

ESD Classification

Human Body Model (Per JESD22-A114C.01) . . . . . . . . . . .2000V

Machine Model (Per EIA/JESD22-A115-A) . . . . . . . . . . . . . .200V

Charged Device Model (Per JESD22-C191-A) . . . . . . . . . .1000V

Operating Conditions

Temperature Range

ISL884xAAxZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C

ISL884xAMxZ. . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Supply Voltage Range (Typical, Note 2)

ISL884xA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 30V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Constantly operated at +150°C may shorten the life of the part.

NOTES:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Technical Brief TB379 for details.

JA

2. All voltages are with respect to GND.

Electrical Specifications ISL884xAA - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic onpage 3 and page 4. V

= 15V, R = 10kΩ, C = 3.3nF, T = -40 to +105°C

DD

T

A

(Note 3). Typical values are at T = +25°C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

UNDERVOLTAGE LOCKOUT

START Threshold (ISL8840A, ISL8841A)

START Threshold (ISL8843A, ISL8845A)

START Threshold (ISL8842A, ISL8844A)

STOP Threshold (ISL8840A, ISL8841A)

STOP Threshold (ISL8843A, ISL8845A)

STOP Threshold (ISL8842A, ISL8844A)

Hysteresis (ISL8840A, ISL8841A)

6.5

7.0

8.4

7.5

9.0

15.3

6.9

8.0

9.6

-

V

8.0

(Note 6)

13.3

14.3

6.6

7.6

8.8

0.4

0.8

5.4

90

V

6.1

V

7.3

V

8.0

V

-

V

Hysteresis (ISL8843A, ISL8845A)

-

V

Hysteresis (ISL8842A, ISL8844A)

-

V

Startup Current, I

DD

V

< START Threshold

125

4.0

5.5

μA

mA

DD

Operating Current, I

(Note 4)

2.9

4.75

DD

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy

Includes 1nF GATE loading

D

Over line (V

= 12V to 30V), load,

4.925

5.000

5.050

V

DD

temperature

Long Term Stability

Current Limit, Sourcing

Current Limit, Sinking

CURRENT SENSE

Input Bias Current

CS Offset Voltage

T

= +125°C, 1000 hours (Note 5)

-

-20

5

-

mV

mA

A

-

V

= 1V

-1.0

95

-

1.0

105

1.30

μA

mV

V

CS

= 0V (Note 5)

100

1.15

COMP to PWM Comparator Offset Voltage

0.80

FN6320.3

April 18, 2007

6

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Electrical Specifications ISL884xAA - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic onpage 3 and page 4. V

= 15V, R = 10kΩ, C = 3.3nF, T = -40 to +105°C

DD

T

A

(Note 3). Typical values are at T = +25°C (Continued)

A

PARAMETER

Input Signal, Maximum

Gain, A = ΔV /ΔV

TEST CONDITIONS

MIN

0.97

2.5

-

TYP

MAX

1.03

3.5

UNITS

V

1.00

3.0

35

0 < V < 910mV, V = 0V

CS FB

V/V

ns

CS

COMP

CS

CS to OUT Delay

55

ERROR AMPLIFIER

Open Loop Voltage Gain

Unity Gain Bandwidth

Reference Voltage

FB Input Bias Current

COMP Sink Current

COMP Source Current

COMP VOH

(Note 5)

60

1.0

90

-

dB

MHz

V

1.5

-

V

= V

2.475

-1.0

1.0

2.500

2.530

FB

COMP

= 0V

-0.2

1.0

μA

mA

V

= 1.5V, V = 2.7V

FB

-

COMP

= 1.5V, V = 2.3V

FB

-0.4

4.80

0.4

-

VREF

1.0

-

= 2.3V

-

FB

COMP VOL

= 2.7V

-

V

PSRR

Frequency = 120Hz, V

30V (Note 5)

= 12V to

60

80

dB

DD

OSCILLATOR

Frequency Accuracy

Initial, T = +25°C

48

51

0.2

-

53

1.0

5

kHz

%

A

Frequency Variation with V

Temperature Stability

T = +25°C, (f

A

- f

)/f

-

DD

30V 10V 30V

(Note 5)

-

%

Amplitude, Peak to Peak

Static Test

RTCT = 2.0V

1.75

1.0

7.8

-

V

RTCT Discharge Voltage (Valley Voltage)

-

V

Discharge Current

OUTPUT

6.5

8.5

mA

Gate VOH

V

to OUT, I

OUT

= -200mA

= 200mA

-

1.0

20

-

2.0

-

V

DD

Gate VOL

OUT to GND, I

OUT

Peak Output Current

Rise Time

C

= 1nF (Note 5)

A

OUT

40

1.2

ns

V

Fall Time

GATE VOL UVLO Clamp Voltage

PWM

VDD = 5V, I = 1mA

LOAD

Maximum Duty Cycle

(ISL8840A, ISL8842A, ISL8843A)

COMP = VREF

COMP = GND

94.0

47.0

-

96.0

48.0

-

%

Maximum Duty Cycle

(ISL8841A, ISL8844A, ISL8845A)

Minimum Duty Cycle

NOTES:

0

3. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.

4. This is the V current consumed when the device is active but not switching. Does not include gate drive current.

DD

5. These parameters, although guaranteed, are not 100% tested in production.

6. Adjust V

above the start threshold and then lower to 15V.

DD

FN6320.3

April 18, 2007

7

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Electrical Specifications ISL884xAM - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V

= 15V, RT = 10kΩ, CT = 3.3nF, T = -55 to +125°C (Note 7), Typical values

A

DD

are at T = +25°C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

UNDERVOLTAGE LOCKOUT

START Threshold (ISL8840A, ISL8841A)

START Threshold (ISL8843A, ISL8845A)

START Threshold (ISL8842A, ISL8844A)

STOP Threshold (ISL8840A, ISL8841A)

STOP Threshold (ISL8843A, ISL8845A)

STOP Threshold (ISL8842A, ISL8844A)

Hysteresis (ISL8840A, ISL8841A)

6.5

7.0

8.4

14.3

6.6

7.6

8.8

0.4

0.8

5.4

90

7.5

9.0

15.3

6.9

8.0

9.6

-

V

8.0

(Note 10)

13.3

V

6.1

V

7.3

V

8.0

V

-

V

Hysteresis (ISL8843A, ISL8845A)

-

V

Hysteresis (ISL8842A, ISL8844A)

-

V

Startup Current, I

DD

V

< START Threshold

125

4.0

5.5

μA

mA

DD

Operating Current, I

(Note 8)

2.9

4.75

DD

Operating Supply Current, I

REFERENCE VOLTAGE

Overall Accuracy

Includes 1nF GATE loading

D

Over line (V

= 12V to 30V), load,

4.900

5.000

5.050

V

DD

temperature

Long Term Stability

Current Limit, Sourcing

Current Limit, Sinking

CURRENT SENSE

Input Bias Current

CS Offset Voltage

T

= +125°C, 1000 hours (Note 9)

-

-20

5

-

mV

mA

A

-

V

= 1V

-1.0

95

-

1.0

105

1.30

1.03

3.5

μA

mV

V

CS

= 0V (Note 9)

100

1.15

1.00

3.0

COMP to PWM Comparator Offset Voltage

Input Signal, Maximum

0.80

0.97

2.5

-

V

Gain, A

= ΔV

/ΔV

0 < V < 910mV, V = 0V

CS FB

V/V

ns

CS

COMP

CS

CS to OUT Delay

35

60

ERROR AMPLIFIER

Open Loop Voltage Gain

Unity Gain Bandwidth

Reference Voltage

FB Input Bias Current

COMP Sink Current

COMP Source Current

COMP VOH

(Note 9)

60

1.0

90

-

dB

MHz

V

1.5

-

V

= V

2.460

-1.0

1.0

2.500

2.535

FB

COMP

= 0V

-0.2

1.0

μA

mA

V

= 1.5V, V = 2.7V

FB

-

COMP

= 1.5V, V = 2.3V

FB

-0.4

4.80

0.4

-

VREF

1.0

-

= 2.3V

-

FB

COMP VOL

= 2.7V

-

V

PSRR

Frequency = 120Hz, V

30V (Note 9)

= 12V to

60

80

dB

DD

OSCILLATOR

Frequency Accuracy

Initial, T = +25°C

48

-

51

0.2

-

53

1.0

5

kHz

%

A

Frequency Variation with V

Temperature Stability

T

= +25°C, (f

- f

)/f

DD

A

30V 10V 30V

(Note 9)

-

%

FN6320.3

April 18, 2007

8

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Electrical Specifications ISL884xAM - Recommended operating conditions unless otherwise noted. Refer to Block Diagram and

Typical Application schematic. V

= 15V, RT = 10kΩ, CT = 3.3nF, T = -55 to +125°C (Note 7), Typical values

A

DD

are at T = +25°C (Continued)

A

PARAMETER

Amplitude, Peak to Peak

TEST CONDITIONS

Static Test

MIN

TYP

1.75

1.0

MAX

UNITS

-

V

RTCT Discharge Voltage (Valley Voltage)

Static Test

Discharge Current

OUTPUT

RTCT = 2.0V

6.2

8.0

8.5

mA

Gate VOH

V

- OUT, I

OUT

= -200mA

= 200mA

-

1.0

20

-

2.0

-

V

DD

Gate VOL

OUT - GND, I

OUT

Peak Output Current

Rise Time

C

= 1nF (Note 9)

A

OUT

40

1.2

ns

V

Fall Time

GATE VOL UVLO Clamp Voltage

PWM

V

= 5V, I = 1mA

LOAD

DD

Maximum Duty Cycle

(ISL8840A, ISL8842A, ISL8843A)

COMP = VREF

COMP = GND

94.0

47.0

-

96.0

48.0

-

%

Maximum Duty Cycle

(ISL8841A, ISL8844A, ISL8845A)

Minimum Duty Cycle

NOTES:

0

7. Specifications at -55°C and +125°C are guaranteed by +25°C test with margin limits.

8. This is the V current consumed when the device is active but not switching. Does not include gate drive current.

DD

9. These parameters, although guaranteed, are not 100% tested in production.

10. Adjust V above the start threshold and then lower to 15V.

DD

Typical Performance Curves

1.01

1.001

1.000

0.999

1.00

0.99

0.98

0.998

0.997

0.996

0.995

-60 -40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0

20 40 60 80 100 120 140

TEMPERATURE (°C)

FIGURE 1. FREQUENCY vs TEMPERATURE

FIGURE 2. REFERENCE VOLTAGE vs TEMPERATURE

FN6320.3

April 18, 2007

9

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Typical Performance Curves (Continued)

3

1.001

1.000

0.998

0.997

0.996

10

100pF

100

10

1

220pF

330pF

470pF

1.0nF

2.2nF

3.3nF

4.7nF

6.8nF

-60 -40 -20

0

20 40 60 80 100 120 140

1

10

RT (kΩ)

100

TEMPERATURE (°C)

FIGURE 3. EA REFERENCE vs TEMPERATURE

FIGURE 4. RESISTANCE FOR CT CAPACITOR VALUES GIVEN

OUT - This is the drive output to the power switching device.

It is a high current output capable of driving the gate of a

power MOSFET with peak currents of 1.0A. This GATE

Pin Descriptions

RTCT - This is the oscillator timing control pin. The

operational frequency and maximum duty cycle are set by

connecting a resistor, RT, between VREF and this pin and a

timing capacitor, CT, from this pin to GND. The oscillator

produces a sawtooth waveform with a programmable

output is actively held low when V

threshold.

is below the UVLO

DD

V

- V is the power connection for the device. The total

DD

frequency range up to 2.0MHz. The charge time, t , the

discharge time, t , the switching frequency, f, and the

D

supply current will depend on the load applied to OUT. Total

current is the sum of the operating current and the

C

I

DD

maximum duty cycle, Dmax, can be approximated from the

following equations:

average output current. Knowing the operating frequency, f,

and the MOSFET gate charge, Qg, the average output

current can be calculated from:

(EQ. 1)

(EQ. 2)

t

≈ 0.533 ⋅ RT ⋅ CT

C

D

(EQ. 5)

I

= Qg × f

OUT

0.008 ⋅ RT – 3.83

⎛

⎝

⎞

⎠

---------------------------------------------

≈ –RT ⋅ CT ⋅ In

To optimize noise immunity, bypass V

to GND with a

and GND pins as

0.008 ⋅ RT – 1.71

DD

ceramic capacitor as close to the V

possible.

DD

f = 1 ⁄ (t + t

)

(EQ. 3)

(EQ. 4)

C

D

VREF - The 5.00V reference voltage output. +1.0/-1.5%

tolerance over line, load and operating temperature. Bypass

to GND with a 0.1μF to 3.3μF capacitor to filter this output as

needed.

D = t ⋅ f

C

The formulae have increased error at higher frequencies due

to propagation delays. Figure 4 may be used as a guideline

in selecting the capacitor and resistor values required for a

given frequency.

Functional Description

Features

COMP - COMP is the output of the error amplifier and the

input of the PWM comparator. The control loop frequency

compensation network is connected between the COMP and

FB pins.

The ISL884xA current mode PWM makes an ideal choice for

low-cost flyback and forward topology applications. With its

greatly improved performance over industry standard parts,

it is the obvious choice for new designs or existing designs

which require updating.

FB - The output voltage feedback is connected to the

inverting input of the error amplifier through this pin. The

non-inverting input of the error amplifier is internally tied to a

reference voltage.

Oscillator

The ISL884xA has a sawtooth oscillator with a

programmable frequency range to 2MHz, which can be

programmed with a resistor from VREF and a capacitor to

GND on the RTCT pin. (Please refer to Figure 4 for the

resistor and capacitance required for a given frequency.)

CS - This is the current sense input to the PWM comparator.

The range of the input signal is nominally 0V to 1.0V and has

an internal offset of 100mV.

GND - GND is the power and small signal reference ground

for all functions.

FN6320.3

April 18, 2007

10

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

From the small signal current-mode model [1] it can be

Soft-Start Operation

shown that the naturally-sampled modulator gain, Fm,

without slope compensation, is in Equation 6.

Soft-start must be implemented externally. One method,

illustrated below, clamps the voltage on COMP.

1

-------------------

Fm =

(EQ. 6)

SnTsw

where Sn is the slope of the sawtooth signal and Tsw is the

duration of the half-cycle. When an external ramp is added,

the modulator gain becomes:

VREF

D1

C1

R1

COMP

GND

1

(EQ. 7)

--------------------------------------

---------------------------

Fm =

=

Q1

(Sn + Se)Tsw

m SnTsw

c

where Se is slope of the external ramp and

Se

-------

= 1 +

m

(EQ. 8)

c

Sn

FIGURE 5. SOFT-START

The criteria for determining the correct amount of external

ramp can be determined by appropriately setting the

damping factor of the double-pole located at the switching

frequency. The double-pole will be critically damped if the

Q-factor is set to 1, over-damped for Q < 1, and

under-damped for Q > 1. An under-damped condition may

result in current loop instability.

The COMP pin is clamped to the voltage on capacitor C1

plus a base-emitter junction by transistor Q1. C1 is charged

from VREF through resistor R1 and the base current of Q1.

At power-up C1 is fully discharged, COMP is at ~0.7V, and

the duty cycle is zero. As C1 charges, the voltage on COMP

increases, and the duty cycle increases in proportion to the

voltage on C1. When COMP reaches the steady state

operating point, the control loop takes over and soft start is

complete. C1 continues to charge up to VREF and no longer

affects COMP. During power down, diode D1 quickly

discharges C1 so that the soft start circuit is properly

initialized prior to the next power on sequence.

1

(EQ. 9)

-------------------------------------------------

Q =

π(m (1 – D) – 0.5)

c

where D is the percent of on time during a switching cycle.

Setting Q = 1 and solving for Se yields

1

π

1

⎛⎛

⎝⎝

⎞

– 1

(EQ. 10)

--

-------------

S

= S

+ 0.5

e

n

⎠

1 – D

Gate Drive

The ISL884xA is capable of sourcing and sinking 1A peak

current. To limit the peak current through the IC, an optional

external resistor may be placed between the totem-pole

output of the IC (OUT pin) and the gate of the MOSFET. This

small series resistor also damps any oscillations caused by

the resonant tank of the parasitic inductances in the traces of

the board and the FET’s input capacitance.

Since Sn and Se are the on time slopes of the current ramp

and the external ramp, respectively, they can be multiplied

by t

ON

to obtain the voltage change that occurs during t

.

ON

1

π

1

⎛⎛

⎝⎝

⎞

– 1

--

-------------

V

= V

+ 0.5

(EQ. 11)

e

n

⎠

1 – D

where Vn is the change in the current feedback signal (ΔI)

during the on time and Ve is the voltage that must be added

by the external ramp.

Slope Compensation

For applications where the maximum duty cycle is less than

50%, slope compensation may be used to improve noise

immunity, particularly at lighter loads. The amount of slope

compensation required for noise immunity is determined

empirically, but is generally about 10% of the full scale

current feedback signal. For applications where the duty

cycle is greater than 50%, slope compensation is required to

prevent instability.

For a flyback converter, Vn can be solved for in terms of

input voltage, current transducer components, and primary

inductance, yielding

D ⋅ T

⋅ V ⋅ R

IN CS

1

π

1

SW

⎛⎛

⎞

– 1

---------------------------------------------------- --

-------------

V

=

+ 0.5

V

e

⎝⎝

⎠

L

1 – D

p

(EQ. 12)

Slope compensation may be accomplished by summing an

external ramp with the current feedback signal or by

subtracting the external ramp from the voltage feedback

error signal. Adding the external ramp to the current

feedback signal is the more popular method.

where R

CS

is the current sense resistor, f is the switching

sw

frequency, L is the primary inductance, V is the minimum

input voltage, and D is the maximum duty cycle.

p

IN

FN6320.3

April 18, 2007

11

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

The current sense signal at the end of the ON time for CCM

operation is:

(1 – D) ⋅ V ⋅ f

sw

N

⋅ R

CS

N

P

⎛

⎜

⎝

⎞

⎟

⎠

O

S

------------------------

-------------------------------------------

V

=

I

+

O

V

(EQ. 13)

CS

2L

s

VREF

R9

R6

where V

is the voltage across the current sense resistor,

L is the secondary winding inductance, and I is the output

CS

s

O

current at current limit. Equation 13 assumes the voltage

drop across the output rectifier is negligible.

RTCT

C4

Since the peak current limit threshold is 1.00V, the total

current feedback signal plus the external ramp voltage must

sum to this value when the output load is at the current limit

threshold.

FIGURE 6. SLOPE COMPENSATION

V

+ V

= 1

CS

(EQ. 14)

Assuming the designer has selected values for the RC filter

e

(R and C ) placed on the CS pin, the value of R required

6

4

9

to add the appropriate external ramp can be found by

superposition.

Substituting Equations 12 and 13 into Equation 14 and

solving for R yields

CS

2.05D ⋅ R

6

---------------------------

(EQ. 16)

1

V

=

V

e

----------------------------------------------------------------------------------------------------------------------------------------------------

=

R

+ R

9

CS

6

1

--

⎛

+ 0.5

⎞

⎟

D ⋅ f ⋅ V

N

(1 – D) ⋅ V ⋅ f

O sw

⎛

⎞

⎟

⎠

π

sw

IN

s

⎜

------------------------------- -----------------

------

-------------------------------------------

⋅

–1

+

⋅ I

+

⎜

O

⎜

⎝

⎟

⎠

L

1 – D

N

p

2L

s

⎝

p

The factor of 2.05 in Equation 16 arises from the peak

amplitude of the sawtooth waveform on RTCT minus a

base-emitter junction drop. That voltage multiplied by the

maximum duty cycle is the voltage source for the slope

(EQ. 15)

Adding slope compensation is accomplished in the

compensation. Rearranging to solve for R yields:

9

ISL884xA using an external buffer transistor and the RTCT

signal. A typical application sums the buffered RTCT signal

with the current sense feedback and applies the result to the

CS pin as shown in Figure 6.

(2.05D – V ) ⋅ R

e

6

---------------------------------------------

R

=

Ω

(EQ. 17)

9

V

e

The value of R

CS

determined in Equation 15 must be

rescaled so that the current sense signal presented at the

CS pin is that predicted by Equation 13. The divider created

by R and R makes this necessary.

6

9

R

+ R

6

9

--------------------

R′

=

⋅ R

(EQ. 18)

CS

R

9

FN6320.3

April 18, 2007

12

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Example:

Fault Conditions

A Fault condition occurs if VREF falls below 4.65V. When a

Fault is detected OUT is disabled. When VREF exceeds

4.80V, the Fault condition clears, and OUT is enabled.

V

= 12V

= 48V

IN

O

L = 800μH

s

Ground Plane Requirements

Ns/Np = 10

Careful layout is essential for satisfactory operation of the

device. A good ground plane must be employed. A unique

section of the ground plane must be designated for high di/dt

Lp = 8.0μH

I

= 200mA

currents associated with the output stage. V

should be

O

DD

bypassed directly to GND with good high frequency

capacitors.

Switching Frequency, f = 200kHz

sw

Duty Cycle, D = 28.6%

References

R = 499Ω

6

[1] Ridley, R., “A New Continuous-Time Model for Current

Mode Control”, IEEE Transactions on Power

Electronics, Vol. 6, No. 2, April 1991.

Solve for the current sense resistor, R , using Equation 15.

CS

R

= 295mΩ

CS

Determine the amount of voltage, Ve, that must be added to

the current feedback signal using Equation 12.

Ve = 92.4mV

Using Equation 17, solve for the summing resistor, R , from

9

CT to CS.

R = 2.67kΩ

9

Determine the new value of R

(R’ ) using Equation 18.

CS

R’

CS

= 350mΩ

Additional slope compensation may be considered for

design margin. The above discussion determines the

minimum external ramp that is required. The buffer transistor

used to create the external ramp from RTCT should have a

sufficiently high gain (>200) so as to minimize the required

base current. Whatever base current is required reduces the

charging current into RTCT and will reduce the oscillator

frequency.

FN6320.3

April 18, 2007

13

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

N

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

A

A1

B

C

D

E

e

0.0532

0.0040

0.013

0.0688

0.0098

0.020

-

1

2

3

L

9

SEATING PLANE

A

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-

-A-

3

h x 45°

D

4

-C-

0.050 BSC

1.27 BSC

-

α

H

h

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

8

7

NOTES:

0°

8°

0°

8°

-

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN6320.3

April 18, 2007

14

ISL8840A, ISL8841A, ISL8842A, ISL8843A, ISL8844A, ISL8845A

Mini Small Outline Plastic Packages (MSOP)

N

M8.118 (JEDEC MO-187AA)

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.25

0.09

2.95

MAX

1.10

0.15

0.95

0.36

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.010

0.004

0.116

0.043

0.006

0.037

0.014

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.026 BSC

0.65 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

0.95 REF

-

0.10 (0.004)

-A-

C

b

8

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

0

-

o

5

15

5

15

-

a

SIDE VIEW

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 2 01/03

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (0.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

to be determined at Datum plane

-A -

10. Datums

and

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6320.3

April 18, 2007

15


型号：	ISL8841AABZ
厂家：	Intersil
描述：	High Performance Industry Standard Single-Ended Current Mode PWM Controller 高性能工业标准的单端电流模式PWM控制器控制器
文件：	总15页 (文件大小：302K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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