ISL89160FBEBZ_技术文档

High Speed, Dual Channel, 6A, 4.5 to 16V , Power

OUT

MOSFET Driver

ISL89160, ISL89161, ISL89162

The ISL89160, ISL89162, and ISL89162 are high-speed, 6A,

dual channel MOSFET drivers. These parts are identical to the

ISL89163, ISL89164, ISL89165 drivers but without the enable

inputs for each channel.

Features

• Dual output, 6A peak current (sink and source)

• Typical ON-resistance <1Ω

• Specified Miller plateau drive currents

• Very low thermal impedance (θ = 3°C/W)

JC

Two input logic thresholds are available: 3.3V (CMOS and TTL

compatible) and 5.0V (CMOS).

• 3.3V and 5V logic inputs with hysteresis are VDD tolerant

• Precision threshold inputs for time delays with external RC

components

Precision thresholds on all logic inputs allow the use of external

RC circuits to generate accurate and stable time delays on both

inputs, INA and INB. This capability is very useful for dead time

control.

• ~ 20ns rise and fall time driving a 10nF load.

• Low operating bias currents

At high switching frequencies, these MOSFET drivers use very

little bias current. Separate, non-overlapping drive circuits are

used to drive each CMOS output FET to prevent shoot-thru

currents in the output stage.

• Pb-Free (RoHs Compliant)

Applications

• Synchronous Rectifier (SR) Driver

• Switch mode power supplies

• Motor Drives, Class D amplifiers, UPS, Inverters

• Pulse Transformer Driver

The undervoltage lock-out (UV) insures that driver outputs remain

off (low) until VDD is sufficiently high for correct logic control.

This prevents unexpected behavior when V is being turned on

DD

or turned off.

• Clock/Line Driver

3.5

V_DD

3.0

POSITIVE THRESHOLD

2.5

2.0

NC

INA

GND

1

2

3

4

8

7

6

5

OUTA

EPAD

1.5

NEGATIVE THRESHOLD

INB

OUTB

4.7µF

1.0

0.5

0.0

-40 -25 10

5

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. TEMPERATURE STABLE LOGIC THRESHOLDS

January 20, 2011

FN7719.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL89160, ISL89161, ISL89162

Block Diagram

V_DD

Separate FET drives, with

non-overlapping outputs,

prevent shoot-thru

For options A and B, the UV

comparator holds off the

For clarity, only one

channel is shown

outputs until V_DD~> 3.3V_DC

.

currents in the output

CMOS FETs resulting with

very low high frequency

operating currents.

ISL89160

INx

OUTx

10k

ISL89161,

ISL89162

EPAD

GND

For proper thermal and electrical

performance, the EPAD must be

connected to the PCB ground plane.

Pin Configurations

Pin Descriptions

ISL89160FR, ISL89160FB

(8 LD TDFN, EPSOIC)

TOP VIEW

ISL89161FR, ISL89161FB

(8 LD TDFN, EPSOIC)

TOP VIEW

NUMBER

SYMBOL

NC

DESCRIPTION

1, 8

No Connect. This pin may be left open or

connected to 0V or VDD

NC

INA

NC

8

7

6

5

1

2

3

4

NC

/INA

GND

/INB

NC

8

7

6

5

1

2

3

4

OUTA

VDD

OUTB

OUTA

VDD

OUTB

2

3

4

5

6

7

INA or /INA Channel A input, 0V to VDD

GND Power Ground, 0V

INB or /INB Channel B enable, 0V to VDD

GND

INB

OUTB

VDD

Channel B output

Power input, 4.5V to 16V

Channel A output, 0V to VDD

Power Ground, 0V

ISL89162FR, ISL89162FB

(8 LD TDFN, EPSOIC)

TOP VIEW

OUTA

EPAD

NC

/INA

GND

INB

NC

8

7

6

5

1

2

3

4

OUTA

VDD

OUTB

FN7719.1

January 20, 2011

2

ISL89160, ISL89161, ISL89162

Ordering Information

PART NUMBER

TEMP RANGE

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 2, 3)

PART MARKING

160A

(°C)

INPUT CONFIGURATION

non-inverting

INPUT LOGIC

ISL89160FRTAZ

ISL89161FRTAZ

ISL89162FRTAZ

ISL89160FBEAZ

ISL89161FBEAZ

ISL89162FBEAZ

ISL89160FRTBZ

ISL89161FRTBZ

ISL89162FRTBZ

ISL89160FBEBZ

ISL89161FBEBZ

ISL89162FBEBZ

NOTES:

-40 to +125

8 Ld 3x3 TDFN

8 Ld EPSOIC

8 Ld 3x3 TDFN

8 Ld EPSOIC

L8.3x3I

M8.15D

L8.3x3I

M8.15D

161A

inverting

162A

inverting + non-inverting

non-inverting

3.3VDC

89160 FBEAZ

89161 FBEAZ

89162 FBEAZ

160B

inverting

inverting + non-inverting

non-inverting

161B

inverting

162B

inverting + non-inverting

non-inverting

5.0VDC

89160 FBEBZ

89161 FBEBZ

89162 FBEBZ

inverting

inverting + non-inverting

1. Add “-T*”, suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL89160, ISL89161, ISL89162. For more information on MSL, please

see Technical Brief TB363.

FN7719.1

January 20, 2011

3

ISL89160, ISL89161, ISL89162

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to 18V

Logic Inputs (INA, INB) . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V + 0.3V

DD

Thermal Resistance (Typical)

8 Ld TDFN Package (Notes 4, 5). . . . . . . . .

8 Ld EPSOIC Package (Notes 4, 5). . . . . . .

θ

(°C/W)

44

42

θ

(°C/W)

JC

DD

JA

3

Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to V + 0.3V

DD

Average Output Current (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150mA

Max Power Dissipation at +25°C in Free Air . . . . . . . . . . . . . . . . . . . . . 2.27W

Max Power Dissipation at +25°C with Copper Plane . . . . . . . . . . . . .33.3W

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

ESD Ratings

Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . . . 2000V

Machine Model Class B (Tested per JESD22-A115-A) . . . . . . . . . . . . 200V

Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V

Latch-Up

Maximum Recommended Operating

Conditions

(Tested per JESD-78B; Class 2, Level A)

Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500 mA

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Supply Voltage, V Relative to GND. . . . . . . . . . . . . . . . . . . . . .4.5V to 16V

DD

Logic Inputs (INA, INB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V

Outputs (OUTA, OUTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V

DD

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379 for details.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output

currents of this driver are self limiting by transconductance or r

and do not required any external components to minimize the peaks. If the

DS(ON)

output is driving a non-capacitive load, such as an LED, maximum output current must be limited by external means to less than the specified

absolute maximum.

DC Electrical Specifications

V

= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits

DD

apply over the operating junction temperature range, -40°C to +125°C.

T = +25°C

J

T = -40°C to +125°C

J

MIN

MAX

PARAMETERS

POWER SUPPLY

Voltage Range

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

(Note 7)

UNITS

V

-

4.5

16

V

DD

INx = GND

5

-

mA

V

Quiescent Current

I

DD

INA = INB = 1MHz, square wave

25

UNDERVOLTAGE

Undervoltage Lock-out

-

3.3

-

V

DD

V

INA = INB = True (Note 10)

V

UV

(Note 9)

~25

Hysteresis

mV

INPUTs (Note 11)

Input Range for INA, INB

V

-

GND

1.12

1.70

1.98

3.00

V

IN

DD

Option A, nominally 37% x 3.3V

Option B, nominally 37% x 5.0V

Option A, nominally 63% x 3.3V

Option B, nominally 63% x 5.0V

1.22

1.85

2.08

3.15

1.32

2.00

2.18

3.30

Logic 0 Threshold

for INA, INB (Note 9)

V

IL

Logic 1 Threshold

for INA, INB (Note 9)

V

C

IH

Input Capacitance of

INA, INB (Note 8)

-

2

-

pF

IN

FN7719.1

January 20, 2011

4

ISL89160, ISL89161, ISL89162

DC Electrical Specifications

V

= 12V, GND = 0V, No load on OUTA or OUTB, unless otherwise specified. Boldface limits

DD

apply over the operating junction temperature range, -40°C to +125°C. (Continued)

T = +25°C

J

T = -40°C to +125°C

J

MIN

MAX

PARAMETERS

Input Bias Current

SYMBOL

TEST CONDITIONS

MIN

-

TYP

-

MAX

-

(Note 7)

UNITS

µA

I

GND<V <V

IN DD

-10

+10

IN

for INA, INB

OUTPUTS

High Level Output Voltage

V

-

V

- 0.1

V

DD

V

OHA OHB

DD

V

OLA

OLB

Low Level Output Voltage

GND

GND + 0.1

Peak Output Source Current

Peak Output Sink Current

NOTES:

I

V

(initial) = 0V, C

LOAD

= 10nF

-

-6

-

A

O

(initial) =12V, C

LOAD

+6

O

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic

capacitance.

9. A 200µs delay further inhibits the release of the output state when the UV positive going threshold is crossed.

10. The true state of a specific part number is defined by the input logic symbol.

11. The true state input voltage for the non-inverted inputs is greater than the Logic 1 threshold voltage. The true state input voltage for the inverted

inputs is less than the logic 0 threshold voltage.

AC Electrical Specifications

V

= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits

DD

apply over the operating junction temperature range, -40°C to +125°C.

T = -40°C

J

to +125°C

T = +25°C

J

TEST CONDITIONS

/NOTES

PARAMETERS

SYMBOL

MIN

-

TYP

20

MAX

-

MIN

MAX

40

UNITS

ns

Output Rise Time (see Figure 4)

t

C

= 10nF,

-

R

LOAD

10% to 90%

Output Fall Time (see Figure 4)

t

C

= 10nF,

-

20

25

-

40

50

ns

F

LOAD

90% to 10%

Output Rising Edge Propagation Delay for

Non-Inverting Inputs (see Figure 3)

t

No load

RDLYn

Output Rising Edge Propagation Delay with Inverting

Inputs (see Figure 3)

t

No load

RDLYi

FDLYn

Output Falling Edge Propagation Delay with

Non-Inverting Inputs (see Figure 3)

Output Falling Edge Propagation Delay with Inverting

Inputs (see Figure 3)

t

FDLYi

Rising Propagation Matching (see Figure 3)

Falling Propagation Matching (see Figure 3)

t

-

<1ns

6

-

ns

A

RM

t

FM

Miller Plateau Sink Current

(See Test Circuit Figure 5)

-I

V

= 10V,

MP

DD

MILLER

= 5V

= 3V

= 2V

V

= 10V,

-

4.7

3.7

-

A

DD

MILLER

V

= 10V,

DD

MILLER

FN7719.1

January 20, 2011

5

ISL89160, ISL89161, ISL89162

AC Electrical Specifications

V

= 12V, GND = 0V, No Load on OUTA or OUTB, Unless Otherwise Specified. Boldface limits

DD

apply over the operating junction temperature range, -40°C to +125°C. (Continued)

T = -40°C

J

to +125°C

T = +25°C

J

TEST CONDITIONS

PARAMETERS

Miller Plateau Source Current

SYMBOL

/NOTES

MIN

-

TYP

5.2

MAX

-

MIN

MAX

-

UNITS

A

I

V

= 10V,

-

MP

DD

(See Test Circuit Figure 6)

= 5V

= 3V

= 2V

MILLER

V

= 10V,

-

5.8

6.9

-

A

DD

MILLER

V

= 10V,

DD

MILLER

Test Waveforms and Circuits

3.3V*

50%

t_RDLY

50%

t_FDLY

INA,

INB

0V

90%

10%

/OUTA

OUTA

t_RDLY

t_FDLY

OUTA

OR

OUTB

/OUTB

OUTB

t_R

t_F

t_RM

t_FM

* logic levels: A option = 3.3V, B option = 5.0V

FIGURE 3. PROP DELAYS AND MATCHING

FIGURE 4. RISE/FALL TIMES

ISL8916x

10V

ISL8916x

0.1µF

10k

0.1µF

10k

V_MILLER

10µF

200ns

10nF

+I_SENSE

10nF

0.1

-I_SENSE

FIGURE 5. MILLER PLATEAU SINK CURRENT TEST CIRCUIT

FIGURE 6. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT

FN7719.1

January 20, 2011

6

ISL89160, ISL89161, ISL89162

Test Waveforms and Circuits (Continued)

Current through

0.1 Resistor

10V

0A

I_MP

Ω

V_MILLER

V_OUT

V_MILLER

-I_MP

0V

Current through

Ω

0.1

Resistor

0

200ns

FIGURE 7. MILLER PLATEAU SINK CURRENT

FIGURE 8. MILLER PLATEAU SOURCE CURRENT

Typical Performance Curves

3.5

35

+125°C

30

25

20

15

10

5

+25°C

-40°C

3.0

+25°C

-40°C

2.5

2.0

4

8

12

16

4

8

12

16

V

DD

FIGURE 10. I vs V (1 MHz)

FIGURE 9. I vs V (STATIC)

DD DD

DD

50

40

30

20

10

0

1.1

1.0

16V

V

LOW

HIGH

OUT

NO LOAD

0.9

0.8

0.7

10V

5V

V

OUT

12V

0.6

0.5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

FREQUENCY (MHz)

-45

-20

5

30

55

80

105

130

TEMPERATURE (°C)

FIGURE 11. I

vs FREQUENCY (+25°C)

FIGURE 12. r

vs TEMPERATURE

DS(ON)

DD

FN7719.1

January 20, 2011

7

ISL89160, ISL89161, ISL89162

Typical Performance Curves(Continued)

25

20

15

30

FALL TIME, C

= 10nF

LOAD

OUTPUT FALLING PROP DELAY

OUTPUT RISING PROP DELAY

25

RISE TIME, C

= 10nF

LOAD

20

15

5

7

9

11

DD

13

15

-45

-20

5

30

55

80

105

130

V

TEMPERATURE (°C)

FIGURE 14. PROPAGATION DELAY vs V

FIGURE 13. OUTPUT RISE/FALL TIME

DD

Functional Description

Overview

D

INx

OUTx

The ISL89160, ISL89161, ISL89162 drivers incorporate several

features including precision input logic thresholds, undervoltage

lock-out, and fast rising high output drive currents.

R_del

c_del

The precision input thresholds facilitate the use of an external RC

network to delay the rising or falling propagation of the driver

output. This is a useful feature to create dead times for bridge

applications to prevent shoot through.

FIGURE 15. DELAY USING RCD NETWORK

The 37% and 63% thresholds were chosen to simplify the

calculations for the desired time delays. When using an RC

circuit to generate a time delay, the delay is simply T (secs) = R

(ohms) x C (farads). Please note that this equation only applies if

the input logic voltage amplitude is 3.3V. If the logic high

amplitude is higher than 3.3V, the equations in Equation 1 can

be used for more precise delay calculations.

To prevent unexpected glitches on the output of the ISL89160,

ISL89161, ISL89162 during power-on or power-off when V is

DD

very low, the Undervoltage (UV) lock-out prevents the outputs of

the ISL89160, ISL89161, ISL89162 driver from turning on. The

UV lock-out forces the driver outputs to be low when VDD < ~3.2

VDC regardless of the input logic level.

High level of the logic signal into the RC

Positive going threshold

V

= 5V

H

= 63% × 3.3V

THRESH

Low level of the logic signal into the RC

V

= 0.1V

The fast rising (or falling) output drive currents of the ISL89160,

ISL89161, ISL89162 minimize the turn-on (off) delays due to the

input capacitance of the driven FET. The switching transition

period at the Miller plateau is also minimized by high drive

currents even at these lower output voltages. (See the specified

Miller plateau currents in the AC Electrical Specifications on

page 5).

L

Timing values

R

C

t

= 100Ω

del

= 1nF

= –R

V

– V

⎛

⎜

⎝

⎞

⎟

⎠

L

THRESH

--------------------------------------

+ 1

C

× LN

del

del del

V

– V

H

L

t

= 51.731ns

Nominal delay time

del

(EQ. 1)

Application Information

Precision Thresholds for Time Delays

For input logic voltage option A, the nominal input negative

transition threshold is 1.22V and the positive transition threshold

is 2.08V (37% and 63% of 3.3V) Likewise, for input logic option B,

the nominal input negative transition threshold is 1.85V and the

positive transition threshold is 3.15V (37% and 63% of 4.0V).

In this example, the high input logic voltage is 5V, the positive

threshold is 63% of 3.3V and the low level input logic is 0.1V.

Note the rising edge propagation delay of the driver must be

added to this value.

The minimum recommended value of C is 100pF. The parasitic

capacitance of the PCB and any attached scope probes will

introduce significant delay errors if smaller values are used.

Larger values of C will further minimize errors.

In Figure 15, R and C delay the rising edge of the input

del del

signal. For the falling edge of the input signal, the diode shorts

out the resistor resulting in a minimal falling edge delay. If the

diode polarity is reversed, the falling edge is delayed and the

rising delay is minimal.

Acceptable values of R are primarily effected by the source

resistance of the logic inputs. Generally, 100Ω resistors or larger

are usable. A practical maximum value, limited by contamination

on the PCB, is 1MΩ.

FN7719.1

January 20, 2011

8

ISL89160, ISL89161, ISL89162

Figure 16 illustrates how the gate charge varies with the gate

voltage in a typical power MOSFET. In this example, the total gate

charge for V = 10V is 21.5nC when V = 40V. This is the

charge that a driver must source to turn-on the MOSFET and

must sink to turn-off the MOSFET.

Power Dissipation of the Driver

The power dissipation of the ISL89160, ISL89161, ISL89162 is

dominated by the losses associated with the gate charge of the

driven bridge FETs and the switching frequency. The internal bias

current also contributes to the total dissipation but is usually not

significant as compared to the gate charge losses.

gs DS

Equation 2 shows calculating the power dissipation of the driver:

R

gate

------------------------------------------

P

= 2 • Q • freq • V

•

+ I (freq) • V

DD

12

10

D

c

GS

DD

R

+ r

DS(ON)

gate

(EQ. 2)

V

= 64V

DS

where:

freq = Switching frequency,

= V bias of the ISL89160, ISL89161, ISL89162

8

6

4

2

0

V

= 40V

DS

V

GS

DD

Q = Gate charge for V

c

GS

I

(freq) = Bias current at the switching frequency (see Figure 9)

DD

r

= ON-resistance of the driver

DS(ON)

R

= External gate resistance (if any).

gate

0

2

4

6

8

10 12 14 16 18 20 22 24

GATE CHARGE (nC)

Note that the gate power dissipation is proportionally shared with

the external gate resistor and the output r . When sizing an

Q

g,

DS(ON)

external gate resistor, do not overlook the power dissipated by

this resistor.

FIGURE 16. MOSFET GATE CHARGE vs GATE VOLTAGE

Typical Application Circuit

V_bridge

ZVS Full Bridge

SQR

PWM

LL

L

R

L

Q_UL

Q_UR

V_GUL

V_GUR

U1A

SQR

ISL89162

LR

T2

T1A

T1B

V_LL

U1B

Q_LL

Q_LR

Red dashed lines

emphasize the

resonant

switching delay

of the low-side

bridge FETs

V_LR

V_GLL

V_GLR

V_GLL

LL

LR

U2A

½ ISL89160

U2B

½ ISL89160

V_GUL

V_GLR

V_GUR

LL: lower left

LR: lower right

UL: upper left

UR: upper right

GLL: gate lower left

This is an example of how the ISL89160, ISL89161, ISL89162,

MOSFET drivers can be applied in a zero voltage switching full

bridge. Two main signals are required: a 50% duty cycle square

wave (SQR) and a PWM signal synchronized to the edges of the

SQR input. An ISL89162 is used to drive T1 with alternating half

cycles driving Q and Q . An ISL89160 is used to drive Q and

UL UR LL

also with alternating half cycles. Unlike the two high-side

Q

LR

bridge FETs, the two low side bridge FETs are turned on with a

rising edge delay. The delay is setup by the RCD network on the

inputs to the ISL89160. The duration of the delay is chosen to

turn on the low-side FETs when the voltage on their respective

drains is at the resonant valley. For a complete description of the

ZVS topology, refer to AN1603 “ISL6752_54 Evaluation Board

Application Note”.

FN7719.1

January 20, 2011

9

ISL89160, ISL89161, ISL89162

General PCB Layout Guidelines

General EPAD Heatsinking

Considerations

The AC performance of the ISL89160, ISL89161, ISL89162

depends significantly on the design of the PC board. The

following layout design guidelines are recommended to achieve

optimum performance:

The thermal pad is electrically connected to the GND supply

through the IC substrate. The epad of the ISL89160, ISL89161,

ISL89162 has two main functions: to provide a quiet GND for the

input threshold comparators and to provide heat sinking for the

IC. The EPAD must be connected to a ground plane and no

switching currents from the driven FET should pass through the

ground plane under the IC.

• Place the driver as close as possible to the driven power FET.

• Understand where the switching power currents flow. The high

amplitude di/dt currents of the driven power FET will induce

significant voltage transients on the associated traces.

Figure 17 is a PCB layout example of how to use vias to remove

heat from the IC through the epad.

• Keep power loops as short as possible by paralleling the

source and return traces.

• Use planes where practical; they are usually more effective

than parallel traces.

EPAD GND

PLANE

EPAD GND

PLANE

• Avoid paralleling high amplitude di/dt traces with low level

signal lines. High di/dt will induce currents and consequently,

noise voltages in the low level signal lines.

• When practical, minimize impedances in low level signal

circuits. The noise, magnetically induced on a 10k resistor, is

10x larger than the noise on a 1k resistor.

BOTTOM

LAYER

• Be aware of magnetic fields emanating from transformers and

inductors. Gaps in these structures are especially bad for

emitting flux.

COMPONENT LAYER

FIGURE 17. TYPICAL PCB PATTERN FOR THERMAL VIAS

• If you must have traces close to magnetic devices, align the

traces so that they are parallel to the flux lines to minimize

coupling.

For maximum heatsinking, it is recommended that a ground

plane, connected to the EPAD, be added to both sides of the PCB.

A via array, within the area of the EPAD, will conduct heat from

the EPAD to the GND plane on the bottom layer. The number of

vias and the size of the GND planes required for adequate

heatsinking is determined by the power dissipated by the

ISL89160, ISL89161, ISL89162, the air flow and the maximum

temperature of the air around the IC.

• The use of low inductance components such as chip resistors

and chip capacitors is highly recommended.

• Use decoupling capacitors to reduce the influence of parasitic

inductance in the VDD and GND leads. To be effective, these

caps must also have the shortest possible conduction paths. If

vias are used, connect several paralleled vias to reduce the

inductance of the vias.

• It may be necessary to add resistance to dampen resonating

parasitic circuits especially on OUTA and OUTB. If an external

gate resistor is unacceptable, then the layout must be

improved to minimize lead inductance.

• Keep high dv/dt nodes away from low level circuits. Guard

banding can be used to shunt away dv/dt injected currents

from sensitive circuits. This is especially true for control circuits

that source the input signals to the ISL89160, ISL89161,

ISL89162.

• Avoid having a signal ground plane under a high amplitude

dv/dt circuit. This will inject di/dt currents into the signal

ground paths.

• Do power dissipation and voltage drop calculations of the

power traces. Many PCB/CAD programs have built in tools for

calculation of trace resistance.

• Large power components (Power FETs, Electrolytic caps, power

resistors, etc.) will have internal parasitic inductance which

cannot be eliminated. This must be accounted for in the PCB

layout and circuit design.

• If you simulate your circuits, consider including parasitic

components especially parasitic inductance.

FN7719.1

January 20, 2011

10

ISL89160, ISL89161, ISL89162

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN7719.1

CHANGE

1/13/11

1/12/11

Removed Option C Reference from Visio Graphics due to parts not releasing yet.

Converted to New Intersil Template

Updated page 1 Graphic by depicting 2 lines showing positive threshold and 2 lines showing negative threshold:

page 1 - Removed Related Literature from due to documentation being nonexistent at this time.

page 2 - Updated Pin Description Table by placing both pin numbers 1 and 8 on same line

page 3 - Updated Ordering Information by adding option B parts

page 4 - Added Note Reference to Inputs section in Electrical Spec Table

page 5 - Changed Note in Electrical Spec Table

From:

Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature

limits established by characterization and are not production tested.

To:

Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or

design.

11/2/10

FN7719.0

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page

on intersil.com: ISL89160, ISL89161, ISL89162

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/sear

FN7719.1

January 20, 2011

11

ISL89160, ISL89161, ISL89162

Package Outline Drawing

L8.3x3I

8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1 6/09

2X 1.950

3.00

A

6X 0.65

B

5

8

(4X)

0.15

1.64 +0.10/ - 0.15

6

PIN 1

INDEX AREA

6

PIN #1 INDEX AREA

4

1

4

8X 0.30

0.10 M C A B

8X 0.400 ± 0.10

TOP VIEW

2.38

+0.10/ - 0.15

BOTTOM VIEW

SEE DETAIL "X"

( 2.38 )

( 1.95)

C

0.10

C

Max 0.80

0.08

C

SIDE VIEW

( 8X 0.60)

(1.64)

( 2.80 )

PIN 1

5

C

0 . 2 REF

(6x 0.65)

0 . 00 MIN.

0 . 05 MAX.

( 8 X 0.30)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN7719.1

January 20, 2011

12

ISL89160, ISL89161, ISL89162

Small Outline Exposed Pad Plastic Packages (EPSOIC)

M8.15D

N

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

E

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.52

0.10

0.36

0.19

4.80

3.811

MAX

1.72

0.25

0.46

0.25

4.98

3.99

NOTES

A

A1

B

C

D

E

e

0.059

0.003

0.0138

0.0075

0.189

0.150

0.067

0.009

0.0192

0.0098

0.196

0.157

-

1

2

3

-

TOP VIEW

9

-

L

3

SEATING PLANE

A

4

-A-

D

0.050 BSC

1.27 BSC

-

h x 45°

H

h

0.230

0.010

0.016

0.244

0.019

0.050

5.84

0.25

0.41

6.20

0.50

1.27

-

-C-

5

α

L

6

e

B

A1

C

N

8

7

0.10(0.004)

0°

8°

0°

8°

-

11

α

P

0.25(0.010) M

SIDE VIEW

C A M B S

0.118

0.078

0.137

0.099

3.00

2.00

3.50

2.50

P1

11

Rev. 0 5/07

NOTES:

1

2

3

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

P1

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

N

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

P

BOTTOM VIEW

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced

variations. Values shown are maximum size of exposed pad

within lead count and body size.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7719.1

January 20, 2011

13


型号：	ISL89160FBEBZ
厂家：	Intersil
描述：	High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver 高速，双通道， 6A ， 4.5〜 16VOUT ，功率MOSFET驱动器驱动器接口集成电路光电二极管
文件：	总13页 (文件大小：372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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