ISL9016IRUWCZ-T_技术文档

ISL9016

®

Data Sheet

January 22, 2009

FN6832.0

150mA Dual LDO with Low Noise, High

PSRR, and Low I

Features

Q

• Dual Integrated 150mA High Performance LDOs

• High PSRR: 80dB @ 1kHz and 45dB @ 1MHz

• Reverse Current Protection

ISL9016 is a high performance dual LDO capable of providing

up to 150mA current on each channel. It features a low

standby current and very high PSRR and is stable with output

capacitance of 1µF to 4.7µF with an ESR of up to 200mΩ.

• Low Quiescent Current

- 49µA (Single LDO Enabled)/80µA (Dual LDOs Enabled)

The device integrates a separate enable function for each

output. The quiescent current is typically 49µA when only

one LDO is enabled and typically 80µA when both LDOs are

enabled. When both LDOs are under shutdown condition,

the drawing current is typically less than 1µA.

• Excellent Load Transient Response

• Typically ±0.8% Output Voltage Accuracy

• Low Output Noise: Typically 25µV

RMS

ISL9016 provides a wide input voltage range from 1.8V to

6.5V. It also has a high PSRR of 80dB at 1kHz and 45dB at

1MHz. ISL9016 also provides output current limit, overheat

protection, reverse current protection, as well as excellent

load transient response.

• Wide Input Voltage Capability: 1.8V to 6.5V

• Low Dropout Voltage: Typically 120mV @ 150mA

• Separate Enable Control for each LDO

• Stable with 1µF to 4.7µF Ceramic Output Capacitors

• Soft-start to Limit Input Current Surge During Enable

• Current Limit and Overheat Protection

ISL9016 is offered in a tiny 1.6mmx1.6mm 6 Ld µTDFN

package. Output voltage options are available from 1.2V to

3.3V. Several combinations of voltage outputs are standard

and others may be available upon request.

• Tiny 6 Ld 1.6mmx1.6mm µTDFN package

• Pb-free (RoHS Compliant)

Pinout

ISL9016

(6 LD 1.6x1.6 µTDFN)

TOP VIEW

Applications

• PDAs, Cell Phones and Smart Phones

• Portable Instruments, MP3/4 Players, PMP, DSC

• Handheld Devices including Medical Handhelds

VIN

GND

EN2

1

2

3

6

5

4

VOUT1

VOUT2

EN1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

1

All other trademarks mentioned are the property of their respective owners.

ISL9016

Ordering Information

PART NUMBER

VO1 VOLTAGE VO2 VOLTAGE

TEMP RANGE

(°C)

PACKAGE

(Pb-Free)

PKG

DWG. #

(Notes 1, 3)

ISL9016IRUWCZ-T

ISL9016IRUWGZ-T

ISL9016IRUWJZ-T

ISL9016IRUWKZ-T

ISL9016IRUBWZ-T

ISL9016IRUBBZ-T

ISL9016IRUCWZ-T

ISL9016IRUCBZ-T

ISL9016IRUFWZ-T

ISL9016IRUFBZ-T

ISL9016IRUFCZ-T

ISL9016IRUFFZ-T

ISL9016IRUGWZ-T

ISL9016IRUGCZ-T

ISL9016IRUGGZ-T

ISL9016IRUJWZ-T

ISL9016IRUJBZ-T

ISL9016IRUJCZ-T

ISL9016IRUJJZ-T

ISL9016IRUKWZ-T

ISL9016IRUKFZ-T

ISL9016IRUKKZ-T

ISL9016IRUMWZ-T

ISL9016IRUMBZ-T

ISL9016IRUMCZ-T

ISL9016IRUMKZ-T

ISL9016IRUNWZ-T

ISL9016IRUNCZ-T

NOTES:

PART MARKING

(V) (Note 2)

N7

N6

N2

N1

R7

R6

R5

R4

R3

N8

N9

P0

P1

R2

N3

P2

P3

N4

N0

P5

P4

N5

P6

P7

P8

P9

R0

R1

1.2

1.8

-40 to +85

6 Ld µTDFN

L6.1.6x1.6A

1.2

2.7

6 Ld µTDFN

1.2

2.8

1.2

2.85

1.2

1.5

1.8

1.2

1.8

1.5

2.5

1.2

2.5

1.5

2.5

1.8

2.5

2.7

1.2

2.7

1.8

2.7

2.8

1.2

2.8

1.5

2.8

1.8

2.8

2.85

3.0

1.2

2.5

2.85

1.2

3.0

1.5

3.0

1.8

3.0

2.85

1.2

3.3

1.8

1. Please refer to TB347 for details on reel specifications.

2. For other output voltages, contact Intersil marketing or local sales office.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4

termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN6832.0

January 22, 2009

2

ISL9016

Absolute Maximum Ratings

Thermal Information

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.1V

Thermal Resistance

θ

(°C/W)

IN

JA

117.5

All Other Pins to GND . . . . . . . . . . . . . . . . . . . . -0.3 to (V + 0.3)V

IN

6 Ld μTDFN Package (Note 4). . . . . . . . . . . . . . .

Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 6.5V

Each LDO Load Current . . . . . . . . . . . . . . . . . . . . . . . .up to 150mA

Ambient Temperature Range (T ) . . . . . . . . . . . . . . .-40°C to +85°C

A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and

the typical specifications are measured at the following conditions: T = +25°C; V = (V + 0.5V) to 6.5V with

A

IN

O

a minimum V of 1.8V; C = 1µF; C = 1µF. Parameters with MIN and/or MAX limits are 100% tested at

IN IN

O

+25°C, unless otherwise specified. Temperature limits established by characterization and are not production

tested.

PARAMETER

DC CHARACTERISTICS

Supply Voltage

SYMBOL

TEST CONDITIONS

MIN

1.8

TYP

MAX

UNITS

V

6.5

V

IN

UVLO Threshold

V

1.710

1.62

1.775

UV+

V

1.55

UV-

Input Quiescent Current

Quiescent condition: I = 0µA; I = 0µA

O1 O2

I

One LDO active

Both LDO active

@ +25°C

49

80

67

µA

%

DD1

DD2

DDS

100

1.0

Shutdown Current

I

0.1

Regulation Voltage Accuracy

V

= V + 0.5V to 6.5V, I = 10µA to 150mA, T = +25°C

-0.8

-1.8

+0.8

+1.8

IN

O

A

= V + 0.5V to 6.5V, I = 10µA to 150mA, T = -40°C to

%

O

A

+85°C

Maximum Output Current

Internal Current Limit

I

Each LDO, Continuous

150

175

mA

mV

°C

MAX

I

V

T

265

250

200

120

145

110

355

425

325

200

LIM

Dropout Voltage (Note 5)

I

= 150mA; 1.2V ≤ V ≤ 2.1V

O

DO1

DO2

DO3

SD+

O

= 150mA; 2.1V ≤ V ≤ 2.8V

O

= 150mA; 2.8V ≤ V

O

Thermal Shutdown Temperature

T

°C

SD-

AC CHARACTERISTICS

Ripple Rejection

I

= 10mA, V = 3.7V(min), V = 2.7V, T = +25°C

IN

O

A

@ 1kHz

80

60

50

45

25

dB

@ 10kHz

@ 100kHz

@ 1MHz

Output Noise Voltage

V

= 4.2V, I = 10mA, T = +25°C, BW = 10Hz to 100kHz

µV

RMS

IN

O

A

DEVICE START-UP CHARACTERISTICS

Device Enable Time

t

Time from assertion of the ENx pin to when the output voltage

reaches 95% of the V (nom)

400

600

µs

EN

O

FN6832.0

January 22, 2009

3

ISL9016

Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and

the typical specifications are measured at the following conditions: T = +25°C; V = (V + 0.5V) to 6.5V with

A

IN

O

a minimum V of 1.8V; C = 1µF; C = 1µF. Parameters with MIN and/or MAX limits are 100% tested at

IN IN

O

+25°C, unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

LDO Soft-Start Ramp Rate

t

Slope of linear portion of LDO output voltage ramp during

start-up

30

60

µs/V

SSR

EN PIN CHARACTERISTICS

Input Low Voltage

V

T

= -20°C to +85°

-0.3

1.1

0.4

V

IL

A

Input High Voltage

V

+ 0.3

IH

IN

Input Leakage Current

I , I

IL IH

0.1

15

µA

REVERSE CURRENT CHARACTERISTICS

Output Reverse Leakage Current

(Note 6)

I

V

= 0V, V = 5.5V

OUT

8

µA

ORLC

IN

NOTES:

5. V x = 0.98*V x(NOM); Valid for VOx greater than 1.80V.

O

6. Output reverse leakage current is measured with VIN pin grounded and VOUT pin connected to 5.5V.

FN6832.0

January 22, 2009

4

ISL9016

Typical Operating Performance

55

50

45

40

35

30

T = +85°C

T = +50°C

T = +85°C

T = +50°C

50

45

40

35

30

T = +25°C

T = 0°C

T = -25°C

T = -40°C

2.4

3.6

4.8

6.0

2.4

3.6

4.8

6.0

INPUT VOLTAGE (V)

FIGURE 1. QUIESCENT CURRENT vs INPUT VOLTAGE

(V = 2.1V, ONLY LDO1 ENABLED)

FIGURE 2. QUIESCENT CURRENT vs INPUT VOLTAGE

(V = 2.1V, ONLY LDO2 ENABLED)

OUT1

OUT2

55

50

45

40

35

30

85

80

75

70

65

60

T = +85°C

T = +50°C

T = +25°C

T = +50°C

T = +25°C

T = 0°C

T = -25°C

T = -40°C

3.6

4.4

5.2

6.0

2.4

3.6

4.8

6.0

INPUT VOLTAGE (V)

FIGURE 3. QUIESCENT CURRENT vs INPUT VOLTAGE

(V = V = 2.1V, LDO1 AND LDO2

FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE

(V = 3.3V, ONLY LDO1 ENABLED)

OUT1

ENABLED)

OUT2

OUT1

55

50

45

40

35

30

85

80

75

70

65

60

T = +85°C

T = +25°C

T = +50°C

T = +85°C

T = +50°C

T = 0°C

T = -25°C

T = -40°C

3.6

4.4

5.2

6.0

3.6

4.4

5.2

6.0

INPUT VOLTAGE (V)

FIGURE 5. QUIESCENT CURRENT vs INPUT VOLTAGE

FIGURE 6. QUIESCENT CURRENT vs INPUT VOLTAGE

(V = V = 3.3V, LDO1 AND LDO2

(V

= 3.3V, ONLY LDO2 ENABLED)

OUT2

OUT1

ENABLED)

OUT2

FN6832.0

January 22, 2009

5

ISL9016

Typical Operating Performance

10

5

15

T = +85°C

10

T = +25°C

0

5

0

-5

-10

-15

-20

-5

T = +25°C

T = -40°C

-10

T = -40°C

4.5

INPUT VOLTAGE (V)

-15

1.5

3.0

6.0

1.5

2.5

3.5

INPUT VOLTAGE (V)

4.5

5.5

FIGURE 7. ΔV

vs INPUT VOLTAGE

FIGURE 8. ΔV

vs INPUT VOLTAGE

OUT

(V

= 1.2V, I

= 50mA)

(V

= 1.2V, I

= 150mA)

OUT_NOMINAL

OUT

OUT_NOMINAL

OUT

3.32

3.31

3.30

3.29

3.28

3.27

3.26

1.22

1.21

1.20

1.19

T = +25°C

T = +85°C

T = +25°C

T = -40°C

30

1.18

3.25

0

60

90

120

150

30

60

90

120

150

LOAD CURRENT (mA)

FIGURE 9. LOAD REGULATION (V = 1.8V, V

IN

= 1.2V)

FIGURE 10. LOAD REGULATION (V = 4.5V, V = 3.3V)

IN OUT

OUT

EN1 = EN2

5V/DIV

V

IN

5V/DIV

V

(AC COUPLED)

OUT1

50mV/DIV

1V/DIV

V

OUT1

V

OUT2

50mV/DIV

I

OUT1

200mA/DIV

1V/DIV

OUT2

100µs/DIV

1ms/DIV

FIGURE 11. ENABLE OPERATION (V = 3.6V,

IN

FIGURE 12. LOAD TRANSIENT RESPONSE (V = 3.6V,

IN

V

= V

= 1.2V)

V

= V

= 1.2V, I

0.01mA TO 150mA)

OUT1

OUT1 OUT2

OUT1

FN6832.0

January 22, 2009

6

ISL9016

Typical Operating Performance

V

IN

5V/DIV

V

(AC COUPLED)

OUT1

50mV/DIV

200mA/DIV

V

(AC COUPLED)

OUT1

1ms/DIV

(AC COUPLED)

V

OUT2

50mV/DIV

V

I

(AC COUPLED)

OUT2

I

OUT1

200mA/DIV

1ms/DIV

FIGURE 13. LOAD TRANSIENT RESPONSE (V = 3.6V,

IN

FIGURE 14. LOAD TRANSIENT RESPONSE (V = 3.6V,

IN

V

= V

= 1.2V, I

0.01mA TO 150mA)

V

= V

= 3.3V, I

0.01mA TO 150mA)

OUT1

OUT2

OUT1 OUT2

OUT1

V

(AC COUPLED)

OUT1

V

(AC COUPLED)

OUT

50mV/DIV

100mV/DIV

V

OUT2

20mV/DIV

I

OUT

OUT1

100mA/DIV

1ms/DIV

di/dt = 150mA/µs

FIGURE 15. LOAD TRANSIENT RESPONSE (V = 1.8V,

IN

FIGURE 16. LOAD TRANSIENT RESPONSE (V = 3.3V,

IN

V

= V

= 1.2V, I

0.01mA TO 150mA)

V = V

= 1.2V, I

0.01mA TO 150mA)

OUT1

OUT2

OUT1

OUT1 OUT2

OUT1

FN6832.0

January 22, 2009

7

ISL9016

Pin Descriptions

PIN #

NAME

DESCRIPTION

1

2

3

VIN

Supply Voltage/LDO Input. Connect a 1µF capacitor to GND.

GND

EN2

GND is the connection to system ground. Connect to PCB Ground plane.

LDO2 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN2 and the control voltage

rail. Do NOT leave it floating.

4

EN1

LDO1 Enable pin. Enable = High, Disable = Low. A 100k resistor should be connected between EN1 and the control voltage

rail. Do NOT leave it floating.

5

6

-

VOUT2 LDO2 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).

VOUT1 LDO1 Output. Connect capacitor with a value from 1µF to 4.7µF to GND (1µF recommended).

E-Pad

Connect the e-pad to the system ground.

Typical Application Diagram

ISL9016

VOUT1

1.2V~3.3V, 0~150mA

VIN (1.8V TO 6.5V)

VIN

VOUT1

VOUT2

1.2V~3.3V, 0~150mA

GND

EN2

VOUT2

EN1

C2

R2

C3

C1

R1

ON

OFF

ON

OFF

C1, C2, C3:1µF, X5R (or X7R) CERAMIC CAPACITOR

R1, R2: 100k

FN6832.0

January 22, 2009

8

ISL9016

Block Diagram

VOUT2

VOUT1

VIN

REVERSE CURRENT

PROTECTION

VOUT1

VIN

EN1

SHORT CIRCUIT

THERMAL PROTECTION

SOFT-START

UNDERVOLTAGE

LOCKOUT

CONTROL

LOGIC

EN2

EN1

VREF1

+

LDO-2

LDO-1

VREF2

VREF1

VREF3

BANDGAP

TEMP-SENSOR

REFERENCE

VOLTAGES

GND

LDO1 and/or LDO2 will be enabled accordingly based on the

voltage signal applied on its related EN pin and start from the

soft-start. Likewise, when one or both EN pins go low, LDO1

and/or LDO2 will be disabled based on the signal applied on

its related EN pin. A 100kΩ (or above) pull-up resistor should

be connected between ENx pin and the external control

voltage (as shown in the “Typical Application Diagram” on

page 8).

Functional Description

ISL9016 contains two high performance LDO’s. High

performance is achieved through a circuit which delivers fast

transient response to varying load conditions. In a quiescent

condition, the ISL9016 adjusts its biasing to achieve the

lowest standby current consumption.

The device also integrates current limit protection, thermal

shutdown protection, reverse current protection and soft-start.

Thermal shutdown protects the device against overheating.

Soft-start limits the start-up input current surges. In some

certain application circuits, the output voltage may be

LDO Protections

ISL9016 offers several protections which make it ideal for

using in battery-powered application circuits.

externally held up, meanwhile, the input voltage could be

connected to ground, or connected to some voltage lower

than the output side, or be left open circuit. ISL9016 features

the reverse current protection; it can limit the current flow from

output to input. This protection will automatically initiate when

ISL9016 provides short-circuit protection by limiting the

output current to typical 265mA. When short circuit happens,

the circuit is limited at 265mA (typical). If the short circuit

lasts long enough, the die temperature increases, and the

over-temperature protection circuit will turn off the output.

V

is detected to be higher than V . When V is pulled to

IN IN

OUT

ground and V

When the die temperature reaches about +145°C, the thermal

protection starts working. Under the overheat condition, only

the LDO sourcing more than 50mA will be shut off. This does

not affect the operation of the other LDO. If both LDOs source

more than 50mA and an overheat condition occurs, both LDO

outputs will be disabled. Once the die temperature falls back

to about +110°C, the disabled LDO(s) are re-enabled and

soft-start automatically takes place.

is held at 5.5V, the current flow from V

OUT

to V is typically less than 8µA.

IN

Enable Control

The ISL9016 has two separate enable pins, EN1 and EN2,

which independently enable/disable each of the LDO

outputs. When both EN1 and EN2 are low, the whole device

is in shutdown mode. In this condition, all on-chip circuits are

off, and the device draws minimum current, typically less

than 0.1mA. When one or both the EN pins go high, the

In certain applications, the following input/output situations

may occur:

FN6832.0

January 22, 2009

9

ISL9016

With output voltage externally held up higher than the input

voltage:

1. Input is pulled to ground;

2. input is left open circuit; and

3. input is pulled to some intermediate voltage

ISL9016 provides the reverse current protection to limit the

current flow from output to input under these situations. When

input is pulled to ground and output is held to 5.5V, the typical

reverse current from output to input side is less than 8µA.

Input and Output Capacitors

The ISL9016 provides a linear regulator that has low

quiescent current, fast transient response, and overall stability

across the recommended operating conditions. A ceramic

capacitor (X5R or X7R) with a capacitance of 1µF to 4.7µF

with an ESR up to 200mΩ is suitable for ISL9016 to maintain

its output stability. The ground connection of the output

capacitor should be connected directly to the GND pin of the

device, and also placed close to the device. Similarly for the

input capacitor, usually a 1µF ceramic capacitor (X5R or X7R)

is suitable for most cases, but if large, fast rising-time load

transient condition is expected, a higher value input capacitor

may be necessary to achieve better performance.

Board Layout Recommendations

A good PCB layout will be an important step to achieve good

performance. It is recommended to design the board with

separate ground planes for input and output, and connect

both ground planes at the GND pin of the device.

Consideration should be taken when placing the

components and route the trace to minimize the ground

impedance, as well as keep the parasitic inductance low.

Usually the input/output capacitors should be placed close to

the device with good ground connection.

FN6832.0

January 22, 2009

10

ISL9016

Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)

L6.1.6x1.6A

6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

A

E

B

6

4

MILLIMETERS

SYMBOL

MIN

0.45

-

NOMINAL

0.50

MAX

0.55

0.05

NOTES

D

PIN 1

A

A1

A3

b

-

REFERENCE

2X

0.15 C

-

1

3

0.127 REF

0.20

-

2X

0.15 C

TOP VIEW

A1

0.15

1.55

0.40

1.55

0.95

0.25

1.65

0.50

1.65

1.05

-

D

1.60

4

e

1.00 REF

D2

E

0.45

-

4

6

1.60

4

L

E2

e

1.00

-

CO.2

D2

0.50 BSC

0.30

-

DAP SIZE 1.30 x 0.76

L

0.25

0.35

-

3

1

b 6X

0.10 M C A B

Rev. 1 6/06

E2

BOTTOM VIEW

NOTES:

1. Dimensions are in mm. Angles in degrees.

2. Coplanarity applies to the exposed pad as well as the terminals.

Coplanarity shall not exceed 0.08mm.

DETAIL A

3. Warpage shall not exceed 0.10mm.

0.10 C

0.08 C

4. Package length/package width are considered as special

characteristics.

6X

5. JEDEC Reference MO-229.

C

A3

6. For additional information, to assist with the PCB Land Pattern

Design effort, see Intersil Technical Brief TB389.

SEATING

PLANE

SIDE VIEW

0.127±0.008

0.127 +0.058

-0.008

TERMINAL THICKNESS

A1

DETAIL A

0.25

0.50

1.00

0.45

2.00

0.30

1.25

6

LAND PATTERN

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6832.0

January 22, 2009

11


型号：	ISL9016IRUWCZ-T
厂家：	Intersil
描述：	150mA Dual LDO with Low Noise, High PSRR, and Low IQ 150毫安双路LDO具有低噪声，高PSRR ，低智商
文件：	总11页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL9016IRUWCZ-T [INTERSIL]

相关型号：

ISL9016IRUWGZ-T

ISL9016IRUWJZ-T

ISL9016IRUWKZ-T

ISL9021

ISL9021A

ISL9021A

ISL9021AIIBZ-EVZ

ISL9021AIIBZ-EVZ

ISL9021AIIBZ-T

ISL9021AIIBZ-T

ISL9021AIICZ-EVZ

ISL9021AIICZ-EVZ