ISL9110IRTNEVAL1Z [INTERSIL]
1.2A High Efficiency Buck-Boost Regulators; 1.2A高效率降压 - 升压型稳压器
| 型号： | ISL9110IRTNEVAL1Z |
| 厂家： | 
Intersil |
| 描述： | 1.2A High Efficiency Buck-Boost Regulators |
| 文件： | 总20页 (文件大小：1026K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.2A High Efficiency Buck-Boost Regulators
ISL9110, ISL9112
Features
• Accepts Input Voltages Above or Below Regulated Output
Voltage
The ISL9110 and ISL9112 are highly-integrated Buck-Boost
switching regulators that accept input voltages either above or
below the regulated output voltage. Unlike other Buck-Boost
regulators, these regulators automatically transition between
operating modes without significant output disturbance.
• Automatic and Seamless Transitions Between Buck and Boost
Modes
• Input Voltage Range: 1.8V to 5.5V
• Output Current: Up to 1.2A
Both parts are capable of delivering up to 1.2A output current,
and provide excellent efficiency due to their fully synchronous
4-switch architecture. No-load quiescent current of only 35µA
also optimizes efficiency under light-load conditions. Forced
PWM and/or synchronization to an external clock may also be
selected for noise sensitive applications.
• High Efficiency: Up to 95%
• 35µA Quiescent Current Maximizes Light-load Efficiency
• 2.5MHz Switching Frequency Minimizes External Component
Size
The ISL9110 is designed for standalone applications and
supports 3.3V and 5V fixed output voltages or variable output
voltages with an external resistor divider. Output voltages as low
as 1V, or as high as 5.2V are supported using an external resistor
divider.
• Selectable Forced-PWM Mode and External Synchronization
2
• I C Interface (ISL9112)
• Fully Protected for Overcurrent, Over-temperature and
Undervoltage
• Small 3mmx3mm TDFN Package
The ISL9112 supports a broader set of programmable features
that may be accessed via an I C bus interface. With a
2
programmable output voltage range of 1.9V to 5V, the ISL9112
is ideal for applications requiring dynamically changing supply
voltages. A programmable slew rate can be selected to provide
smooth transitions between output voltage settings.
Applications
• Regulated 3.3V from a Single Li-Ion Battery
• Smart Phones and Tablet Computers
• Handheld Devices
The ISL9110 and ISL9112 require only a single inductor and very
few external components. Power supply solution size is
minimized by a tiny 3mmx3mm package and a 2.5MHz
switching frequency, which further reduces the size of external
components.
• Point-of-Load Regulators
Related Literature
• See AN1648 “ISL9110IRTNEVAL1Z, ISL9110IRT7EVAL1Z,
ISL9110IRTAEVAL1Z Evaluation Board User Guide”
• See AN1647 “ISL9112IRTNEVAL1Z, ISL9112IRT7EVAL1Z
EvaluationBoard User Guide”
100
95
VIN
=
ISL9110IRTNZ
1.8V TO 5.5V
5
4
PVIN
LX1
90
C1
L1
10µF
V
= 5V
2.2µH
IN
2
1
6
10
9
8
7
VIN
LX2
85
80
75
70
VOUT
=
MODE VOUT
EN
3.3V/1A
C2
10µF
BAT
PG
12
V
= 3V
STATUS
OUTPUTS
IN
FB
V
= 2.5V
IN
V
= 3.3V
OUT
0.01
0.05
0.25
1.25
I
(A)
OUT
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY
July 13, 2012
FN7649.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL9110, ISL9112
Block Diagram
LX1
4
LX2
2
PVIN
VOUT
PGND
5
1
3
SOFT
DISCHARGE
EN
VREF
GATE
DRIVERS
& ANTI-
EN
9
6
EN
SHOOT THRU
VIN
EN
BAT
8
PVIN
MONITOR
VOUT
CLAMP
THERMAL
SHUTDOWN
PWM
CONTROL
CURRENT
DETECT
MODE/SYNC
SCL
10
7
EN
EN
PG
FB
7
I2C
EN
VOUT
MONITOR
SDA
8
12
OSC
EN
REF
ERROR
AMP
VOLTAGE
PROG.
11
GND
Pin Configurations
Pin Descriptions
PIN # ISL9110 ISL9112
ISL9110
DESCRIPTION
(12 LD TDFN)
TOP VIEW
1
VOUT
VOUT
Buck/boost output. Connect a 10µF
capacitor to PGND.
FB
VOUT
LX2
12
11
1
2
3
4
5
6
2
3
4
5
LX2
PGND
LX1
LX2
Inductor connection, output side.
GND
PGND Power ground for high switching current.
10 MODE/SYNC
9 EN
PGND
LX1
ISL9110
PAD
LX1
Inductor connection, input side.
PVIN
VIN
8 BAT
PVIN
PVIN
Power input. Range: 1.8V to 5.5V. Connect a
10µF capacitor to PGND.
PG
7
6
7
VIN
PG
VIN
-
Supply input. Range: 1.8V to 5.5V.
Open drain output.
Provides output-power-good status.
ISL9112
(12 LD TDFN)
TOP VIEW
2
-
SCL
-
Logic input, I C clock.
8
BAT
Open drain output.
Provides input-power-good status.
1
2
3
4
5
6
FB
12
11
VOUT
LX2
GND
2
-
SDA
EN
Logic I/O, open drain, I C data.
PGND
LX1
10 MODE/SYNC
ISL9112
PAD
9
EN
Logic input, drive high to enable device.
EN
9
8
7
PVIN
VIN
SDA
SCL
10
MODE / MODE / Logic input, high for auto PFM mode. Low for
SYNC
SYNC forced PWM operation.
Ext. clock sync input. Range: 2.75MHz to
3.25MHz.
11
12
GND
FB
GND
FB
Analog ground pin.
Voltage feedback pin.
Exposed pad; connect to PGND.
PAD
PAD
PAD
FN7649.2
July 13, 2012
2
ISL9110, ISL9112
Ordering Information
PART NUMBER
PART
V
HICCUP
MODE
TEMP RANGE
(°C)
PKG.
DWG. #
OUT
(Notes 3, 4)
MARKING
(V)
3.3
5.0
ADJ.
3.3
5.0
ADJ.
PACKAGE
ISL9110IRTNZ (Notes 1, 2)
ISL9110IRT7Z (Notes 1, 2)
ISL9110IRTAZ (Notes 1, 2)
ISL9112IRTNZ (Notes 1, 2)
ISL9112IRT7Z (Notes 1, 2)
ISL9110BIRTAZ (Notes 1, 2)
ISL9110IRTNEVAL1Z
ISL9110IRT7EVAL1Z
ISL9110IRTAEVAL1Z
ISL9112IRTNEVAL1Z
ISL9112IRT7EVAL1Z
NOTES:
GASA
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
12 Ld Exposed Pad 3x3 TDFN
12 Ld Exposed Pad 3x3 TDFN
12 Ld Exposed Pad 3x3 TDFN
12 Ld Exposed Pad 3x3 TDFN
12 Ld Exposed Pad 3x3 TDFN
12 Ld Exposed Pad 3x3 TDFN
L12.3x3C
GATA
L12.3x3C
L12.3x3C
L12.3x3C
L12.3x3C
L12.3x3C
GAUA
GAVA
GAWA
GBAF
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9110 or ISL9112. For more information on MSL please see techbrief
TB363.
4. The ISL9110 and ISL9112 can be special ordered with any output voltage between 1.9V and 5.0V in 100mV steps.
FN7649.2
July 13, 2012
3
ISL9110, ISL9112
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
I C Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal Supply and References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Enable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
POR Sequence and Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Short Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PG Status Output (ISL9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
BAT Status Output (ISL9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Ultrasonic Mode (ISL9112 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
External Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Buck-Boost Conversion Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PFM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation With VIN Close to VOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Voltage Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Digital Slew Rate Control (ISL9112 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register Description (ISL9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2
I C Serial Interface (ISL9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protocol Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Voltage Programming, Adj. Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Feed-Forward Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Non-Adjustable Version FB Pin Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PVIN and VOUT Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
The TDFN Package Requires Additional PCB Layout Rules for the Thermal Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FN7649.2
July 13, 2012
4
ISL9110, ISL9112
Absolute Maximum Ratings
Thermal Information
PVIN, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
LX1, LX2 (Note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
FB (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
Thermal Resistance (Typical)
12 Ld TDFN Package (Notes 5, 6) . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
θ
JA (°C/W)
42
θ
JC (°C/W)
5.5
FB (fixed V
versions). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
OUT
GND, PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V
ESD Rating
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . . . 3kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 250V
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 1.2A
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. LX1 and LX2 pins can withstand switching transients of -1.5V for 100ns, and 7V for 20ms.
Analog Specifications V = V
= V = 3.6V, V = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, T = +25°C. Boldface limits apply over the
EN OUT A
VIN
PVIN
operating temperature range, -40°C to +85°C.
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8) (Note 9) (Note 8) UNITS
POWER SUPPLY
V
Input Voltage Range
1.8
5.5
V
V
IN
V
VIN Undervoltage Lockout Threshold
Rising
Falling
1.725
1.650
35
1.775
UVLO
1.550
V
I
VIN Supply Current
PFM mode, no external load on Vout (Note 10)
EN = GND, V = 3.6V
60
µA
µA
VIN
I
VIN Supply Current, Shutdown
0.05
1.0
SD
IN
OUTPUT VOLTAGE REGULATION
V
Output Voltage Range
ISL9110IRTAZ, I
= 100mA
= 100mA
1.00
1.90
-2
5.20
5.00
+2
V
OUT
OUT
ISL9112, I
V
OUT
Output Voltage Accuracy
V
V
= 3.7V, V
= 3.3V, I
= 3.3V, I
= 0mA, PWM mode
= 1mA, PFM mode
%
%
IN
IN
OUT
OUT
OUT
= 3.7V, V
-3
+4
OUT
V
FB Pin Voltage Regulation
FB Pin Bias Current
For adjustable output version
For adjustable output version
0.79
0.80
0.81
1
V
FB
I
µA
FB
ΔV
ΔV
ΔV
/
/
/
/
Line Regulation, PWM Mode
I
= 500mA, V
= 3.3V, MODE = GND, V step
IN
±0.005
±0.005
±12.5
±0.4
mV/mV
OUT
OUT OUT
ΔV
from 2.3V to 5.5V
IN
Load Regulation, PWM Mode
Line Regulation, PFM Mode
Load Regulation, PFM Mode
V
= 3.7V, V = 3.3V, MODE = GND, I
step
mV/mA
mV/V
OUT
IN
OUT OUT
ΔI
from 0mA to 500mA
OUT
I
= 100mA, V
= 3.3V, MODE = VIN, V step
IN
OUT
OUT
OUT
ΔV
from 2.3V to 5.5V
I
ΔV
OUT
V
=3.7V, V
= 3.3V, MODE = VIN, I
step from
mV/mA
IN OUT OUT
ΔI
0mA to 100mA
OUT
V
Output Voltage Clamp
Rising, V = 3.6V
5.25
5.95
V
CLAMP
IN
Output Voltage Clamp Hysteresis
V
= 3.6V
400
mV
IN
FN7649.2
July 13, 2012
5
ISL9110, ISL9112
Analog Specifications V = V
= V = 3.6V, V = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, T = +25°C. Boldface limits apply over the
EN OUT A
operating temperature range, -40°C to +85°C. (Continued)
VIN
PVIN
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8) (Note 9) (Note 8) UNITS
DC/DC SWITCHING SPECIFICATIONS
f
Oscillator Frequency
Minimum On Time
2.25
2.50
80
2.75
MHz
ns
SW
t
ONMIN
IPFETLEAK LX1 Pin Leakage Current
INFETLEAK LX2 Pin Leakage Current
SOFT-START and SOFT DISCHARGE
-1
-1
1
1
µA
µA
t
Soft-start Time
Time from when EN signal asserts to when output
voltage ramp starts.
1
1
ms
ms
SS
Time from when output voltage ramp starts to
when output voltage reaches 95% of its nominal
value with device operating in buck mode.
V
= 4V, V = 3.3V, I = 200mA
IN
OUT O
Time from when output voltage ramp starts to
when output voltage reaches 95% of its nominal
value with device operating in boost mode.
2
ms
V
= 2V, V = 3.3V, I = 200mA
IN
OUT O
R
VOUT Soft-Discharge ON-Resistance
V
= 3.6V, EN < VIL
120
Ω
DISCHG
IN
POWER MOSFET
R
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
V
V
V
V
V
= 3.6V, I = 200mA
0.12
0.15
0.10
0.13
2.4
0.17
0.23
0.15
0.23
2.8
Ω
Ω
Ω
Ω
A
DSON_P
DSON_N
PK_LMT
IN
IN
IN
IN
IN
O
= 2.5V, I = 200mA
O
R
= 3.6V, I = 200mA
O
= 2.5V, I = 200mA
O
I
= 3.6V
2.0
PFM/PWM TRANSITION
Load Current Threshold, PFM to PWM
V
V
= 3.6V, V
= 3.6V, V
= 3.3V
= 3.3V
200
75
mA
mA
MHz
°C
IN
IN
OUT
Load Current Threshold, PWM to PFM
External Synchronization Frequency Range
Thermal Shutdown
OUT
2.75
1.85
3.25
2.15
155
30
Thermal Shutdown Hysteresis
°C
BATTERY MONITOR AND POWER GOOD COMPARATORS
VT
Battery Monitor Voltage Threshold
Battery Monitor Voltage Hysteresis
Battery Monitor Debounce Time
PG Delay Time (Rising)
2.0
100
25
1
V
mV
µs
ms
µs
V
BMON
BMON
BMON
VH
t
PG Delay Time (Falling)
20
Minimum Supply Voltage for Valid PG Signal EN = VIN
1.2
PG
PG
PG Range - Lower (Rising)
PG Range - Lower (Falling)
PG Range - Upper (Rising)
PG Range - Upper (Falling)
Compliance Voltage - PG, BAT
Percentage of programmed voltage
Percentage of programmed voltage
Percentage of programmed voltage
Percentage of programmed voltage
90
87
%
RNGLR
RNGLF
RNGUR
RNGUF
%
PG
PG
112
110
%
%
V
= 3.6V, I
= 1mA
SINK
0.3
V
IN
FN7649.2
July 13, 2012
6
ISL9110, ISL9112
Analog Specifications V = V
= V = 3.6V, V = 3.3V, L1 = 2.2µH, C1 = C2 = 10µF, T = +25°C. Boldface limits apply over the
EN OUT A
operating temperature range, -40°C to +85°C. (Continued)
VIN
PVIN
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8) (Note 9) (Note 8) UNITS
LOGIC INPUTS
I
Input Leakage
0.05
1
µA
V
LEAK
V
Input HIGH Voltage
Input LOW Voltage
1.4
IH
V
0.4
V
IL
2
I C Interface Timing Specification For SCL, and SDA pins, unless otherwise noted.
MIN
TYP
MAX
SYMBOL
PARAMETER
Pin Capacitance
TEST CONDITIONS
(Note 8)
(Note 9) (Note 8) UNITS
C
(Note 11)
(Note 11)
15
400
50
pF
kHz
ns
pin
f
SCL Frequency
SCL
t
Pulse Width Suppression Time at SDA
and SCL Inputs
Any pulse narrower than the max spec is
suppressed (Note 11)
sp
t
SCL Falling Edge to SDA Output Data Valid SCL falling edge crossing V , until SDA exits the
IL
900
ns
ns
AA
V
to V window (Note 11)
IL
IH
t
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing V during a STOP condition, to SDA
IH
1300
BUF
crossing V during the following START
IH
condition (Note 11)
t
Clock LOW Time
Measured at the V crossings (Note 11)
IL
1300
600
ns
ns
ns
LOW
t
Clock HIGH Time
Measured at the V crossings (Note 11)
IH
HIGH
t
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
600
SU:STA
crossing V (Note 11)
IH
t
START Condition Hold Time
Input Data Set-up Time
Input Data Hold Time
From SDA falling edge crossing V to SCL falling
IL
600
100
0
ns
ns
ns
ns
ns
ns
HD:STA
edge crossing V (Note 11)
IH
t
From SDA exiting the V to V window, to SCL
IL IH
SU:DAT
rising edge crossing V (Note 11)
IL
t
From SCL rising edge crossing V to SDA
IH
HD:DAT
entering the V to V window (Note 11)
IL IH
t
STOP Condition Set-up Time
From SCL rising edge crossing V , to SDA rising
IH
600
1300
0
SU:STO
edge crossing V (Note 11)
IL
t
STOP Condition Hold Time for Read, or From SDA rising edge to SCL falling edge; both
Volatile Only Write
HD:STO
crossing V (Note 11)
IH
t
Output Data Hold Time
From SCL falling edge crossing V , until SDA
IL
DH
enters the V to V window (Note 11)
IL IH
t
SDA and SCL Rise Time
From V to V (Note 11)
IL IH
20 + 0.1 x Cb
250
250
400
ns
ns
R
t
SDA and SCL Fall Time
From V to V (Note 11)
IH IL
20 + 0.1 x Cb
F
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip (Note 11)
10
1
pF
kΩ
Rpu
SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by t and t
R F
For Cb = 400pF, max is about 2kΩ~2.5kΩ
For Cb = 40pF, max is about 15kΩ~20kΩ
(Note 11)
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Typical values are for T = +25°C and V = 3.6V.
IN
A
10. Quiescent current measurements are taken when the output is not switching.
11. ISL9112 only. Limits established by characterization and are not production tested.
FN7649.2
July 13, 2012
7
ISL9110, ISL9112
Typical Performance Curves
100
95
90
85
80
75
70
100
95
90
85
80
75
70
V
= 4.5V
IN
V
= 4V
IN
V
= 3V
IN
V
= 4.5V
IN
V
= 5V
IN
V
= 4V
IN
V
= 2V
V
= 2V
IN
IN
V
= 3V
IN
V
= 2.5V
IN
V
= 5V
IN
V
= 2.5V
IN
V
= 3.3V
V
= 2.0V
OUT
OUT
0.01
0.05
0.25
1.25
0.01
0.05
0.25
1.25
I
(A)
I
(A)
OUT
OUT
FIGURE 3. EFFICIENCY vs OUTPUT CURRENT, V
= 2V
FIGURE 4. EFFICIENCY vs OUTPUT CURRENT, V
= 3.3V
OUT
OUT
100
95
90
85
80
75
70
2.5
2.0
1.5
1.0
0.5
0.0
V
= 4V
IN
V
= 2V
OUT
V
= 5V
IN
V
= 4.5V
IN
V
= 3.3V
OUT
V
= 2V
IN
V
= 5V
OUT
V
= 2.5V
0.05
IN
V
= 3V
IN
V
= 4.0V
OUT
0.01
0.25
1.25
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
V
IN
I
(A)
OUT
FIGURE 5. EFFICIENCY vs OUTPUT CURRENT, V
= 4V
FIGURE 6. MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE
OUT
9
8
7
6
5
4
60
55
+85°C
50
+85°C
+25°C
+25°C
45
40
0°C
0°C
-40°C
35
-40°C
2.5
V
= 3.3V
OUT
V
= 3.3V
OUT
30
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
1.5
3.5
(V)
4.5
5.5
V
V
IN
IN
FIGURE 7. PWM MODE QUIESCENT CURRENT, V
NO LOAD
= 3.3V,
FIGURE 8. PFM MODE QUIESCENT CURRENT, V
NO LOAD
= 3.3V,
OUT
OUT
FN7649.2
July 13, 2012
8
ISL9110, ISL9112
Typical Performance Curves (Continued)
V
= 4.5V → 2.5V
V
= 2.5V → 4.5V
IN
IN
V
= 3.3V
V
= 3.3V
OUT
OUT
I
= 500mA
I
= 500mA
OUT
OUT
LX1
5V/DIV
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
400µs/DIV
400µs/DIV
FIGURE 9. STEADY STATE TRANSITION FROM BUCK TO BOOST
FIGURE 10. STEADY STATE TRANSITION FROM BOOST TO BUCK
LX1
2V/DIV
VOUT
50mV/DIV
LX2
2V/DIV
VIN
2V/DIV
VOUT
50mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
V
= 4.5V → 2.5V → 4.5V
IN
V
OUT
OUT
= 3.6V
= 3.3V
= 0.6A
IN
V
= 3.3V
OUT
V
I
I
= 400mA
OUT
50µs/DIV
400ns/DIV
FIGURE 11. STEADY STATE V NEAR V
IN
FIGURE 12. INPUT TRANSIENT
OUT
LX1
5V/DIV
LX1
5V/DIV
LX2
5V/DIV
LX2
5V/DIV
VOUT
VOUT
0.1V/DIV
0.1V/DIV
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
V
= 3.6V
= 3.3V
V
= 2V
IN
OUT
IN
= 3.3V
V
V
OUT
= 0A TO 0.4A
I
= 0A TO 1A
I
OUT
OUT
100µs/DIV
100µs/DIV
FIGURE 13. TRANSIENT LOAD RESPONSE
FIGURE 14. TRANSIENT LOAD RESPONSE
FN7649.2
July 13, 2012
9
ISL9110, ISL9112
Typical Performance Curves (Continued)
LX1
2V/DIV
LX1
5V/DIV
LX2
2V/DIV
LX2
5V/DIV
VOUT
10mV/DIV
VOUT
10mV/DIV
INDUCTOR
CURRENT
0.5A/DIV
INDUCTOR
CURRENT
0.5A/DIV
V
= 4.5V
= 3.3V
= 1A
IN
OUT
V
= 2.5V
= 3.3V
IN
OUT
V
V
I
OUT
I
= 500mA
OUT
400ns/DIV
400ns/DIV
FIGURE 15. SWITCHING WAVEFORMS, BOOST MODE
FIGURE 16. SWITCHING WAVEFORMS, BUCK MODE
0.25
0.25
0.20
0.15
0.10
0.05
0.00
0.20
0.15
0.10
0.05
0.00
+40°C
+40°C
-40°C
+85°C
+85°C
0°C
-40°C
0°C
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
1.5
2.0
2.5
3.0
3.5
(V)
4.0
4.5
5.0
5.5
V
V
IN
IN
FIGURE 17. NFET R
vs INPUT VOLTAGE
FIGURE 18. PFET R
vs INPUT VOLTAGE
DS(ON)
DS(ON)
3.290
3.285
3.280
3.275
3.270
0.810
0.805
0.800
0.795
0.790
NO LOAD
(PFM)
I
= 0.1A
(PFM)
OUT
I
= 0.8A (PWM)
OUT
I
= 1.2A
(PWM)
OUT
I
= 0.4A (PWM)
2.5
OUT
1.5
3.5
(V)
4.5
5.5
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
V
IN
FIGURE 19. V
vs TEMPERATURE, T = -40°C TO +85°C
A
FIGURE 20. OUTPUT VOLTAGE vs V VOLTAGE (V
IN
= 3.3V)
REF
OUT
FN7649.2
July 13, 2012
10
ISL9110, ISL9112
Typical Performance Curves (Continued)
V
V
I
= 4V
= 3.3V
V
= 2V
= 3.3V
IN
OUT
= 200mA
IN
V
I
OUT
= 200mA
LX1
2V/DIV
LX1
2V/DIV
OUT
OUT
LX2
2V/DIV
LX2
2V/DIV
VOUT
2V/DIV
VOUT
2V/DIV
EN
2V/DIV
EN
2V/DIV
400µs/DIV
400µs/DIV
FIGURE 21. SOFT-START, V = 4V, V
IN
= 3.3V
FIGURE 22. SOFT-START, V = 2V, V
IN
= 3.3V
OUT
OUT
3.315
3.310
3.305
3.300
3.295
3.290
3.285
3.310
3.305
3.300
3.295
3.290
3.285
3.280
LOAD CURRENT FALLING
LOAD CURRENT RISING
LOAD CURRENT RISING
LOAD CURRENT FALLING
3.280
0.0
0.0
0.1
0.2
I
0.3
0.4
0.5
0.1
0.2
0.3
0.4
0.5
I
(mA)
(mA)
OUT
OUT
FIGURE 23. OUTPUT VOLTAGE vs LOAD CURRENT
(V = 2.5V, V = 3.3V, AUTO PFM/PWM MODE)
FIGURE 24. OUTPUT VOLTAGE vs LOAD CURRENT
(V = 4.5V, V = 3.3V, AUTO PFM/PWM MODE)
IN
OUT
IN OUT
V
= 3.7V
= 3.3V
SCL
2V/DIV
IN
OUT
V
SDA
2V/DIV
EN
1V/DIV
VOUT
1V/DIV
V
= 5V
VOUT
IN
V
= 3.0V → 4.0V → 3.0V
200mV/DIV
OUT
SLEWRATE = 0b111
4ms/DIV
1ms/DIV
FIGURE 25. OUTPUT SOFT-DISCHARGE
FIGURE 26. DIGITAL SLEW OPERATION (ISL9112)
FN7649.2
July 13, 2012
11
ISL9110, ISL9112
The V
OUT
ramp time is not constant for all operating conditions.
Functional Description
Functional Overview
Refer to the “Block Diagram” on page 2. The ISL9110, ISL9112
implements a complete buck boost switching regulator, with
PWM controller, internal switches, references, protection
circuitry, and control inputs.
Soft-start into boost mode will take longer than soft-start into
buck mode. The total soft-start time into buck operating mode is
typically 2ms, whereas the typical soft-start time into boost
mode operating mode is typically 3ms. Increasing the load
current will increase these typical soft-start times.
Overcurrent Protection
The PWM controller automatically switches between buck and
boost modes as necessary to maintain a steady output voltage,
with changing input voltages and dynamic external loads.
When the current in the P-Channel MOSFET is sensed to reach
the current limit for 16 consecutive switching cycles, the internal
protection circuit is triggered, and switching is stopped for
approximately 20ms. The device then performs a soft-start cycle.
If the external output overcurrent condition exists after the
soft-start cycle, the device will again detect 16 consecutive
switching cycles reaching the peak current threshold. The
process will repeat as long as the external overcurrent condition
is present. This behavior is called ‘hiccup mode’.
The ISL9110 provides output-power-good and input-power-good
open-drain status outputs on pins 7 and 8. In the ISL9112, these
2
pins are used for an I C interface, allowing programmable output
voltage and access to the ultrasonic mode and slew rate limit
control bits.
Internal Supply and References
Referring to the “Block Diagram” on page 2, the ISL9110,
ISL9112 provides two power input pins. The PVIN pin supplies
input power to the DC/DC converter, while the VIN pin provides
Short Circuit Protection
The ISL9110, ISL9112 provides short-circuit protection by
monitoring the feedback voltage. When feedback voltage is
sensed to be lower than a certain threshold, the PWM oscillator
frequency is reduced in order to protect the device from damage.
The P-Channel MOSFET peak current limit remains active during
this state.
operating voltage source required for stable V
generation.
REF
Separate ground pins (GND and PGND) are provided to avoid
problems caused by ground shift due to the high switching
currents.
Undervoltage Lockout
Enable Input
The undervoltage lockout (UVLO) feature prevents abnormal
operation in the event that the supply voltage is too low to
guarantee proper operation. When the VIN voltage falls below the
UVLO threshold, the regulator is disabled.
A master enable pin EN allows the device to be enabled. Driving
EN low invokes a power-down mode, where most internal device
functions, including input and output power good detection, are
disabled.
PG Status Output (ISL9110 only)
Soft Discharge
When the device is disabled by driving EN low, an internal resistor
between VOUT and GND is activated. This internal resistor has
typical 120Ω resistance.
An open drain output-power-good signal is provided in the
ISL9110. An internal window comparator is used to detect when
VOUT is significantly higher or lower than the target output
voltage. The PG output will be driven low when sensed VOUT
voltage is outside of this ‘power good’ window. When VOUT
voltage is inside the ‘power good’ window, the PG pin goes Hi-Z.
POR Sequence and Soft-start
Bringing the EN pin high allows the device to power-up. A number
of events occur during the start-up sequence. The internal voltage
reference powers up, and stabilizes. The device then starts
operating. There is a typical 1ms delay between assertion of the
EN pin and the start of switching regulator soft-start ramp.
The PG detection circuit detects this condition by monitoring
voltage on the FB pin. Hysteresis is provided for the upper and
lower PG thresholds to avoid oscillation of the PG output.
BAT Status Output (ISL9110 only)
The ISL9110 provides an open drain input-power-good status
output. The BAT status pin will be driven low when VIN rises
The soft-start feature minimizes output voltage overshoot and
input inrush currents. During soft-start, the reference voltage is
ramped to provide a ramping V
voltage. While output voltage
OUT
above the VT
threshold. The BAT status output goes Hi-Z
threshold. Hysteresis is
threshold to avoid oscillation of the BAT
BMON
is lower than approximately 20% of the target output voltage,
switching frequency is reduced to a fraction of the normal
switching frequency to aid in producing low duty cycles necessary
to avoid input inrush current spikes. Once the output voltage
exceeds 20% of the target voltage, switching frequency is
increased to its nominal value.
when V
falls below the VT
BMON
BAT
provided for the VT
output.
BMON
Ultrasonic Mode (ISL9112 only)
The ISL9112 provides an ultrasonic mode that can be enabled
2
When the target output voltage is higher than the input voltage,
there will be a transition from buck mode to boost mode during
the soft-start sequence. At the time of this transition, the ramp
rate of the reference voltage is decreased, such that the output
voltage slew rate is decreased. This provides a slower output
voltage slew rate.
through I C control by setting the ULTRA bit in the control register.
In ultrasonic mode, the PFM switching frequency is forced to be
above the audio frequency range.
This ultrasonic mode applies only to PFM mode operation. With
the ULTRA bit set to ‘1’, PFM mode switching frequency is forced
FN7649.2
July 13, 2012
12
ISL9110, ISL9112
well above the audio frequency range (f
SW
60kHz). This mode of operation, however, reduces the efficiency
at light load.
becomes typically
During PFM operation in boost mode, the ISL9110, ISL9112
closes Switch A and Switch C to ramp up the current in the
inductor. When inductor current reaches a certain threshold, the
device turns off Switches A and C, then turns on Switches B and
D. With Switches B and D closed, output voltage increases as the
inductor current ramps down.
Thermal Shutdown
A built-in thermal protection feature protects the ISL9110,
ISL9112 if the die temperature reaches +155°C (typical). At this
die temperature, the regulator is completely shut down. The die
temperature continues to be monitored in this thermal-shutdown
mode. When the die temperature falls to +125°C (typical), the
device will resume normal operation.
In most operating conditions, there will be multiple PFM pulses
to charge up the output capacitor. These pulses continue until
V
has achieved the upper threshold of the PFM hysteretic
OUT
controller. Switching then stops, and remains stopped until V
OUT
decays to the lower threshold of the hysteretic PFM controller.
When exiting thermal shutdown, the ISL9110, ISL9112 will
execute its soft-start sequence.
Operation With VIN Close to VOUT
When the output voltage is close to the input voltage, the
ISL9110, ISL9112 will rapidly and smoothly switch from boost to
buck mode as needed to maintain the regulated output voltage.
This behavior provides excellent efficiency and very low output
voltage ripple.
External Synchronization
An external sync feature is provided. Applying a clock signal with
a frequency between 2.75MHz and 3.25MHz at the MODE/SYNC
input forces the ISL9110, ISL9112 to synchronize to this external
clock. The MODE/SYNC input supports standard logic levels.
Output Voltage Programming
Buck-Boost Conversion Topology
The ISL9110 is available in fixed and adjustable output voltage
versions. To use the fixed output version, the VOUT pin must be
connected directly to FB.
The ISL9110, ISL9112 operates in either buck or boost mode.
When operating in conditions where VIN is close to VOUT, the
ISL9110 alternates between buck and boost mode as necessary
to provide a regulated output voltage.
In the adjustable output voltage version (ISL9110IRTAZ), an
external resistor divider is required to program the output
voltage. The FB pin has very low input leakage current, so it is
possible to use large value resistors (e.g. R1 = 1MΩ and
R2 = 324kΩ) in the resistor divider connected to the FB input.
L1
LX1
LX2
4
2
SWITCH A
SWITCH D
The ISL9112 is available in a fixed output version only. The
factory programmed output voltage can be changed via the I C
PVIN
5
1
VOUT
2
interface. Details about the ISL9112 programmable VOUT
voltage can be found in the section “Register Description
(ISL9112)” on page 13.
SWITCH B
SWITCH C
Digital Slew Rate Control (ISL9112 only)
When changing voltages using the I C interface, the ISL9110 can
FIGURE 27. BUCK BOOST TOPOLOGY
2
be programmed to control the rate of voltage increase or
decrease as it transitions from one voltage setting to the next.
Figure 27 shows a simplified diagram of the internal switches
and external inductor.
The default configuration disables this digital slew rate feature.
To enable the slew rate feature, an I C command is sent to the
PWM Operation
2
In buck PWM mode, Switch D is continuously closed, and Switch
C is continuously open. Switches A and B operate as a
synchronous buck converter when in this mode.
ISL9112, changing the value of the SLEWRATE bit field to a value
other than 0b000. Details about the digital slew rate settings can
be found in Table 3.
In boost PWM mode, Switch A remains closed and Switch B
remains open. Switches C and D operate as a synchronous boost
converter when in this mode.
Register Description (ISL9112)
The ISL9112 has a two I C accessible control registers that are
2
used to set output voltage, operating mode, and digital slew rate.
These registers can be read and written to at any time that the
ISL9112 is enabled. Attempts to communicate with the ISL9112
PFM Operation
During PFM operation in buck mode, Switch D is continuously
closed, and Switch C is continuously open. Switches A and B
operate in discontinuous mode during PFM operation.
2
via its I C interface when the ISL9112 is disabled (EN = Low) are
not supported.
FN7649.2
July 13, 2012
13
ISL9110, ISL9112
TABLE 2. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE (Continued)
TABLE 1. REGISTER ADDRESS 0x00: VOLTAGE CONTROL
OUTPUT VOLTAGE
(V)
BIT NAME TYPE RESET
4:0 DCDOUT R/W 00000 V
DESCRIPTION
DCDOUT[4:0]
0b10010
0b10011
0b10100
0b10101
0b10110
0b10111
0b11000
0b11001
0b11010
0b11011
0b11100
0b11101
0b11110
0b11111
programming. See Table 2.
OUT
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
5
ULTRA R/W
0
Ultrasonic mode select. Not applicable in
forced PWM mode:
0: Ultrasonic feature disabled
1: Ultrasonic feature enabled
6
7
Reserved R/W
I2CEN R/W
0
0
2
I C programming enable bit:
2
0: Device ignores I C command, and uses
last programmed DCDOUT and ULTRA
settings; or if no I C communication has
occurred since POR, the factory
programmed default DCDOUT and ULTRA
settings are used.
1: Device uses the I C programmed
DCDOUT and ULTRA settings.
2
2
Bits DCDOUT[4:0] set the output voltage, as shown in Equation 1
and Table 2. The ISL9112 output voltage range is 1.9V to 5.0V.
(EQ. 1)
V
= 1.9V + (n • 0.1V), where n = 0 to 31
OUT
A safety mechanism is provided to prevent unintentional changes to
the output voltage by errant host software. The MSB of the control
register (I2CEN bit, see Table 1) must be set to ‘1’ in order for the
TABLE 3. REGISTER ADDRESS 0x01: SLEW RATE CONTROL
BIT
NAME
TYPE
R/W
RESET
000
DESCRIPTION
2
ISL9112 to recognize the I C command as valid. If a value of ‘0’ is
2
written to this bit, the I C command is ignored, and output voltage
2:0 SLEWRATE
Slew rate control (typ),
expressed as µs per LSB
change in DCDOUT value:
0b000 = 0µs/ΔLSB
and operating mode will revert to the factory programmed default
(3.3V for ISL9112IRTNZ; 5V for ISL9112IRT7Z).
TABLE 2. DCDOUT[4:0] VALUE vs OUTPUT VOLTAGE
0b001 = 1.5µs/ΔLSB
0b010 = 3.1µs/ΔLSB
0b011 = 6.3µs/ΔLSB
0b100 = 12.5µs/ΔLSB
0b101 = 25µs/ΔLSB
0b110 = 50µs/ΔLSB
0b111 = 100µ /ΔLSB
OUTPUT VOLTAGE
DCDOUT[4:0]
0b00000
0b00001
0b00010
0b00011
0b00100
0b00101
0b00110
0b00111
0b01000
0b01001
0b01010
0b01011
0b01100
0b01101
0b01110
0b01111
0b10000
0b10001
(V)
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
7:3
Reserved
R/W
00000
2
I C Serial Interface (ISL9112)
The ISL9112 supports a bi-directional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL9112 operates as a slave device in all
applications.
2
All communication over the I C interface is conducted by sending
the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 28). Upon
power-up of the ISL9112, the SDA pin is in the input mode.
FN7649.2
July 13, 2012
14
ISL9110, ISL9112
2
All I C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL9112 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 28). A START condition is ignored
during the power-up sequence and when EN input is low.
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte (containing the Slave Address with the R/W
bit set to 0), a valid Register Address Byte, a Data Byte, and a
STOP condition. After each of the three bytes, the ISL9112
responds with an ACK. The master will then send a STOP to
complete the command.
2
All I C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 28). A STOP condition at the end of a write
operation initiates the reconfiguration of the ISL9112’s voltage
feedback loop as necessary to provide the programmed output
voltage.
STOP conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and its
associated ACK signal. If a STOP condition is issued in the middle
of a data byte, or before 1 full data byte + ACK is sent, then the
ISL9112 will ignore the command, and not change output
voltage or other settings.
An ACK, Acknowledge, is a software convention used to indicate
a successful data transfer. The transmitting device, either master
or slave, releases the SDA bus after transmitting eight bits.
During the ninth clock cycle, the receiver pulls the SDA line LOW
to acknowledge the reception of the eight bits of data (see
Figure 29).
Read Operation
A Read operation is shown in Figure 31. It consists of 4 bytes. The
host generates a START condition, then transmits an Identification
byte (containing the Slave Address with the R/W bit set to 0). The
ISL9112 responds with an ACK. The host then transmits the
Register Address byte, and the ISL9112 responds with another ACK.
The ISL9112 responds with an ACK after recognition of a START
condition followed by a valid Identification Byte, and once again
after successful receipt of a Register Address Byte. The ISL9112
also responds with an ACK after receiving a Data Byte of a write
operation. The master must respond with an ACK after receiving
a Data Byte of a read operation.
The host then generates a Repeat START condition, or a STOP
condition followed by a START condition. The host then transmits
an Identification byte (containing the Slave Address with the R/W
bit set to 1). The ISL9112 responds with an ACK, indicating it is
ready to begin providing the requested data.
A valid Identification Byte contains 0b0011100 as the seven
2
MSBs, corresponding to the ISL9112 I C Slave Address. The LSB
The ISL9112 then transmits the data byte by asserting control of
the SDA pin while the host generates clock pulses on the SCL pin.
When transmission of the data byte is complete, the host
generates a NACK condition followed by a STOP condition. This
of the Identification byte is the Read/Write bit. Its value is “1” for
a Read operation, and “0” for a Write operations (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT
2
completes the I C Read operation.
0
0
1
1
1
0
0
R/W
The ISL9112 register map supports only one register, at register
address 0x00. Attempts to read other register addresses are not
supported, and should not be attempted. Similarly, I C block
(MSB)
(LSB)
2
reads and writes are not supported by the ISL9112. The ISL9112
has only one register to read or write, therefore block reads and
writes are not necessary.
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE
CHANGE
STABLE
FIGURE 28. VALID DATA CHANGES, START AND STOP CONDITIONS
FN7649.2
July 13, 2012
15
ISL9110, ISL9112
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT
FROM RECEIVER
START
ACK
FIGURE 29. ACKNOWLEDGE RESPONSE FROM RECEIVER
ISL9112 I2C W RITE PRO TOCO L
SYSTEM HO ST
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
A
DATA BYTE
A
P
ISL9112
A – ACKNO W LEDGE
N – NO T
ACKNO W LEDG E
S – START
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
DCDV1
(5 BITS)
R/W
P – STOP
2
FIGURE 30. I C REGISTER WRITE PROTOCOL
ISL9112 I2C READ PROTOCOL #1
SYSTEM
HOST
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
A
S
0
0
1
1
1
0
0
1
A
DATA BYTE
N
P
ISL9112
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
I2C SLAVE
7-BIT ADDRESS
DCDV1
(5 BITS)
A – ACKNOWLEDGE
N – NOT
ACKNOWLEDGE
S – START
R/W
R/W
P – STOP
ISL9112 I2C READ PROTOCOL #2
S
0
0
1
1
1
0
0
0
A
0
0
0
0
0
0
0
0
A
P
S
0
0
1
1
1
0
0
1
A
DATA BYTE
N
P
I2C SLAVE
7-BIT ADDRESS
REGISTER
ADDRESS = 0x00
I2C SLAVE
7-BIT ADDRESS
DCDV1
(5 BITS)
R/W
R/W
2
FIGURE 31. I C REGISTER READ PROTOCOL
FN7649.2
July 13, 2012
16
ISL9110, ISL9112
Non-Adjustable Version FB Pin Connection
The fixed output versions of the ISL9110 and the I C-adjustable
ISL9112 do not require external resistors or a capacitor on the FB
pin. Simply connect VOUT to FB, as shown in Figure 33.
Applications Information
Component Selection
The ISL9112 and the fixed-output versions of the ISL9110
require only three external power components to implement the
buck boost converter: an inductor, an input capacitor, and an
output capacitor.
2
VIN
=
ISL9112
1.8V TO 5.5V
5
4
PVIN
LX1
C1
L1
10µF
2.2µH
2
1
The adjustable ISL9110 versions require three additional
components to program the output voltage. Two external
resistors program the output voltage, and a small capacitor is
added to improve stability and response.
6
10
9
8
7
LX2
VIN
C3
0.1µF
VOUT
=
MODE VOUT
EN
3.3V/1A
I2C
BUS
C2
10µF
SDA
SCL
12
FB
An optional input supply filtering capacitor (“C3” in Figure 32)
can be used to reduce the supply noise on the VIN pin, which
provides power to the internal reference. In most applications,
this capacitor is not needed.
FIGURE 33. TYPICAL ISL9110IRTNZ APPLICATION
VIN
=
ISL9110
PVIN
1.8V TO 5.5V
5
4
LX1
C1
L1
2.2µH
Inductor Selection
10µF
2
1
6
10
9
8
7
VIN
LX2
An inductor with high frequency core material (e.g. ferrite core)
should be used to minimize core losses and provide good
efficiency. The inductor must be able to handle the peak
switching currents without saturating.
C3
0.1µF
VOUT
3.3V/1A
=
MODE
EN
VOUT
C4
56pF
R1
1M
C2
10µF
BAT
PG
12
STATUS
OUTPUTS
FB
R2
324k
A 2.2µH inductor with ≥2.4A saturation current rating is
recommended. Select an inductor with low DCR to provide good
efficiency. In applications where radiated noise must be
minimized, a toroidal or shielded inductor can be used.
FIGURE 32. TYPICAL ISL9110IRTAZ APPLICATION
TABLE 5. INDUCTOR VENDOR INFORMATION
MANUFACTURER
Coilcraft
SERIES
LPS4018
WEBSITE
www.coilcraft.com
www.murata.com
www.t-yuden.com
Output Voltage Programming, Adj. Version
Setting and controlling the output voltage of the ISL9110IRTAZ
(adjustable output version) can be accomplished by selecting the
external resistor values.
Murata
LQH44P
Taiyo Yuden
NRS4018
NRS5012
Equation 2 can be used to derive the R1 and R2 resistor values:
R1
R2
⎛
⎞
⎠
(EQ. 2)
-------
V
= 0.8V • 1 +
Sumida
Toko
CDRH3D23/HP www.sumida.com
CDRH4D22/HP
OUT
⎝
When designing a PCB, include a GND guard band around the
feedback resistor network to reduce noise and improve accuracy
and stability. Resistors R1 and R2 should be positioned close to
the FB pin.
DEM3518C
www.toko.co.jp
PVIN and VOUT Capacitor Selection
The input and output capacitors should be ceramic X5R type with
low ESL and ESR. The recommended input capacitor value is
10µF. The recommended VOUT capacitor value is 10µF to 22µF.
Feed-Forward Capacitor Selection
A small capacitor in parallel with resistor R1 is required to
provide the specified load and line regulation. The suggested
value of this capacitor is 56pF for R1 = 1MΩ. An NPO type
capacitor is recommended.
TABLE 6. CAPACITOR VENDOR INFORMATION
MANUFACTURER
AVX
SERIES
WEBSITE
www.avx.com
X5R
X5R
X5R
X5R
Murata
Taiyo Yuden
TDK
www.murata.com
www.t-yuden.com
www.tdk.com
FN7649.2
July 13, 2012
17
ISL9110, ISL9112
Application Example 1.
An application using the fixed-output ISL9110IRTNZ is shown in
Figure 34. This application requires only three external
components.
VIN
=
ISL9110IRTNZ
1.8V TO 5.5V
5
4
PVIN
LX1
C1
L1
10µF
2.2µH
2
1
6
10
9
8
7
VIN
LX2
VOUT
=
MODE VOUT
EN
BAT
3.3V/1A
C2
10µF
12
STATUS
OUTPUTS
FB
PG
FIGURE 34. TYPICAL ISL9110IRTNZ APPLICATION
Application Example 2.
An application requiring V
= 3.0V, using the adjustable-output
OUT
ISL9110IRTAZ is shown in Figure 35. This application requires six
external components.
VIN
=
ISL9110IRTAZ
1.8V TO 5.5V
5
4
PVIN
LX1
C1
L1
10µF
2.2µH
2
1
6
10
9
8
7
VIN
LX2
VOUT
=
MODE VOUT
EN
BAT
3.0V/1A
C4
56pF
R1
1M
FIGURE 37. RECOMMENDED PCB LAYOUT
C2
10µF
12
STATUS
OUTPUTS
FB
PG
R2
365k
The TDFN Package Requires Additional PCB
Layout Rules for the Thermal Pad
The thermal pad is electrically connected to the PGND supply. Its
primary function is to provide heat sinking for the IC. However,
because of the connection to PGND, the thermal pad must be
tied to the GND supply to prevent unwanted current flow to the
thermal pad. Maximum AC performance is achieved if the
thermal pad is attached to a dedicated ground layer in a
multi-layered PC board.
FIGURE 35. TYPICAL ISL9110IRTAZ APPLICATION
Application Example 3.
2
An application requiring V
= 3.3V, using the I C-controllable
OUT
ISL9112IRTNZ is shown in Figure 36. This application requires
three external components. Output voltage can be changed via
I C control.
2
The thermal pad requirements are proportional to power
dissipation and ambient temperature. A dedicated layer
eliminates the need for individual thermal pad area. When a
dedicated layer is not possible, an isolated thermal pad on
another layer should be used. Pad area requirements should be
evaluated on a case by case basis.
VIN
=
ISL9112IRTNZ
1.8V TO 5.5V
5
4
PVIN
LX1
C1
L1
10µF
2.2µH
2
1
6
10
9
8
7
LX2
VIN
VOUT
3.3V/1A
=
MODE VOUT
EN
I2C
BUS
C2
10µF
SDA
SCL
12
FB
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
FIGURE 36. TYPICAL ISL9112IRTNZ APPLICATION
Recommended PCB Layout
Correct PCB layout is critical for proper operation of the ISL9110.
The input and output capacitors should be positioned as closely
to the IC as possible. The ground connections of the input and
output capacitors should be kept as short as possible, and
should be on the component layer to avoid problems that are
caused by high switching currents flowing through PCB vias.
FIGURE 38. PCB VIA PATTERN
FN7649.2
July 13, 2012
18
ISL9110, ISL9112
We recommend that you fill the thermal pad area with vias. Fill
the thermal pad area with vias that are spaced 3x their radius
(typically), center-to-center, from each other. Keep the vias small
but not so small that their inside diameter prevents solder
wicking through the holes during reflow.
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias to the ground plane. Instead use a solid
connection with no gaps for improved thermal performance.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7649.2
CHANGE
June 28, 2012
May 17, 2012
Corrected Application Note titles in “Related Literature” on page 1.
On page 2, pin configuration diagrams, changed "MODE" to "MODE/SYNC".
On page 3, added ISL9110BIRTAZ to ordering table.
On page 3, added "Hiccup Mode" column in ordering table.
On page 3, corrected Evaluation Board numbers.
On page 13, corrected "EN/SYNC", to "MODE/SYNC" in “External Synchronization”
August 30, 2011
FN7649.1
Page 3:
Removed "ISL9110EVAL1Z" from “Ordering Information” table
Added "ISL9110IRTAZ-EVAL1Z" to “Ordering Information” table
Added "ISL9110IRTNZ-EVAL1Z" to “Ordering Information” table
Added "ISL9110IRT7Z-EVAL1Z" to “Ordering Information” table
Added "ISL9112IRT7Z-EVAL1Z" to “Ordering Information” table
“Inductor Selection” on page 17:
Corrected "A 10µH inductor.." to "A 2.2µH inductor.."
Initial release.
June 16, 2011
FN7649.0
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL9110, ISL9112
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7649.2
July 13, 2012
19
ISL9110, ISL9112
Package Outline Drawing
L12.3x3C
12 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (0.4mm PITCH)
Rev 0, 11/09
3.00
6
A
PIN #1
INDEX AREA
B
6
PIN 1
INDEX AREA
0.40
2.45±0.1
0.15
(4X)
12x 0.20
0.10M C A B
1.70±0.1
12x 0.40
4
0.20 ±0.05
TOP VIEW
BOTTOM VIEW
PACKAGE
OUTLINE
SEE DETAIL "X"
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
0 . 75
(12 x0.20)
SIDE VIEW
2.45
(10 x0.40)
5
C
0 . 2 REF
(12 x0.20)
(12 x0.40)
1.70
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7649.2
July 13, 2012
20
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