ISL94208_14 [INTERSIL]
4- to 6-Cell Li-ion Battery Management Analog Front-End;
| 型号： | ISL94208_14 |
| 厂家： | 
Intersil |
| 描述： | 4- to 6-Cell Li-ion Battery Management Analog Front-End 电池 |
| 文件： | 总36页 (文件大小：916K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4- to 6-Cell Li-ion Battery Management Analog
Front-End
ISL94208
Features
The ISL94208 battery management IC is designed for use with
a microcontroller and features an analog front-end with
overcurrent protection for multi-cell Li-ion battery packs. The
ISL94208 supports battery packs consisting of 4 to 6 cells in
series and one or more cells in parallel.
• Software selectable overcurrent protection levels and
variable protect detection times
- 4 discharge overcurrent thresholds
- 4 short circuit thresholds
- 4 charge overcurrent thresholds
- 8 overcurrent delay times (charge)
- 8 overcurrent delay times (discharge)
- 2 short circuit delay times (discharge)
Using an internal analog multiplexer, the ISL94208 allows a
separate microcontroller with an A/D converter to monitor
each cell voltage plus internal and external temperature.
The ISL94208 provides integral overcurrent and short circuit
protection circuitry, an internal 3.3V voltage regulator, internal
cell balancing switches, and drive circuitry for external FET
devices for control of pack charge and discharge.
• Automatic FET turn-off and cell balance disable on reaching
external (battery) or internal (IC) temperature limit
• Automatic cell balance turn off on IC over-temperature
• Integrated charge/discharge FET drive circuitry
Related Literature
• ISL94208EVZ Evaluation Kit User Guide
• Internal cell balancing FETs handle up to 200mA of
balancing current for each cell
• Sleep operation with negative or positive edge wake-up
• <10µA Sleep mode
Applications
• Power tools
• Portable equipment
• Battery backup systems
• Military electronics
P+
ISL94208
VCC
VBACK
WKUP
VCELL6
CB6
VCELL5
RGC
CB5
RGO
VCELL4
µC
CB4
SCL
SCL
VCC
VFET2
SDA
SDA
VCELL3
TEMPI
CB3
RESET
TEMP3V
VFET1
INT
CHRG
VCELL2
AO
A/D INPUT
I/O
CB2
VMON
VBACK
CFET
DFET
VCELL1
CB1
VCELL0
B-
VSS
P-
FIGURE 1. TYPICAL APPLICATION
June 21, 2013
FN8306.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL94208
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL94208IRZ
ISL94208EVZ
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
94208 IRZ
-40 to +85
32 Ld 5x5 QFN
L32.5x5B
Evaluation Board
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL94208. For more information on MSL, please see tech brief TB363
Pin Configuration
ISL94208
(32 LD QFN)
TOP VIEW
32 31 30 29 28 27 26 25
TEMPI
24
23
22
21
20
19
18
17
1
2
3
4
VCC
AO
VCELL6
VMON
CFET
CB6
VCELL5
CB5
PAD
DFET
5
6
7
8
CSENSE
DSENSE
VCELL4
CB4
VCELL3
ISREF
9
10 11 12 13 14 15 16
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1
VCC
VCC supply. This pin provides the operating voltage for the IC circuitry. Connect to the positive terminal of the
battery pack through a filter.
14, 12,
10, 8,
6, 4,
2
VCELL0, VCELL1, Battery terminal N voltage input. For N = 1 to 6, VCELLN connects to the positive terminal of CELLN and the
VCELL2, VCELL3, negative terminal of CELLN + 1.
VCELL4, VCELL5,
VCELL6
13
VBACK
Sleep mode backup supply. This pin is used to power the logic when the device is asleep and the RGO output
turns off.
31, 32
VFET1, VFET2
FET Drivers power Supply. These pins are used to provide the reference voltages for the power FET gate drivers.
Typically VFET2 connects to VCELL3 (or equivalent voltage) and VFET1 connects to VCELL2 (or equivalent
voltage).
15,11, 9
7, 5, 3
CB1, CB2, CB3, Cell balancing FET driver output N (N = 1 to 6). An internal FET between the CBN and the VCELL(N - 1) can be
CB4, CB5, CB6 turned on to discharge CELLN more than other cells, or to shunt some of the charging current away from CELLN.
This function is used to reduce the voltage on an individual cell relative to other cells in the pack. The cell
balancing FETs are turned on or off by an external controller, using the I2C interface.
16
VSS
Ground. This pin connects to the most negative terminal in the battery string.
FN8306.1
June 21, 2013
2
ISL94208
Pin Descriptions(Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
17
ISREF
Current sense reference. This input provides a separate reference point for the charge and discharge current
monitoring circuits. WIth a separate reference connection, it is possible to minimize errors that result from
voltage drops on the ground lead when the load is drawing large currents. If a separate reference is not
necessary, connect this pin to VSS.
18
19
20
DSENSE
CSENSE
DFET
Discharge current sense monitor. This input monitors the discharge current by monitoring a voltage across a
sense resistor, or across the discharge path FET, or by using a FET with a current sense pin. The voltage on this
pin is measured with reference to ISREF.
Charge current sense monitor. This input monitors the charge current by monitoring a voltage across a sense
resistor, or the voltage across the charge path FET, or by using a FET with a current sense pin. The voltage on
this pin is measured with reference to ISREF.
Discharge FET control. The ISL94208 controls the gate of a discharge path FET through this pin. The power FET
is an N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the
microcontroller, but the ISL94208 also turns off the FET in the event of an overcurrent or short circuit condition.
If the microcontroller detects an undervoltage condition on any of the battery cells, it can turn off the discharge
FET by controlling this output with a control bit.
21
22
CFET
Charge FET control. The ISL94208 controls the gate of a charge path FET through this pin. The power FET is an
N-Channel device. The FET is turned on only by the microcontroller. The FET can be turned off by the
microcontroller, but the ISL94208 also turns off the FET in the event of an overcurrent condition. If the
microcontroller detects an overvoltage condition on any of the battery cells, it can turn off the FET by controlling
this output with a control bit.
VMON
Discharge load monitoring. In the event of an overcurrent or short circuit condition, the microcontroller can
enable an internal resistor that connects between the VMON pin and VSS. When the FETs open because of an
overcurrent or short circuit condition and the load remains, the voltage at VMON will be near the VCC voltage.
When the load is released, the voltage at VMON drops below a threshold indicating that the overcurrent or short
circuit condition is resolved. At this point, the LDFAIL flag is cleared and operation can resume.
23
24
AO
Analog multiplexer output. The analog output pin is used to monitor the cell voltages and temperature sensor
voltages. An external microcontroller selects the specific voltage being applied to the output by writing to a
control register.
TEMPI
Temperature monitor input. The voltage across a thermistor is monitored at this pin to determine the
temperature of the battery cells. When this input drops below TEMP3V/13, an external over-temperature
condition is reported. The TEMPI voltage can be fed to the AO output pin through an analog multiplexer to be
monitored by the microcontroller.
25
26
TEMP3V
Temperature monitor output control. This pin outputs a voltage to be used in a divider that consists of a fixed
resistor and a thermistor. The thermistor is located in close proximity to the battery cells. The TEMP3V output is
connected internally to the RGO voltage through a PMOS switch only during a measurement of the temperature,
otherwise the TEMP3V output is off. The TEMP3V output can be turned on continuously with a special control bit.
Microcontroller wake up control. The TEMP3V pin is also turned on when any of the DSC, DOC, or COC bits are
set. This can be used to wake up a sleeping microcontroller to respond to overcurrent conditions with its own
control mechanism.
RGO
Regulated output voltage. This pin connects to the emitter of an external NPN transistor and works in
conjunction with the RGC pin to provide a regulated 3.3V. The voltage at this pin provides feedback for the
regulator and power for many of the ISL94208 internal circuits as well as providing the 3.3V output voltage for
the microcontroller and other external circuits.
27
28
RGC
Regulated output control. This pin connects to the base of an external NPN transistor and works in conjunction
with the RGO pin to provide a regulated 3.3V. The RGC output provides the control signal for the external
transistor to provide the 3.3V regulated voltage on the RGO pin.
WKUP
Wake up voltage. This input wakes up the part when the voltage crosses a turn-on threshold (wake up is edge
triggered). The condition of the pin is reflected in the WKUP bit (the WKUP bit is level sensitive).
WKPOL bit = “1”: the device wakes up on the rising edge of the WKUP pin. The WKUP bit is HIGH only when the
WKUP pin voltage > threshold.
WKPOL bit = “0”, the device wakes up on the falling edge of the WKUP pin. The WKUP bit is HIGH only when the
WKUP pin voltage < threshold.
FN8306.1
June 21, 2013
3
ISL94208
Pin Descriptions(Continued)
PIN NUMBER
PIN NAME
DESCRIPTION
29
SDA
Serial Data. This is the bidirectional data line for an I2C interface. This pin should be pulled up to 3.3V using a
resistor.
30
-
SCL
Serial Clock. This is the clock input for an I2C communication link. This pin should be pulled up to 3.3V using a
resistor.
PAD
Thermal Pad. Connect to VSS.
Block Diagram
TEMPI TEMP3V
VCC
VCELL6
VCELL5
VCELL4
VCELL3
VCELL2
VCELL1
VCELL0
TEMPERATURE
3.3VDC
RGC
RGO
VSS
SENSOR
REGULATOR
CIRCUITS
CELL
VOLTAGES
2
AO
6
CB6
CB5
CB4
CB3
CB2
CB1
I2C, CONTROL
LOGIC, REGISTERS,
OSCILLATOR
SCL
SDA
CELL
BALANCE
CIRCUITS
OVERCURRENT
CIRCUITS
FET CONTROL
CIRCUITRY
POWER
BACKUP
SUPPLY
WKUP
CONTROL
FN8306.1
June 21, 2013
4
ISL94208
Table of Contents
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Wake Up Timing (WKPOL = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Wake Up Timing (WKPOL = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Change in Voltage Source, FET Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Automatic Temperature Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Discharge Overcurrent/Short Circuit Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Charge Overcurrent Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Serial Interface Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Symbol Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Device Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Battery Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
System Power-Up/Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WKUP Pin Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
WKPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
WKPOL = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Protection Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overcurrent Safety Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Load Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Over-Temperature Safety Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Analog Multiplexer Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Temperature Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cell Balancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Definition of Cell Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Cell Balance Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
External VMON/CFET Protection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
User Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interface Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Clock and Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Start Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Acknowledge (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Current Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Operation State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Application Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Integrated Charge/Discharge Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Separate Charge/Discharge Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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5
ISL94208
PC Board Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Alternate VFET Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
FN8306.1
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6
ISL94208
Absolute Maximum Ratings (Note 4)
Thermal Information
Power Supply Voltage, V
Cell voltage, VCELL
-0.5V to 36.0V
Thermal Resistance (Typical)
32 Ld QFN (Notes 5, 6) . . . . . . . . . . . . . . . .
θ
JA (°C/W)
30
θ
JC (°C/W)
CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7
VCELLn (n = 5, 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 27.0V
VCELLn (n = 3, 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V
VCELLn (n = 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 9.0V
VCELLn - VCELLn-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . -0.5V to 5V
VCELL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5V
VCELL0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 0.5V
Cell Balance, CB
CB6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 36V
CB6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
CB4, CB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 27V
CB4, CB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC + 0.5V
CB2, CB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 18.0V
CB1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
CBn -VCn-1 (n = 1, 2, 3, 4, 5, 6) . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 7.0V
FET Control
Continuous Package Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . .400mW
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions (Note 4)
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Voltage:
VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 26.4V
SCL, SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 3.6V
VBACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCELL1 or 2.0V to 4.6V
VCELL1 - VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VCELLn - VCELLn-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 4.3V
VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 to 8.6
VFET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 to 12.9
VFET2 - VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 4.5V
ISREF - VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1V to 0.1V
(CSENSE - ISREF), (DSENSE - ISREF) . . . . . . . . . . . . . . . . . . . . -0.5V to 1.5V
DFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VFET2
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VFET2
WKUP (WKPOL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VBACK
WKUP (WKPOL=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 27V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VCC
VFET2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 18V
VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 to 13V
VFET2-VFET1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 5V
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18.0V to 18V
CFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-18.0V to VVFET2 + 0.5V
DFET
-0.5V to 18V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VVFET2 + 0.5V
Terminal Voltage,
SCL, SDA, CSENSE, DSENSE, TEMPI, RGO, AO, TEMP3V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5 to V
+ 0.5V
RGO
ISREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5V to V + 0.5
SS
- 0.5 to 5V
VBACK, RGC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to 36V
VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VCC + 0.5V
WKUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .- 0.5V to 27V
WKUP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.5V to VCC + 0.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. All Absolute Maximum Ratings and Recommended Operating Conditions referenced to VSS, unless otherwise noted.
5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
6. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
Power-Up Condition 1
SYMBOL
TEST CONDITION
(Note 7)
TYP
4
(Note 7)
UNIT
VPORVCC VCC voltage (Note 8)
6.5
V
V
V
Power-Up Condition 2 Threshold
(Rising)
VPOR
VBACK - VSS (rising) (Note 8)
1.6
1.55
2.05
1.95
0°C to +60°C
Power-Up Condition 2 Threshold
Hysteresis
VHYS
VBACK - VSS (falling) (Note 8)
0µA < IRGC < 350µA
0.02
0.1
0.30
3.6
V
3.3V Regulated Voltage
VRGO
3.0
3.3
V
3.3VDC Voltage Regulator Control
Current Limit
I
(Control current at output of RGC.
Recommend NPN with gain of 70+)
0.35
0.50
mA
RGC
FN8306.1
June 21, 2013
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ISL94208
Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Supply Current
SYMBOL
IVCC1
TEST CONDITION
(Note 7)
TYP
300
400
(Note 7)
UNIT
µA
V
Power-up defaults, WKUP pin = 0V
510
700
CC
IVCC2
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H
µA
IVCC3
IVFET1
IVFET3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
1
10
1.5
1
µA
µA
µA
VFET1 Supply Current
(Normal or Sleep Mode)
0.1
0.1
VFET2 Supply Current
(Normal or Sleep Mode)
DFET, CFET outputs floating
RGO Supply Current
IRGO1
IRGO2
Power-up defaults, WKUP pin = 0V
300
450
410
650
µA
µA
LDMONEN bit = 1, VMON floating,
CFET = 1, DFET=1, WKPOL bit = 1,
VWKUP = 10V, [AO3:AO0] bits = 03H
IRGO3
Default register settings, except
SLEEP bit = 1. WKUP pin = VCELL1
0.4
1
µA
VBACK Input Current
(Falling edge wake up; WKPOL = 0)
(Normal or Sleep Mode)
IVBACK01 WKUP ≤ V
(max)
WKUP2
7
12
3
µA
µA
IVBACK02
V
(max) < WKUP < 5V
WKUP2
0.5
VBACK Input Current
(Rising edge wake up; WKPOL = 1)
(Normal Mode)
IVBACK11 WKUP < V
WKUP > V
(min) or;
(max)
0.5
3
µA
WKUP1
WKUP1
IVBACK12
V
(min) ≤ WKUP ≤ V
WKUP1
(max)
WKUP1
120
180
0.5
40
300
500
3
µA
µA
µA
µA
IVBACK13 WKUP ≥ V
(min)
WKUP1
WKUP1
(Sleep Mode)
IVBACK14 WKUP < V
(min)
VCELL Input Current (Monitoring)
IVCELLA Sinking current at:
65
VCELL6 (measure VCELL6 or VCELL5) and
VCELL5 (measure VCELL6 or VCELL5) and
VCELL4 (measure VCELL5)
IVCELLB Sinking current at:
30
50
µA
VCELL4 (measure VCELL4) and
VCELL3 (measure VCELL4 or VCELL3) and
VCELL2 (measure VCELL3)
IVCELLC
Sourcing current at:
VCELL2 (measure VCELL2) and
VCELL1 (measure VCELL2)
-40
-38
-20
-18
µA
µA
IVCELLD Sourcing current at:
VCELL1 (measure VCELL1) and
VCELL0 (measure VCELL1)
VCELL Input Current Differential
(Monitoring)
IVCELLDIFF Difference in monitoring current between
VCELLn and VCELL(n-1); n = 1, 2, 3, 4
-2
-4
-1
2
4
1
µA
µA
µA
Difference in monitoring current between
VCELLn and VCELL(n-1); n = 5, 6
VCELL Input Current (Non-Monitoring)
IVCELLN VCELLn and VCELL(n-1)
(n = 1, 2, 3, 4, 5, or 6)
±0.1
n is a non-selected cell
FN8306.1
June 21, 2013
8
ISL94208
Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITION
(Note 7)
TYP
(Note 7)
UNIT
OVERCURRENT/SHORT CIRCUIT PROTECTION SPECIFICATIONS
Discharge Overcurrent Detection
Threshold
Sense Voltage Relative To ISREF
(Default Highlighted)
V
VOCD = 0.10V (OCDV1, OCDV0 = 0, 0)
VOCD = 0.12V (OCDV1, OCDV0 = 0, 1)
0.08
0.10
0.12
0.14
-0.12
-0.14
-0.16
-0.18
0.15
0.30
0.60
1.10
1.1
0.10
0.12
0.14
0.16
-0.10
-0.12
-0.14
-0.16
0.20
0.35
0.65
1.20
1.45
0.12
0.14
0.16
0.18
-0.07
-0.09
-0.11
-0.13
0.25
0.40
0.70
1.30
1.8
V
V
V
V
V
V
V
V
V
V
V
V
V
OCD
V
OCD = 0.14V (OCDV1, OCDV0 = 1, 0)
OCD = 0.16V (OCDV1, OCDV0 = 1, 1)
V
Charge Overcurrent Detection
Threshold
Sense Voltage Relative to ISREF
(Default Highlighted)
V
VOCC = 0.10V (OCCV1, OCCV0 = 0, 0)
VOCC = 0.12V (OCCV1, OCCV0 = 0, 1)
OCC
V
OCC = 0.14V (OCCV1, OCCV0 = 1, 0)
OCC = 0.16V (OCCV1, OCCV0 = 1, 1)
V
Short Current Detection Threshold
Voltage Relative to ISREF
(Default Highlighted)
V
VSC = 0.20V (SCDV1, SCDV0 = 0, 0)
SC
V
V
V
SC = 0.35V (SCDV1, SCDV0 = 0, 1)
SC = 0.65V (SCDV1, SCDV0 = 1, 0)
SC = 1.20V (SCDV1, SCDV0 = 1, 1)
Load Monitor Input Threshold
(Falling Edge)
V
LDMONEN bit = “1”
VMON
Load Monitor Input Threshold
(Hysteresis)
V
LDMONEN bit = “1”
0.25
mV
VMONH
Load Monitor Current
I
V(VMON) between VVMON and V(VCC
)
20
90
40
60
µA
µs
VMON
Short Circuit Time-out
(Default Highlighted)
Short circuit detection delay (SCLONG
bit = ‘0’)
190
290
tSCD
Short circuit detection delay (SCLONG
bit = ‘1’)
5
80
10
160
320
640
1280
2.50
5
15
240
480
960
1920
3.75
7.5
ms
ms
ms
ms
ms
ms
ms
ms
ms
Over Discharge Current Time-out
(Default Highlighted)
t
= 160ms (OCDT1, OCDT0 = 0, 0 and
tOCD
OCD
DTDIV = 0)
t
= 320ms (OCDT1, OCDT0 = 0, 1 and
160
320
640
1.25
2.5
5
OCD
DTDIV = 0)
t
= 640ms (OCDT1, OCDT0 = 1, 0 and
OCD
DTDIV = 0)
t
= 1280ms (OCDT1, OCDT0 = 1, 1 and
OCD
DTDIV = 0)
t
= 2.5ms (OCDT1, OCDT0 = 0, 0 and
OCD
DTDIV = 1)
t
= 5ms (OCDT1, OCDT0 = 0, 1 and
OCD
DTDIV = 1)
t
= 10ms (OCDT1, OCDT0 = 1, 0 and
10
15
OCD
DTDIV = 1)
t
= 20ms (OCDT1, OCDT0 = 1, 1 and
10
20
30
OCD
DTDIV = 1)
FN8306.1
June 21, 2013
9
ISL94208
Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITION
(Note 7)
TYP
80
(Note 7)
UNIT
ms
Over Charge Current Time-out
(Default Highlighted)
t
t
= 80ms (OCCT1,OCCT0 = 0, 0 and
OCC
40
120
240
480
960
3.75
7.5
OCC
CTDIV = 0)
t
= 160ms (OCCT1, OCCT0 = 0, 1 and
80
160
320
640
2.50
5
ms
ms
ms
ms
ms
ms
ms
OCC
CTDIV = 0)
t
= 320ms (OCCT1, OCCT0 = 1, 0 and
160
320
1.25
2.5
5
OCC
CTDIV = 0)
t
= 640ms (OCCT1, OCCT0 = 1, 1 and
OCC
CTDIV = 0)
t
= 2.5ms (OCCT1, OCCT0 = 0, 0 and
OCC
CTDIV = 1)
t
= 5ms (OCCT1, OCCT0 = 0, 1 and
OCC
CTDIV = 1)
t
= 10ms (OCCT1, OCCT0 = 1, 0 and
10
15
OCC
CTDIV = 1)
t
= 20ms (OCCT1, OCCT0 = 1, 1 and
10
20
30
OCC
CTDIV = 1)
OVER-TEMPERATURE PROTECTION SPECIFICATIONS
Internal Temperature Shutdown
Threshold
TI
NTSD
125
20
°C
°C
ms
Internal Temperature Hysteresis
THYS
Temperature drop needed to restore
operation after over-temperature shutdown
Internal Over-temperature Turn-On
Delay Time
tITD
128
External Temperature Output Current
External Temperature Limit Threshold
IX
Current output capability at TEMP3V pin
Voltage at VTEMPI; Relative to
1.2
-20
mA
mV
T
TX
0
110
1
+20
160
TF
V
TEMP3V falling edge
-----------------------------
13
External Temperature Limit Hysteresis
External Temperature Monitor Delay
TX
60
mV
ms
TH
TD
V
TEMP3V
13
-----------------------------
Voltage at VTEMPI relative to
tX
Delay between activating the external
sensor and the internal over-temperature
detection
External Temperature Autoscan On
Time
tXTAON
TEMP3V is ON (3.3V)
5
ms
ms
External Temperature Autoscan Off
Time
tXTAOFF TEMP3V output is off.
635
ANALOG OUTPUT SPECIFICATIONS
Cell Monitor Analog Output Voltage
Accuracy
VAOC
[VCELLN - VCELLN-1]/2 - AO
-15
-10
4
30
10
mV
mV
Cell Monitor Analog Output External
Temperature Accuracy
VAOXT
External temperature monitoring accuracy.
Voltage error at AO when monitoring TEMPI
voltage (measured with TEMPI = 1V)
Internal Temperature Monitor Output
Voltage Slope
VI
Internal temperature monitor voltage
change
-3.5
mV/°C
V
NTMON
Internal Temperature Monitor Output
TI
Output at +25°C
1.31
NT25
FN8306.1
June 21, 2013
10
ISL94208
Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
tVSC
TEST CONDITION
(Note 7)
TYP
(Note 7)
UNIT
ms
AO Output Stabilization Time
From SCL falling edge at data bit 0 of
command to AO output stable within 0.5%
of final value. AO voltage steps from 0V to
2V. (CAO = 10pF). (Note 10)
0.1
CELL BALANCE SPECIFICATIONS
Cell Balance Transistor rDS(ON)
Cell Balance Transistor Current
WAKE UP/SLEEP SPECIFICATIONS
RCB
ICB
5
10
Ω
200
mA
Device WKUP Pin Voltage Threshold
(WKUP Pin Active High - Rising Edge)
V
V
WKUP pin rising edge (WKPOL = 1)
Device wakes up and sets WKUP flag HIGH
3.5
5.0
7.0
V
WKUP1
Device Wkup Pin Hysteresis
(WKUP Pin Active High)
WKUP pin falling edge hysteresis
(WKPOL = 1) sets WKUP flag LOW (does not
automatically enter sleep mode)
100
mV
WKUP1
HYS
Input Resistance On WKUP
RWKUP
Resistance from WKUP pin to VSS
(WKPOL = 1)
250
360
450
kΩ
Device WKUP Pin Active Voltage
Threshold (WKUP Pin Active
Low-Falling Edge)
V
WKUP pin falling edge (WKPOL = 0)
Device wakes up and sets WKUP flag HIGH
VBACK - 2.2
VBACK - 1.8
VBACK - 1.4
V
WKUP2
Device Wkup Pin Hysteresis
(WKUP Pin Active Low)
V
WKUP pin rising edge hysteresis
(WKPOL = 0) sets WKUP flag LOW (does not
automatically enter sleep mode)
200
40
mV
ms
WKUP2
HYS
Device Wake-up Delay
t
Delay after voltage on WKUP pin crosses
the threshold (rising or falling) before
activating the WKUP bit
20
60
WKUP
FET CONTROL SPECIFICATIONS
VFET1 Voltage
VVFET1A
VVFET1B
VVFET2A
VVFET2B
tCO
5.6
4.4
8.4
6.6
10.8
10.8
14.4
14.4
V
V
0°C to +85°C
0°C to +85°C
VFET2 Voltage
V
V
Control Outputs Response Time
(CFET, DFET)
Bit 0 to start of control signal (DFET)
Bit 1 to start of control signal (CFET)
1.0
µs
CFET Gate Voltage
VCFET
VDFET
No load on CFET
No load on DFET
VFET2- 0.5
VFET2- 0.5
80
VFET2
VFET2
450
V
V
DFET Gate Voltage
FET Turn On Current (DFET)
IDF(ON) DFET voltage = 0 to VFET2 -1.5V
200
200
180
µA
-20°C to +85°C
FET Turn On Current (CFET)
I
CF(ON) CFET voltage = 0 to VFET2 - 1.5V
-20°C to +85°C
80
450
µA
FET Turn Off Current (DFET)
DFET Resistance to VSS
IDF(OFF) DFET voltage = FET2 to 1V
100
mA
RDF(OFF) VDFET < 1V (When turning off the FET)
11
Ω
SERIAL INTERFACE CHARACTERISTICS
SCL Clock Frequency
fSCL
400
50
kHz
ns
Pulse Width Suppression Time at SDA
and SCL Inputs
tIN
Any pulse narrower than the max spec is
suppressed
SCL Falling Edge to SDA Output Data
Valid
tAA
From SCL falling crossing VIH(min), until
SDA exits the VIL(max) to VIH(min) window
0.9
µs
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Electrical Specifications
V
= 6V to 26.4V and -40°C to +85°C, unless otherwise specified. Boldface limits apply over the
CC
operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
SYMBOL
tBUF
TEST CONDITION
(Note 7)
TYP
(Note 7)
UNIT
µs
Time the Bus Must Be Free Before
Start of New Transmission
SDA crossing VIH(min) during a STOP
condition to SDA crossing VIH(min) during
the following START condition
1.3
Clock Low Time
tLOW
tHIGH
Measured at the VIL(max) crossing
Measured at the VIH(min) crossing
1.3
0.6
0.6
µs
µs
µs
Clock High Time
Start Condition Setup Time
tSU:STA
SCL rising edge to SDA falling edge. Both
crossing the VIH(min) level
Start Condition Hold Time
Input Data Setup Time
Input Data Hold Time
tHD:STA
From SDA falling edge crossing VIL(max) to
SCL falling edge crossing VIH(min)
0.6
100
0
µs
ns
µs
tSU:DAT
From SDA exiting the VIL(max) to VIH(min)
window to SCL rising edge crossing VIL(min)
tHD:DAT From SCL falling edge crossing VIH(min) to
SDA entering the VIL(max) to VIH(min)
window
0.9
Stop Condition Setup Time
Stop Condition Hold Time
Data Output Hold Time
tSU:STO
From SCL rising edge crossing VIH(min) to
SDA rising edge crossing VIL(max)
0.6
0.6
0
µs
µs
ns
tHD:STO From SDA rising edge to SCL falling edge.
Both crossing VIH(min)
tDH
From SCL falling edge crossing VIL(max)
until SDA enters the VIL(max) to VIH(min)
window. (Note 9)
SDA and SCL Rise Time
tR
From VIL(max) to VIH(min) (Notes 11, 12)
From VIH(min) to VIL(max) (Notes 11, 12)
Total on-chip and off-chip (Notes 11, 12)
20 + 0.1 x
Cb
300
300
400
ns
ns
SDA and SCL Fall Time
tF
20 + 0.1 x
Cb
Capacitive Loading Of SDA Or SCL
Cb
10
1
pF
SDA and SCL Bus Pull-up Resistor
Off Chip
ROUT
Maximum is determined by tR and tF.
For CB = 400pF, max is about 2kΩ ~ 2.5kΩ
For CB = 40pF, max is about 15kΩ to 20kΩ
(Notes 11, 12)
kΩ
Input Leakage Current (SCL, SDA)
Input Buffer Low Voltage (SCL, SDA)
Input Buffer High Voltage (SCL, SDA)
Output Buffer Low Voltage (SDA)
SDA and SCL Input Buffer Hysteresis
NOTES:
I
-10
10
µA
V
LI
V
Voltage relative to VSS of the device.
Voltage relative to VSS of the device.
-0.3
V
x 0.3
IL
RGO
V
V
x 0.7
V
+ 0.1V
V
IH
RGO
RGO
0.4
VOL
I
= 1mA
V
OL
I2CHYST Sleep bit = 0
0.05 * VRGO
V
7. Compliance to data sheet limits is assured by one or more methods: production test, characterization and/or design.
8. Power-up of the device requires VBACK and VCC to be above the limits specified.
9. The device provides an internal hold time of at least 300ns for the SDA signal to bridge the unidentified region of the falling edge of SCL.
10. Maximum output capacitance = 15pF.
11. These are I2C specific parameters and are not production tested. However, they are used to set conditions for testing to validate specification.
12. Limits should be considered typical and are not production tested.
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Timing Diagrams
Wake Up Timing (WKPOL = 0)
<t
WKUP
V
V
WKUP2H
WKUP2
WKUP PIN
<t
WKUP
t
t
WKUP
WKUP
WKUP BIT
Wake Up Timing (WKPOL = 1)
<t
WKUP
V
WKUP1
V
WKUP1H
WKUP PIN
<t
WKUP
t
t
WKUP
WKUP
WKUP BIT
Change in Voltage Source, FET Control
SCL
BIT
3
BIT
2
BIT
1
BIT
0
BIT
1
BIT
0
SDA
AO
DATA
t
t
VSC
VSC
t
t
t
CO
CO
CO
DFET
CFET
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Automatic Temperature Scan
AUTO TEMP CONTROL
(INTERNAL ACTIVATION)
(t
)
XTAOFF
635ms
MONITOR TIME = 5ms
(t
)
3.3V
XTAON
HIGH IMPEDANCE
TEMP3V PIN
EXTERNAL
TEMPERATURE
OVER-TEMPERATURE
THRESHOLD
TMP3V/13
DELAY TIME = 1ms
MONITOR TEMP DURING THIS
DELAY TIME = 1ms
XTD
(t
)
TIME PERIOD
XOT BIT
FET SHUTDOWN AND CELL BALANCE TURN OFF
(IF ENABLED)
Discharge Overcurrent/Short Circuit Monitor
(Assumes DENOCD and DENSCD bits are ‘0’)
V
SC
V
OCD
V
DSENSE
t
t
t
SCD
SCD
OCD
‘1’
‘0’
‘0’
DOC BIT
DSC BIT
‘1’
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
REGISTER 1 READ
VFET2
DFET
OUTPUT
µC TURNS ON DFET
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ISL94208
Charge Overcurrent Monitor
(Assumes DENOCC bit is ‘0’)
V
CSENSE
V
OCC
t
OCC
‘1’
‘0’
COC BIT
3.3V
TEMP3V
OUTPUT
REGISTER 1 READ
12V
CFET
OUTPUT
µC TURNS ON CFET
Serial Interface Bus Timing
t
t
t
R
HIGH
LOW
t
F
t
SCL
t
SU:STA
t
t
SU:DAT
HD:DAT
SU:STO
t
HD:STA
SDA
(INPUT TIMING)
t
BUF
t
t
AA
DH
SDA
(OUTPUT TIMING)
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
WAVEFORM
INPUTS
OUTPUTS
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
MUST BE
STEADY
WILL BE
STEADY
N/A
CENTER LINE
IS HIGH
IMPEDANCE
MAY CHANGE
FROM LOW
TO HIGH
WILL CHANGE
FROM LOW
TO HIGH
MAY CHANGE
FROM HIGH
TO LOW
WILL CHANGE
FROM HIGH
TO LOW
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ISL94208
Registers
TABLE 1. REGISTERS
READ/
WRITE
ADDR
00H
REGISTER
7
6
5
4
3
2
1
0
Config/Op
Status
Read only
Reserved
Reserved
1
WKUP
WKUP pin
Status
Reserved
Reserved
Reserved
Reserved
01H
Operating
Status
(Note 15)
Read only
Reserved
Reserved
XOT
Ext over
temp
IOT
Int
Over-Temp
LDFAIL
DSC
DOC
COC
Load Fail Short Circuit Discharge Charge OC
(VMON)
OC
02H
03H
04H
Cell Balance Read/Write Reserved
CB6ON
UFLG0
CB5ON
Reserved
Reserved
CB4ON
CB3ON
CB2ON
CB1ON
Reserved
AO0
Cell Balance Fet Control Bits
Analog Out Read/Write
FET Control Read/Write
UFLG1
User Flag 1 User Flag 0
Reserved
Reserved
AO3
AO2
AO1
Analog Output Select Bits
SLEEP
LDMONEN
Turn on
VMON
Reserved
Reserved
CFET
Turn On
Charge FET Discharge
DFET
Turn On
Force Sleep
(Note 16)
Connection
(Note 17)
FET
(Note 17)
05H
06H
07H
Discharge Read/Write
DENOCD
OCDV1
OCDV0
DENSCD
SCDV1
SCDV0
OCDT1
OCDT0
Set
(Write only if
DISSETEN
bit set)
Turn Off
Automatic
OCD control
Overcurrent Discharge
Threshold Voltage
Turn-off
automatic
SCD control
Short Circuit Discharge
Threshold Voltage
Overcurrent Discharge
Time-out
Charge Set Read/Write
(Write only if
CHSETEN
DENOCC
OCCV1
OCCV0
SCLONG
Long
CTDIV
Divide
DTDIV
Divide
OCCT1
OCCT0
Turn Off
Automatic
OCC control
Overcurrent Charge
Threshold Voltage
Overcurrent Charge
Time-out
Short-circuit ChargeTime Discharge
bit set)
Delay
by 32
Time by 64
Feature Set Read/Write ATMPOFF
DIS3
TMP3ON
Turn-on
Temp3V
DISXTSD
Disable
External
Thermal
Shutdown
DISITSD
Disable
Internal
Thermal
Shutdown
POR
Force POR
DISWKUP
Disable
WKUP pin
WKPOL
Wake Up
Polarity
(Write Only
if FSETEN
Bit Set)
Turn Off Disable3.3V
Automatic Reg. (Device
External
Requires
External
3.3V)
Temp Scan
08H
Write
Enable
Read/Write
NA
FSETEN
Enable
CHSETEN
Enable
DISSETEN
Enable
UFLG3
User Flag 3 User Flag 2
UFLG2
Reserved
Reserved
Reserved
Feature Set Charge Set Discharge
Writes Writes Set Writes
09H:FFH
Reserved
Reserved
NOTES:
13. A “1” written to a control or configuration bit causes the action to be taken. A “1” read from a status bit indicates that the condition exists.
14. “Reserved” indicates that the bit or register is reserved for future expansion. When writing to addresses 2, 3, 4, and 8: write a reserved bit with the
value “0”. Do not write to reserved registers at addresses 09H through FFH. Ignore reserved bits that are returned in a read operation.
15. These status bits are automatically cleared when the register is read. All other status bits are cleared when the condition is cleared.
16. This SLEEP bit is cleared on initial power up, by the WKUP pin going high (when WKPOL = ”1”), by the WKUP pin going low (when WKPOL = ”0”), or
by writing a “0” to the location with an I2C command.
17. When the automatic responses are enabled, these bits are automatically reset by hardware when an overcurrent or short circuit condition turns off
the FETs. At all other times, an I2C write operation controls the output to the respective FET and a read returns the current state of the FET drive output
circuit (though not the actual voltage at the output pin).
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Status Registers
TABLE 2. CONFIG/OP STATUS REGISTER (ADDR: 00H)
DESCRIPTION
BIT
FUNCTION
7, 6, 3, 2, RESERVED
1, 0
Reserved for future expansion.
5
4
1
This bit is always a “1”.
WKUP
This bit is set and reset by hardware.
Wakeup pin status When ‘WKPOL’ is HIGH:
• ’WKUP’ bit HIGH = WKUP pin > Threshold voltage
• ‘WKUP’ bit LOW = WKUP pin < Threshold voltage
When ‘WKPOL’ is LOW:
• ’WKUP’ bit HIGH = WKUP pin < Threshold voltage
• ‘WKUP’ bit LOW = WKUP pin > Threshold voltage
TABLE 3. OPERATING STATUS REGISTER (ADDR: 01H)
DESCRIPTION
BIT
7, 6
5
FUNCTION
RESERVED
Reserved for future expansion.
XOT
Ext Over-temp
This bit is set to “1” when the external temperature sensor input indicates an over-temperature condition. If the
over-temperature condition has cleared, this bit is reset when the register is read.
4
3
IOT
This bit is set to “1” when the internal temperature sensor input indicates an over-temperature condition. If the
over-temperature condition has cleared, this bit is reset when the register is read.
Int Over-temp
LDFAIL
When the VMON function is enabled (LDMONEN = 1), this bit is set to “1” by hardware when a discharge overcurrent or
Load Fail (VMON) short circuit condition occurs. If the load fail condition is cleared or under a light load, the bit is reset when the register
is read.
2
1
0
DSC
Short Circuit
This bit is set by hardware when a short circuit condition occurs during discharge. If the discharge short circuit condition
is removed, the bit is reset when the register is read.
DOC
Discharge OC
This bit is set by hardware when an overcurrent condition occurs during discharge. If the discharge overcurrent condition
is removed, the bit is reset when the register is read.
COC
Charge OC
This bit is set by hardware when an overcurrent condition occurs during charge. If the charge overcurrent condition is
removed, the bit is reset when the register is read.
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Control Registers
TABLE 4. CELL BALANCE CONTROL REGISTER (ADDR: 02H)
CONTROL REGISTER BITS
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
CB5ON
CB4ON
CB4ON
CB3ON
CB2ON
CB1ON
BALANCE
x
x
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
1
0
x
x
x
x
x
x
x
x
x
x
Cell1 ON
Cell1 OFF
Cell2 ON
Cell2 OFF
Cell3 ON
Cell3 OFF
Cell4 ON
Cell4 OFF
Cell5 ON
Cell5 OFF
Cell6 ON
Cell6 OFF
Bit 7 and Bit 0 RESERVED
TABLE 5. ANALOG OUT CONTROL REGISTER (ADDR: 03H)
DESCRIPTION
BITS
7
FUNCTION
UFLG1
User Flag 1
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
6
UFLG0
User Flag 0
General purpose flag usable by microcontroller software. This bit is battery backed up, even
when RGO turns off.
5:4
RESERVED
Reserved for future expansion
BIT 3
AO3
BIT 2
AO2
BIT 1
AO1
BIT 0
AO0
0
OUTPUT VOLTAGE
0
0
0
High Impedance Output (Low Power State)
Remember to reset the AO3:AO0 bits to ‘0000’ after measurements to
minimize unnecessary current draw from the cells.
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
0
1
V(VCELL1) - V(VCELL0)
V(VCELL2) - V(VCELL1
V(VCELL3) - V(VCELL2
V(VCELL4) - V(VCELL3
V(VCELL5) - V(VCELL4
V(VCELL6) - V(VCELL5
)
)
)
)
)
External Temperature.
Internal Temperature Sensor Voltage V(TEMPI).
RESERVED
Other cases
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ISL94208
Configuration Registers
The device is configured for specific application requirements
using the Configuration Registers. The configuration registers
consist of SRAM memory. In the wake up state, this memory is
powered by the RGO output. In a sleep state, this memory is
powered by VBACK.
TABLE 6. FET CONTROL REGISTER (ADDR: 04H)
BIT
7
FUNCTION
DESCRIPTION
SLEEP
Force Sleep
Setting this bit to “1” forces the device to go into a sleep condition. This turns off both FET outputs,
the cell balance outputs and the voltage regulator. This also resets the CFET, DFET, and
CB6ON:CB1ON bits. The SLEEP bit is automatically reset to “0” when the device wakes up. This bit
does not reset the AO3:AO0 bits (if the WKUP pin is Active, when attempting to put the device into
the Sleep mode, then the SLEEP bit needs to be reset from “1” to “0” prior to setting it to “1” to
initiate sleep).
6
LDMONEN
Turn on VMON connection
Writing a “1” to this bit turns on the VMON circuit. Writing a “0” to this bit turns off the VMON circuit.
As such, the microcontroller has full control of the operation of this circuit.
5:2
1
RESERVED
CFET
Reserved for future expansion.
Setting this bit to “1” turns on the charge FET.
Setting this bit to “0” turns off the charge FET.
This bit is automatically reset in the event of a charge overcurrent condition, unless the automatic
response is disabled by the DENOCC bit.
This bit is automatically reset in the event of an external over temperature condition, unless the
response is disabled by the DISXTSD bit.
This bit is automatically reset in the event of an internal over temperature condition, unless the
response is disabled by the DISITSD bit.
0
DFET
Setting this bit to “1” turns on the discharge FET.
Setting this bit to “0” turns off the discharge FET.
This bit is automatically reset in the event of a discharge overcurrent or discharge short circuit
condition, unless the automatic response is disabled by the DENOCD or DENSCD bits.
This bit is automatically reset in the event of an external over temperature condition, unless the
response is disabled by the DISXTSD bit.
This bit is automatically reset in the event of an internal over temperature condition, unless the
response is disabled by the DISITSD bit.
TABLE 7. DISCHARGE SET CONFIG REGISTER (ADDR: 05H)
DESCRIPTION
SETTING
Bit 7
FUNCTION
DENOCD
Turn off automatic OC
discharge control
When set to ‘0’, a discharge overcurrent condition automatically turns off the FETs.
When set to ‘1’, a discharge overcurrent condition will not automatically turn off the FETs.
In either case, this condition sets the DOC bit, which also turns on the TEMP3V output.
BIT 6
BIT 5
OCDV1
OCDV0
OVERCURRENT DISCHARGE VOLTAGE THRESHOLD
0
0
0
1
0
1
VOCD = 0.10V
VOCD = 0.12V
VOCD = 0.14V
VOCD = 0.16V
1
1
Bit 4
DENSCD
When set to ‘0’, a discharge short circuit condition turns off the FETs.
Turn off automatic SC
discharge control
When set to ‘1’, a discharge short circuit condition does not automatically turn off the FETs.
In either case, the condition sets the SCD bit, which also turns on the TEMP3V output.
BIT 3
BIT 2
SCDV1
SCDV0
SHORT CIRCUIT DISCHARGE VOLTAGE THRESHOLD
0
0
1
1
0
1
0
1
VSCD = 0.20V
VSCD = 0.35V
VSCD = 0.65V
VSCD = 1.20V
BIT 1
BIT 0
OCDT1
OCDT0
OVERCURRENT DISCHARGE TIME-OUT
0
0
1
1
0
1
0
1
tOCD = 160ms (2.5ms if DTDIV = 1)
tOCD = 320ms (5ms if DTDIV = 1)
tOCD = 640ms (10ms if DTDIV = 1)
tOCD = 1280ms (20ms if DTDIV = 1)
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ISL94208
TABLE 8. CHARGE/TIME SCALE CONFIG REGISTER (ADDR: 06H)
DESCRIPTION
SETTING
Bit 7
FUNCTION
DENOCC
When set to ‘0’, a charge overcurrent condition automatically turns off the FETs.
Turn off automatic OC charge control When set to ‘1’, a charge overcurrent condition does not automatically turn off the FETs.
In either case, this condition sets the COC bit, which also turns on the TEMP3V output.
BIT 6
BIT 5
OCCV1
OCCV0
OVERCURRENT CHARGE VOLTAGE THRESHOLD
0
0
0
1
0
1
V
OCD = 0.10V
VOCD = 0.12V
1
V
OCD = 0.14V
OCD = 0.16V
1
V
Bit 4
SCLONG
Short circuit long delay
When this bit is set to ‘0’, a short circuit needs to be in effect for 190µs before a shutdown
begins. When this bit is set to ‘1’, a short circuit needs to be in effect for 10ms before a
shutdown begins.
Bit 3
Bit 2
CTDIV
When set to “1”, the charge overcurrent delay time is divided by 32.
When set to “0”, the charge overcurrent delay time is divided by 1.
Divide charge time by 32
DTDIV
When set to “1”, the discharge overcurrent delay time is divided by 64.
When set to “0”, the discharge overcurrent delay time is divided by 1.
Divide discharge time by 64
BIT 1
BIT 0
OCCT1
OCCT0
OVERCURRENT CHARGE TIME-OUT
0
0
1
1
0
1
0
1
tOCC = 80ms (2.5ms if CTDIV=1)
tOCC = 160ms (5ms if CTDIV=1)
tOCC = 320ms (10ms if CTDIV=1)
tOCC = 640ms (20ms if CTDIV=1)
TABLE 9. FEATURE SET CONFIGURATION REGISTER (ADDR: 07H)
DESCRIPTION
BIT
FUNCTION
7
6
5
4
ATMPOFF
When set to ‘1’ this bit disables the automatic temperature scan. When set to ‘0’, the temperature
Turn off automatic external temp scan is turned on for 5ms in every 640ms.
DIS3
Disable 3.3V reg
Setting this bit to “1” disables the internal 3.3V regulator. Setting this bit to “1” requires that there
be an external 3.3V regulator connected to the RGO pin.
TMP3ON
Turn on Temp 3.3V
Setting this bit to “1” turns ON the TEMP3V output to the external temperature sensor. The output
will remain on as long as this bit remains “1”.
DISXTSD
Disable external thermal shutdown
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an external over-temperature condition. While the automatic response is disabled, the
XOT flag is set so the microcontroller can initiate a shutdown based on the XOT flag.
3
DISITSD
Setting this bit to “1” disables the automatic shutdown of the cell balance and power FETs in
response to an internal over-temperature condition. While the automatic response is disabled, the
IOT flag is set so the microcontroller can initiate a shutdown based on the IOT flag.
Disable internal thermal shutdown
2
1
POR
Force POR
Setting this bit to “1” forces a Power On Reset (POR) condition. This resets all internal registers to
zero.
DISWKUP
Setting this bit to “1” disables the WKUP pin function.
Disable WKUP pin
CAUTION: Setting this pin to ‘1’ disables hardware wake up functionality. If the device then goes to
sleep, it cannot be awakened without an I2C command that resets this bit, or by power cycling the
device.
0
WKPOL
Wake up polarity
Setting this bit to “1” sets the device to wake up on a rising edge at the WKUP pin.
Setting this bit to “0” sets the device to wake up on a falling edge at the WKUP pin. When
WKPOL= 0, limit the maximum voltage on the WKUP pin to no more than the voltage on VBACK.
.
FN8306.1
June 21, 2013
20
ISL94208
TABLE 10. WRITE ENABLE REGISTER (ADDR: 08H)
DESCRIPTION
BIT
7
FUNCTION
FSETEN
When set to “1”, allows writes to the Feature Set register. When set to “0”, prevents writes to the Feature Set
Enable discharge set writes register (Addr: 07H). Default on initial power-up is “0”.
6
5
4
3
CHSETEN
Enable charge set writes
When set to “1”, allows writes to the Charge Set register. When set to “0”, prevents writes to the Feature Set
register (Addr: 06H). Default on initial power-up is “0”.
DISSETEN
When set to “1”, allows writes to the Discharge Set register (Addr: 05H). When set to “0”, prevents writes to
Enable discharge set writes the Feature Set register. Default on initial power-up is “0”.
UFLG3
User Flag 3
General purpose flag usable by microcontroller software. This bit is powered by the voltage on VBACK when
RGO turns off.
UFLG2
User Flag 3
General purpose flag usable by microcontroller software. This bit is powered by the voltage on VBACK when
RGO turns off.
2, 1, 0 RESERVED
Reserved for future expansion.
FN8306.1
June 21, 2013
21
ISL94208
Connection guidelines for systems using 4, 5, or 6 cells are
shown in Figure 3 (minus the input filters and diodes).
Device Description
Instructed by the microcontroller, the ISL94208 performs cell
voltage monitoring and cell balancing operations, overcurrent
and short circuit monitoring with automatic pack shutdown using
built-in selectable time delays, and automatic turn off of the
power FETs and cell balancing FETs in an over-temperature
condition. All automatic functions of the ISL94208 can be turned
off and the microcontroller can manage the operations through
software.
6 CELLS
5 CELLS
VCC
VCC
VCELL6
VCELL6
CB6
VCELL5
CB6
VCELL5
CB5
VCELL4
CB5
VCELL4
VFET2
Battery Connection
CB4
CB4
VFET2
VFET1
VFET1
VCELL3
VCELL3
The ISL94208 supports packs of 4 to 6 series connected Li-ion
cells. One connection, with input filtering components, for six
cells is shown in Figure 2. Input capacitors are not normally
needed and are not recommended. These capacitors rapidly
charge when the batteries connect. This surge current is limited
only by the input resistors and may be high enough to damage
elements in the IC. If capacitors are needed, use the largest
possible series input resistor.
CB3
VCELL2
CB3
VCELL2
CB2
VCELL1
CB2
VCELL1
VBACK
VBACK
CB1
VCELL0
VSS
CB1
VCELL0
VSS
When using input filters, the time constants on all inputs should
be the same.
4 CELLS
VCC
VCELL6
27V
VCC
CB6
VCELL5
2.2µF/35V
68nF/35V
22nF/35V
68nF/35V
22nF/35V
20Ω
VCELL6
500Ω
CB5
VCELL4
VFET2
VFET1
CB6
1.5kΩ
500Ω
1.5kΩ
CB4
VCELL3
VCELL5
CB5
CB3
VCELL2
VCELL4
CB4
CB2
VCELL1
VBACK
500Ω
1.5kΩ
1kΩ
68nF/35V
22nF/35V
33nF/16V
CB1
VCELL0
VSS
VFET2
VCELL3
CB3
Note: Multiple cells can be connected in parallel.
500Ω
68nF/16V
22nF/16V
33nF/16V
FIGURE 3. BATTERY CONNECTION OPTIONS
1.5kΩ
VFET1
System Power-Up/Power-Down
The ISL94208 powers up when the voltage on VBACK and VCC
both exceed their POR threshold. At this time, the ISL94208
wakes up and turns on the RGO output.
1kΩ
500Ω
1.5kΩ
VCELL2
CB2
68nF/16V
22nF/16V
RGO provides a regulated 3.3VDC ±10% voltage at pin RGO. It
does this by using a control voltage on the RGC pin to drive an
external NPN transistor (see Figure 4). The transistor should have
a beta of at least 70 to provide ample current to the device and
external circuits and should have a breakdown voltage greater
than 30V (preferably 50V). The voltage at the emitter of the NPN
transistor is monitored and regulated to 3.3V by the control
signal RGC. RGO also powers most of the ISL94208 internal
circuits. A 500Ω resistor is recommended in the collector of the
NPN transistor to minimize initial current surge when the
regulator turns on.
VBACK
VCELL1
1kΩ
500Ω
1.5kΩ
33nF/16V
68nF/16V
22nF/16V
CB1
VCELL0
500Ω
68nF/16V
VSS
@ 4V BALANCE
CURRENT = 2mA
FIGURE 2. ISL94208 INPUT FILTERS
FN8306.1
June 21, 2013
22
ISL94208
Once powered up, the device remains in a wake up state until put
WKPOL = 1
to sleep by the microcontroller (typically when the cells drop too
low in voltage) or until the VBACK or VCC voltages drop below their
POR threshold.
In an active High connection (WKPOL = ‘1’) the device wakes up
when the WKUP pin is pulled high, normally by a connection
through an external switch.
To put the part to sleep, when configured as an active High
WKUP, if the WKUP pin is Low, then a single rising edge on the
SLEEP bit puts the part to sleep. However, if the WKUP pin is
High, the device needs to see a falling edge of the SLEEP bit, (or
the WKUP pin needs to be pulled Low), before the rising edge of
the SLEEP bit can force the device into the Sleep mode. A WKUP/
Sleep Timing timing diagram for WKPOL = 1 is shown in Figure 6.
See an example wake up circuit, using the microcontroller to
control wake up, in Figure 6. This microcontroller would need to
be powered by a separate supply.
VCC
500Ω
RGC
3.3V
RGO
VSS
10µF
In either active Low or active High wake up, there is a filter that
ignores WKUP pulses that are shorter than a tWKUP period. If the
device is in SLEEP mode when the WKUP signal goes active, then
the regulator turns on to power the wake up circuits. However, the
part is not fully awake, it is in a pseudo sleep mode, until the Wake
up condition is latched, after which the device is fully active.
GND
FIGURE 4. VOLTAGE REGULATOR CIRCUITS
WKUP Pin Operation
There are two ways to design a wake up of the ISL94208.
When using the active high wake up option, it is not
recommended that the WKUP voltage remain high while the
device is in sleep mode. Doing so results in excessive current on
the VBACK pin.
WKPOL = 0
In an active Low connection (WKPOL = “0” - default), the device
wakes up when the WKUP pin goes Low when compared to a
reference based on the VBACK voltage. This normally happens in a
pack when a charger connects to the battery terminals.
To put the part to sleep, when configured as an active Low WKUP,
if the WKUP pin is High, then a single rising edge on the SLEEP
bit puts the part to sleep. However, if the WKUP pin is Low, the
device needs to see a falling edge of the SLEEP bit (or the WKUP
pin needs to be pulled High), before the rising edge of the SLEEP
bit can force the device into the Sleep mode. A WKUP/Sleep
Timing timing diagram for WKPOL = 0 is shown in Figure 7.
ISL94208
WKUP
WKUP
(STATUS)
5V
When using the falling edge option, the voltage on the WKUP pin
should not exceed the voltage on VBACK for extended periods of
time. Also, if WKUP is pulled up to the VBACK pin (or CELL1) then
the connection of the charger or load should only maintain the
WKUP connection for a short time to minimize the drain of CELL
1. Also, for the falling edge option, maintaining the WKUP
voltage low results in higher VBACK current. See the electrical
table. For an example wake up circuit, see Figure 6.
360kΩ*
WAKE UP
CIRCUITS
WKPOL
(CONTROL)
V
BACK
VSS
* INTERNAL RESISTOR
ONLY CONNECTED WHEN
WKPOL = 1.
FIGURE 5. SIMPLIFIED WAKE UP CONTROL CIRCUITS
FN8306.1
June 21, 2013
23
ISL94208
CHRG+
DSC+
CHRG+
DSC+
PACK+
VBACK
PACK+
49.9kΩ
200kΩ
VBACK
WKUP
V
49.9kΩ
V
100kΩ
49.9kΩ
WKUP
ISL94208
ISL94208
200kΩ
µC
CFET DFET VSS
CFET DFET VSS
0.47µF/35V
TURN ON TO WAKE, THEN TURN OFF
(>60ms HIGH TIME)
DSC-
DSC-
CHRG-
CHRG-
WKPOL = 0
WKPOL = 1
NOTES:
18. WKPOL = 0 - The DSC- connection wakes the ISL94208 when the load connects.
19. WKPOL = 0 - The charger connection has three terminals. One terminal indicates that the charger is connected.
20. WKPOL = 1 - This connection wakes the pack under control of a microcontroller. This microcontroller needs to be powered by a separate regulator.
FIGURE 6. EXAMPLE EXTERNAL WAKE UP CIRCUITS
Maintaining this condition causes high
Maintaining this condition causes high
current on VBACK (~7µA)
current on VBACK (~7µA)
t
WKUP
Note 21
#
>100µs
Falling
Edge
Threshold
Falling
Edge
Threshold
WKUP PIN
WKUP PIN
WKUP BIT
#
Note 21
WKUP
t
t
WKUP
t
WKUP
<t
t
t
WKUP
WKUP
WKUP
<t
WKUP
WKUP BIT
SLEEP BIT
>50µs
>50µs
Note 23
**
**
Note 23
§
§
SLEEP BIT
Note 24
2
2
I C WRITE
I C WRITE
(SLEEP BIT)
(SLEEP BIT)
1
1 0 1
0
1
4V
RGC PIN
1V
ON
RGC PIN
OFF
*
*
Note 22
SLEEP
Note 22
SLEEP
AWAKE
AWAKE
SLEEP
AWAKE
AWAKE
AWAKE
WKUP PIN NORMALLY ABOVE FALLING EDGE THRESHOLD
WKUP PIN NORMALLY BELOW FALLING EDGE THRESHOLD
FIGURE 7. SLEEP/WAKEUP TIMING (WKPOL BIT = 0)
FN8306.1
June 21, 2013
24
ISL94208
Maintaining this condition causes high
current on VBACK (~200uA)
t
WKUP
Note 21
#
>100µs
Note 21
Rising
Edge
Threshold
#
Rising
Edge
Threshold
WKUP PIN
WKUP PIN
WKUP BIT
t
t
WKUP
WKUP
<t
t
t
WKUP
<t
WKUP
WKUP
WKUP
t
WKUP
WKUP BIT
SLEEP BIT
>50µs
>50µs
Note 24
Note 23
**
**
Note 23
Note 24
§
§
SLEEP BIT
2
2
I C WRITE
I C WRITE
(SLEEP BIT)
(SLEEP BIT)
1
1 0 1
0
1
ON
RGC PIN
OFF
ON
RGC PIN
OFF
*
*
Note 22
SLEEP
AWAKE
AWAKE
SLEEP
SLEEP
AWAKE
AWAKE
AWAKE
WKUP PIN NORMALLY BELOW RISING EDGE THRESHOLD
NOTES:
WKUP PIN NORMALLY ABOVE RISING EDGE THRESHOLD
21. # These are Glitches on the WKUP pin that are not long enough to exceed the internal filter and are not detected as valid signals.
22. * These periods are pseudo-sleep. The regulator turns on to power the wake-up circuits, but Wake up is not complete until the WKUP bit is latched.
23. ** The rising edge of the WKUP bit resets the SLEEP bit, if not already reset.
24. § When the WKUP pin is Active during Awake periods, the device needs a falling edge on the SLEEP bit (while the WKUP pin is above the threshold)
before the SLEEP bit can force sleep. The diagram shows two methods of doing this.
FIGURE 8. SLEEP/WAKEUP TIMING (WKPOL BIT = 1)
discharge FET gate low, turning off the FET quickly. The CFET output
Protection Functions
turns off and allows the gate of the charge FET to be pulled low
through a resistor.
In the default recommended condition, the ISL94208
automatically responds to discharge overcurrent, discharge short
circuit, charge overcurrent, internal over-temperature, and
external over-temperature conditions. The designer can set
optional over-ride conditions that allow the response to be
dictated by the microcontroller. These are discussed in the
following.
By turning off the FETs the ISL94208 prevents damage to the
battery pack caused by excessive current into or out of to the cells
(as in the case of a faulty charger or short circuit condition).
When the ISL94208 detects a discharge overcurrent condition, both
power FETs are turned off and the DOC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
response to overcurrent during discharge is prevented by setting the
DENOCD bit to “1”. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually turn
on the load monitor function first (by setting the LDMONEN bit) and
monitor the LDFAIL bit to detect that the overcurrent condition has
been removed.
Overcurrent Safety Functions
The ISL94208 continually monitors the discharge current by
monitoring the voltage at the CSENSE and DSENSE pins. If that
voltage exceeds a selected value for a time exceeding a selected
delay, then the device enters an overcurrent or short circuit
protection mode. In these modes, the ISL94208 automatically
turns off both power FETs and hence prevents current from
flowing through the terminals P+ and P-. See Figure 20 on
Page 32.
When the ISL94208 detects a discharge short circuit condition, both
power FETs are turned off and DSC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
response to short circuit during discharge is prevented by setting the
DENSCD bit to “1”. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually turn
on the load monitor function first (by setting the LDMONEN bit) and
monitor the LDFAIL bit to detect that the overcurrent condition has
been removed.
The voltage thresholds and the response times of the overcurrent
protection circuits are selectable for discharge overcurrent,
charge overcurrent, and discharge short circuit conditions. The
specific settings are determined by bits in the Discharge Set
Configuration Register (ADDR:05H) on Page 19, and the Charge/
Time Scale Configuration Scale Register (ADDR:06H) on
Page 20. In addition, refer to “Registers” on page 16.
When the ISL94208 detects a charge overcurrent condition, both
power FETs are turned off and COC bit is set. When the FETs are
turned off, the DFET and CFET bits are also reset. The automatic
In an overcurrent condition, the ISL94208 automatically turns off
the voltage on CFET and DFET pins. The DFET output drives the
FN8306.1
June 21, 2013
25
ISL94208
response to overcurrent during discharge is prevented by setting the
i.e. some action must be taken before the pack is again turned
DENOCC bit to “1”. The external microcontroller can turn on the FETs
at any time to recover from this condition, but it would usually wait
to do this until the cell voltages are not overcharged and that the
overcurrent condition has been removed (or the microcontroller
could wait until the pack is removed from the charger and then
re-attached).
on.
The load monitor circuit can be turned on or off by the
microcontroller. It is normally turned off to minimize current
consumption. It must be activated by the external microcontroller
for it to operate. The circuit works by internally connecting the
VMON pin to VSS through a resistor. The circuit operates as
shown in Figure 9.
An alternative method of providing the protection function, if desired
by the designer, is to turn off the automatic safety response. In this
case, the ISL94208 devices still monitor the conditions and set the
status bits, but takes no action in overcurrent or short circuit
conditions. Safety of the pack depends, instead, on the
microcontroller sending commands to the ISL94208 to turn off the
FETs.
In a typical pack operation, when an overcurrent or short circuit
event happens, the DFET turns off, opening the battery circuit to
the load. At this time, the RL is small and the load monitor is
initially off. In this condition, the voltage at VMON rises to nearly
the pack voltage.
Once the power FETs turn off, the microcontroller activates the
load monitor by setting the LDMONEN bit. This turns on an
internal FET that adds a pull down resistor to the load monitor
circuit. While still in the overload condition the combination of
the load resistor, an external adjustment resistor (R1), and the
internal load monitor resistor form a voltage divider. R1 is chosen
so that when the load is released to a sufficient level, the LDFAIL
condition is reset.
To facilitate a microcontroller response to an overcurrent condition,
especially if the microcontroller is in a low power state, a charge
overcurrent flag (COC), a discharge overcurrent flag (DOC), or the
short circuit flag (DSC) being set causes the ISL94208 TEMP3V
output to turn on and pull high (see Figure 10). This output can be
used as an external interrupt by the microcontroller to wake-up
quickly to handle the overcurrent condition.
P+
The diode in the VMON circuit is necessary to prevent the VMON
voltage from going negative with respect to VSS when a charger
connects between P+ and P- and the charger voltage is
significantly larger than the battery stack voltage.
VSS
R
L
OPEN
Over-Temperature Safety Functions
P-
POWER FETs
EXTERNAL TEMPERATURE MONITORING
R
1
The external temperature is monitored by using a voltage divider
consisting of a fixed resistor and a thermistor. This divider is
powered by the ISL94208 TEMP3V output. This output is
normally controlled so it is on for only short periods to minimize
current consumption.
ISL94208
VMON
V
REF
LDFAIL
= 1 if VMON >V
= 0 if VMON £ V
Without microcontroller intervention, and in the default state, the
ISL94208 provides an automatic temperature scan. This scan
circuit repeatedly turns on TEMP3V output (and the external
temperature monitor) for 5ms out of every 640ms. In this way,
the external temperature is monitored even if the microcontroller
is asleep.
VMONH
VMONL
LDMONEN
VSS
When the TEMP3V output turns on, the ISL94208 waits 1ms for
the temperature reading to stabilize, then compares the external
temperature voltage with an internal voltage divider that is set to
TEMP3V/13. If the thermistor voltage is below the reference
threshold after the delay, an external temperature fail condition
exists. To set the external over-temperature limit, set the value of
RX resistor to the 12 times the resistance of the thermistor at the
desired over-temp threshold.
FIGURE 9. LOAD MONITOR CIRCUIT
Load Monitoring
The load monitor function in the ISL94208 (see Figure 9) is used
primarily to detect that the load has been removed following an
overcurrent or short circuit condition during discharge. This can
be used in a control algorithm to prevent the FETs from turning
on while the overload or short circuit condition remains.
The TEMP3V output pin also turns on when the microcontroller
sets the AO3:AO0 bits to select that the external temperature
voltage. This causes the TEMPI voltage to be placed on AO and
activates (after 1ms) the over-temperature detection. As long as
the AO3:AO0 bits point to the external temperature, the TEMP3V
output remains on. Because of the manual scan of the
temperature, it may be desired to turn off the automatic scan,
although they can be used at the same time without
interference. To turn off the automatic scan, set the ATMPOFF bit.
The load monitor can also be used by the microcontroller
algorithms after an undervoltage condition on any cells causes
the FETs to turn off. Use of the load monitor prevents the FETs
from turning on while the load is still present. This minimizes the
possible “on-off-on cycles” that can occur when a load is applied
in a low capacity pack. It can also be part of a system protection
mechanism to prevent the load from turning on automatically -
FN8306.1
June 21, 2013
26
ISL94208
The microcontroller can over-ride both the automatic temperature
external temperature voltage is not divided by 2 as are the cell
voltages. Instead it is a direct reflection of the voltage at the
TEMPI pin.
scan and the microcontroller controlled temperature scan by
setting the TEMP3ON configuration bit. This turns on the TEMP3V
output to keep the temperature control voltage on all the time, for
a continuous monitoring of an over-temperature condition. This
likely will consume a significant amount of current, so this feature
is usually used for special or test purposes.
A similar operation occurs when monitoring the internal
temperature through the AO output, except there is no external
“calibration” of the voltage associated with the internal
temperature. For the internal temperature monitoring, the
voltage at the output is linear with respect to temperature. See
“Electrical Specifications” on Page 10 for information about the
output voltage at +25°C and the output slope relative to
temperature.
PROTECTION
By default, when the ISL94208 detects an internal or external
over-temperature condition, the FETs are turned off, the cell
balancing function is disabled, and the IOT bit or XOT bit
(respectively) is set.
4ms
508ms
Turning off the FETs in the event of an over-temperature
condition prevents continued discharge or charge of the cells
when they are over heated. Turning off the cell balancing in the
event of an over-temperature condition prevents damage to the
IC in the event too many cells are being balanced, causing too
much power dissipation in the ISL94208.
2
2
I C
I C
OSC
ATMPOFF
TMP3ON
In the event of an automatic over-temperature condition, cell
balancing is prevented and FETs are held off until the
temperature drops back below the temperature recovery
threshold. During this temperature shutdown period, the
microcontroller can monitor the internal temperature through the
analog output pin (AO), but any writes to the CFET bit, DFET bit, or
cell balancing bits are ignored
RGO
AO3:AO0
DECODE
EXT TEMP
TO
µC
TEMP3V
The automatic response to an internal over-temperature is
prevented by setting the DISITSD bit to “1”. The automatic
response to an external over-temperature is prevented by setting
the DISXTSD bit to “1”. In either case, it is important for the
microcontroller to monitor the internal and external temperature
to protect the pack and the electronics in an over-temperature
condition.
R
X
TEMPI
MUX
AO
1ms
DELAY
R
th
EXTERNAL
TEMP
MONITOR
VSS
XOT
Analog Multiplexer Selection
TEMP FAIL
INDICATOR
The ISL94208 devices can be used to externally monitor
individual battery cell voltages and temperatures. Each quantity
can be monitored at the analog output pin (AO). The desired
voltage is selected using the I2C interface and the AO3:AO0 bits.
See Figure 11 and Table 5 on page 18. Remember to reset the
AO3:AO0 bits to ‘0000’ after measurements to minimize
unnecessary current draw from the cells.
FIGURE 10. EXTERNAL TEMPERATURE MONITORING AND
CONTROL
Cell Balancing
Overview
Voltage Monitoring
A typical ISL94208 Li-ion battery pack consists of four to six cells
in series, with one or more cells in parallel. This combination
gives both the voltage and power necessary for many battery
powered applications. While the series/parallel combination of
Li-ion cells is common, the configuration is not as efficient as it
could be, because any capacity mismatch between
series-connected cells reduces the overall pack capacity. This
mismatch is greater as the number of series cells and the load
current increase. Cell balancing techniques increase the
capacity, and the operating time, of Li-ion battery packs.
Since the voltage on each of the Li-ion Cells are normally higher
than the regulated supply voltage, and since the voltages on the
upper cells is much higher than is tolerated by a microcontroller,
it is necessary to both level shift and divide the voltage before it
can be monitored by the microcontroller or an external A/D
converter. To get into the voltage range required by the external
circuits, the voltage level shifter divides the cell voltage by 2 and
references it to VSS. Therefore, a Li-ion cell with a voltage of 4.2V
becomes a voltage of 2.1V on the AO pin.
Temperature Monitoring
The voltage representing the external temperature applied at the
TEMPI terminal is directed to the AO terminal through a MUX, as
selected by the AO control bits (see Figures 10 and 11). The
Definition of Cell Balancing
Cell balancing is defined as the application of differential
currents to individual cells (or combinations of cells) in a series
FN8306.1
June 21, 2013
27
ISL94208
string. Without cell balancing, cells in a series string receive
needed when there is a separate charge and discharge path,
because the voltages on Pack- (discharge) are always positive.
nominally identical currents. A battery pack requires additional
components and circuitry to achieve cell balancing. For the
ISL94208 devices, the only external components required are
balancing resistors.
When the pack is designed with a single set of charge/discharge
FETs, the ISL94208 CFET pin should be protected in the event of
an overcurrent or short circuit shutdown. When this happens, the
FET opens suddenly. The flyback voltage from the motor windings
could exceed the maximum input voltage on the CFET pin.
Therefore, it is recommended that an additional external series
diode be placed between the CFET pin of the ISL94208 and the
gate of the Charge FET. See Diode D3 in Figure 13. This reduces
the CFET gate voltage, but not significantly.
VCELL7
VCELL6
LEVEL
SHIFT
SCL
SDA
2
I C
LEVEL
SHIFT
REGS
Finally, to protect the Charge FET itself in the event of a large
negative voltage on the Pack- pin, zener diode D4 is added. A
large negative voltage can occur when the Pack- pin goes
significantly negative, while the CFET pin is being internally
clamped. The zener voltage of D4 should be less than the
VGS(max) specification of the FET.
AO3:AO0
VCELL2
VCELL1
LEVEL
SHIFT
DECODE
MUX
LEVEL
SHIFT
2
AO
VCELL7
VSS
ISL94208
21Ω
1W
EXT TEMP.
CB7
TEMPI
INT
TEMP
MUX
200mA
CELL
BALANCE
CONTROL
(REG 02H)
7 6 5 4 3 2 1
FIGURE 11. ANALOG OUTPUT MONITORING DIAGRAM
VCELL1
CB1
21Ω
1W
Cell Balance Operation
Cell balancing is accomplished through a microcontroller
algorithm. This algorithm compares the cell voltages (a
representation of the pack capacity) and turns on balancing for
the cells that have the higher voltages. There are many
parameters that should be considered when writing this
algorithm. An example cell balancing algorithm is available in
the ISL94208EVAL1Z evaluation kit.
VSS
FIGURE 12. CELL BALANCING CONTROL EXAMPLE WITH 200mA
BALANCING CURRENT
The microcontroller turns on a specific cell balancing switch by
setting a bit in the Cell Balance Register. Each bit in the register
corresponds to one cell’s balancing control. When the bit is set,
an internal cell balancing FET turns on. This connects an external
resistor across the specified cell. The maximum current that can
be drawn from (or bypassed around) the cell is 200mA. This
current is set by selecting the value of the external resistor.
Figure 12 shows an example with a 200mA (maximum)
balancing current.
PACK+
PACK-
D
1
VMON
D
4
10MΩ
ISL94208
1MΩ
D
3
With lower balancing current, more balancing FETs can be turned
on at once, without exceeding the device power dissipation limits
or generating excessive balancing current that will heat the
external resistor.
CFET
DFET
External VMON/CFET Protection
Mechanisms
When there is a single charge/discharge path, a blocking diode
is recommended in the VMON to Pack- path in ISL94208
solution. See D1 in Figure 13. This diode is to protect against a
negative voltage on the VMON pin that can occur when the FETs
are off and the charger connects to the pack. This diode is not
FIGURE 13. USE OF A DIODES FOR PROTECTING THE CFET AND
VMON PINS
FN8306.1
June 21, 2013
28
ISL94208
The device responds with an Acknowledge after recognition of a
User Flags
START condition and the correct Slave byte. If a Write operation is
selected, the device responds with an Acknowledge after the
receipt of each subsequent eight bits. The device acknowledges
all incoming data and Address bytes, except for the Slave byte
when the contents do not match the device’s address.
The ISL94208 contains four flags in the register area that the
microcontroller can use for general purpose indicators. These
bits are designated UFLG3, UFLG2, UFLG1, and UFLG0. The
microcontroller can set or reset these bits by writing into the
appropriate register.
In the Read mode, the device transmits eight bits of data,
releases the SDA line, then monitor the line for an Acknowledge.
If an acknowledge is detected and no STOP condition is
generated by the Master, the device continues transmitting data.
The device terminates further data transmissions if an
acknowledge is not detected. The Master must then issue a STOP
condition to return the device to Standby mode and place the
device into a known state.
The user flag bits are battery backed up (by the VBACK pin
voltage), so the contents remain even after exiting Sleep mode.
However, if the microcontroller sets the POR bit to force a power
on reset, all of the user flags are also reset. In addition, if the
voltage on VBACK ever drops below the POR voltage, the
contents of the user flags (as well as all other register values)
would be lost.
2
I C Interface
Interface Conventions
SCL
SDA
The device provides an I2C communications interface. The
protocol defines any device that sends data onto the bus as a
transmitter, and the receiving device as the receiver. The device
controlling the transfer is called the Master and the device being
controlled is called the Slave. The Master always initiates data
transfers, and provides the clock for both transmit and receive
operations. Therefore, the ISL94208 devices operate as slaves in
all applications.
DATA
DATA
DATA
STABLE
CHANGE
STABLE
FIGURE 14. VALID DATA CHANGES ON I2C BUS
.
When sending or receiving data, the convention is that the most
significant bit (MSB) is sent first. Therefore, the first address bit
sent is bit 7.
SCL
SDA
Clock and Data
Data states on the SDA line can change only while SCL is LOW.
SDA state changes while SCL HIGH are reserved for indicating
START and STOP conditions. See Figure 14.
START
STOP
Start Condition
All commands are preceded by the START condition, which is a
HIGH-to-LOW transition of SDA when SCL is HIGH. The device
continuously monitors the SDA and SCL lines for the START
condition and does not respond to any command until this
condition has been met. See Figure 15.
FIGURE 15. I2C START AND STOP BITS
SCL FROM
1
8
9
MASTER
Stop Condition
DATA OUTPUT
FROM
TRANSMITTER
All communications must be terminated by a STOP condition,
which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The
STOP condition is also used to place the device into the Standby
power mode after a Read sequence. A STOP condition is only
issued after the transmitting device has released the bus. See
Figure 15.
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Acknowledge (ACK)
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either Master
or Slave, releases the bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
acknowledge that it received the eight bits of data. See
Figure 16.
FN8306.1
June 21, 2013
29
ISL94208
STOP bit, the Master may send additional data to the device
Write Operations
without re-sending the Slave and Register Address bytes. After
writing to address 0AH, the address “wraps around” to address 0.
Do not continue to write to addresses higher than address 08H,
since these addresses access registers that are reserved. Writing
to these locations can result in unexpected device operation.
For a Write operation, the device requires a Slave byte and a
Register Address byte. The Slave byte specifies the particular device
on the I2C bus that the Master is writing to. The Register Address
specifies one of the registers in that device. After receipt of each
byte, the device responds with an Acknowledge, and awaits the next
eight bits from the Master. After the Acknowledge, following the
transfer of data, the Master terminates the transfer by generating a
STOP condition (see Figure 17).
When receiving data from the Master, the value in the Data byte
is transferred into the register specified by the Register address
byte on the falling edge of the clock following the 8th data bit.
After receiving the Acknowledge after the Data byte, the device
automatically increments the address. So, before sending the
S
T
A
S
T
O
P
SLAVE
R
REGISTER
ADDRESS
BYTE
T
DATA
SDA BUS
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
ISL94208: SLAVE BYTE = 50H
FIGURE 17. WRITE SEQUENCE
Random Read
S
T
A
R
T
S
T
A
R
T
S
T
O
P
A
C
K
SLAVE
BYTE
SLAVE
BYTE
REGISTER
ADDRESS
SDA BUS
0 1 0 1 0 0 0 1
0 1 0 1 0 0 0 0
A
C
K
A
C
K
A
C
K
DATA
ISL94208: SLAVE BYTE = 010100xH
Current Address Read
S
T
A
R
T
S
SLAVE
BYTE
A
C
K
T
O
P
0 1 0 1 0 0 0 1
A
C
K
DATA
FIGURE 18. READ SEQUENCE
FN8306.1
June 21, 2013
30
ISL94208
3. Write the DISSETEN bit (Addr 8:bit 5) to “1” to enable changes
Register Protection
to the data in the Feature Set register (Address 5).
The Discharge Set, Charge Set, and Feature Set configuration
registers are write protected on initial power up. In order to write
to these registers it is necessary to set a bit to enable each one.
These write enable bits are in the Write Enable register (Address
08H).
The microcontroller can reset these bits back to zero to prevent
inadvertent writes that change the operation of the pack.
Operation State Machine
Figure 19 shows a device state machine, which illustrates how
the ISL94208 responds to various conditions.
1. Write the FSETEN bit (Addr 8:bit 7) to “1” to enable changes to
the data in the Feature Set register (Address 7).
2. Write the CHSETEN bit (Addr 8:bit 6) to “1” to enable changes
to the data in the Feature Set register (Address 6).
POWER FAILS AND VCC OR VBACK OR BOTH SUPPLIES DO NOT MEET MINIMUM
VOLTAGE REQUIREMENTS
POWER DOWN STATE
I2C interface is disabled.
Biasing is disabled.
All registers set to default values
(All = “0”)
Power is applied and both VCC and VBACK meet minimum
voltage requirements
POWER UP STATE
I2C interface is enabled.
Biasing is enabled.
Voltage Regulator is enabled.
SLEEP bit
MAIN OPERATING STATE (AWAKE)
SLEEP STATE
(WKUP not active)
• Voltage Regulator is ON
• Voltage regulator is OFF
• Biasing is OFF
SLEEP bit
• Logic and registers are powered by RGO
• CFET, DFET, and Cell Balancing outputs
are ON or OFF. (Require an external
command to turn on).
• Logic and Registers are powered by
VBACK
• CFET, DFET, and Cell Balancing outputs
are OFF.
• The Over Temperature protection circuit
is active.
WKUP goes above or below
threshold (edge triggered).
• Charge and Discharge current
protection circuits are OFF.
• Overcurrent protection (OCP) circuits are
active when the either of the CFET and
DFET outputs are enabled. The OCP
circuits are off when both the CFET and
DFET outputs are off.
Or, SLEEP bit is set to ‘0’
• Voltage and Temperature monitoring
circuits are OFF.
• I2C communication is active (If VBACK
voltage is high enough to operate with
the external device).
• Overcurrent conditions force the power
FETs to turn OFF. Over temperature
conditions force the power FETs and Cell
Balance output OFF.
• Voltage and Temperature monitoring
circuits are awaiting external control.
FIGURE 19. DEVICE OPERATION STATE MACHINE
FN8306.1
June 21, 2013
31
ISL94208
Application Circuits
The following application circuits are ideas to consider when developing a battery pack implementation. There are many more ways
that the pack can be designed.
Integrated Charge/Discharge Path
P+
VBACK
27Ω
500Ω
VFET2
VFET1
200kΩ
VCC
CHGR Present
WKUP
VCELL6
100kΩ
2N7002
20Ω
200Ω
20Ω
ISL94208
CB6
VCELL5
RGC
RGO
15V
200Ω
20Ω
CB5
1µF
VCELL4
200Ω
20Ω
CB4
V
CC
µC
200Ω
200Ω
RESET
OPTIONAL
LEDS/
RESISTORS
TEMP3V
VCELL3
GP
I/O
TEMPI
SCL
SDA
200Ω
20Ω
CB3
SCL
SDA
INT
CHRG
VCELL2
200Ω
20Ω
100Ω
3.6V
A/D IN
AO
CB2
I/O
VCELL1
VMON
CFET
VBACK
200Ω
20Ω
CB1
DFET
PACK INTERFACE
NOT NEEDED DURING
DISCHARGE
VCELL0
V
10µF 10µF10µF
SS
B-
P-/CH-
16V (<CFET VGS
)
MAX
MINIMIZE LENGTH
MAXIMIZE COPPER
FIGURE 20. 6-CELL APPLICATION CIRCUIT INTEGRATED CHARGE/DISCHARGE PATH
FN8306.1
June 21, 2013
32
ISL94208
Separate Charge/Discharge Path
P+
VBACK
200kΩ
500
20Ω
VFET2
VFET1
VCC
CHGR Present
WKUP
VCELL6
100kΩ
2N7002
20
200Ω
20Ω
Ω
ISL94208
CB6
VCELL5
RGC
RGO
15V
200Ω
20Ω
CB5
1µF
VCELL4
200Ω
CB4
V
CC
µC
200Ω
200Ω
20Ω
RESET
OPTIONAL
LEDS/
RESISTORS
TEMP3V
VCELL3
GP
I/O
TEMPI
SCL
SDA
200Ω
20Ω
CB3
SCL
SDA
INT
CHRG
VCELL2
100Ω
200Ω
20Ω
A/D IN
AO
CB2
I/O
VCELL1
3.6V
VMON
CFET
DFET
VBACK
200Ω
20Ω
CB1
PACK INTERFACE
NOT NEEDED DURING
DISCHARGE
VCELL0
V
SS
10µF
B-
16V (<CFET VGS
)
MAX
0.47µF
35V
CHG-
P-
OPTIONAL
MINIMIZE LENGTH
MAXIMIZE COPPER
FIGURE 21. 6-CELL APPLICATION CIRCUIT SEPARATE CHARGE/DISCHARGE PATH
FN8306.1
June 21, 2013
33
ISL94208
Alternate VFET Power Supply
PC Board Layout
The circuit in Figure 22 shows an alternate connection for
powering the Charge and Discharge FETs. If the designer is
concerned that the cells become unbalanced by supplying the
FET reference from only one or two cells, then a regulator can be
used that is powered by the full stack. In this case, the VFET 1 pin
needs a supply that is less than VFET2, but not zero. In the circuit
below, a 4.3V zener provides the desired reference.
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high performance from
your PC board.
• The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
• Minimize signal trace lengths. This is especially true for the
CSENSE, DSENSE, and VCELL0-VCELL6 inputs. Trace
inductance and capacitance can easily affect circuit
performance.
This circuit provides another benefit. In the normal connection,
as the cells discharge, the voltages on VFET2 and VFET3 also
drop. When the difference between VFET2 nd VFET1 goes below
about 2.8V, the FET driver has a difficult time providing the
current to control the FETs. This limits the cell voltage to 2.8V.
However, by using the external regulator, the pack voltage can
drop to 8.6V (or a little below) and still provide adequate FET
drive. For a 6-cell pack, the minimum cell voltage is 1.4V per cell.
For a 4-cell pack, it is 2.15V per cell.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This is especially true for the DSENSE, CSENSE, and
ISREF lines, since their inputs are normally very low voltage.
• Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines. Placing signal lines on internal layers with ground
planes on top and bottom of the board provides best immunity
to electromagnetic interference.
ISL94208
8.6V
ISL80136
VBAT
VFET2
RGO
VFET1
ADJ
EN
300kΩ
50kΩ
4.3V
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
10µF
16V
0.47µF
16V
RGO
100kΩ
QFN Package
VSS
The QFN package requires additional PCB layout rules or the
Thermal Pad. The thermal pad is electrically connected to VSS
supply through the high resistance IC substrate. The thermal pad
provide heat sinking for the IC. If the design uses the RGO pin to
supply power to external components or if the device is balancing
significant current through the internal balance FETs, then the IC
can experience significant internal power dissipation. To deal with
this, careful layout of the thermal pad and the use of thermal vias
to direct the heat away from the IC is an important consideration.
Besides heat dissipation, the thermal pad also provides noise
reduction by providing a ground plane under the IC.
FIGURE 22. ISL94208 EXAMPLE ALTERNATIVE VFET POWER
SUPPLY
FN8306.1
June 21, 2013
34
ISL94208
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8306.1
CHANGE
June 11, 2013
Figure 1: Updated application diagram.
Page 7: Changed Recommended Operating Conditions for WKUP voltage.
Page 8: Reduced Max Limit for VFET1 and VFET2 current.
Page 8: Added several operating conditions for VBACK current Specifications adjusted Max Limit to
comply with the new conditions.
Page 8: Reduced the Limits for VCELL Input Current (Non-Monitoring).
Page 21: On the description of the WKPOL bit, added the comment, “When WKPOL=0, limit the
maximum voltage on the WKUP pin to no more than the voltage on VBACK.”
Page 23: Changed the circuit in Figure 2 on the use of input filters and changed the related text.
Page 23: Changed the circuits in Figure 3 regarding the recommended connection of fewer than 6 cells.
Page 24: Added text describing the WKPOL=0 and WKPOL=1 operation and changed the example Wake
up circuit in Figure 6.
Page 25: Changed the comments in Figure 7 to clarify operation of external microcontroller control of
wake up.
Page 25 and 26: Added comments to Figure 8 and Figure 9.
Pages 34 and 35: Updated the example applications circuits in Figure 20 and 21.
November 26, 2012
FN8306.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/
en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8306.1
June 21, 2013
35
ISL94208
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 5/10
4X
3.5
0.50
5.00
28X
A
6
B
PIN #1 INDEX AREA
32
25
6
1
24
PIN 1
INDEX AREA
3 .30 ± 0 . 15
17
8
(4X)
0.15
9
16
0.10 M
C A B
+
0.07
32X 0.40 ± 0.10
4
32X 0.23
- 0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08
C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
( 32X 0 . 60)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8306.1
June 21, 2013
36
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